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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Go to the source code of this file.
Data Structures | |
| struct | omap_sdrc_params |
Macros | |
| #define | SDRC_SYSCONFIG 0x010 |
| #define | SDRC_CS_CFG 0x040 |
| #define | SDRC_SHARING 0x044 |
| #define | SDRC_ERR_TYPE 0x04C |
| #define | SDRC_DLLA_CTRL 0x060 |
| #define | SDRC_DLLA_STATUS 0x064 |
| #define | SDRC_DLLB_CTRL 0x068 |
| #define | SDRC_DLLB_STATUS 0x06C |
| #define | SDRC_POWER 0x070 |
| #define | SDRC_MCFG_0 0x080 |
| #define | SDRC_MR_0 0x084 |
| #define | SDRC_EMR2_0 0x08c |
| #define | SDRC_ACTIM_CTRL_A_0 0x09c |
| #define | SDRC_ACTIM_CTRL_B_0 0x0a0 |
| #define | SDRC_RFR_CTRL_0 0x0a4 |
| #define | SDRC_MANUAL_0 0x0a8 |
| #define | SDRC_MCFG_1 0x0B0 |
| #define | SDRC_MR_1 0x0B4 |
| #define | SDRC_EMR2_1 0x0BC |
| #define | SDRC_ACTIM_CTRL_A_1 0x0C4 |
| #define | SDRC_ACTIM_CTRL_B_1 0x0C8 |
| #define | SDRC_RFR_CTRL_1 0x0D4 |
| #define | SDRC_MANUAL_1 0x0D8 |
| #define | SDRC_POWER_AUTOCOUNT_SHIFT 8 |
| #define | SDRC_POWER_AUTOCOUNT_MASK (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT) |
| #define | SDRC_POWER_CLKCTRL_SHIFT 4 |
| #define | SDRC_POWER_CLKCTRL_MASK (0x3 << SDRC_POWER_CLKCTRL_SHIFT) |
| #define | SDRC_SELF_REFRESH_ON_AUTOCOUNT (0x2 << SDRC_POWER_CLKCTRL_SHIFT) |
| #define | SDRC_RFR_CTRL_165MHz (0x00044c00 | 1) |
| #define | SDRC_RFR_CTRL_133MHz (0x0003de00 | 1) |
| #define | SDRC_RFR_CTRL_100MHz (0x0002da01 | 1) |
| #define | SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */ |
| #define | SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */ |
| #define | OMAP242X_SMS_REGADDR(reg) (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg) |
| #define | OMAP243X_SMS_REGADDR(reg) (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg) |
| #define | OMAP343X_SMS_REGADDR(reg) (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg) |
| #define | SMS_SYSCONFIG 0x010 |
| #define | SMS_ROT_CONTROL(context) (0x180 + 0x10 * context) |
| #define | SMS_ROT_SIZE(context) (0x184 + 0x10 * context) |
| #define | SMS_ROT_PHYSICAL_BA(context) (0x188 + 0x10 * context) |
Functions | |
| int | omap2_sdrc_get_params (unsigned long r, struct omap_sdrc_params **sdrc_cs0, struct omap_sdrc_params **sdrc_cs1) |
| void | omap2_sms_save_context (void) |
| void | omap2_sms_restore_context (void) |
| void | omap2_sms_write_rot_control (u32 val, unsigned ctx) |
| void | omap2_sms_write_rot_size (u32 val, unsigned ctx) |
| void | omap2_sms_write_rot_physical_ba (u32 val, unsigned ctx) |
| #define OMAP242X_SMS_REGADDR | ( | reg | ) | (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg) |
| #define OMAP243X_SMS_REGADDR | ( | reg | ) | (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg) |
| #define OMAP343X_SMS_REGADDR | ( | reg | ) | (void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg) |
| #define SDRC_POWER_AUTOCOUNT_MASK (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT) |
| #define SDRC_POWER_CLKCTRL_MASK (0x3 << SDRC_POWER_CLKCTRL_SHIFT) |
| #define SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */ |
| #define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */ |
| #define SDRC_SELF_REFRESH_ON_AUTOCOUNT (0x2 << SDRC_POWER_CLKCTRL_SHIFT) |
| #define SMS_ROT_PHYSICAL_BA | ( | context | ) | (0x188 + 0x10 * context) |
| int omap2_sdrc_get_params | ( | unsigned long | r, |
| struct omap_sdrc_params ** | sdrc_cs0, | ||
| struct omap_sdrc_params ** | sdrc_cs1 | ||
| ) |
omap2_sdrc_get_params - return SDRC register values for a given clock rate : SDRC clock rate (in Hz) : chip select 0 ram timings ** : chip select 1 ram timings **
Return pre-calculated values for the SDRC_ACTIM_CTRLA, SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01] structs,for a given SDRC clock rate 'r'. These parameters control various timing delays in the SDRAM controller that are expressed in terms of the number of SDRC clock cycles to wait; hence the clock rate dependency.
Supports 2 different timing parameters for both chip selects.
Note 1: the sdrc_init_params_cs[01] must be sorted rate descending. Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size as sdrc_init_params_cs_0.
Fills in the struct omap_sdrc_params * for each chip select. Returns 0 upon success or -1 upon failure.
1.8.2