#include <linux/types.h>
#include <scsi/libsas.h>

Data Structures
struct	mpi_msg_hdr

struct	phy_start_req

struct	phy_stop_req

struct	set_dev_bits_fis

struct	pio_setup_fis

struct	sata_completion_resp

struct	hw_event_resp

struct	reg_dev_req

struct	dereg_dev_req

struct	dev_reg_resp

struct	local_phy_ctl_req

struct	local_phy_ctl_resp

struct	port_ctl_req

struct	hw_event_ack_req

struct	ssp_completion_resp

struct	sata_event_resp

struct	ssp_event_resp

struct	general_event_resp

struct	smp_req

struct	smp_completion_resp

struct	task_abort_req

struct	task_abort_resp

struct	sas_diag_start_end_req

struct	sas_diag_execute_req

struct	set_dev_state_req

struct	sas_re_initialization_req

struct	sata_start_req

struct	ssp_ini_tm_start_req

struct	ssp_info_unit

struct	ssp_ini_io_start_req

struct	fw_flash_Update_req

struct	fw_flash_Update_resp

struct	get_nvm_data_req

struct	set_nvm_data_req

struct	get_nvm_data_resp

struct	sas_diag_start_end_resp

struct	sas_diag_execute_resp

struct	set_dev_state_resp

Macros
#define	OPC_INB_ECHO 1 /* 0x000 */

#define	OPC_INB_PHYSTART 4 /* 0x004 */

#define	OPC_INB_PHYSTOP 5 /* 0x005 */

#define	OPC_INB_SSPINIIOSTART 6 /* 0x006 */

#define	OPC_INB_SSPINITMSTART 7 /* 0x007 */

#define	OPC_INB_SSPINIEXTIOSTART 8 /* 0x008 */

#define	OPC_INB_DEV_HANDLE_ACCEPT 9 /* 0x009 */

#define	OPC_INB_SSPTGTIOSTART 10 /* 0x00A */

#define	OPC_INB_SSPTGTRSPSTART 11 /* 0x00B */

#define	OPC_INB_SSPINIEDCIOSTART 12 /* 0x00C */

#define	OPC_INB_SSPINIEXTEDCIOSTART 13 /* 0x00D */

#define	OPC_INB_SSPTGTEDCIOSTART 14 /* 0x00E */

#define	OPC_INB_SSP_ABORT 15 /* 0x00F */

#define	OPC_INB_DEREG_DEV_HANDLE 16 /* 0x010 */

#define	OPC_INB_GET_DEV_HANDLE 17 /* 0x011 */

#define	OPC_INB_SMP_REQUEST 18 /* 0x012 */

#define	OPC_INB_SMP_RESPONSE 19 /* 0x013 */

#define	OPC_INB_SMP_ABORT 20 /* 0x014 */

#define	OPC_INB_REG_DEV 22 /* 0x016 */

#define	OPC_INB_SATA_HOST_OPSTART 23 /* 0x017 */

#define	OPC_INB_SATA_ABORT 24 /* 0x018 */

#define	OPC_INB_LOCAL_PHY_CONTROL 25 /* 0x019 */

#define	OPC_INB_GET_DEV_INFO 26 /* 0x01A */

#define	OPC_INB_FW_FLASH_UPDATE 32 /* 0x020 */

#define	OPC_INB_GPIO 34 /* 0x022 */

#define	OPC_INB_SAS_DIAG_MODE_START_END 35 /* 0x023 */

#define	OPC_INB_SAS_DIAG_EXECUTE 36 /* 0x024 */

#define	OPC_INB_SAS_HW_EVENT_ACK 37 /* 0x025 */

#define	OPC_INB_GET_TIME_STAMP 38 /* 0x026 */

#define	OPC_INB_PORT_CONTROL 39 /* 0x027 */

#define	OPC_INB_GET_NVMD_DATA 40 /* 0x028 */

#define	OPC_INB_SET_NVMD_DATA 41 /* 0x029 */

#define	OPC_INB_SET_DEVICE_STATE 42 /* 0x02A */

#define	OPC_INB_GET_DEVICE_STATE 43 /* 0x02B */

#define	OPC_INB_SET_DEV_INFO 44 /* 0x02C */

#define	OPC_INB_SAS_RE_INITIALIZE 45 /* 0x02D */

#define	OPC_OUB_ECHO 1 /* 0x001 */

#define	OPC_OUB_HW_EVENT 4 /* 0x004 */

#define	OPC_OUB_SSP_COMP 5 /* 0x005 */

#define	OPC_OUB_SMP_COMP 6 /* 0x006 */

#define	OPC_OUB_LOCAL_PHY_CNTRL 7 /* 0x007 */

#define	OPC_OUB_DEV_REGIST 10 /* 0x00A */

#define	OPC_OUB_DEREG_DEV 11 /* 0x00B */

#define	OPC_OUB_GET_DEV_HANDLE 12 /* 0x00C */

#define	OPC_OUB_SATA_COMP 13 /* 0x00D */

#define	OPC_OUB_SATA_EVENT 14 /* 0x00E */

#define	OPC_OUB_SSP_EVENT 15 /* 0x00F */

#define	OPC_OUB_DEV_HANDLE_ARRIV 16 /* 0x010 */

#define	OPC_OUB_SMP_RECV_EVENT 17 /* 0x011 */

#define	OPC_OUB_SSP_RECV_EVENT 18 /* 0x012 */

#define	OPC_OUB_DEV_INFO 19 /* 0x013 */

#define	OPC_OUB_FW_FLASH_UPDATE 20 /* 0x014 */

#define	OPC_OUB_GPIO_RESPONSE 22 /* 0x016 */

#define	OPC_OUB_GPIO_EVENT 23 /* 0x017 */

#define	OPC_OUB_GENERAL_EVENT 24 /* 0x018 */

#define	OPC_OUB_SSP_ABORT_RSP 26 /* 0x01A */

#define	OPC_OUB_SATA_ABORT_RSP 27 /* 0x01B */

#define	OPC_OUB_SAS_DIAG_MODE_START_END 28 /* 0x01C */

#define	OPC_OUB_SAS_DIAG_EXECUTE 29 /* 0x01D */

#define	OPC_OUB_GET_TIME_STAMP 30 /* 0x01E */

#define	OPC_OUB_SAS_HW_EVENT_ACK 31 /* 0x01F */

#define	OPC_OUB_PORT_CONTROL 32 /* 0x020 */

#define	OPC_OUB_SKIP_ENTRY 33 /* 0x021 */

#define	OPC_OUB_SMP_ABORT_RSP 34 /* 0x022 */

#define	OPC_OUB_GET_NVMD_DATA 35 /* 0x023 */

#define	OPC_OUB_SET_NVMD_DATA 36 /* 0x024 */

#define	OPC_OUB_DEVICE_HANDLE_REMOVAL 37 /* 0x025 */

#define	OPC_OUB_SET_DEVICE_STATE 38 /* 0x026 */

#define	OPC_OUB_GET_DEVICE_STATE 39 /* 0x027 */

#define	OPC_OUB_SET_DEV_INFO 40 /* 0x028 */

#define	OPC_OUB_SAS_RE_INITIALIZE 41 /* 0x029 */

#define	SPINHOLD_DISABLE (0x00 << 14)

#define	SPINHOLD_ENABLE (0x01 << 14)

#define	LINKMODE_SAS (0x01 << 12)

#define	LINKMODE_DSATA (0x02 << 12)

#define	LINKMODE_AUTO (0x03 << 12)

#define	LINKRATE_15 (0x01 << 8)

#define	LINKRATE_30 (0x02 << 8)

#define	LINKRATE_60 (0x04 << 8)

#define	OP_BITS 0x0000FF00

#define	ID_BITS 0x0000000F

#define	SSP_RESCV_BIT 0x00010000

#define	GENERAL_EVENT_PAYLOAD 14

#define	OPCODE_BITS 0x00000fff

#define	ABORT_MASK 0x3

#define	ABORT_SINGLE 0x0

#define	ABORT_ALL 0x1

#define	SAS_DIAG_PARAM_BYTES 24

#define	FWFLASH_IOMB_RESERVED_LEN 0x07

#define	TWI_DEVICE 0x0

#define	C_SEEPROM 0x1

#define	VPD_FLASH 0x4

#define	AAP1_RDUMP 0x5

#define	IOP_RDUMP 0x6

#define	EXPAN_ROM 0x7

#define	IPMode 0x80000000

#define	NVMD_TYPE 0x0000000F

#define	NVMD_STAT 0x0000FFFF

#define	NVMD_LEN 0xFF000000

#define	NDS_BITS 0x0F

#define	PDS_BITS 0xF0

#define	HW_EVENT_RESET_START 0x01

#define	HW_EVENT_CHIP_RESET_COMPLETE 0x02

#define	HW_EVENT_PHY_STOP_STATUS 0x03

#define	HW_EVENT_SAS_PHY_UP 0x04

#define	HW_EVENT_SATA_PHY_UP 0x05

#define	HW_EVENT_SATA_SPINUP_HOLD 0x06

#define	HW_EVENT_PHY_DOWN 0x07

#define	HW_EVENT_PORT_INVALID 0x08

#define	HW_EVENT_BROADCAST_CHANGE 0x09

#define	HW_EVENT_PHY_ERROR 0x0A

#define	HW_EVENT_BROADCAST_SES 0x0B

#define	HW_EVENT_INBOUND_CRC_ERROR 0x0C

#define	HW_EVENT_HARD_RESET_RECEIVED 0x0D

#define	HW_EVENT_MALFUNCTION 0x0E

#define	HW_EVENT_ID_FRAME_TIMEOUT 0x0F

#define	HW_EVENT_BROADCAST_EXP 0x10

#define	HW_EVENT_PHY_START_STATUS 0x11

#define	HW_EVENT_LINK_ERR_INVALID_DWORD 0x12

#define	HW_EVENT_LINK_ERR_DISPARITY_ERROR 0x13

#define	HW_EVENT_LINK_ERR_CODE_VIOLATION 0x14

#define	HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH 0x15

#define	HW_EVENT_LINK_ERR_PHY_RESET_FAILED 0x16

#define	HW_EVENT_PORT_RECOVERY_TIMER_TMO 0x17

#define	HW_EVENT_PORT_RECOVER 0x18

#define	HW_EVENT_PORT_RESET_TIMER_TMO 0x19

#define	HW_EVENT_PORT_RESET_COMPLETE 0x20

#define	EVENT_BROADCAST_ASYNCH_EVENT 0x21

#define	PORT_NOT_ESTABLISHED 0x00

#define	PORT_VALID 0x01

#define	PORT_LOSTCOMM 0x02

#define	PORT_IN_RESET 0x04

#define	PORT_INVALID 0x08

#define	IO_SUCCESS 0x00

#define	IO_ABORTED 0x01

#define	IO_OVERFLOW 0x02

#define	IO_UNDERFLOW 0x03

#define	IO_FAILED 0x04

#define	IO_ABORT_RESET 0x05

#define	IO_NOT_VALID 0x06

#define	IO_NO_DEVICE 0x07

#define	IO_ILLEGAL_PARAMETER 0x08

#define	IO_LINK_FAILURE 0x09

#define	IO_PROG_ERROR 0x0A

#define	IO_EDC_IN_ERROR 0x0B

#define	IO_EDC_OUT_ERROR 0x0C

#define	IO_ERROR_HW_TIMEOUT 0x0D

#define	IO_XFER_ERROR_BREAK 0x0E

#define	IO_XFER_ERROR_PHY_NOT_READY 0x0F

#define	IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED 0x10

#define	IO_OPEN_CNX_ERROR_ZONE_VIOLATION 0x11

#define	IO_OPEN_CNX_ERROR_BREAK 0x12

#define	IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS 0x13

#define	IO_OPEN_CNX_ERROR_BAD_DESTINATION 0x14

#define	IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED 0x15

#define	IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY 0x16

#define	IO_OPEN_CNX_ERROR_WRONG_DESTINATION 0x17

#define	IO_OPEN_CNX_ERROR_UNKNOWN_ERROR 0x18

#define	IO_XFER_ERROR_NAK_RECEIVED 0x19

#define	IO_XFER_ERROR_ACK_NAK_TIMEOUT 0x1A

#define	IO_XFER_ERROR_PEER_ABORTED 0x1B

#define	IO_XFER_ERROR_RX_FRAME 0x1C

#define	IO_XFER_ERROR_DMA 0x1D

#define	IO_XFER_ERROR_CREDIT_TIMEOUT 0x1E

#define	IO_XFER_ERROR_SATA_LINK_TIMEOUT 0x1F

#define	IO_XFER_ERROR_SATA 0x20

#define	IO_XFER_ERROR_ABORTED_DUE_TO_SRST 0x22

#define	IO_XFER_ERROR_REJECTED_NCQ_MODE 0x21

#define	IO_XFER_ERROR_ABORTED_NCQ_MODE 0x23

#define	IO_XFER_OPEN_RETRY_TIMEOUT 0x24

#define	IO_XFER_SMP_RESP_CONNECTION_ERROR 0x25

#define	IO_XFER_ERROR_UNEXPECTED_PHASE 0x26

#define	IO_XFER_ERROR_XFER_RDY_OVERRUN 0x27

#define	IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED 0x28

#define	IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT 0x30

#define	IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK 0x31

#define	IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK 0x32

#define	IO_XFER_ERROR_OFFSET_MISMATCH 0x34

#define	IO_XFER_ERROR_XFER_ZERO_DATA_LEN 0x35

#define	IO_XFER_CMD_FRAME_ISSUED 0x36

#define	IO_ERROR_INTERNAL_SMP_RESOURCE 0x37

#define	IO_PORT_IN_RESET 0x38

#define	IO_DS_NON_OPERATIONAL 0x39

#define	IO_DS_IN_RECOVERY 0x3A

#define	IO_TM_TAG_NOT_FOUND 0x3B

#define	IO_XFER_PIO_SETUP_ERROR 0x3C

#define	IO_SSP_EXT_IU_ZERO_LEN_ERROR 0x3D

#define	IO_DS_IN_ERROR 0x3E

#define	IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY 0x3F

#define	IO_ABORT_IN_PROGRESS 0x40

#define	IO_ABORT_DELAYED 0x41

#define	IO_INVALID_LENGTH 0x42

#define	IO_ERROR_UNKNOWN_GENERIC 0x43

#define	SPC_MSGU_CFG_TABLE_UPDATE 0x01/* Inbound doorbell bit0 */

#define	SPC_MSGU_CFG_TABLE_RESET 0x02/* Inbound doorbell bit1 */

#define	SPC_MSGU_CFG_TABLE_FREEZE 0x04/* Inbound doorbell bit2 */

#define	SPC_MSGU_CFG_TABLE_UNFREEZE 0x08/* Inbound doorbell bit4 */

#define	MSGU_IBDB_SET 0x04

#define	MSGU_HOST_INT_STATUS 0x08

#define	MSGU_HOST_INT_MASK 0x0C

#define	MSGU_IOPIB_INT_STATUS 0x18

#define	MSGU_IOPIB_INT_MASK 0x1C

#define	MSGU_IBDB_CLEAR 0x20/* RevB - Host not use */

#define	MSGU_MSGU_CONTROL 0x24

#define	MSGU_ODR 0x3C/* RevB */

#define	MSGU_ODCR 0x40/* RevB */

#define	MSGU_SCRATCH_PAD_0 0x44

#define	MSGU_SCRATCH_PAD_1 0x48

#define	MSGU_SCRATCH_PAD_2 0x4C

#define	MSGU_SCRATCH_PAD_3 0x50

#define	MSGU_HOST_SCRATCH_PAD_0 0x54

#define	MSGU_HOST_SCRATCH_PAD_1 0x58

#define	MSGU_HOST_SCRATCH_PAD_2 0x5C

#define	MSGU_HOST_SCRATCH_PAD_3 0x60

#define	MSGU_HOST_SCRATCH_PAD_4 0x64

#define	MSGU_HOST_SCRATCH_PAD_5 0x68

#define	MSGU_HOST_SCRATCH_PAD_6 0x6C

#define	MSGU_HOST_SCRATCH_PAD_7 0x70

#define	MSGU_ODMR 0x74/* RevB */

#define	ODMR_MASK_ALL

#define	ODMR_CLEAR_ALL

#define	ODCR_CLEAR_ALL

#define	MSIX_TABLE_OFFSET 0x2000

#define	MSIX_TABLE_ELEMENT_SIZE 0x10

#define	MSIX_INTERRUPT_CONTROL_OFFSET 0xC

#define	MSIX_TABLE_BASE (MSIX_TABLE_OFFSET + MSIX_INTERRUPT_CONTROL_OFFSET)

#define	MSIX_INTERRUPT_DISABLE 0x1

#define	MSIX_INTERRUPT_ENABLE 0x0

#define	SCRATCH_PAD1_POR 0x00 /* power on reset state */

#define	SCRATCH_PAD1_SFR 0x01 /* soft reset state */

#define	SCRATCH_PAD1_ERR 0x02 /* error state */

#define	SCRATCH_PAD1_RDY 0x03 /* ready state */

#define	SCRATCH_PAD1_RST 0x04 /* soft reset toggle flag */

#define	SCRATCH_PAD1_AAP1RDY_RST 0x08 /* AAP1 ready for soft reset */

#define	SCRATCH_PAD1_STATE_MASK

#define	SCRATCH_PAD1_RESERVED

#define	SCRATCH_PAD2_POR 0x00 /* power on state */

#define	SCRATCH_PAD2_SFR 0x01 /* soft reset state */

#define	SCRATCH_PAD2_ERR 0x02 /* error state */

#define	SCRATCH_PAD2_RDY 0x03 /* ready state */

#define	SCRATCH_PAD2_FWRDY_RST 0x04 /* FW ready for soft reset flag*/

#define	SCRATCH_PAD2_IOPRDY_RST 0x08 /* IOP ready for soft reset */

#define	SCRATCH_PAD2_STATE_MASK

#define	SCRATCH_PAD2_RESERVED

#define	SCRATCH_PAD_ERROR_MASK 0xFFFFFC00 /* Error mask bits */

#define	SCRATCH_PAD_STATE_MASK 0x00000003 /* State Mask bits */

#define	MAIN_SIGNATURE_OFFSET 0x00/* DWORD 0x00 */

#define	MAIN_INTERFACE_REVISION 0x04/* DWORD 0x01 */

#define	MAIN_FW_REVISION 0x08/* DWORD 0x02 */

#define	MAIN_MAX_OUTSTANDING_IO_OFFSET 0x0C/* DWORD 0x03 */

#define	MAIN_MAX_SGL_OFFSET 0x10/* DWORD 0x04 */

#define	MAIN_CNTRL_CAP_OFFSET 0x14/* DWORD 0x05 */

#define	MAIN_GST_OFFSET 0x18/* DWORD 0x06 */

#define	MAIN_IBQ_OFFSET 0x1C/* DWORD 0x07 */

#define	MAIN_OBQ_OFFSET 0x20/* DWORD 0x08 */

#define	MAIN_IQNPPD_HPPD_OFFSET 0x24/* DWORD 0x09 */

#define	MAIN_OB_HW_EVENT_PID03_OFFSET 0x28/* DWORD 0x0A */

#define	MAIN_OB_HW_EVENT_PID47_OFFSET 0x2C/* DWORD 0x0B */

#define	MAIN_OB_NCQ_EVENT_PID03_OFFSET 0x30/* DWORD 0x0C */

#define	MAIN_OB_NCQ_EVENT_PID47_OFFSET 0x34/* DWORD 0x0D */

#define	MAIN_TITNX_EVENT_PID03_OFFSET 0x38/* DWORD 0x0E */

#define	MAIN_TITNX_EVENT_PID47_OFFSET 0x3C/* DWORD 0x0F */

#define	MAIN_OB_SSP_EVENT_PID03_OFFSET 0x40/* DWORD 0x10 */

#define	MAIN_OB_SSP_EVENT_PID47_OFFSET 0x44/* DWORD 0x11 */

#define	MAIN_OB_SMP_EVENT_PID03_OFFSET 0x48/* DWORD 0x12 */

#define	MAIN_OB_SMP_EVENT_PID47_OFFSET 0x4C/* DWORD 0x13 */

#define	MAIN_EVENT_LOG_ADDR_HI 0x50/* DWORD 0x14 */

#define	MAIN_EVENT_LOG_ADDR_LO 0x54/* DWORD 0x15 */

#define	MAIN_EVENT_LOG_BUFF_SIZE 0x58/* DWORD 0x16 */

#define	MAIN_EVENT_LOG_OPTION 0x5C/* DWORD 0x17 */

#define	MAIN_IOP_EVENT_LOG_ADDR_HI 0x60/* DWORD 0x18 */

#define	MAIN_IOP_EVENT_LOG_ADDR_LO 0x64/* DWORD 0x19 */

#define	MAIN_IOP_EVENT_LOG_BUFF_SIZE 0x68/* DWORD 0x1A */

#define	MAIN_IOP_EVENT_LOG_OPTION 0x6C/* DWORD 0x1B */

#define	MAIN_FATAL_ERROR_INTERRUPT 0x70/* DWORD 0x1C */

#define	MAIN_FATAL_ERROR_RDUMP0_OFFSET 0x74/* DWORD 0x1D */

#define	MAIN_FATAL_ERROR_RDUMP0_LENGTH 0x78/* DWORD 0x1E */

#define	MAIN_FATAL_ERROR_RDUMP1_OFFSET 0x7C/* DWORD 0x1F */

#define	MAIN_FATAL_ERROR_RDUMP1_LENGTH 0x80/* DWORD 0x20 */

#define	MAIN_HDA_FLAGS_OFFSET 0x84/* DWORD 0x21 */

#define	MAIN_ANALOG_SETUP_OFFSET 0x88/* DWORD 0x22 */

#define	GST_GSTLEN_MPIS_OFFSET 0x00

#define	GST_IQ_FREEZE_STATE0_OFFSET 0x04

#define	GST_IQ_FREEZE_STATE1_OFFSET 0x08

#define	GST_MSGUTCNT_OFFSET 0x0C

#define	GST_IOPTCNT_OFFSET 0x10

#define	GST_PHYSTATE_OFFSET 0x18

#define	GST_PHYSTATE0_OFFSET 0x18

#define	GST_PHYSTATE1_OFFSET 0x1C

#define	GST_PHYSTATE2_OFFSET 0x20

#define	GST_PHYSTATE3_OFFSET 0x24

#define	GST_PHYSTATE4_OFFSET 0x28

#define	GST_PHYSTATE5_OFFSET 0x2C

#define	GST_PHYSTATE6_OFFSET 0x30

#define	GST_PHYSTATE7_OFFSET 0x34

#define	GST_RERRINFO_OFFSET 0x44

#define	GST_MPI_STATE_UNINIT 0x00

#define	GST_MPI_STATE_INIT 0x01

#define	GST_MPI_STATE_TERMINATION 0x02

#define	GST_MPI_STATE_ERROR 0x03

#define	GST_MPI_STATE_MASK 0x07

#define	MBIC_NMI_ENABLE_VPE0_IOP 0x000418

#define	MBIC_NMI_ENABLE_VPE0_AAP1 0x000418

#define	PCIE_EVENT_INTERRUPT_ENABLE 0x003040

#define	PCIE_EVENT_INTERRUPT 0x003044

#define	PCIE_ERROR_INTERRUPT_ENABLE 0x003048

#define	PCIE_ERROR_INTERRUPT 0x00304C

#define	SPC_SOFT_RESET_SIGNATURE 0x252acbcd

#define	SPC_REG_RESET 0x000000/* reset register */

#define	SPC_REG_RESET_OSSP 0x00000001

#define	SPC_REG_RESET_RAAE 0x00000002

#define	SPC_REG_RESET_PCS_SPBC 0x00000004

#define	SPC_REG_RESET_PCS_IOP_SS 0x00000008

#define	SPC_REG_RESET_PCS_AAP1_SS 0x00000010

#define	SPC_REG_RESET_PCS_AAP2_SS 0x00000020

#define	SPC_REG_RESET_PCS_LM 0x00000040

#define	SPC_REG_RESET_PCS 0x00000080

#define	SPC_REG_RESET_GSM 0x00000100

#define	SPC_REG_RESET_DDR2 0x00010000

#define	SPC_REG_RESET_BDMA_CORE 0x00020000

#define	SPC_REG_RESET_BDMA_SXCBI 0x00040000

#define	SPC_REG_RESET_PCIE_AL_SXCBI 0x00080000

#define	SPC_REG_RESET_PCIE_PWR 0x00100000

#define	SPC_REG_RESET_PCIE_SFT 0x00200000

#define	SPC_REG_RESET_PCS_SXCBI 0x00400000

#define	SPC_REG_RESET_LMS_SXCBI 0x00800000

#define	SPC_REG_RESET_PMIC_SXCBI 0x01000000

#define	SPC_REG_RESET_PMIC_CORE 0x02000000

#define	SPC_REG_RESET_PCIE_PC_SXCBI 0x04000000

#define	SPC_REG_RESET_DEVICE 0x80000000

#define	SPC_IBW_AXI_TRANSLATION_LOW 0x003258

#define	MBIC_AAP1_ADDR_BASE 0x060000

#define	MBIC_IOP_ADDR_BASE 0x070000

#define	GSM_ADDR_BASE 0x0700000

#define	GSM_CONFIG_RESET 0x00000000

#define	RAM_ECC_DB_ERR 0x00000018

#define	GSM_READ_ADDR_PARITY_INDIC 0x00000058

#define	GSM_WRITE_ADDR_PARITY_INDIC 0x00000060

#define	GSM_WRITE_DATA_PARITY_INDIC 0x00000068

#define	GSM_READ_ADDR_PARITY_CHECK 0x00000038

#define	GSM_WRITE_ADDR_PARITY_CHECK 0x00000040

#define	GSM_WRITE_DATA_PARITY_CHECK 0x00000048

#define	RB6_ACCESS_REG 0x6A0000

#define	HDAC_EXEC_CMD 0x0002

#define	HDA_C_PA 0xcb

#define	HDA_SEQ_ID_BITS 0x00ff0000

#define	HDA_GSM_OFFSET_BITS 0x00FFFFFF

#define	MBIC_AAP1_ADDR_BASE 0x060000

#define	MBIC_IOP_ADDR_BASE 0x070000

#define	GSM_ADDR_BASE 0x0700000

#define	SPC_TOP_LEVEL_ADDR_BASE 0x000000

#define	GSM_CONFIG_RESET_VALUE 0x00003b00

#define	GPIO_ADDR_BASE 0x00090000

#define	GPIO_GPIO_0_0UTPUT_CTL_OFFSET 0x0000010c

#define	SPC_RB6_OFFSET 0x80C0

#define	RB6_MAGIC_NUMBER_RST 0x1234

#define	DEVREG_SUCCESS 0x00

#define	DEVREG_FAILURE_OUT_OF_RESOURCE 0x01

#define	DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED 0x02

#define	DEVREG_FAILURE_INVALID_PHY_ID 0x03

#define	DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED 0x04

#define	DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE 0x05

#define	DEVREG_FAILURE_PORT_NOT_VALID_STATE 0x06

#define	DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID 0x07

Functions
struct mpi_msg_hdr	__attribute__ ((packed, aligned(4)))

struct set_dev_bits_fis	__attribute__ ((packed))

Variables
__le32	header

__le32	tag

__le32	ase_sh_lm_slr_phyid

struct sas_identify_frame	sas_identify

u32	reserved [5]

__le32	phy_id

u8	fis_type

u8	n_i_pmport

u8	status

u8	error

u32	_r_a

u8	i_d_pmPort

u8	lbal

u8	lbam

u8	lbah

u8	device

u8	lbal_exp

u8	lbam_exp

u8	lbah_exp

u8	sector_count

u8	sector_count_exp

u8	_r_b

u8	e_status

u8	_r_c [2]

u8	transfer_count

__le32	param

u32	sata_resp [12]

__le32	lr_evt_status_phyid_portid

__le32	evt_param

__le32	npip_portstate

struct dev_to_host_fis	sata_fis

__le32	phyid_portid

__le32	dtype_dlr_retry

__le32	firstburstsize_ITNexustimeout

u8	sas_addr [SAS_ADDR_SIZE]

__le32	upper_device_id

__le32	device_id

__le32	phyop_phyid

u32	reserved1 [13]

__le32	portop_portid

__le32	param0

__le32	param1

__le32	sea_phyid_portid

__le32	ssptag_rescv_rescpad

struct ssp_response_iu	ssp_resp_iu

__le32	residual_count

__le32	event

__le32	port_id

__le32	inb_IOMB_payload [14]

__le32	len_ip_ir

u8	smp_req16 [16]

union {
u8 smp_req [32]

struct {
__le64 long_req_addr

__le32 long_req_size

u32 _r_a

__le64 long_resp_addr

__le32 long_resp_size

u32 _r_b

} long_smp_req

};

__le32	tag_to_abort

__le32	abort_all

__le32	scp

__le32	operation_phyid

__le32	cmdtype_cmddesc_phyid

__le32	pat1_pat2

__le32	threshold

__le32	codepat_errmsk

__le32	pmon

__le32	pERF1CTL

__le32	nds

__le32	SSAHOLT

__le32	reserved_maxPorts

__le32	open_reject_cmdretries_data_retries

__le32	sata_hol_tmo

__le32	data_len

__le32	ncqtag_atap_dir_m

u32	reserved2

u32	addr_low

u32	addr_high

__le32	len

__le32	esgl

__le32	relate_tag

__le32	tmf

u8	lun [8]

__le32	ds_ads_m

u8	efb_prio_attr

u8	additional_cdb_len

u8	cdb [16]

__le32	dir_m_tlr

struct ssp_info_unit	ssp_iu

__le32	cur_image_offset

__le32	cur_image_len

__le32	total_image_len

u32	reserved0 [7]

__le32	sgl_addr_lo

__le32	sgl_addr_hi

__le32	ext_reserved

__le32	len_ir_vpdd

__le32	vpd_offset

__le32	resp_addr_lo

__le32	resp_addr_hi

__le32	resp_len

__le32	ir_tda_bn_dps_das_nvm

__le32	dlen_status

__le32	nvm_data [12]

__le32	Status

__le32	ReportData

__le32	pds_nds

Macro Definition Documentation

#define AAP1_RDUMP 0x5

Definition at line 639 of file pm8001_hwi.h.

#define ABORT_ALL 0x1

Definition at line 438 of file pm8001_hwi.h.

#define ABORT_MASK 0x3

Definition at line 436 of file pm8001_hwi.h.

#define ABORT_SINGLE 0x0

Definition at line 437 of file pm8001_hwi.h.

#define C_SEEPROM 0x1

Definition at line 637 of file pm8001_hwi.h.

#define DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED 0x02

Definition at line 1014 of file pm8001_hwi.h.

#define DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID 0x07

Definition at line 1019 of file pm8001_hwi.h.

#define DEVREG_FAILURE_INVALID_PHY_ID 0x03

Definition at line 1015 of file pm8001_hwi.h.

#define DEVREG_FAILURE_OUT_OF_RESOURCE 0x01

Definition at line 1013 of file pm8001_hwi.h.

#define DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED 0x04

Definition at line 1016 of file pm8001_hwi.h.

#define DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE 0x05

Definition at line 1017 of file pm8001_hwi.h.

#define DEVREG_FAILURE_PORT_NOT_VALID_STATE 0x06

Definition at line 1018 of file pm8001_hwi.h.

#define DEVREG_SUCCESS 0x00

Definition at line 1012 of file pm8001_hwi.h.

#define EVENT_BROADCAST_ASYNCH_EVENT 0x21

Definition at line 732 of file pm8001_hwi.h.

#define EXPAN_ROM 0x7

Definition at line 641 of file pm8001_hwi.h.

#define FWFLASH_IOMB_RESERVED_LEN 0x07

Definition at line 595 of file pm8001_hwi.h.

#define GENERAL_EVENT_PAYLOAD 14

Definition at line 383 of file pm8001_hwi.h.

#define GPIO_ADDR_BASE 0x00090000

Definition at line 1003 of file pm8001_hwi.h.

#define GPIO_GPIO_0_0UTPUT_CTL_OFFSET 0x0000010c

Definition at line 1004 of file pm8001_hwi.h.

#define GSM_ADDR_BASE 0x0700000

Definition at line 1000 of file pm8001_hwi.h.

#define GSM_ADDR_BASE 0x0700000

Definition at line 1000 of file pm8001_hwi.h.

#define GSM_CONFIG_RESET 0x00000000

Definition at line 984 of file pm8001_hwi.h.

#define GSM_CONFIG_RESET_VALUE 0x00003b00

Definition at line 1002 of file pm8001_hwi.h.

#define GSM_READ_ADDR_PARITY_CHECK 0x00000038

Definition at line 989 of file pm8001_hwi.h.

#define GSM_READ_ADDR_PARITY_INDIC 0x00000058

Definition at line 986 of file pm8001_hwi.h.

#define GSM_WRITE_ADDR_PARITY_CHECK 0x00000040

Definition at line 990 of file pm8001_hwi.h.

#define GSM_WRITE_ADDR_PARITY_INDIC 0x00000060

Definition at line 987 of file pm8001_hwi.h.

#define GSM_WRITE_DATA_PARITY_CHECK 0x00000048

Definition at line 991 of file pm8001_hwi.h.

#define GSM_WRITE_DATA_PARITY_INDIC 0x00000068

Definition at line 988 of file pm8001_hwi.h.

#define GST_GSTLEN_MPIS_OFFSET 0x00

Definition at line 917 of file pm8001_hwi.h.

#define GST_IOPTCNT_OFFSET 0x10

Definition at line 921 of file pm8001_hwi.h.

#define GST_IQ_FREEZE_STATE0_OFFSET 0x04

Definition at line 918 of file pm8001_hwi.h.

#define GST_IQ_FREEZE_STATE1_OFFSET 0x08

Definition at line 919 of file pm8001_hwi.h.

#define GST_MPI_STATE_ERROR 0x03

Definition at line 937 of file pm8001_hwi.h.

#define GST_MPI_STATE_INIT 0x01

Definition at line 935 of file pm8001_hwi.h.

#define GST_MPI_STATE_MASK 0x07

Definition at line 938 of file pm8001_hwi.h.

#define GST_MPI_STATE_TERMINATION 0x02

Definition at line 936 of file pm8001_hwi.h.

#define GST_MPI_STATE_UNINIT 0x00

Definition at line 934 of file pm8001_hwi.h.

#define GST_MSGUTCNT_OFFSET 0x0C

Definition at line 920 of file pm8001_hwi.h.

#define GST_PHYSTATE0_OFFSET 0x18

Definition at line 923 of file pm8001_hwi.h.

#define GST_PHYSTATE1_OFFSET 0x1C

Definition at line 924 of file pm8001_hwi.h.

#define GST_PHYSTATE2_OFFSET 0x20

Definition at line 925 of file pm8001_hwi.h.

#define GST_PHYSTATE3_OFFSET 0x24

Definition at line 926 of file pm8001_hwi.h.

#define GST_PHYSTATE4_OFFSET 0x28

Definition at line 927 of file pm8001_hwi.h.

#define GST_PHYSTATE5_OFFSET 0x2C

Definition at line 928 of file pm8001_hwi.h.

#define GST_PHYSTATE6_OFFSET 0x30

Definition at line 929 of file pm8001_hwi.h.

#define GST_PHYSTATE7_OFFSET 0x34

Definition at line 930 of file pm8001_hwi.h.

#define GST_PHYSTATE_OFFSET 0x18

Definition at line 922 of file pm8001_hwi.h.

#define GST_RERRINFO_OFFSET 0x44

Definition at line 931 of file pm8001_hwi.h.

#define HDA_C_PA 0xcb

Definition at line 995 of file pm8001_hwi.h.

#define HDA_GSM_OFFSET_BITS 0x00FFFFFF

Definition at line 997 of file pm8001_hwi.h.

#define HDA_SEQ_ID_BITS 0x00ff0000

Definition at line 996 of file pm8001_hwi.h.

#define HDAC_EXEC_CMD 0x0002

Definition at line 994 of file pm8001_hwi.h.

#define HW_EVENT_BROADCAST_CHANGE 0x09

Definition at line 714 of file pm8001_hwi.h.

#define HW_EVENT_BROADCAST_EXP 0x10

Definition at line 721 of file pm8001_hwi.h.

#define HW_EVENT_BROADCAST_SES 0x0B

Definition at line 716 of file pm8001_hwi.h.

#define HW_EVENT_CHIP_RESET_COMPLETE 0x02

Definition at line 707 of file pm8001_hwi.h.

#define HW_EVENT_HARD_RESET_RECEIVED 0x0D

Definition at line 718 of file pm8001_hwi.h.

#define HW_EVENT_ID_FRAME_TIMEOUT 0x0F

Definition at line 720 of file pm8001_hwi.h.

#define HW_EVENT_INBOUND_CRC_ERROR 0x0C

Definition at line 717 of file pm8001_hwi.h.

#define HW_EVENT_LINK_ERR_CODE_VIOLATION 0x14

Definition at line 725 of file pm8001_hwi.h.

#define HW_EVENT_LINK_ERR_DISPARITY_ERROR 0x13

Definition at line 724 of file pm8001_hwi.h.

#define HW_EVENT_LINK_ERR_INVALID_DWORD 0x12

Definition at line 723 of file pm8001_hwi.h.

#define HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH 0x15

Definition at line 726 of file pm8001_hwi.h.

#define HW_EVENT_LINK_ERR_PHY_RESET_FAILED 0x16

Definition at line 727 of file pm8001_hwi.h.

#define HW_EVENT_MALFUNCTION 0x0E

Definition at line 719 of file pm8001_hwi.h.

#define HW_EVENT_PHY_DOWN 0x07

Definition at line 712 of file pm8001_hwi.h.

#define HW_EVENT_PHY_ERROR 0x0A

Definition at line 715 of file pm8001_hwi.h.

#define HW_EVENT_PHY_START_STATUS 0x11

Definition at line 722 of file pm8001_hwi.h.

#define HW_EVENT_PHY_STOP_STATUS 0x03

Definition at line 708 of file pm8001_hwi.h.

#define HW_EVENT_PORT_INVALID 0x08

Definition at line 713 of file pm8001_hwi.h.

#define HW_EVENT_PORT_RECOVER 0x18

Definition at line 729 of file pm8001_hwi.h.

#define HW_EVENT_PORT_RECOVERY_TIMER_TMO 0x17

Definition at line 728 of file pm8001_hwi.h.

#define HW_EVENT_PORT_RESET_COMPLETE 0x20

Definition at line 731 of file pm8001_hwi.h.

#define HW_EVENT_PORT_RESET_TIMER_TMO 0x19

Definition at line 730 of file pm8001_hwi.h.

#define HW_EVENT_RESET_START 0x01

Definition at line 706 of file pm8001_hwi.h.

#define HW_EVENT_SAS_PHY_UP 0x04

Definition at line 709 of file pm8001_hwi.h.

#define HW_EVENT_SATA_PHY_UP 0x05

Definition at line 710 of file pm8001_hwi.h.

#define HW_EVENT_SATA_SPINUP_HOLD 0x06

Definition at line 711 of file pm8001_hwi.h.

#define ID_BITS 0x0000000F

Definition at line 301 of file pm8001_hwi.h.

#define IO_ABORT_DELAYED 0x41

Definition at line 804 of file pm8001_hwi.h.

#define IO_ABORT_IN_PROGRESS 0x40

Definition at line 803 of file pm8001_hwi.h.

#define IO_ABORT_RESET 0x05

Definition at line 750 of file pm8001_hwi.h.

#define IO_ABORTED 0x01

Definition at line 746 of file pm8001_hwi.h.

#define IO_DS_IN_ERROR 0x3E

Definition at line 801 of file pm8001_hwi.h.

#define IO_DS_IN_RECOVERY 0x3A

Definition at line 797 of file pm8001_hwi.h.

#define IO_DS_NON_OPERATIONAL 0x39

Definition at line 796 of file pm8001_hwi.h.

#define IO_EDC_IN_ERROR 0x0B

Definition at line 756 of file pm8001_hwi.h.

#define IO_EDC_OUT_ERROR 0x0C

Definition at line 757 of file pm8001_hwi.h.

#define IO_ERROR_HW_TIMEOUT 0x0D

Definition at line 758 of file pm8001_hwi.h.

#define IO_ERROR_INTERNAL_SMP_RESOURCE 0x37

Definition at line 794 of file pm8001_hwi.h.

#define IO_ERROR_UNKNOWN_GENERIC 0x43

Definition at line 811 of file pm8001_hwi.h.

#define IO_FAILED 0x04

Definition at line 749 of file pm8001_hwi.h.

#define IO_ILLEGAL_PARAMETER 0x08

Definition at line 753 of file pm8001_hwi.h.

#define IO_INVALID_LENGTH 0x42

Definition at line 805 of file pm8001_hwi.h.

#define IO_LINK_FAILURE 0x09

Definition at line 754 of file pm8001_hwi.h.

#define IO_NO_DEVICE 0x07

Definition at line 752 of file pm8001_hwi.h.

#define IO_NOT_VALID 0x06

Definition at line 751 of file pm8001_hwi.h.

#define IO_OPEN_CNX_ERROR_BAD_DESTINATION 0x14

Definition at line 765 of file pm8001_hwi.h.

#define IO_OPEN_CNX_ERROR_BREAK 0x12

Definition at line 763 of file pm8001_hwi.h.

#define IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED 0x15

Definition at line 766 of file pm8001_hwi.h.

#define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY 0x3F

Definition at line 802 of file pm8001_hwi.h.

#define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS 0x13

Definition at line 764 of file pm8001_hwi.h.

#define IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED 0x10

Definition at line 761 of file pm8001_hwi.h.

#define IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY 0x16

Definition at line 767 of file pm8001_hwi.h.

#define IO_OPEN_CNX_ERROR_UNKNOWN_ERROR 0x18

Definition at line 769 of file pm8001_hwi.h.

#define IO_OPEN_CNX_ERROR_WRONG_DESTINATION 0x17

Definition at line 768 of file pm8001_hwi.h.

#define IO_OPEN_CNX_ERROR_ZONE_VIOLATION 0x11

Definition at line 762 of file pm8001_hwi.h.

#define IO_OVERFLOW 0x02

Definition at line 747 of file pm8001_hwi.h.

#define IO_PORT_IN_RESET 0x38

Definition at line 795 of file pm8001_hwi.h.

#define IO_PROG_ERROR 0x0A

Definition at line 755 of file pm8001_hwi.h.

#define IO_SSP_EXT_IU_ZERO_LEN_ERROR 0x3D

Definition at line 800 of file pm8001_hwi.h.

#define IO_SUCCESS 0x00

Definition at line 745 of file pm8001_hwi.h.

#define IO_TM_TAG_NOT_FOUND 0x3B

Definition at line 798 of file pm8001_hwi.h.

#define IO_UNDERFLOW 0x03

Definition at line 748 of file pm8001_hwi.h.

#define IO_XFER_CMD_FRAME_ISSUED 0x36

Definition at line 793 of file pm8001_hwi.h.

#define IO_XFER_ERROR_ABORTED_DUE_TO_SRST 0x22

Definition at line 778 of file pm8001_hwi.h.

#define IO_XFER_ERROR_ABORTED_NCQ_MODE 0x23

Definition at line 780 of file pm8001_hwi.h.

#define IO_XFER_ERROR_ACK_NAK_TIMEOUT 0x1A

Definition at line 771 of file pm8001_hwi.h.

#define IO_XFER_ERROR_BREAK 0x0E

Definition at line 759 of file pm8001_hwi.h.

#define IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT 0x30

Definition at line 787 of file pm8001_hwi.h.

#define IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK 0x31

Definition at line 788 of file pm8001_hwi.h.

#define IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK 0x32

Definition at line 789 of file pm8001_hwi.h.

#define IO_XFER_ERROR_CREDIT_TIMEOUT 0x1E

Definition at line 775 of file pm8001_hwi.h.

#define IO_XFER_ERROR_DMA 0x1D

Definition at line 774 of file pm8001_hwi.h.

#define IO_XFER_ERROR_NAK_RECEIVED 0x19

Definition at line 770 of file pm8001_hwi.h.

#define IO_XFER_ERROR_OFFSET_MISMATCH 0x34

Definition at line 791 of file pm8001_hwi.h.

#define IO_XFER_ERROR_PEER_ABORTED 0x1B

Definition at line 772 of file pm8001_hwi.h.

#define IO_XFER_ERROR_PHY_NOT_READY 0x0F

Definition at line 760 of file pm8001_hwi.h.

#define IO_XFER_ERROR_REJECTED_NCQ_MODE 0x21

Definition at line 779 of file pm8001_hwi.h.

#define IO_XFER_ERROR_RX_FRAME 0x1C

Definition at line 773 of file pm8001_hwi.h.

#define IO_XFER_ERROR_SATA 0x20

Definition at line 777 of file pm8001_hwi.h.

#define IO_XFER_ERROR_SATA_LINK_TIMEOUT 0x1F

Definition at line 776 of file pm8001_hwi.h.

#define IO_XFER_ERROR_UNEXPECTED_PHASE 0x26

Definition at line 783 of file pm8001_hwi.h.

#define IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED 0x28

Definition at line 785 of file pm8001_hwi.h.

#define IO_XFER_ERROR_XFER_RDY_OVERRUN 0x27

Definition at line 784 of file pm8001_hwi.h.

#define IO_XFER_ERROR_XFER_ZERO_DATA_LEN 0x35

Definition at line 792 of file pm8001_hwi.h.

#define IO_XFER_OPEN_RETRY_TIMEOUT 0x24

Definition at line 781 of file pm8001_hwi.h.

#define IO_XFER_PIO_SETUP_ERROR 0x3C

Definition at line 799 of file pm8001_hwi.h.

#define IO_XFER_SMP_RESP_CONNECTION_ERROR 0x25

Definition at line 782 of file pm8001_hwi.h.

#define IOP_RDUMP 0x6

Definition at line 640 of file pm8001_hwi.h.

#define IPMode 0x80000000

Definition at line 643 of file pm8001_hwi.h.

#define LINKMODE_AUTO (0x03 << 12)

Definition at line 129 of file pm8001_hwi.h.

#define LINKMODE_DSATA (0x02 << 12)

Definition at line 128 of file pm8001_hwi.h.

#define LINKMODE_SAS (0x01 << 12)

Definition at line 127 of file pm8001_hwi.h.

#define LINKRATE_15 (0x01 << 8)

Definition at line 130 of file pm8001_hwi.h.

#define LINKRATE_30 (0x02 << 8)

Definition at line 131 of file pm8001_hwi.h.

#define LINKRATE_60 (0x04 << 8)

Definition at line 132 of file pm8001_hwi.h.

#define MAIN_ANALOG_SETUP_OFFSET 0x88/* DWORD 0x22 */

Definition at line 914 of file pm8001_hwi.h.

#define MAIN_CNTRL_CAP_OFFSET 0x14/* DWORD 0x05 */

Definition at line 885 of file pm8001_hwi.h.

#define MAIN_EVENT_LOG_ADDR_HI 0x50/* DWORD 0x14 */

Definition at line 900 of file pm8001_hwi.h.

#define MAIN_EVENT_LOG_ADDR_LO 0x54/* DWORD 0x15 */

Definition at line 901 of file pm8001_hwi.h.

#define MAIN_EVENT_LOG_BUFF_SIZE 0x58/* DWORD 0x16 */

Definition at line 902 of file pm8001_hwi.h.

#define MAIN_EVENT_LOG_OPTION 0x5C/* DWORD 0x17 */

Definition at line 903 of file pm8001_hwi.h.

#define MAIN_FATAL_ERROR_INTERRUPT 0x70/* DWORD 0x1C */

Definition at line 908 of file pm8001_hwi.h.

#define MAIN_FATAL_ERROR_RDUMP0_LENGTH 0x78/* DWORD 0x1E */

Definition at line 910 of file pm8001_hwi.h.

#define MAIN_FATAL_ERROR_RDUMP0_OFFSET 0x74/* DWORD 0x1D */

Definition at line 909 of file pm8001_hwi.h.

#define MAIN_FATAL_ERROR_RDUMP1_LENGTH 0x80/* DWORD 0x20 */

Definition at line 912 of file pm8001_hwi.h.

#define MAIN_FATAL_ERROR_RDUMP1_OFFSET 0x7C/* DWORD 0x1F */

Definition at line 911 of file pm8001_hwi.h.

#define MAIN_FW_REVISION 0x08/* DWORD 0x02 */

Definition at line 882 of file pm8001_hwi.h.

#define MAIN_GST_OFFSET 0x18/* DWORD 0x06 */

Definition at line 886 of file pm8001_hwi.h.

#define MAIN_HDA_FLAGS_OFFSET 0x84/* DWORD 0x21 */

Definition at line 913 of file pm8001_hwi.h.

#define MAIN_IBQ_OFFSET 0x1C/* DWORD 0x07 */

Definition at line 887 of file pm8001_hwi.h.

#define MAIN_INTERFACE_REVISION 0x04/* DWORD 0x01 */

Definition at line 881 of file pm8001_hwi.h.

#define MAIN_IOP_EVENT_LOG_ADDR_HI 0x60/* DWORD 0x18 */

Definition at line 904 of file pm8001_hwi.h.

#define MAIN_IOP_EVENT_LOG_ADDR_LO 0x64/* DWORD 0x19 */

Definition at line 905 of file pm8001_hwi.h.

#define MAIN_IOP_EVENT_LOG_BUFF_SIZE 0x68/* DWORD 0x1A */

Definition at line 906 of file pm8001_hwi.h.

#define MAIN_IOP_EVENT_LOG_OPTION 0x6C/* DWORD 0x1B */

Definition at line 907 of file pm8001_hwi.h.

#define MAIN_IQNPPD_HPPD_OFFSET 0x24/* DWORD 0x09 */

Definition at line 889 of file pm8001_hwi.h.

#define MAIN_MAX_OUTSTANDING_IO_OFFSET 0x0C/* DWORD 0x03 */

Definition at line 883 of file pm8001_hwi.h.

#define MAIN_MAX_SGL_OFFSET 0x10/* DWORD 0x04 */

Definition at line 884 of file pm8001_hwi.h.

#define MAIN_OB_HW_EVENT_PID03_OFFSET 0x28/* DWORD 0x0A */

Definition at line 890 of file pm8001_hwi.h.

#define MAIN_OB_HW_EVENT_PID47_OFFSET 0x2C/* DWORD 0x0B */

Definition at line 891 of file pm8001_hwi.h.

#define MAIN_OB_NCQ_EVENT_PID03_OFFSET 0x30/* DWORD 0x0C */

Definition at line 892 of file pm8001_hwi.h.

#define MAIN_OB_NCQ_EVENT_PID47_OFFSET 0x34/* DWORD 0x0D */

Definition at line 893 of file pm8001_hwi.h.

#define MAIN_OB_SMP_EVENT_PID03_OFFSET 0x48/* DWORD 0x12 */

Definition at line 898 of file pm8001_hwi.h.

#define MAIN_OB_SMP_EVENT_PID47_OFFSET 0x4C/* DWORD 0x13 */

Definition at line 899 of file pm8001_hwi.h.

#define MAIN_OB_SSP_EVENT_PID03_OFFSET 0x40/* DWORD 0x10 */

Definition at line 896 of file pm8001_hwi.h.

#define MAIN_OB_SSP_EVENT_PID47_OFFSET 0x44/* DWORD 0x11 */

Definition at line 897 of file pm8001_hwi.h.

#define MAIN_OBQ_OFFSET 0x20/* DWORD 0x08 */

Definition at line 888 of file pm8001_hwi.h.

#define MAIN_SIGNATURE_OFFSET 0x00/* DWORD 0x00 */

Definition at line 880 of file pm8001_hwi.h.

#define MAIN_TITNX_EVENT_PID03_OFFSET 0x38/* DWORD 0x0E */

Definition at line 894 of file pm8001_hwi.h.

#define MAIN_TITNX_EVENT_PID47_OFFSET 0x3C/* DWORD 0x0F */

Definition at line 895 of file pm8001_hwi.h.

#define MBIC_AAP1_ADDR_BASE 0x060000

Definition at line 998 of file pm8001_hwi.h.

#define MBIC_AAP1_ADDR_BASE 0x060000

Definition at line 998 of file pm8001_hwi.h.

#define MBIC_IOP_ADDR_BASE 0x070000

Definition at line 999 of file pm8001_hwi.h.

#define MBIC_IOP_ADDR_BASE 0x070000

Definition at line 999 of file pm8001_hwi.h.

#define MBIC_NMI_ENABLE_VPE0_AAP1 0x000418

Definition at line 941 of file pm8001_hwi.h.

#define MBIC_NMI_ENABLE_VPE0_IOP 0x000418

Definition at line 940 of file pm8001_hwi.h.

#define MSGU_HOST_INT_MASK 0x0C

Definition at line 821 of file pm8001_hwi.h.

#define MSGU_HOST_INT_STATUS 0x08

Definition at line 820 of file pm8001_hwi.h.

#define MSGU_HOST_SCRATCH_PAD_0 0x54

Definition at line 832 of file pm8001_hwi.h.

#define MSGU_HOST_SCRATCH_PAD_1 0x58

Definition at line 833 of file pm8001_hwi.h.

#define MSGU_HOST_SCRATCH_PAD_2 0x5C

Definition at line 834 of file pm8001_hwi.h.

#define MSGU_HOST_SCRATCH_PAD_3 0x60

Definition at line 835 of file pm8001_hwi.h.

#define MSGU_HOST_SCRATCH_PAD_4 0x64

Definition at line 836 of file pm8001_hwi.h.

#define MSGU_HOST_SCRATCH_PAD_5 0x68

Definition at line 837 of file pm8001_hwi.h.

#define MSGU_HOST_SCRATCH_PAD_6 0x6C

Definition at line 838 of file pm8001_hwi.h.

#define MSGU_HOST_SCRATCH_PAD_7 0x70

Definition at line 839 of file pm8001_hwi.h.

#define MSGU_IBDB_CLEAR 0x20/* RevB - Host not use */

Definition at line 824 of file pm8001_hwi.h.

#define MSGU_IBDB_SET 0x04

Definition at line 819 of file pm8001_hwi.h.

#define MSGU_IOPIB_INT_MASK 0x1C

Definition at line 823 of file pm8001_hwi.h.

#define MSGU_IOPIB_INT_STATUS 0x18

Definition at line 822 of file pm8001_hwi.h.

#define MSGU_MSGU_CONTROL 0x24

Definition at line 825 of file pm8001_hwi.h.

#define MSGU_ODCR 0x40/* RevB */

Definition at line 827 of file pm8001_hwi.h.

#define MSGU_ODMR 0x74/* RevB */

Definition at line 840 of file pm8001_hwi.h.

#define MSGU_ODR 0x3C/* RevB */

Definition at line 826 of file pm8001_hwi.h.

#define MSGU_SCRATCH_PAD_0 0x44

Definition at line 828 of file pm8001_hwi.h.

#define MSGU_SCRATCH_PAD_1 0x48

Definition at line 829 of file pm8001_hwi.h.

#define MSGU_SCRATCH_PAD_2 0x4C

Definition at line 830 of file pm8001_hwi.h.

#define MSGU_SCRATCH_PAD_3 0x50

Definition at line 831 of file pm8001_hwi.h.

#define MSIX_INTERRUPT_CONTROL_OFFSET 0xC

Definition at line 850 of file pm8001_hwi.h.

#define MSIX_INTERRUPT_DISABLE 0x1

Definition at line 852 of file pm8001_hwi.h.

#define MSIX_INTERRUPT_ENABLE 0x0

Definition at line 853 of file pm8001_hwi.h.

#define MSIX_TABLE_BASE (MSIX_TABLE_OFFSET + MSIX_INTERRUPT_CONTROL_OFFSET)

Definition at line 851 of file pm8001_hwi.h.

#define MSIX_TABLE_ELEMENT_SIZE 0x10

Definition at line 849 of file pm8001_hwi.h.

#define MSIX_TABLE_OFFSET 0x2000

Definition at line 848 of file pm8001_hwi.h.

#define NDS_BITS 0x0F

Definition at line 699 of file pm8001_hwi.h.

#define NVMD_LEN 0xFF000000

Definition at line 646 of file pm8001_hwi.h.

#define NVMD_STAT 0x0000FFFF

Definition at line 645 of file pm8001_hwi.h.

#define NVMD_TYPE 0x0000000F

Definition at line 644 of file pm8001_hwi.h.

#define ODCR_CLEAR_ALL

Value:

0xFFFFFFFF /* mask all

interrupt vector*/

Definition at line 846 of file pm8001_hwi.h.

#define ODMR_CLEAR_ALL

Value:

0/* clear all

interrupt vector */

Definition at line 844 of file pm8001_hwi.h.

#define ODMR_MASK_ALL

Value:

0xFFFFFFFF/* mask all

interrupt vector */

Definition at line 843 of file pm8001_hwi.h.

#define OP_BITS 0x0000FF00

Definition at line 300 of file pm8001_hwi.h.

#define OPC_INB_DEREG_DEV_HANDLE 16 /* 0x010 */

Definition at line 61 of file pm8001_hwi.h.

#define OPC_INB_DEV_HANDLE_ACCEPT 9 /* 0x009 */

Definition at line 54 of file pm8001_hwi.h.

#define OPC_INB_ECHO 1 /* 0x000 */

Definition at line 48 of file pm8001_hwi.h.

#define OPC_INB_FW_FLASH_UPDATE 32 /* 0x020 */

Definition at line 72 of file pm8001_hwi.h.

#define OPC_INB_GET_DEV_HANDLE 17 /* 0x011 */

Definition at line 62 of file pm8001_hwi.h.

#define OPC_INB_GET_DEV_INFO 26 /* 0x01A */

Definition at line 71 of file pm8001_hwi.h.

#define OPC_INB_GET_DEVICE_STATE 43 /* 0x02B */

Definition at line 82 of file pm8001_hwi.h.

#define OPC_INB_GET_NVMD_DATA 40 /* 0x028 */

Definition at line 79 of file pm8001_hwi.h.

#define OPC_INB_GET_TIME_STAMP 38 /* 0x026 */

Definition at line 77 of file pm8001_hwi.h.

#define OPC_INB_GPIO 34 /* 0x022 */

Definition at line 73 of file pm8001_hwi.h.

#define OPC_INB_LOCAL_PHY_CONTROL 25 /* 0x019 */

Definition at line 70 of file pm8001_hwi.h.

#define OPC_INB_PHYSTART 4 /* 0x004 */

Definition at line 49 of file pm8001_hwi.h.

#define OPC_INB_PHYSTOP 5 /* 0x005 */

Definition at line 50 of file pm8001_hwi.h.

#define OPC_INB_PORT_CONTROL 39 /* 0x027 */

Definition at line 78 of file pm8001_hwi.h.

#define OPC_INB_REG_DEV 22 /* 0x016 */

Definition at line 67 of file pm8001_hwi.h.

#define OPC_INB_SAS_DIAG_EXECUTE 36 /* 0x024 */

Definition at line 75 of file pm8001_hwi.h.

#define OPC_INB_SAS_DIAG_MODE_START_END 35 /* 0x023 */

Definition at line 74 of file pm8001_hwi.h.

#define OPC_INB_SAS_HW_EVENT_ACK 37 /* 0x025 */

Definition at line 76 of file pm8001_hwi.h.

#define OPC_INB_SAS_RE_INITIALIZE 45 /* 0x02D */

Definition at line 84 of file pm8001_hwi.h.

#define OPC_INB_SATA_ABORT 24 /* 0x018 */

Definition at line 69 of file pm8001_hwi.h.

#define OPC_INB_SATA_HOST_OPSTART 23 /* 0x017 */

Definition at line 68 of file pm8001_hwi.h.

#define OPC_INB_SET_DEV_INFO 44 /* 0x02C */

Definition at line 83 of file pm8001_hwi.h.

#define OPC_INB_SET_DEVICE_STATE 42 /* 0x02A */

Definition at line 81 of file pm8001_hwi.h.

#define OPC_INB_SET_NVMD_DATA 41 /* 0x029 */

Definition at line 80 of file pm8001_hwi.h.

#define OPC_INB_SMP_ABORT 20 /* 0x014 */

Definition at line 66 of file pm8001_hwi.h.

#define OPC_INB_SMP_REQUEST 18 /* 0x012 */

Definition at line 63 of file pm8001_hwi.h.

#define OPC_INB_SMP_RESPONSE 19 /* 0x013 */

Definition at line 65 of file pm8001_hwi.h.

#define OPC_INB_SSP_ABORT 15 /* 0x00F */

Definition at line 60 of file pm8001_hwi.h.

#define OPC_INB_SSPINIEDCIOSTART 12 /* 0x00C */

Definition at line 57 of file pm8001_hwi.h.

#define OPC_INB_SSPINIEXTEDCIOSTART 13 /* 0x00D */

Definition at line 58 of file pm8001_hwi.h.

#define OPC_INB_SSPINIEXTIOSTART 8 /* 0x008 */

Definition at line 53 of file pm8001_hwi.h.

#define OPC_INB_SSPINIIOSTART 6 /* 0x006 */

Definition at line 51 of file pm8001_hwi.h.

#define OPC_INB_SSPINITMSTART 7 /* 0x007 */

Definition at line 52 of file pm8001_hwi.h.

#define OPC_INB_SSPTGTEDCIOSTART 14 /* 0x00E */

Definition at line 59 of file pm8001_hwi.h.

#define OPC_INB_SSPTGTIOSTART 10 /* 0x00A */

Definition at line 55 of file pm8001_hwi.h.

#define OPC_INB_SSPTGTRSPSTART 11 /* 0x00B */

Definition at line 56 of file pm8001_hwi.h.

#define OPC_OUB_DEREG_DEV 11 /* 0x00B */

Definition at line 93 of file pm8001_hwi.h.

#define OPC_OUB_DEV_HANDLE_ARRIV 16 /* 0x010 */

Definition at line 98 of file pm8001_hwi.h.

#define OPC_OUB_DEV_INFO 19 /* 0x013 */

Definition at line 102 of file pm8001_hwi.h.

#define OPC_OUB_DEV_REGIST 10 /* 0x00A */

Definition at line 92 of file pm8001_hwi.h.

#define OPC_OUB_DEVICE_HANDLE_REMOVAL 37 /* 0x025 */

Definition at line 118 of file pm8001_hwi.h.

#define OPC_OUB_ECHO 1 /* 0x001 */

Definition at line 87 of file pm8001_hwi.h.

#define OPC_OUB_FW_FLASH_UPDATE 20 /* 0x014 */

Definition at line 103 of file pm8001_hwi.h.

#define OPC_OUB_GENERAL_EVENT 24 /* 0x018 */

Definition at line 106 of file pm8001_hwi.h.

#define OPC_OUB_GET_DEV_HANDLE 12 /* 0x00C */

Definition at line 94 of file pm8001_hwi.h.

#define OPC_OUB_GET_DEVICE_STATE 39 /* 0x027 */

Definition at line 120 of file pm8001_hwi.h.

#define OPC_OUB_GET_NVMD_DATA 35 /* 0x023 */

Definition at line 116 of file pm8001_hwi.h.

#define OPC_OUB_GET_TIME_STAMP 30 /* 0x01E */

Definition at line 111 of file pm8001_hwi.h.

#define OPC_OUB_GPIO_EVENT 23 /* 0x017 */

Definition at line 105 of file pm8001_hwi.h.

#define OPC_OUB_GPIO_RESPONSE 22 /* 0x016 */

Definition at line 104 of file pm8001_hwi.h.

#define OPC_OUB_HW_EVENT 4 /* 0x004 */

Definition at line 88 of file pm8001_hwi.h.

#define OPC_OUB_LOCAL_PHY_CNTRL 7 /* 0x007 */

Definition at line 91 of file pm8001_hwi.h.

#define OPC_OUB_PORT_CONTROL 32 /* 0x020 */

Definition at line 113 of file pm8001_hwi.h.

#define OPC_OUB_SAS_DIAG_EXECUTE 29 /* 0x01D */

Definition at line 110 of file pm8001_hwi.h.

#define OPC_OUB_SAS_DIAG_MODE_START_END 28 /* 0x01C */

Definition at line 109 of file pm8001_hwi.h.

#define OPC_OUB_SAS_HW_EVENT_ACK 31 /* 0x01F */

Definition at line 112 of file pm8001_hwi.h.

#define OPC_OUB_SAS_RE_INITIALIZE 41 /* 0x029 */

Definition at line 122 of file pm8001_hwi.h.

#define OPC_OUB_SATA_ABORT_RSP 27 /* 0x01B */

Definition at line 108 of file pm8001_hwi.h.

#define OPC_OUB_SATA_COMP 13 /* 0x00D */

Definition at line 95 of file pm8001_hwi.h.

#define OPC_OUB_SATA_EVENT 14 /* 0x00E */

Definition at line 96 of file pm8001_hwi.h.

#define OPC_OUB_SET_DEV_INFO 40 /* 0x028 */

Definition at line 121 of file pm8001_hwi.h.

#define OPC_OUB_SET_DEVICE_STATE 38 /* 0x026 */

Definition at line 119 of file pm8001_hwi.h.

#define OPC_OUB_SET_NVMD_DATA 36 /* 0x024 */

Definition at line 117 of file pm8001_hwi.h.

#define OPC_OUB_SKIP_ENTRY 33 /* 0x021 */

Definition at line 114 of file pm8001_hwi.h.

#define OPC_OUB_SMP_ABORT_RSP 34 /* 0x022 */

Definition at line 115 of file pm8001_hwi.h.

#define OPC_OUB_SMP_COMP 6 /* 0x006 */

Definition at line 90 of file pm8001_hwi.h.

#define OPC_OUB_SMP_RECV_EVENT 17 /* 0x011 */

Definition at line 100 of file pm8001_hwi.h.

#define OPC_OUB_SSP_ABORT_RSP 26 /* 0x01A */

Definition at line 107 of file pm8001_hwi.h.

#define OPC_OUB_SSP_COMP 5 /* 0x005 */

Definition at line 89 of file pm8001_hwi.h.

#define OPC_OUB_SSP_EVENT 15 /* 0x00F */

Definition at line 97 of file pm8001_hwi.h.

#define OPC_OUB_SSP_RECV_EVENT 18 /* 0x012 */

Definition at line 101 of file pm8001_hwi.h.

#define OPCODE_BITS 0x00000fff

Definition at line 384 of file pm8001_hwi.h.

#define PCIE_ERROR_INTERRUPT 0x00304C

Definition at line 946 of file pm8001_hwi.h.

#define PCIE_ERROR_INTERRUPT_ENABLE 0x003048

Definition at line 945 of file pm8001_hwi.h.

#define PCIE_EVENT_INTERRUPT 0x003044

Definition at line 944 of file pm8001_hwi.h.

#define PCIE_EVENT_INTERRUPT_ENABLE 0x003040

Definition at line 943 of file pm8001_hwi.h.

#define PDS_BITS 0xF0

Definition at line 700 of file pm8001_hwi.h.

#define PORT_IN_RESET 0x04

Definition at line 738 of file pm8001_hwi.h.

#define PORT_INVALID 0x08

Definition at line 739 of file pm8001_hwi.h.

#define PORT_LOSTCOMM 0x02

Definition at line 737 of file pm8001_hwi.h.

#define PORT_NOT_ESTABLISHED 0x00

Definition at line 735 of file pm8001_hwi.h.

#define PORT_VALID 0x01

Definition at line 736 of file pm8001_hwi.h.

#define RAM_ECC_DB_ERR 0x00000018

Definition at line 985 of file pm8001_hwi.h.

#define RB6_ACCESS_REG 0x6A0000

Definition at line 993 of file pm8001_hwi.h.

#define RB6_MAGIC_NUMBER_RST 0x1234

Definition at line 1009 of file pm8001_hwi.h.

#define SAS_DIAG_PARAM_BYTES 24

Definition at line 479 of file pm8001_hwi.h.

#define SCRATCH_PAD1_AAP1RDY_RST 0x08 /* AAP1 ready for soft reset */

Definition at line 862 of file pm8001_hwi.h.

#define SCRATCH_PAD1_ERR 0x02 /* error state */

Definition at line 859 of file pm8001_hwi.h.

#define SCRATCH_PAD1_POR 0x00 /* power on reset state */

Definition at line 857 of file pm8001_hwi.h.

#define SCRATCH_PAD1_RDY 0x03 /* ready state */

Definition at line 860 of file pm8001_hwi.h.

#define SCRATCH_PAD1_RESERVED

Value:

0x000003F8 /* Scratch Pad1

Reserved bit 3 to 9 */

Definition at line 864 of file pm8001_hwi.h.

#define SCRATCH_PAD1_RST 0x04 /* soft reset toggle flag */

Definition at line 861 of file pm8001_hwi.h.

#define SCRATCH_PAD1_SFR 0x01 /* soft reset state */

Definition at line 858 of file pm8001_hwi.h.

#define SCRATCH_PAD1_STATE_MASK

Value:

0xFFFFFFF0 /* ScratchPad1

Mask, bit1-0 State, bit2 Soft Reset, bit3 FW RDY for Soft Reset */

Definition at line 863 of file pm8001_hwi.h.

#define SCRATCH_PAD2_ERR 0x02 /* error state */

Definition at line 869 of file pm8001_hwi.h.

#define SCRATCH_PAD2_FWRDY_RST 0x04 /* FW ready for soft reset flag*/

Definition at line 871 of file pm8001_hwi.h.

#define SCRATCH_PAD2_IOPRDY_RST 0x08 /* IOP ready for soft reset */

Definition at line 872 of file pm8001_hwi.h.

#define SCRATCH_PAD2_POR 0x00 /* power on state */

Definition at line 867 of file pm8001_hwi.h.

#define SCRATCH_PAD2_RDY 0x03 /* ready state */

Definition at line 870 of file pm8001_hwi.h.

#define SCRATCH_PAD2_RESERVED

Value:

0x000003FC /* Scratch Pad1

Reserved bit 2 to 9 */

Definition at line 874 of file pm8001_hwi.h.

#define SCRATCH_PAD2_SFR 0x01 /* soft reset state */

Definition at line 868 of file pm8001_hwi.h.

#define SCRATCH_PAD2_STATE_MASK

Value:

0xFFFFFFF4 /* ScratchPad 2

Mask, bit1-0 State */

Definition at line 873 of file pm8001_hwi.h.

#define SCRATCH_PAD_ERROR_MASK 0xFFFFFC00 /* Error mask bits */

Definition at line 876 of file pm8001_hwi.h.

#define SCRATCH_PAD_STATE_MASK 0x00000003 /* State Mask bits */

Definition at line 877 of file pm8001_hwi.h.

#define SPC_IBW_AXI_TRANSLATION_LOW 0x003258

Definition at line 978 of file pm8001_hwi.h.

#define SPC_MSGU_CFG_TABLE_FREEZE 0x04/* Inbound doorbell bit2 */

Definition at line 817 of file pm8001_hwi.h.

#define SPC_MSGU_CFG_TABLE_RESET 0x02/* Inbound doorbell bit1 */

Definition at line 816 of file pm8001_hwi.h.

#define SPC_MSGU_CFG_TABLE_UNFREEZE 0x08/* Inbound doorbell bit4 */

Definition at line 818 of file pm8001_hwi.h.

#define SPC_MSGU_CFG_TABLE_UPDATE 0x01/* Inbound doorbell bit0 */

Definition at line 815 of file pm8001_hwi.h.

#define SPC_RB6_OFFSET 0x80C0

Definition at line 1007 of file pm8001_hwi.h.

#define SPC_REG_RESET 0x000000/* reset register */

Definition at line 952 of file pm8001_hwi.h.

#define SPC_REG_RESET_BDMA_CORE 0x00020000

Definition at line 965 of file pm8001_hwi.h.

#define SPC_REG_RESET_BDMA_SXCBI 0x00040000

Definition at line 966 of file pm8001_hwi.h.

#define SPC_REG_RESET_DDR2 0x00010000

Definition at line 964 of file pm8001_hwi.h.

#define SPC_REG_RESET_DEVICE 0x80000000

Definition at line 975 of file pm8001_hwi.h.

#define SPC_REG_RESET_GSM 0x00000100

Definition at line 963 of file pm8001_hwi.h.

#define SPC_REG_RESET_LMS_SXCBI 0x00800000

Definition at line 971 of file pm8001_hwi.h.

#define SPC_REG_RESET_OSSP 0x00000001

Definition at line 955 of file pm8001_hwi.h.

#define SPC_REG_RESET_PCIE_AL_SXCBI 0x00080000

Definition at line 967 of file pm8001_hwi.h.

#define SPC_REG_RESET_PCIE_PC_SXCBI 0x04000000

Definition at line 974 of file pm8001_hwi.h.

#define SPC_REG_RESET_PCIE_PWR 0x00100000

Definition at line 968 of file pm8001_hwi.h.

#define SPC_REG_RESET_PCIE_SFT 0x00200000

Definition at line 969 of file pm8001_hwi.h.

#define SPC_REG_RESET_PCS 0x00000080

Definition at line 962 of file pm8001_hwi.h.

#define SPC_REG_RESET_PCS_AAP1_SS 0x00000010

Definition at line 959 of file pm8001_hwi.h.

#define SPC_REG_RESET_PCS_AAP2_SS 0x00000020

Definition at line 960 of file pm8001_hwi.h.

#define SPC_REG_RESET_PCS_IOP_SS 0x00000008

Definition at line 958 of file pm8001_hwi.h.

#define SPC_REG_RESET_PCS_LM 0x00000040

Definition at line 961 of file pm8001_hwi.h.

#define SPC_REG_RESET_PCS_SPBC 0x00000004

Definition at line 957 of file pm8001_hwi.h.

#define SPC_REG_RESET_PCS_SXCBI 0x00400000

Definition at line 970 of file pm8001_hwi.h.

#define SPC_REG_RESET_PMIC_CORE 0x02000000

Definition at line 973 of file pm8001_hwi.h.

#define SPC_REG_RESET_PMIC_SXCBI 0x01000000

Definition at line 972 of file pm8001_hwi.h.

#define SPC_REG_RESET_RAAE 0x00000002

Definition at line 956 of file pm8001_hwi.h.

#define SPC_SOFT_RESET_SIGNATURE 0x252acbcd

Definition at line 948 of file pm8001_hwi.h.

#define SPC_TOP_LEVEL_ADDR_BASE 0x000000

Definition at line 1001 of file pm8001_hwi.h.

#define SPINHOLD_DISABLE (0x00 << 14)

Definition at line 125 of file pm8001_hwi.h.

#define SPINHOLD_ENABLE (0x01 << 14)

Definition at line 126 of file pm8001_hwi.h.

#define SSP_RESCV_BIT 0x00010000

Definition at line 345 of file pm8001_hwi.h.

#define TWI_DEVICE 0x0

Definition at line 636 of file pm8001_hwi.h.

#define VPD_FLASH 0x4

Definition at line 638 of file pm8001_hwi.h.

Function Documentation

struct mpi_msg_hdr __attribute__ ( (packed, aligned(4)) )

read

Scatter-gather list for preada/pwritea calls.

< Client physical address of the buffer segment.

< Page table entry describing the caching and location override characteristics of the buffer segment. Some drivers ignore this element and will require that the NOCACHE flag be set on their requests.

< Length of the buffer segment.

Definition at line 1740 of file hypervisor.h.

struct set_dev_bits_fis __attribute__ ( (packed) )

read

mcontroller : adapter info structure for old mimd_t apps

: base address : irq number : number of logical drives : pci bus : pci device : pci function : pci id : vendor id : slot number : unique id

Definition at line 171 of file esd_usb2.c.

Variable Documentation

union { ... }

__le32 _r_a[12]

Definition at line 190 of file pm8001_hwi.h.

u32 _r_b

Definition at line 229 of file pm8001_hwi.h.

u8 _r_c[2]

Definition at line 231 of file pm8001_hwi.h.

__le32 abort_all

Definition at line 437 of file pm8001_hwi.h.

u8 additional_cdb_len

Definition at line 566 of file pm8001_hwi.h.

__le32 addr_high

Definition at line 538 of file pm8001_hwi.h.

__le32 addr_low

Definition at line 537 of file pm8001_hwi.h.

__le32 ase_sh_lm_slr_phyid

Definition at line 158 of file pm8001_hwi.h.

u8 cdb[16]

Definition at line 569 of file pm8001_hwi.h.

__le32 cmdtype_cmddesc_phyid

Definition at line 478 of file pm8001_hwi.h.

__le32 codepat_errmsk

Definition at line 481 of file pm8001_hwi.h.

__le32 cur_image_len

Definition at line 595 of file pm8001_hwi.h.

__le32 cur_image_offset

Definition at line 594 of file pm8001_hwi.h.

__le32 data_len

Definition at line 532 of file pm8001_hwi.h.

u8 device

Definition at line 222 of file pm8001_hwi.h.

__le32 device_id

Definition at line 263 of file pm8001_hwi.h.

__le32 dir_m_tlr

Definition at line 579 of file pm8001_hwi.h.

__le32 dlen_status

Definition at line 659 of file pm8001_hwi.h.

__le32 ds_ads_m

Definition at line 549 of file pm8001_hwi.h.

__le32 dtype_dlr_retry

Definition at line 251 of file pm8001_hwi.h.

u8 e_status

Definition at line 230 of file pm8001_hwi.h.

u8 efb_prio_attr

Definition at line 561 of file pm8001_hwi.h.

u8 error

Definition at line 189 of file pm8001_hwi.h.

__le32 esgl

Definition at line 540 of file pm8001_hwi.h.

__le32 event

Definition at line 360 of file pm8001_hwi.h.

__le32 evt_param

Definition at line 234 of file pm8001_hwi.h.

__le32 ext_reserved

Definition at line 601 of file pm8001_hwi.h.

__le32 firstburstsize_ITNexustimeout

Definition at line 252 of file pm8001_hwi.h.

u8 fis_type

Definition at line 182 of file pm8001_hwi.h.

__le32 header

Definition at line 145 of file pm8001_hwi.h.

u8 i_d_pmPort

Definition at line 210 of file pm8001_hwi.h.

__le32 inb_IOMB_payload[14]

Definition at line 382 of file pm8001_hwi.h.

__le32 ir_tda_bn_dps_das_nvm

Definition at line 658 of file pm8001_hwi.h.

u8 lbah

Definition at line 221 of file pm8001_hwi.h.

u8 lbah_exp

Definition at line 225 of file pm8001_hwi.h.

u8 lbal

Definition at line 219 of file pm8001_hwi.h.

u8 lbal_exp

Definition at line 223 of file pm8001_hwi.h.

u8 lbam

Definition at line 220 of file pm8001_hwi.h.

u8 lbam_exp

Definition at line 224 of file pm8001_hwi.h.

__le32 len

Definition at line 539 of file pm8001_hwi.h.

__le32 len_ip_ir

Definition at line 414 of file pm8001_hwi.h.

__le32 len_ir_vpdd

Definition at line 623 of file pm8001_hwi.h.

__le64 long_req_addr

Definition at line 424 of file pm8001_hwi.h.

__le32 long_req_size

Definition at line 425 of file pm8001_hwi.h.

__le64 long_resp_addr

Definition at line 427 of file pm8001_hwi.h.

__le32 long_resp_size

Definition at line 428 of file pm8001_hwi.h.

struct { ... } long_smp_req

__le32 lr_evt_status_phyid_portid

Definition at line 233 of file pm8001_hwi.h.

u8 lun[8]

Definition at line 548 of file pm8001_hwi.h.

u8 n_i_pmport

Definition at line 183 of file pm8001_hwi.h.

__le32 ncqtag_atap_dir_m

Definition at line 533 of file pm8001_hwi.h.

__le32 nds

Definition at line 493 of file pm8001_hwi.h.

__le32 npip_portstate

Definition at line 235 of file pm8001_hwi.h.

__le32 nvm_data[12]

Definition at line 660 of file pm8001_hwi.h.

__le32 open_reject_cmdretries_data_retries

Definition at line 520 of file pm8001_hwi.h.

__le32 operation_phyid

Definition at line 462 of file pm8001_hwi.h.

struct mspro_param_register param

Definition at line 222 of file pm8001_hwi.h.

__le32 param0

Definition at line 317 of file pm8001_hwi.h.

__le32 param1

Definition at line 318 of file pm8001_hwi.h.

__le32 pat1_pat2

Definition at line 479 of file pm8001_hwi.h.

__le32 pds_nds

Definition at line 700 of file pm8001_hwi.h.

__le32 pERF1CTL

Definition at line 483 of file pm8001_hwi.h.

__le32 phy_id

Definition at line 169 of file pm8001_hwi.h.

__le32 phyid_portid

Definition at line 250 of file pm8001_hwi.h.

__le32 phyop_phyid

Definition at line 287 of file pm8001_hwi.h.

__le32 pmon

Definition at line 482 of file pm8001_hwi.h.

__le32 port_id

Definition at line 361 of file pm8001_hwi.h.

__le32 portop_portid

Definition at line 316 of file pm8001_hwi.h.

__le32 relate_tag

Definition at line 546 of file pm8001_hwi.h.

__le32 ReportData

Definition at line 686 of file pm8001_hwi.h.

u32 reserved[11]

Definition at line 160 of file pm8001_hwi.h.

u32 reserved0[7]

Definition at line 597 of file pm8001_hwi.h.

u32 reserved1

Definition at line 288 of file pm8001_hwi.h.

u8 reserved2

Definition at line 536 of file pm8001_hwi.h.

__le32 reserved_maxPorts

Definition at line 519 of file pm8001_hwi.h.

__le32 residual_count

Definition at line 348 of file pm8001_hwi.h.

__le32 resp_addr_hi

Definition at line 627 of file pm8001_hwi.h.

__le32 resp_addr_lo

Definition at line 626 of file pm8001_hwi.h.

__le32 resp_len

Definition at line 628 of file pm8001_hwi.h.

u8 sas_addr[SAS_ADDR_SIZE]

Definition at line 253 of file pm8001_hwi.h.

struct sas_identify_frame sas_identify

Definition at line 159 of file pm8001_hwi.h.

struct host_to_dev_fis sata_fis

Definition at line 237 of file pm8001_hwi.h.

__le32 sata_hol_tmo

Definition at line 523 of file pm8001_hwi.h.

u32 sata_resp[12]

Definition at line 223 of file pm8001_hwi.h.

__le32 scp

Definition at line 452 of file pm8001_hwi.h.

__le32 sea_phyid_portid

Definition at line 330 of file pm8001_hwi.h.

u8 sector_count

Definition at line 227 of file pm8001_hwi.h.

u8 sector_count_exp

Definition at line 228 of file pm8001_hwi.h.

__le32 sgl_addr_hi

Definition at line 599 of file pm8001_hwi.h.

__le32 sgl_addr_lo

Definition at line 598 of file pm8001_hwi.h.

u8 smp_req[32]

Definition at line 422 of file pm8001_hwi.h.

u8 smp_req16[16]

Definition at line 420 of file pm8001_hwi.h.

__le32 SSAHOLT

Definition at line 513 of file pm8001_hwi.h.

struct ssp_info_unit ssp_iu

Definition at line 580 of file pm8001_hwi.h.

struct ssp_response_iu ssp_resp_iu

Definition at line 347 of file pm8001_hwi.h.

__le32 ssptag_rescv_rescpad

Definition at line 346 of file pm8001_hwi.h.

__le32 status

Definition at line 188 of file pm8001_hwi.h.

__le32 Status

Definition at line 685 of file pm8001_hwi.h.

__le32 tag

Definition at line 157 of file pm8001_hwi.h.

__le32 tag_to_abort

Definition at line 436 of file pm8001_hwi.h.

__le32 threshold

Definition at line 480 of file pm8001_hwi.h.

__le32 tmf

Definition at line 547 of file pm8001_hwi.h.

__le32 total_image_len

Definition at line 596 of file pm8001_hwi.h.

u8 transfer_count

Definition at line 232 of file pm8001_hwi.h.

__le32 upper_device_id

Definition at line 254 of file pm8001_hwi.h.

__le32 vpd_offset

Definition at line 624 of file pm8001_hwi.h.

Data Structures

Macros

Functions

Variables

Macro Definition Documentation

Function Documentation

Variable Documentation