#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <plat/prcm.h>
#include "soc.h"
#include "common.h"
#include "vp.h"
#include "prm2xxx_3xxx.h"
#include "cm2xxx_3xxx.h"
#include "prm-regbits-24xx.h"
#include "prm-regbits-34xx.h"

Data Structures
struct	omap3_vp

Macros
#define	MAX_VP_ID ARRAY_SIZE(omap3_vp);

Functions
u32	omap2_prm_read_mod_reg (s16 module, u16 idx)

void	omap2_prm_write_mod_reg (u32 val, s16 module, u16 idx)

u32	omap2_prm_rmw_mod_reg_bits (u32 mask, u32 bits, s16 module, s16 idx)

u32	omap2_prm_read_mod_bits_shift (s16 domain, s16 idx, u32 mask)

u32	omap2_prm_set_mod_reg_bits (u32 bits, s16 module, s16 idx)

u32	omap2_prm_clear_mod_reg_bits (u32 bits, s16 module, s16 idx)

int	omap2_prm_is_hardreset_asserted (s16 prm_mod, u8 shift)

int	omap2_prm_assert_hardreset (s16 prm_mod, u8 shift)

int	omap2_prm_deassert_hardreset (s16 prm_mod, u8 rst_shift, u8 st_shift)

u32	omap3_prm_vp_check_txdone (u8 vp_id)

void	omap3_prm_vp_clear_txdone (u8 vp_id)

u32	omap3_prm_vcvp_read (u8 offset)

void	omap3_prm_vcvp_write (u32 val, u8 offset)

u32	omap3_prm_vcvp_rmw (u32 mask, u32 bits, u8 offset)

void	omap3xxx_prm_read_pending_irqs (unsigned long *events)

void	omap3xxx_prm_ocp_barrier (void)

void	omap3xxx_prm_save_and_clear_irqen (u32 *saved_mask)

void	omap3xxx_prm_restore_irqen (u32 *saved_mask)

void	omap3xxx_prm_reconfigure_io_chain (void)

	subsys_initcall (omap3xxx_prcm_init)

Macro Definition Documentation

#define MAX_VP_ID ARRAY_SIZE(omap3_vp);

Definition at line 200 of file prm2xxx_3xxx.c.

Function Documentation

int omap2_prm_assert_hardreset	(	s16	prm_mod,
		u8	shift
	)

omap2_prm_assert_hardreset - assert the HW reset line of a submodule : PRM submodule base (e.g. CORE_MOD) : register bit shift corresponding to the reset line to assert

Some IPs like dsp or iva contain processors that require an HW reset line to be asserted / deasserted in order to fully enable the IP. These modules may have multiple hard-reset lines that reset different 'submodules' inside the IP block. This function will place the submodule into reset. Returns 0 upon success or -EINVAL upon an argument error.

Definition at line 126 of file prm2xxx_3xxx.c.

u32 omap2_prm_clear_mod_reg_bits	(	u32	bits,
		s16	module,
		s16	idx
	)

Definition at line 89 of file prm2xxx_3xxx.c.

int omap2_prm_deassert_hardreset	(	s16	prm_mod,
		u8	rst_shift,
		u8	st_shift
	)

omap2_prm_deassert_hardreset - deassert a submodule hardreset line and wait : PRM submodule base (e.g. CORE_MOD) : register bit shift corresponding to the reset line to deassert : register bit shift for the status of the deasserted submodule

Some IPs like dsp or iva contain processors that require an HW reset line to be asserted / deasserted in order to fully enable the IP. These modules may have multiple hard-reset lines that reset different 'submodules' inside the IP block. This function will take the submodule out of reset and wait until the PRCM indicates that the reset has completed before returning. Returns 0 upon success or -EINVAL upon an argument error, -EEXIST if the submodule was already out of reset, or -EBUSY if the submodule did not exit reset promptly.

Definition at line 154 of file prm2xxx_3xxx.c.

int omap2_prm_is_hardreset_asserted	(	s16	prm_mod,
		u8	shift
	)

omap2_prm_is_hardreset_asserted - read the HW reset line state of submodules contained in the hwmod module : PRM submodule base (e.g. CORE_MOD) : register bit shift corresponding to the reset line to check

Returns 1 if the (sub)module hardreset line is currently asserted, 0 if the (sub)module hardreset line is not currently asserted, or -EINVAL if called while running on a non-OMAP2/3 chip.

Definition at line 105 of file prm2xxx_3xxx.c.

u32 omap2_prm_read_mod_bits_shift	(	s16	domain,
		s16	idx,
		u32	mask
	)

Definition at line 73 of file prm2xxx_3xxx.c.

u32 omap2_prm_read_mod_reg	(	s16	module,
		u16	idx
	)

Definition at line 49 of file prm2xxx_3xxx.c.

u32 omap2_prm_rmw_mod_reg_bits	(	u32	mask,
		u32	bits,
		s16	module,
		s16	idx
	)

Definition at line 60 of file prm2xxx_3xxx.c.

u32 omap2_prm_set_mod_reg_bits	(	u32	bits,
		s16	module,
		s16	idx
	)

Definition at line 84 of file prm2xxx_3xxx.c.

void omap2_prm_write_mod_reg	(	u32	val,
		s16	module,
		u16	idx
	)

Definition at line 54 of file prm2xxx_3xxx.c.

u32 omap3_prm_vcvp_read ( u8 offset )

Definition at line 220 of file prm2xxx_3xxx.c.

u32 omap3_prm_vcvp_rmw	(	u32	mask,
		u32	bits,
		u8	offset
	)

Definition at line 230 of file prm2xxx_3xxx.c.

void omap3_prm_vcvp_write	(	u32	val,
		u8	offset
	)

Definition at line 225 of file prm2xxx_3xxx.c.

u32 omap3_prm_vp_check_txdone ( u8 vp_id )

Definition at line 202 of file prm2xxx_3xxx.c.

void omap3_prm_vp_clear_txdone ( u8 vp_id )

Definition at line 212 of file prm2xxx_3xxx.c.

void omap3xxx_prm_ocp_barrier ( void )

omap3xxx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete

Force any buffered writes to the PRM IP block to complete. Needed by the PRM IRQ handler, which reads and writes directly to the IP block, to avoid race conditions after acknowledging or clearing IRQ bits. No return value.

Definition at line 262 of file prm2xxx_3xxx.c.

void omap3xxx_prm_read_pending_irqs ( unsigned long * events )

omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into : ptr to a u32, preallocated by caller

Read PRM_IRQSTATUS_MPU bits, AND'ed with the currently-enabled PRM MPU IRQs, and store the result into the u32 pointed to by . No return value.

Definition at line 243 of file prm2xxx_3xxx.c.

void omap3xxx_prm_reconfigure_io_chain ( void )

omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain

Clear any previously-latched I/O wakeup events and ensure that the I/O wakeup gates are aligned with the current mux settings. Works by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then deasserting WUCLKIN and clearing the ST_IO_CHAIN WKST bit. No return value.

Definition at line 313 of file prm2xxx_3xxx.c.

void omap3xxx_prm_restore_irqen ( u32 * saved_mask )

omap3xxx_prm_restore_irqen - set PRM_IRQENABLE_MPU register from args : ptr to a u32 array of IRQENABLE bits saved previously

Restore the PRM_IRQENABLE_MPU register from . Intended to be used in the PRM interrupt handler resume callback to restore values saved by omap3xxx_prm_save_and_clear_irqen(). No OCP barrier should be needed here; any pending PRM interrupts will fire once the writes reach the PRM. No return value.

Definition at line 298 of file prm2xxx_3xxx.c.

void omap3xxx_prm_save_and_clear_irqen ( u32 * saved_mask )

omap3xxx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU reg : ptr to a u32 array to save IRQENABLE bits

Save the PRM_IRQENABLE_MPU register to . must be allocated by the caller. Intended to be used in the PRM interrupt handler suspend callback. The OCP barrier is needed to ensure the write to disable PRM interrupts reaches the PRM before returning; otherwise, spurious interrupts might occur. No return value.

Definition at line 278 of file prm2xxx_3xxx.c.

subsys_initcall ( omap3xxx_prcm_init )

Data Structures

Macros

Functions

Macro Definition Documentation

Function Documentation