prm2xxx_3xxx.c

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/*
 * OMAP2/3 PRM module functions
 *
 * Copyright (C) 2010-2011 Texas Instruments, Inc.
 * Copyright (C) 2010 Nokia Corporation
 * Benoît Cousson
 * Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/irq.h>

#include <plat/prcm.h>

#include "soc.h"
#include "common.h"
#include "vp.h"

#include "prm2xxx_3xxx.h"
#include "cm2xxx_3xxx.h"
#include "prm-regbits-24xx.h"
#include "prm-regbits-34xx.h"

static const struct omap_prcm_irq omap3_prcm_irqs[] = {
    OMAP_PRCM_IRQ("wkup",   0,  0),
    OMAP_PRCM_IRQ("io", 9,  1),
};

static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
    .ack            = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
    .mask           = OMAP3_PRM_IRQENABLE_MPU_OFFSET,
    .nr_regs        = 1,
    .irqs           = omap3_prcm_irqs,
    .nr_irqs        = ARRAY_SIZE(omap3_prcm_irqs),
    .irq            = 11 + OMAP_INTC_START,
    .read_pending_irqs  = &omap3xxx_prm_read_pending_irqs,
    .ocp_barrier        = &omap3xxx_prm_ocp_barrier,
    .save_and_clear_irqen   = &omap3xxx_prm_save_and_clear_irqen,
    .restore_irqen      = &omap3xxx_prm_restore_irqen,
};

u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
{
    return __raw_readl(prm_base + module + idx);
}

void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
{
    __raw_writel(val, prm_base + module + idx);
}

/* Read-modify-write a register in a PRM module. Caller must lock */
u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
{
    u32 v;

    v = omap2_prm_read_mod_reg(module, idx);
    v &= ~mask;
    v |= bits;
    omap2_prm_write_mod_reg(v, module, idx);

    return v;
}

/* Read a PRM register, AND it, and shift the result down to bit 0 */
u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
{
    u32 v;

    v = omap2_prm_read_mod_reg(domain, idx);
    v &= mask;
    v >>= __ffs(mask);

    return v;
}

u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
{
    return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx);
}

u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
{
    return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
}


int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
{
    if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
        return -EINVAL;

    return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL,
                       (1 << shift));
}

int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
{
    u32 mask;

    if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
        return -EINVAL;

    mask = 1 << shift;
    omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL);

    return 0;
}

int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift)
{
    u32 rst, st;
    int c;

    if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
        return -EINVAL;

    rst = 1 << rst_shift;
    st = 1 << st_shift;

    /* Check the current status to avoid de-asserting the line twice */
    if (omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, rst) == 0)
        return -EEXIST;

    /* Clear the reset status by writing 1 to the status bit */
    omap2_prm_rmw_mod_reg_bits(0xffffffff, st, prm_mod, OMAP2_RM_RSTST);
    /* de-assert the reset control line */
    omap2_prm_rmw_mod_reg_bits(rst, 0, prm_mod, OMAP2_RM_RSTCTRL);
    /* wait the status to be set */
    omap_test_timeout(omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST,
                          st),
              MAX_MODULE_HARDRESET_WAIT, c);

    return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
}

/* PRM VP */

/*
 * struct omap3_vp - OMAP3 VP register access description.
 * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
 */
struct omap3_vp {
    u32 tranxdone_status;
};

static struct omap3_vp omap3_vp[] = {
    [OMAP3_VP_VDD_MPU_ID] = {
        .tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
    },
    [OMAP3_VP_VDD_CORE_ID] = {
        .tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
    },
};

#define MAX_VP_ID ARRAY_SIZE(omap3_vp);

u32 omap3_prm_vp_check_txdone(u8 vp_id)
{
    struct omap3_vp *vp = &omap3_vp[vp_id];
    u32 irqstatus;

    irqstatus = omap2_prm_read_mod_reg(OCP_MOD,
                       OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
    return irqstatus & vp->tranxdone_status;
}

void omap3_prm_vp_clear_txdone(u8 vp_id)
{
    struct omap3_vp *vp = &omap3_vp[vp_id];

    omap2_prm_write_mod_reg(vp->tranxdone_status,
                OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
}

u32 omap3_prm_vcvp_read(u8 offset)
{
    return omap2_prm_read_mod_reg(OMAP3430_GR_MOD, offset);
}

void omap3_prm_vcvp_write(u32 val, u8 offset)
{
    omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset);
}

u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
{
    return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset);
}

void omap3xxx_prm_read_pending_irqs(unsigned long *events)
{
    u32 mask, st;

    /* XXX Can the mask read be avoided (e.g., can it come from RAM?) */
    mask = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
    st = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);

    events[0] = mask & st;
}

void omap3xxx_prm_ocp_barrier(void)
{
    omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
}

void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask)
{
    saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD,
                           OMAP3_PRM_IRQENABLE_MPU_OFFSET);
    omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);

    /* OCP barrier */
    omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
}

void omap3xxx_prm_restore_irqen(u32 *saved_mask)
{
    omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD,
                OMAP3_PRM_IRQENABLE_MPU_OFFSET);
}

void omap3xxx_prm_reconfigure_io_chain(void)
{
    int i = 0;

    omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
                   PM_WKEN);

    omap_test_timeout(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
              OMAP3430_ST_IO_CHAIN_MASK,
              MAX_IOPAD_LATCH_TIME, i);
    if (i == MAX_IOPAD_LATCH_TIME)
        pr_warn("PRM: I/O chain clock line assertion timed out\n");

    omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
                     PM_WKEN);

    omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD,
                   PM_WKST);

    omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST);
}

static void __init omap3xxx_prm_enable_io_wakeup(void)
{
    if (omap3_has_io_wakeup())
        omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
                       PM_WKEN);
}

static int __init omap3xxx_prcm_init(void)
{
    int ret = 0;

    if (cpu_is_omap34xx()) {
        omap3xxx_prm_enable_io_wakeup();
        ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
        if (!ret)
            irq_set_status_flags(omap_prcm_event_to_irq("io"),
                         IRQ_NOAUTOEN);
    }

    return ret;
}
subsys_initcall(omap3xxx_prcm_init);