#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/initval.h>
#include <sound/soc.h>
#include <sound/pxa2xx-lib.h>
#include <mach/hardware.h>
#include <mach/dma.h>
#include <mach/audio.h>
#include "pxa2xx-i2s.h"

Data Structures
struct	pxa_i2s_port

Macros
#define	SACR0 __REG(0x40400000) /* Global Control Register */

#define	SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */

#define	SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */

#define	SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */

#define	SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */

#define	SADIV __REG(0x40400060) /* Audio Clock Divider Register. */

#define	SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */

#define	SACR0_RFTH(x) ((x) << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */

#define	SACR0_TFTH(x) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */

#define	SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */

#define	SACR0_EFWR (1 << 4) /* Enable EFWR Function */

#define	SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */

#define	SACR0_BCKD (1 << 2) /* Bit Clock Direction */

#define	SACR0_ENB (1 << 0) /* Enable I2S Link */

#define	SACR1_ENLBF (1 << 5) /* Enable Loopback */

#define	SACR1_DRPL (1 << 4) /* Disable Replaying Function */

#define	SACR1_DREC (1 << 3) /* Disable Recording Function */

#define	SACR1_AMSL (1 << 0) /* Specify Alternate Mode */

#define	SASR0_I2SOFF (1 << 7) /* Controller Status */

#define	SASR0_ROR (1 << 6) /* Rx FIFO Overrun */

#define	SASR0_TUR (1 << 5) /* Tx FIFO Underrun */

#define	SASR0_RFS (1 << 4) /* Rx FIFO Service Request */

#define	SASR0_TFS (1 << 3) /* Tx FIFO Service Request */

#define	SASR0_BSY (1 << 2) /* I2S Busy */

#define	SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */

#define	SASR0_TNF (1 << 0) /* Tx FIFO Not Empty */

#define	SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */

#define	SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */

#define	SAIMR_ROR (1 << 6) /* Enable Rx FIFO Overrun Condition Interrupt */

#define	SAIMR_TUR (1 << 5) /* Enable Tx FIFO Underrun Condition Interrupt */

#define	SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */

#define	SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */

#define	pxa2xx_i2s_suspend NULL

#define	pxa2xx_i2s_resume NULL

#define	PXA2XX_I2S_RATES

Functions
	module_init (pxa2xx_i2s_init)

	module_exit (pxa2xx_i2s_exit)

	MODULE_AUTHOR ("Liam Girdwood, [email protected]")

	MODULE_DESCRIPTION ("pxa2xx I2S SoC Interface")

	MODULE_LICENSE ("GPL")

	MODULE_ALIAS ("platform:pxa2xx-i2s")

Macro Definition Documentation

#define PXA2XX_I2S_RATES

Value:

(SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
        SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
        SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)

Definition at line 331 of file pxa2xx-i2s.c.

#define pxa2xx_i2s_resume NULL

Definition at line 299 of file pxa2xx-i2s.c.

#define pxa2xx_i2s_suspend NULL

Definition at line 298 of file pxa2xx-i2s.c.

#define SACR0 __REG(0x40400000) /* Global Control Register */

Definition at line 36 of file pxa2xx-i2s.c.

#define SACR0_BCKD (1 << 2) /* Bit Clock Direction */

Definition at line 49 of file pxa2xx-i2s.c.

#define SACR0_EFWR (1 << 4) /* Enable EFWR Function */

Definition at line 47 of file pxa2xx-i2s.c.

#define SACR0_ENB (1 << 0) /* Enable I2S Link */

Definition at line 50 of file pxa2xx-i2s.c.

#define SACR0_RFTH ( x ) ((x) << 12) /* Rx FIFO Interrupt or DMA Trigger Threshold */

Definition at line 44 of file pxa2xx-i2s.c.

#define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */

Definition at line 48 of file pxa2xx-i2s.c.

#define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */

Definition at line 46 of file pxa2xx-i2s.c.

#define SACR0_TFTH ( x ) ((x) << 8) /* Tx FIFO Interrupt or DMA Trigger Threshold */

Definition at line 45 of file pxa2xx-i2s.c.

#define SACR1 __REG(0x40400004) /* Serial Audio I 2 S/MSB-Justified Control Register */

Definition at line 37 of file pxa2xx-i2s.c.

#define SACR1_AMSL (1 << 0) /* Specify Alternate Mode */

Definition at line 54 of file pxa2xx-i2s.c.

#define SACR1_DREC (1 << 3) /* Disable Recording Function */

Definition at line 53 of file pxa2xx-i2s.c.

#define SACR1_DRPL (1 << 4) /* Disable Replaying Function */

Definition at line 52 of file pxa2xx-i2s.c.

#define SACR1_ENLBF (1 << 5) /* Enable Loopback */

Definition at line 51 of file pxa2xx-i2s.c.

#define SADIV __REG(0x40400060) /* Audio Clock Divider Register. */

Definition at line 41 of file pxa2xx-i2s.c.

#define SADR __REG(0x40400080) /* Serial Audio Data Register (TX and RX FIFO access Register). */

Definition at line 42 of file pxa2xx-i2s.c.

#define SAICR __REG(0x40400018) /* Serial Audio Interrupt Clear Register */

Definition at line 40 of file pxa2xx-i2s.c.

#define SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */

Definition at line 65 of file pxa2xx-i2s.c.

#define SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */

Definition at line 66 of file pxa2xx-i2s.c.

#define SAIMR __REG(0x40400014) /* Serial Audio Interrupt Mask Register */

Definition at line 39 of file pxa2xx-i2s.c.

#define SAIMR_RFS (1 << 4) /* Enable Rx FIFO Service Interrupt */

Definition at line 70 of file pxa2xx-i2s.c.

#define SAIMR_ROR (1 << 6) /* Enable Rx FIFO Overrun Condition Interrupt */

Definition at line 68 of file pxa2xx-i2s.c.

#define SAIMR_TFS (1 << 3) /* Enable Tx FIFO Service Interrupt */

Definition at line 71 of file pxa2xx-i2s.c.

#define SAIMR_TUR (1 << 5) /* Enable Tx FIFO Underrun Condition Interrupt */

Definition at line 69 of file pxa2xx-i2s.c.

#define SASR0 __REG(0x4040000C) /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */

Definition at line 38 of file pxa2xx-i2s.c.

#define SASR0_BSY (1 << 2) /* I2S Busy */

Definition at line 61 of file pxa2xx-i2s.c.

#define SASR0_I2SOFF (1 << 7) /* Controller Status */

Definition at line 56 of file pxa2xx-i2s.c.

#define SASR0_RFS (1 << 4) /* Rx FIFO Service Request */

Definition at line 59 of file pxa2xx-i2s.c.

#define SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */

Definition at line 62 of file pxa2xx-i2s.c.

#define SASR0_ROR (1 << 6) /* Rx FIFO Overrun */

Definition at line 57 of file pxa2xx-i2s.c.

#define SASR0_TFS (1 << 3) /* Tx FIFO Service Request */

Definition at line 60 of file pxa2xx-i2s.c.

#define SASR0_TNF (1 << 0) /* Tx FIFO Not Empty */

Definition at line 63 of file pxa2xx-i2s.c.

#define SASR0_TUR (1 << 5) /* Tx FIFO Underrun */

Definition at line 58 of file pxa2xx-i2s.c.

Function Documentation

MODULE_ALIAS ( "platform:pxa2xx-i2s" )

MODULE_AUTHOR	(	"Liam	Girdwood,
		lrg @slimlogic.co.uk"
	)

MODULE_DESCRIPTION ( "pxa2xx I2S SoC Interface" )

module_exit ( pxa2xx_i2s_exit )

module_init ( pxa2xx_i2s_init )

MODULE_LICENSE ( "GPL" )

Data Structures

Macros

Functions

Macro Definition Documentation

Function Documentation