#include <linux/init.h>
#include <linux/module.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/errno.h>
#include <linux/fs.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/moduleparam.h>
#include <linux/time.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <media/v4l2-common.h>
#include <media/v4l2-dev.h>
#include <media/videobuf-dma-sg.h>
#include <media/soc_camera.h>
#include <media/soc_mediabus.h>
#include <linux/videodev2.h>
#include <mach/dma.h>
#include <linux/platform_data/camera-pxa.h>

Data Structures
struct	pxa_cam_dma

struct	pxa_buffer

struct	pxa_camera_dev

struct	pxa_cam

Macros
#define	PXA_CAM_VERSION "0.0.6"

#define	PXA_CAM_DRV_NAME "pxa27x-camera"

#define	CICR0 0x0000

#define	CICR1 0x0004

#define	CICR2 0x0008

#define	CICR3 0x000C

#define	CICR4 0x0010

#define	CISR 0x0014

#define	CIFR 0x0018

#define	CITOR 0x001C

#define	CIBR0 0x0028

#define	CIBR1 0x0030

#define	CIBR2 0x0038

#define	CICR0_DMAEN (1 << 31) /* DMA request enable */

#define	CICR0_PAR_EN (1 << 30) /* Parity enable */

#define	CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */

#define	CICR0_ENB (1 << 28) /* Camera interface enable */

#define	CICR0_DIS (1 << 27) /* Camera interface disable */

#define	CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */

#define	CICR0_TOM (1 << 9) /* Time-out mask */

#define	CICR0_RDAVM (1 << 8) /* Receive-data-available mask */

#define	CICR0_FEM (1 << 7) /* FIFO-empty mask */

#define	CICR0_EOLM (1 << 6) /* End-of-line mask */

#define	CICR0_PERRM (1 << 5) /* Parity-error mask */

#define	CICR0_QDM (1 << 4) /* Quick-disable mask */

#define	CICR0_CDM (1 << 3) /* Disable-done mask */

#define	CICR0_SOFM (1 << 2) /* Start-of-frame mask */

#define	CICR0_EOFM (1 << 1) /* End-of-frame mask */

#define	CICR0_FOM (1 << 0) /* FIFO-overrun mask */

#define	CICR1_TBIT (1 << 31) /* Transparency bit */

#define	CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */

#define	CICR1_PPL (0x7ff << 15) /* Pixels per line mask */

#define	CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */

#define	CICR1_RGB_F (1 << 11) /* RGB format */

#define	CICR1_YCBCR_F (1 << 10) /* YCbCr format */

#define	CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */

#define	CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */

#define	CICR1_COLOR_SP (0x3 << 3) /* Color space mask */

#define	CICR1_DW (0x7 << 0) /* Data width mask */

#define	CICR2_BLW

#define	CICR2_ELW

#define	CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */

#define	CICR2_BFPW

#define	CICR2_FSW

#define	CICR3_BFW

#define	CICR3_EFW

#define	CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */

#define	CICR3_BFPW

#define	CICR3_LPF (0x7ff << 0) /* Lines per frame mask */

#define	CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */

#define	CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */

#define	CICR4_PCP (1 << 22) /* Pixel clock polarity */

#define	CICR4_HSP (1 << 21) /* Horizontal sync polarity */

#define	CICR4_VSP (1 << 20) /* Vertical sync polarity */

#define	CICR4_MCLK_EN (1 << 19) /* MCLK enable */

#define	CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */

#define	CICR4_DIV (0xff << 0) /* Clock divisor mask */

#define	CISR_FTO (1 << 15) /* FIFO time-out */

#define	CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */

#define	CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */

#define	CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */

#define	CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */

#define	CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */

#define	CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */

#define	CISR_EOL (1 << 8) /* End of line */

#define	CISR_PAR_ERR (1 << 7) /* Parity error */

#define	CISR_CQD (1 << 6) /* Camera interface quick disable */

#define	CISR_CDD (1 << 5) /* Camera interface disable done */

#define	CISR_SOF (1 << 4) /* Start of frame */

#define	CISR_EOF (1 << 3) /* End of frame */

#define	CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */

#define	CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */

#define	CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */

#define	CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */

#define	CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */

#define	CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */

#define	CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */

#define	CIFR_RESET_F (1 << 3) /* Reset input FIFOs */

#define	CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */

#define	CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */

#define	CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */

#define	CICR0_SIM_MP (0 << 24)

#define	CICR0_SIM_SP (1 << 24)

#define	CICR0_SIM_MS (2 << 24)

#define	CICR0_SIM_EP (3 << 24)

#define	CICR0_SIM_ES (4 << 24)

#define	CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */

#define	CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */

#define	CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */

#define	CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */

#define	CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */

#define	CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */

#define	CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */

#define	CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */

#define	CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */

#define	CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */

#define	CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */

#define	CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */

#define	CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */

#define	CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */

#define	CICR0_IRQ_MASK

Enumerations
enum	pxa_camera_active_dma { DMA_Y = 0x1, DMA_U = 0x2, DMA_V = 0x4 }

Functions
	module_platform_driver (pxa_camera_driver)

	MODULE_DESCRIPTION ("PXA27x SoC Camera Host driver")

	MODULE_AUTHOR ("Guennadi Liakhovetski <[email protected]>")

	MODULE_LICENSE ("GPL")

	MODULE_VERSION (PXA_CAM_VERSION)

	MODULE_ALIAS ("platform:"PXA_CAM_DRV_NAME)

Macro Definition Documentation

#define CIBR0 0x0028

Definition at line 54 of file pxa_camera.c.

#define CIBR1 0x0030

Definition at line 55 of file pxa_camera.c.

#define CIBR2 0x0038

Definition at line 56 of file pxa_camera.c.

#define CICR0 0x0000

Definition at line 46 of file pxa_camera.c.

#define CICR0_CDM (1 << 3) /* Disable-done mask */

Definition at line 70 of file pxa_camera.c.

#define CICR0_DIS (1 << 27) /* Camera interface disable */

Definition at line 62 of file pxa_camera.c.

#define CICR0_DMAEN (1 << 31) /* DMA request enable */

Definition at line 58 of file pxa_camera.c.

#define CICR0_ENB (1 << 28) /* Camera interface enable */

Definition at line 61 of file pxa_camera.c.

#define CICR0_EOFM (1 << 1) /* End-of-frame mask */

Definition at line 72 of file pxa_camera.c.

#define CICR0_EOLM (1 << 6) /* End-of-line mask */

Definition at line 67 of file pxa_camera.c.

#define CICR0_FEM (1 << 7) /* FIFO-empty mask */

Definition at line 66 of file pxa_camera.c.

#define CICR0_FOM (1 << 0) /* FIFO-overrun mask */

Definition at line 73 of file pxa_camera.c.

#define CICR0_IRQ_MASK

Value:

(CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
            CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
            CICR0_EOFM | CICR0_FOM)

Definition at line 156 of file pxa_camera.c.

#define CICR0_PAR_EN (1 << 30) /* Parity enable */

Definition at line 59 of file pxa_camera.c.

#define CICR0_PERRM (1 << 5) /* Parity-error mask */

Definition at line 68 of file pxa_camera.c.

#define CICR0_QDM (1 << 4) /* Quick-disable mask */

Definition at line 69 of file pxa_camera.c.

#define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */

Definition at line 65 of file pxa_camera.c.

#define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */

Definition at line 63 of file pxa_camera.c.

#define CICR0_SIM_EP (3 << 24)

Definition at line 136 of file pxa_camera.c.

#define CICR0_SIM_ES (4 << 24)

Definition at line 137 of file pxa_camera.c.

#define CICR0_SIM_MP (0 << 24)

Definition at line 133 of file pxa_camera.c.

#define CICR0_SIM_MS (2 << 24)

Definition at line 135 of file pxa_camera.c.

#define CICR0_SIM_SP (1 << 24)

Definition at line 134 of file pxa_camera.c.

#define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */

Definition at line 60 of file pxa_camera.c.

#define CICR0_SOFM (1 << 2) /* Start-of-frame mask */

Definition at line 71 of file pxa_camera.c.

#define CICR0_TOM (1 << 9) /* Time-out mask */

Definition at line 64 of file pxa_camera.c.

#define CICR1 0x0004

Definition at line 47 of file pxa_camera.c.

#define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */

Definition at line 83 of file pxa_camera.c.

#define CICR1_COLOR_SP_VAL ( x ) (((x) << 3) & CICR1_COLOR_SP) /* color space */

Definition at line 141 of file pxa_camera.c.

#define CICR1_DW (0x7 << 0) /* Data width mask */

Definition at line 84 of file pxa_camera.c.

#define CICR1_DW_VAL ( x ) ((x) & CICR1_DW) /* Data bus width */

Definition at line 139 of file pxa_camera.c.

#define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */

Definition at line 77 of file pxa_camera.c.

#define CICR1_PPL_VAL ( x ) (((x) << 15) & CICR1_PPL) /* Pixels per line */

Definition at line 140 of file pxa_camera.c.

#define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */

Definition at line 82 of file pxa_camera.c.

#define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */

Definition at line 81 of file pxa_camera.c.

#define CICR1_RGB_BPP_VAL ( x ) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */

Definition at line 142 of file pxa_camera.c.

#define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */

Definition at line 78 of file pxa_camera.c.

#define CICR1_RGB_F (1 << 11) /* RGB format */

Definition at line 79 of file pxa_camera.c.

#define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */

Definition at line 76 of file pxa_camera.c.

#define CICR1_RGBT_CONV_VAL ( x ) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */

Definition at line 143 of file pxa_camera.c.

#define CICR1_TBIT (1 << 31) /* Transparency bit */

Definition at line 75 of file pxa_camera.c.

#define CICR1_YCBCR_F (1 << 10) /* YCbCr format */

Definition at line 80 of file pxa_camera.c.

#define CICR2 0x0008

Definition at line 48 of file pxa_camera.c.

#define CICR2_BFPW

Value:

(0x3f << 3) /* Beginning-of-frame pixel clock

wait count mask */

Definition at line 89 of file pxa_camera.c.

#define CICR2_BFPW_VAL ( x ) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */

Definition at line 148 of file pxa_camera.c.

#define CICR2_BLW

Value:

(0xff << 24) /* Beginning-of-line pixel clock

wait count mask */

Definition at line 86 of file pxa_camera.c.

#define CICR2_BLW_VAL ( x ) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */

Definition at line 145 of file pxa_camera.c.

#define CICR2_ELW

Value:

(0xff << 16) /* End-of-line pixel clock

wait count mask */

Definition at line 87 of file pxa_camera.c.

#define CICR2_ELW_VAL ( x ) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */

Definition at line 146 of file pxa_camera.c.

#define CICR2_FSW

Value:

(0x7 << 0) /* Frame stabilization

wait count mask */

Definition at line 90 of file pxa_camera.c.

#define CICR2_FSW_VAL ( x ) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */

Definition at line 149 of file pxa_camera.c.

#define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */

Definition at line 88 of file pxa_camera.c.

#define CICR2_HSW_VAL ( x ) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */

Definition at line 147 of file pxa_camera.c.

#define CICR3 0x000C

Definition at line 49 of file pxa_camera.c.

#define CICR3_BFPW

Value:

(0x3f << 3) /* Beginning-of-frame pixel clock

wait count mask */

Definition at line 95 of file pxa_camera.c.

#define CICR3_BFW

Value:

(0xff << 24) /* Beginning-of-frame line clock

wait count mask */

Definition at line 92 of file pxa_camera.c.

#define CICR3_BFW_VAL ( x ) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */

Definition at line 151 of file pxa_camera.c.

#define CICR3_EFW

Value:

(0xff << 16) /* End-of-frame line clock

wait count mask */

Definition at line 93 of file pxa_camera.c.

#define CICR3_EFW_VAL ( x ) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */

Definition at line 152 of file pxa_camera.c.

#define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */

Definition at line 96 of file pxa_camera.c.

#define CICR3_LPF_VAL ( x ) (((x) << 0) & CICR3_LPF) /* Lines per frame */

Definition at line 154 of file pxa_camera.c.

#define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */

Definition at line 94 of file pxa_camera.c.

#define CICR3_VSW_VAL ( x ) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */

Definition at line 153 of file pxa_camera.c.

#define CICR4 0x0010

Definition at line 50 of file pxa_camera.c.

#define CICR4_DIV (0xff << 0) /* Clock divisor mask */

Definition at line 105 of file pxa_camera.c.

#define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */

Definition at line 104 of file pxa_camera.c.

#define CICR4_HSP (1 << 21) /* Horizontal sync polarity */

Definition at line 101 of file pxa_camera.c.

#define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */

Definition at line 98 of file pxa_camera.c.

#define CICR4_MCLK_EN (1 << 19) /* MCLK enable */

Definition at line 103 of file pxa_camera.c.

#define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */

Definition at line 99 of file pxa_camera.c.

#define CICR4_PCP (1 << 22) /* Pixel clock polarity */

Definition at line 100 of file pxa_camera.c.

#define CICR4_VSP (1 << 20) /* Vertical sync polarity */

Definition at line 102 of file pxa_camera.c.

#define CIFR 0x0018

Definition at line 52 of file pxa_camera.c.

#define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */

Definition at line 131 of file pxa_camera.c.

#define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */

Definition at line 130 of file pxa_camera.c.

#define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */

Definition at line 129 of file pxa_camera.c.

#define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */

Definition at line 126 of file pxa_camera.c.

#define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */

Definition at line 125 of file pxa_camera.c.

#define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */

Definition at line 124 of file pxa_camera.c.

#define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */

Definition at line 128 of file pxa_camera.c.

#define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */

Definition at line 127 of file pxa_camera.c.

#define CISR 0x0014

Definition at line 51 of file pxa_camera.c.

#define CISR_CDD (1 << 5) /* Camera interface disable done */

Definition at line 117 of file pxa_camera.c.

#define CISR_CQD (1 << 6) /* Camera interface quick disable */

Definition at line 116 of file pxa_camera.c.

#define CISR_EOF (1 << 3) /* End of frame */

Definition at line 119 of file pxa_camera.c.

#define CISR_EOL (1 << 8) /* End of line */

Definition at line 114 of file pxa_camera.c.

#define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */

Definition at line 113 of file pxa_camera.c.

#define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */

Definition at line 112 of file pxa_camera.c.

#define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */

Definition at line 111 of file pxa_camera.c.

#define CISR_FTO (1 << 15) /* FIFO time-out */

Definition at line 107 of file pxa_camera.c.

#define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */

Definition at line 122 of file pxa_camera.c.

#define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */

Definition at line 121 of file pxa_camera.c.

#define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */

Definition at line 120 of file pxa_camera.c.

#define CISR_PAR_ERR (1 << 7) /* Parity error */

Definition at line 115 of file pxa_camera.c.

#define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */

Definition at line 110 of file pxa_camera.c.

#define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */

Definition at line 109 of file pxa_camera.c.

#define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */

Definition at line 108 of file pxa_camera.c.

#define CISR_SOF (1 << 4) /* Start of frame */

Definition at line 118 of file pxa_camera.c.

#define CITOR 0x001C

Definition at line 53 of file pxa_camera.c.

#define PXA_CAM_DRV_NAME "pxa27x-camera"

Definition at line 43 of file pxa_camera.c.

#define PXA_CAM_VERSION "0.0.6"

Definition at line 42 of file pxa_camera.c.

Enumeration Type Documentation

enum pxa_camera_active_dma

Enumerator:

DMA_Y
DMA_U
DMA_V

Definition at line 163 of file pxa_camera.c.

Function Documentation

MODULE_ALIAS ( "platform:" PXA_CAM_DRV_NAME )

MODULE_AUTHOR ( "Guennadi Liakhovetski <[email protected]>" )

MODULE_DESCRIPTION ( "PXA27x SoC Camera Host driver" )

MODULE_LICENSE ( "GPL" )

module_platform_driver ( pxa_camera_driver )

MODULE_VERSION ( PXA_CAM_VERSION )

Data Structures

Macros

Enumerations

Functions

Macro Definition Documentation

Enumeration Type Documentation

Function Documentation