qib_wc_x86_64.c File Reference

#include <linux/pci.h>
#include <asm/mtrr.h>
#include <asm/processor.h>
#include "qib.h"

Go to the source code of this file.

Functions
int	qib_enable_wc (struct qib_devdata *dd)
void	qib_disable_wc (struct qib_devdata *dd)
int	qib_unordered_wc (void)

Function Documentation

void qib_disable_wc

(

struct qib_devdata *

dd

)

qib_disable_wc - disable write combining for MMIO writes to the device : qlogic_ib device

Definition at line 142 of file qib_wc_x86_64.c.

int qib_enable_wc

(

struct qib_devdata *

dd

)

qib_enable_wc - enable write combining for MMIO writes to the device : qlogic_ib device

This routine is x86_64-specific; it twiddles the CPU's MTRRs to enable write combining.

Definition at line 53 of file qib_wc_x86_64.c.

int qib_unordered_wc

(

void

)

qib_unordered_wc - indicate whether write combining is ordered

Because our performance depends on our ability to do write combining mmio writes in the most efficient way, we need to know if we are on an Intel or AMD x86_64 processor. AMD x86_64 processors flush WC buffers out in the order completed, and so no special flushing is required to get correct ordering. Intel processors, however, will flush write buffers out in "random" orders, and so explicit ordering is needed at times.

Definition at line 168 of file qib_wc_x86_64.c.