Linux Kernel
3.7.1
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Go to the source code of this file.
Data Structures | |
struct | port_ctrl_stat_regs |
struct | host_mem_cfg_regs |
struct | device_reg_82xx |
struct | device_reg_83xx |
struct | isp_reg |
struct | shadow_regs |
union | external_hw_config_reg |
struct | qla_fdt_layout |
struct | qla_flt_location |
struct | qla_flt_header |
struct | qla_flt_region |
struct | addr_ctrl_blk |
struct | init_fw_ctrl_blk |
struct | addr_ctrl_blk_def |
struct | ql4_chap_table |
struct | dev_db_entry |
struct | sys_info_phys_addr |
struct | flash_sys_info |
struct | mbx_sys_info |
struct | about_fw_info |
struct | crash_record |
struct | conn_event_log_entry |
struct | qla4_header |
struct | queue_entry |
struct | data_seg_a64 |
struct | command_t3_entry |
struct | continuation_t1_entry |
struct | qla4_marker_entry |
struct | status_entry |
struct | status_cont_entry |
struct | passthru0 |
struct | passthru_status |
struct | mbox_cmd_iocb |
struct | mbox_status_iocb |
struct | response |
struct | ql_iscsi_stats |
struct | qla4_8xxx_minidump_template_hdr |
Variables | |
__le32 | nvram |
__le32 | reserved1 [2] |
__le32 | intr_mask |
__le32 | semaphore |
__le32 | ext_hw_conf |
__le32 | flow_ctrl |
__le32 | port_ctrl |
__le32 | port_status |
__le32 | reserved3 [8] |
__le32 | req_q_out |
__le32 | reserved4 [23] |
__le32 | gp_out |
__le32 | gp_in |
__le32 | reserved5 [5] |
__le32 | port_err_status |
union { | |
struct port_ctrl_stat_regs p0 | |
struct host_mem_cfg_regs p1 | |
}; | |
#define ACB_SUPPORTED |
#define COMMAND_SEG COMMAND_SEG_A64 |
#define CONTINUE_SEG CONTINUE_SEG_A64 |
#define DDB_OPT_IPV6_FW_DEFINED_LINK_LOCAL 0x800 /* pre connection */ |
#define DDB_OPT_IPV6_NULL_LINK_LOCAL 0x800 /* post connection */ |
#define ET_COMMAND ET_CMND_T3 |
#define ET_CONTINUE ET_CONT_T1 |
#define FLASH_EOF_OFFSET |
#define FLASH_OFFSET_DB_END (FLASH_OFFSET_DB_INFO + 0x7fff) |
#define INTR_PENDING |
#define IP_ADDR_COUNT |
#define IPV6_ADDOPT_NEIGHBOR_DISCOVERY_ADDR_ENABLE |
#define ISP_CONTROL_FN_MASK CSR_FUNC_NUM |
#define MIN_DISC_DEV_DB_ENTRY MAX_PRST_DEV_DB_ENTRIES |
#define QL4022_DDR_RAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (4+16)) |
#define QL4022_DRVR_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (1+16)) |
#define QL4022_FLASH_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (13+16)) |
#define QL4022_NVRAM_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (10+16)) |
#define QL4022_PHY_GIO_SEM_MASK (QL4022_RESOURCE_MASK_BASE_CODE << (7+16)) |
union { ... } |