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ql4_fw.h File Reference

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Data Structures

struct  port_ctrl_stat_regs
 
struct  host_mem_cfg_regs
 
struct  device_reg_82xx
 
struct  device_reg_83xx
 
struct  isp_reg
 
struct  shadow_regs
 
union  external_hw_config_reg
 
struct  qla_fdt_layout
 
struct  qla_flt_location
 
struct  qla_flt_header
 
struct  qla_flt_region
 
struct  addr_ctrl_blk
 
struct  init_fw_ctrl_blk
 
struct  addr_ctrl_blk_def
 
struct  ql4_chap_table
 
struct  dev_db_entry
 
struct  sys_info_phys_addr
 
struct  flash_sys_info
 
struct  mbx_sys_info
 
struct  about_fw_info
 
struct  crash_record
 
struct  conn_event_log_entry
 
struct  qla4_header
 
struct  queue_entry
 
struct  data_seg_a64
 
struct  command_t3_entry
 
struct  continuation_t1_entry
 
struct  qla4_marker_entry
 
struct  status_entry
 
struct  status_cont_entry
 
struct  passthru0
 
struct  passthru_status
 
struct  mbox_cmd_iocb
 
struct  mbox_status_iocb
 
struct  response
 
struct  ql_iscsi_stats
 
struct  qla4_8xxx_minidump_template_hdr
 

Macros

#define MAX_PRST_DEV_DB_ENTRIES   64
 
#define MIN_DISC_DEV_DB_ENTRY   MAX_PRST_DEV_DB_ENTRIES
 
#define MAX_DEV_DB_ENTRIES   512
 
#define MAX_DEV_DB_ENTRIES_40XX   256
 
#define HINT_MBX_INT_PENDING   BIT_0
 
#define HSRX_RISC_MB_INT   BIT_0 /* RISC to Host Mailbox interrupt */
 
#define HSRX_RISC_IOCB_INT   BIT_1 /* RISC to Host IOCB interrupt */
 
#define ISRX_82XX_RISC_INT   BIT_0 /* RISC interrupt. */
 
#define INT_ENABLE_FW_MB   (1 << 2)
 
#define INT_MASK_FW_MB   (1 << 2)
 
#define MBOX_REG_COUNT   8
 
#define QL4010_DRVR_SEM_BITS   0x00000030
 
#define QL4010_GPIO_SEM_BITS   0x000000c0
 
#define QL4010_SDRAM_SEM_BITS   0x00000300
 
#define QL4010_PHY_SEM_BITS   0x00000c00
 
#define QL4010_NVRAM_SEM_BITS   0x00003000
 
#define QL4010_FLASH_SEM_BITS   0x0000c000
 
#define QL4010_DRVR_SEM_MASK   0x00300000
 
#define QL4010_GPIO_SEM_MASK   0x00c00000
 
#define QL4010_SDRAM_SEM_MASK   0x03000000
 
#define QL4010_PHY_SEM_MASK   0x0c000000
 
#define QL4010_NVRAM_SEM_MASK   0x30000000
 
#define QL4010_FLASH_SEM_MASK   0xc0000000
 
#define QL4022_RESOURCE_MASK_BASE_CODE   0x7
 
#define QL4022_RESOURCE_BITS_BASE_CODE   0x4
 
#define QL4022_DRVR_SEM_MASK   (QL4022_RESOURCE_MASK_BASE_CODE << (1+16))
 
#define QL4022_DDR_RAM_SEM_MASK   (QL4022_RESOURCE_MASK_BASE_CODE << (4+16))
 
#define QL4022_PHY_GIO_SEM_MASK   (QL4022_RESOURCE_MASK_BASE_CODE << (7+16))
 
#define QL4022_NVRAM_SEM_MASK   (QL4022_RESOURCE_MASK_BASE_CODE << (10+16))
 
#define QL4022_FLASH_SEM_MASK   (QL4022_RESOURCE_MASK_BASE_CODE << (13+16))
 
#define NVRAM_PORT0_BOOT_MODE   0x03b1
 
#define NVRAM_PORT0_BOOT_PRI_TGT   0x03b2
 
#define NVRAM_PORT0_BOOT_SEC_TGT   0x03bb
 
#define NVRAM_PORT1_BOOT_MODE   0x07b1
 
#define NVRAM_PORT1_BOOT_PRI_TGT   0x07b2
 
#define NVRAM_PORT1_BOOT_SEC_TGT   0x07bb
 
#define PORT_CTRL_STAT_PAGE   0 /* 4022 */
 
#define HOST_MEM_CFG_PAGE   1 /* 4022 */
 
#define LOCAL_RAM_CFG_PAGE   2 /* 4022 */
 
#define PROT_STAT_PAGE   3 /* 4022 */
 
#define CSR_SCSI_PAGE_SELECT   0x00000003
 
#define CSR_SCSI_INTR_ENABLE   0x00000004 /* 4010 */
 
#define CSR_SCSI_RESET_INTR   0x00000008
 
#define CSR_SCSI_COMPLETION_INTR   0x00000010
 
#define CSR_SCSI_PROCESSOR_INTR   0x00000020
 
#define CSR_INTR_RISC   0x00000040
 
#define CSR_BOOT_ENABLE   0x00000080
 
#define CSR_NET_PAGE_SELECT   0x00000300 /* 4010 */
 
#define CSR_FUNC_NUM   0x00000700 /* 4022 */
 
#define CSR_NET_RESET_INTR   0x00000800 /* 4010 */
 
#define CSR_FORCE_SOFT_RESET   0x00002000 /* 4022 */
 
#define CSR_FATAL_ERROR   0x00004000
 
#define CSR_SOFT_RESET   0x00008000
 
#define ISP_CONTROL_FN_MASK   CSR_FUNC_NUM
 
#define ISP_CONTROL_FN0_SCSI   0x0500
 
#define ISP_CONTROL_FN1_SCSI   0x0700
 
#define INTR_PENDING
 
#define IMR_SCSI_INTR_ENABLE   0x00000004 /* 4022 */
 
#define NVR_WRITE_ENABLE   0x00000010 /* 4022 */
 
#define QL4010_NVRAM_SIZE   0x200
 
#define QL40X2_NVRAM_SIZE   0x800
 
#define GPOR_TOPCAT_RESET   0x00000004
 
#define FA_FLASH_LAYOUT_ADDR_82   0xFC400
 
#define FA_FLASH_DESCR_ADDR_82   0xFC000
 
#define FA_BOOT_LOAD_ADDR_82   0x04000
 
#define FA_BOOT_CODE_ADDR_82   0x20000
 
#define FA_RISC_CODE_ADDR_82   0x40000
 
#define FA_GOLD_RISC_CODE_ADDR_82   0x80000
 
#define FA_FLASH_ISCSI_CHAP   0x540000
 
#define FA_FLASH_CHAP_SIZE   0xC0000
 
#define FLT_REG_FDT   0x1a
 
#define FLT_REG_FLT   0x1c
 
#define FLT_REG_BOOTLOAD_82   0x72
 
#define FLT_REG_FW_82   0x74
 
#define FLT_REG_FW_82_1   0x97
 
#define FLT_REG_GOLD_FW_82   0x75
 
#define FLT_REG_BOOT_CODE_82   0x78
 
#define FLT_REG_ISCSI_PARAM   0x65
 
#define FLT_REG_ISCSI_CHAP   0x63
 
#define MBOX_CMD_ABOUT_FW   0x0009
 
#define MBOX_CMD_PING   0x000B
 
#define PING_IPV6_PROTOCOL_ENABLE   0x1
 
#define PING_IPV6_LINKLOCAL_ADDR   0x4
 
#define PING_IPV6_ADDR0   0x8
 
#define PING_IPV6_ADDR1   0xC
 
#define MBOX_CMD_ENABLE_INTRS   0x0010
 
#define INTR_DISABLE   0
 
#define INTR_ENABLE   1
 
#define MBOX_CMD_STOP_FW   0x0014
 
#define MBOX_CMD_ABORT_TASK   0x0015
 
#define MBOX_CMD_LUN_RESET   0x0016
 
#define MBOX_CMD_TARGET_WARM_RESET   0x0017
 
#define MBOX_CMD_GET_MANAGEMENT_DATA   0x001E
 
#define MBOX_CMD_GET_FW_STATUS   0x001F
 
#define MBOX_CMD_SET_ISNS_SERVICE   0x0021
 
#define ISNS_DISABLE   0
 
#define ISNS_ENABLE   1
 
#define MBOX_CMD_COPY_FLASH   0x0024
 
#define MBOX_CMD_WRITE_FLASH   0x0025
 
#define MBOX_CMD_READ_FLASH   0x0026
 
#define MBOX_CMD_CLEAR_DATABASE_ENTRY   0x0031
 
#define MBOX_CMD_CONN_OPEN   0x0074
 
#define MBOX_CMD_CONN_CLOSE_SESS_LOGOUT   0x0056
 
#define LOGOUT_OPTION_CLOSE_SESSION   0x0002
 
#define LOGOUT_OPTION_RELOGIN   0x0004
 
#define LOGOUT_OPTION_FREE_DDB   0x0008
 
#define MBOX_CMD_SET_PARAM   0x0059
 
#define SET_DRVR_VERSION   0x200
 
#define MAX_DRVR_VER_LEN   24
 
#define MBOX_CMD_EXECUTE_IOCB_A64   0x005A
 
#define MBOX_CMD_INITIALIZE_FIRMWARE   0x0060
 
#define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK   0x0061
 
#define MBOX_CMD_REQUEST_DATABASE_ENTRY   0x0062
 
#define MBOX_CMD_SET_DATABASE_ENTRY   0x0063
 
#define MBOX_CMD_GET_DATABASE_ENTRY   0x0064
 
#define DDB_DS_UNASSIGNED   0x00
 
#define DDB_DS_NO_CONNECTION_ACTIVE   0x01
 
#define DDB_DS_DISCOVERY   0x02
 
#define DDB_DS_SESSION_ACTIVE   0x04
 
#define DDB_DS_SESSION_FAILED   0x06
 
#define DDB_DS_LOGIN_IN_PROCESS   0x07
 
#define MBOX_CMD_GET_FW_STATE   0x0069
 
#define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK_DEFAULTS   0x006A
 
#define MBOX_CMD_GET_SYS_INFO   0x0078
 
#define MBOX_CMD_GET_NVRAM   0x0078 /* For 40xx */
 
#define MBOX_CMD_SET_NVRAM   0x0079 /* For 40xx */
 
#define MBOX_CMD_RESTORE_FACTORY_DEFAULTS   0x0087
 
#define MBOX_CMD_SET_ACB   0x0088
 
#define MBOX_CMD_GET_ACB   0x0089
 
#define MBOX_CMD_DISABLE_ACB   0x008A
 
#define MBOX_CMD_GET_IPV6_NEIGHBOR_CACHE   0x008B
 
#define MBOX_CMD_GET_IPV6_DEST_CACHE   0x008C
 
#define MBOX_CMD_GET_IPV6_DEF_ROUTER_LIST   0x008D
 
#define MBOX_CMD_GET_IPV6_LCL_PREFIX_LIST   0x008E
 
#define MBOX_CMD_SET_IPV6_NEIGHBOR_CACHE   0x0090
 
#define MBOX_CMD_GET_IP_ADDR_STATE   0x0091
 
#define MBOX_CMD_SEND_IPV6_ROUTER_SOL   0x0092
 
#define MBOX_CMD_GET_DB_ENTRY_CURRENT_IP_ADDR   0x0093
 
#define MBOX_CMD_MINIDUMP   0x0129
 
#define MINIDUMP_GET_SIZE_SUBCOMMAND   0x00
 
#define MINIDUMP_GET_TMPLT_SUBCOMMAND   0x01
 
#define FW_STATE_READY   0x0000
 
#define FW_STATE_CONFIG_WAIT   0x0001
 
#define FW_STATE_WAIT_AUTOCONNECT   0x0002
 
#define FW_STATE_ERROR   0x0004
 
#define FW_STATE_CONFIGURING_IP   0x0008
 
#define FW_ADDSTATE_OPTICAL_MEDIA   0x0001
 
#define FW_ADDSTATE_DHCPv4_ENABLED   0x0002
 
#define FW_ADDSTATE_DHCPv4_LEASE_ACQUIRED   0x0004
 
#define FW_ADDSTATE_DHCPv4_LEASE_EXPIRED   0x0008
 
#define FW_ADDSTATE_LINK_UP   0x0010
 
#define FW_ADDSTATE_ISNS_SVC_ENABLED   0x0020
 
#define FW_ADDSTATE_LINK_SPEED_10MBPS   0x0100
 
#define FW_ADDSTATE_LINK_SPEED_100MBPS   0x0200
 
#define FW_ADDSTATE_LINK_SPEED_1GBPS   0x0400
 
#define FW_ADDSTATE_LINK_SPEED_10GBPS   0x0800
 
#define MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS   0x006B
 
#define IPV6_DEFAULT_DDB_ENTRY   0x0001
 
#define MBOX_CMD_CONN_OPEN_SESS_LOGIN   0x0074
 
#define MBOX_CMD_GET_CRASH_RECORD   0x0076 /* 4010 only */
 
#define MBOX_CMD_GET_CONN_EVENT_LOG   0x0077
 
#define MBOX_CMD_IDC_ACK   0x0101
 
#define MBOX_CMD_PORT_RESET   0x0120
 
#define MBOX_CMD_SET_PORT_CONFIG   0x0122
 
#define MBOX_COMPLETION_STATUS   4
 
#define MBOX_STS_BUSY   0x0007
 
#define MBOX_STS_INTERMEDIATE_COMPLETION   0x1000
 
#define MBOX_STS_COMMAND_COMPLETE   0x4000
 
#define MBOX_STS_COMMAND_ERROR   0x4005
 
#define MBOX_ASYNC_EVENT_STATUS   8
 
#define MBOX_ASTS_SYSTEM_ERROR   0x8002
 
#define MBOX_ASTS_REQUEST_TRANSFER_ERROR   0x8003
 
#define MBOX_ASTS_RESPONSE_TRANSFER_ERROR   0x8004
 
#define MBOX_ASTS_PROTOCOL_STATISTIC_ALARM   0x8005
 
#define MBOX_ASTS_SCSI_COMMAND_PDU_REJECTED   0x8006
 
#define MBOX_ASTS_LINK_UP   0x8010
 
#define MBOX_ASTS_LINK_DOWN   0x8011
 
#define MBOX_ASTS_DATABASE_CHANGED   0x8014
 
#define MBOX_ASTS_UNSOLICITED_PDU_RECEIVED   0x8015
 
#define MBOX_ASTS_SELF_TEST_FAILED   0x8016
 
#define MBOX_ASTS_LOGIN_FAILED   0x8017
 
#define MBOX_ASTS_DNS   0x8018
 
#define MBOX_ASTS_HEARTBEAT   0x8019
 
#define MBOX_ASTS_NVRAM_INVALID   0x801A
 
#define MBOX_ASTS_MAC_ADDRESS_CHANGED   0x801B
 
#define MBOX_ASTS_IP_ADDRESS_CHANGED   0x801C
 
#define MBOX_ASTS_DHCP_LEASE_EXPIRED   0x801D
 
#define MBOX_ASTS_DHCP_LEASE_ACQUIRED   0x801F
 
#define MBOX_ASTS_ISNS_UNSOLICITED_PDU_RECEIVED   0x8021
 
#define MBOX_ASTS_DUPLICATE_IP   0x8025
 
#define MBOX_ASTS_ARP_COMPLETE   0x8026
 
#define MBOX_ASTS_SUBNET_STATE_CHANGE   0x8027
 
#define MBOX_ASTS_RESPONSE_QUEUE_FULL   0x8028
 
#define MBOX_ASTS_IP_ADDR_STATE_CHANGED   0x8029
 
#define MBOX_ASTS_IPV6_PREFIX_EXPIRED   0x802B
 
#define MBOX_ASTS_IPV6_ND_PREFIX_IGNORED   0x802C
 
#define MBOX_ASTS_IPV6_LCL_PREFIX_IGNORED   0x802D
 
#define MBOX_ASTS_ICMPV6_ERROR_MSG_RCVD   0x802E
 
#define MBOX_ASTS_IDC_COMPLETE   0x8100
 
#define MBOX_ASTS_IDC_NOTIFY   0x8101
 
#define MBOX_ASTS_TXSCVR_INSERTED   0x8130
 
#define MBOX_ASTS_TXSCVR_REMOVED   0x8131
 
#define ISNS_EVENT_DATA_RECEIVED   0x0000
 
#define ISNS_EVENT_CONNECTION_OPENED   0x0001
 
#define ISNS_EVENT_CONNECTION_FAILED   0x0002
 
#define MBOX_ASTS_IPSEC_SYSTEM_FATAL_ERROR   0x8022
 
#define MBOX_ASTS_SUBNET_STATE_CHANGE   0x8027
 
#define ACB_STATE_UNCONFIGURED   0x00
 
#define ACB_STATE_INVALID   0x01
 
#define ACB_STATE_ACQUIRING   0x02
 
#define ACB_STATE_TENTATIVE   0x03
 
#define ACB_STATE_DEPRICATED   0x04
 
#define ACB_STATE_VALID   0x05
 
#define ACB_STATE_DISABLING   0x06
 
#define FLASH_SEGMENT_IFCB   0x04000000
 
#define FLASH_OPT_RMW_HOLD   0
 
#define FLASH_OPT_RMW_INIT   1
 
#define FLASH_OPT_COMMIT   2
 
#define FLASH_OPT_RMW_COMMIT   3
 
#define IFCB_VER_MIN   0x01
 
#define IFCB_VER_MAX   0x02
 
#define FWOPT_HEARTBEAT_ENABLE   0x1000
 
#define FWOPT_SESSION_MODE   0x0040
 
#define FWOPT_INITIATOR_MODE   0x0020
 
#define FWOPT_TARGET_MODE   0x0010
 
#define FWOPT_ENABLE_CRBDB   0x8000
 
#define ADFWOPT_SERIALIZE_TASK_MGMT   0x0400
 
#define ADFWOPT_AUTOCONN_DISABLE   0x0002
 
#define TCPOPT_DHCP_ENABLE   0x0200
 
#define IPOPT_IPV4_PROTOCOL_ENABLE   0x8000
 
#define IPOPT_VLAN_TAGGING_ENABLE   0x2000
 
#define ACB_NOT_SUPPORTED   0x00
 
#define ACB_SUPPORTED
 
#define IPV6_OPT_IPV6_PROTOCOL_ENABLE   0x8000
 
#define IPV6_OPT_VLAN_TAGGING_ENABLE   0x2000
 
#define IPV6_ADDOPT_NEIGHBOR_DISCOVERY_ADDR_ENABLE
 
#define IPV6_ADDOPT_AUTOCONFIG_LINK_LOCAL_ADDR   0x0001
 
#define IP_ADDRSTATE_UNCONFIGURED   0
 
#define IP_ADDRSTATE_INVALID   1
 
#define IP_ADDRSTATE_ACQUIRING   2
 
#define IP_ADDRSTATE_TENTATIVE   3
 
#define IP_ADDRSTATE_DEPRICATED   4
 
#define IP_ADDRSTATE_PREFERRED   5
 
#define IP_ADDRSTATE_DISABLING   6
 
#define IPV6_RTRSTATE_UNKNOWN   0
 
#define IPV6_RTRSTATE_MANUAL   1
 
#define IPV6_RTRSTATE_ADVERTISED   3
 
#define IPV6_RTRSTATE_STALE   4
 
#define IP_ADDR_COUNT
 
#define IP_STATE_MASK   0x0F000000
 
#define IP_STATE_SHIFT   24
 
#define PRIMARI_ACB   0
 
#define SECONDARY_ACB   1
 
#define MAX_CHAP_ENTRIES_40XX   128
 
#define MAX_CHAP_ENTRIES_82XX   1024
 
#define MAX_RESRV_CHAP_IDX   3
 
#define FLASH_CHAP_OFFSET   0x06000000
 
#define MIN_CHAP_SECRET_LEN   12
 
#define MAX_CHAP_SECRET_LEN   100
 
#define MAX_CHAP_NAME_LEN   256
 
#define CHAP_VALID_COOKIE   0x4092
 
#define CHAP_INVALID_COOKIE   0xFFEE
 
#define DDB_OPT_DISC_SESSION   0x10
 
#define DDB_OPT_TARGET   0x02 /* device is a target */
 
#define DDB_OPT_IPV6_DEVICE   0x100
 
#define DDB_OPT_AUTO_SENDTGTS_DISABLE   0x40
 
#define DDB_OPT_IPV6_NULL_LINK_LOCAL   0x800 /* post connection */
 
#define DDB_OPT_IPV6_FW_DEFINED_LINK_LOCAL   0x800 /* pre connection */
 
#define BYTE_UNITS   512
 
#define DDB_VALID_COOKIE   0x9034
 
#define FLASH_OFFSET_SYS_INFO   0x02000000
 
#define FLASH_DEFAULTBLOCKSIZE   0x20000
 
#define FLASH_EOF_OFFSET
 
#define FLASH_RAW_ACCESS_ADDR   0x8e000000
 
#define BOOT_PARAM_OFFSET_PORT0   0x3b0
 
#define BOOT_PARAM_OFFSET_PORT1   0x7b0
 
#define FLASH_OFFSET_DB_INFO   0x05000000
 
#define FLASH_OFFSET_DB_END   (FLASH_OFFSET_DB_INFO + 0x7fff)
 
#define MAX_CONN_EVENT_LOG_ENTRIES   100
 
#define IOCB_MAX_CDB_LEN   16 /* Bytes in a CBD */
 
#define IOCB_MAX_SENSEDATA_LEN   32 /* Bytes of sense data */
 
#define IOCB_MAX_EXT_SENSEDATA_LEN   60 /* Bytes of extended sense data */
 
#define ET_STATUS   0x03
 
#define ET_MARKER   0x04
 
#define ET_CONT_T1   0x0A
 
#define ET_STATUS_CONTINUATION   0x10
 
#define ET_CMND_T3   0x19
 
#define ET_PASSTHRU0   0x3A
 
#define ET_PASSTHRU_STATUS   0x3C
 
#define ET_MBOX_CMD   0x38
 
#define ET_MBOX_STATUS   0x39
 
#define SD_ISCSI_PDU   0x01
 
#define COMMAND_SEG_A64   1
 
#define CONTINUE_SEG_A64   5
 
#define CF_WRITE   0x20
 
#define CF_READ   0x40
 
#define CF_NO_DATA   0x00
 
#define CF_HEAD_TAG   0x03
 
#define CF_ORDERED_TAG   0x02
 
#define CF_SIMPLE_TAG   0x01
 
#define COMMAND_SEG   COMMAND_SEG_A64
 
#define CONTINUE_SEG   CONTINUE_SEG_A64
 
#define ET_COMMAND   ET_CMND_T3
 
#define ET_CONTINUE   ET_CONT_T1
 
#define MM_LUN_RESET   0
 
#define MM_TGT_WARM_RESET   1
 
#define SCSI_CHECK_CONDITION   0x02
 
#define ISCSI_FLAG_RESIDUAL_UNDER   0x02
 
#define ISCSI_FLAG_RESIDUAL_OVER   0x04
 
#define SCS_COMPLETE   0x00
 
#define SCS_INCOMPLETE   0x01
 
#define SCS_RESET_OCCURRED   0x04
 
#define SCS_ABORTED   0x05
 
#define SCS_TIMEOUT   0x06
 
#define SCS_DATA_OVERRUN   0x07
 
#define SCS_DATA_UNDERRUN   0x15
 
#define SCS_QUEUE_FULL   0x1C
 
#define SCS_DEVICE_UNAVAILABLE   0x28
 
#define SCS_DEVICE_LOGGED_OUT   0x29
 
#define ISNS_DEFAULT_SERVER_CONN_ID   ((uint16_t)0x8000)
 
#define PT_FLAG_ETHERNET_FRAME   0x8000
 
#define PT_FLAG_ISNS_PDU   0x8000
 
#define PT_FLAG_SEND_BUFFER   0x0200
 
#define PT_FLAG_WAIT_4_RESPONSE   0x0100
 
#define PT_FLAG_ISCSI_PDU   0x1000
 
#define PT_DEFAULT_TIMEOUT   30 /* seconds */
 
#define PASSTHRU_STATUS_COMPLETE   0x01
 
#define RESPONSE_PROCESSED   0xDEADDEAD /* Signature */
 
#define QLA8XXX_DBG_STATE_ARRAY_LEN   16
 
#define QLA8XXX_DBG_CAP_SIZE_ARRAY_LEN   8
 
#define QLA8XXX_DBG_RSVD_ARRAY_LEN   8
 
#define QLA83XX_DBG_OCM_WNDREG_ARRAY_LEN   16
 
#define QLA83XX_SS_OCM_WNDREG_INDEX   3
 
#define QLA83XX_SS_PCI_INDEX   0
 

Variables

__le32 nvram
 
__le32 reserved1 [2]
 
__le32 intr_mask
 
__le32 semaphore
 
__le32 ext_hw_conf
 
__le32 flow_ctrl
 
__le32 port_ctrl
 
__le32 port_status
 
__le32 reserved3 [8]
 
__le32 req_q_out
 
__le32 reserved4 [23]
 
__le32 gp_out
 
__le32 gp_in
 
__le32 reserved5 [5]
 
__le32 port_err_status
 
union {
   struct port_ctrl_stat_regs   p0
 
   struct host_mem_cfg_regs   p1
 
}; 
 

Macro Definition Documentation

#define ACB_NOT_SUPPORTED   0x00

Definition at line 574 of file ql4_fw.h.

#define ACB_STATE_ACQUIRING   0x02

Definition at line 511 of file ql4_fw.h.

#define ACB_STATE_DEPRICATED   0x04

Definition at line 513 of file ql4_fw.h.

#define ACB_STATE_DISABLING   0x06

Definition at line 515 of file ql4_fw.h.

#define ACB_STATE_INVALID   0x01

Definition at line 510 of file ql4_fw.h.

#define ACB_STATE_TENTATIVE   0x03

Definition at line 512 of file ql4_fw.h.

#define ACB_STATE_UNCONFIGURED   0x00

Definition at line 509 of file ql4_fw.h.

#define ACB_STATE_VALID   0x05

Definition at line 514 of file ql4_fw.h.

#define ACB_SUPPORTED
Value:
0x02 /* Capable of ACB Version 2
Features */

Definition at line 575 of file ql4_fw.h.

#define ADFWOPT_AUTOCONN_DISABLE   0x0002

Definition at line 547 of file ql4_fw.h.

#define ADFWOPT_SERIALIZE_TASK_MGMT   0x0400

Definition at line 546 of file ql4_fw.h.

#define BOOT_PARAM_OFFSET_PORT0   0x3b0

Definition at line 833 of file ql4_fw.h.

#define BOOT_PARAM_OFFSET_PORT1   0x7b0

Definition at line 834 of file ql4_fw.h.

#define BYTE_UNITS   512

Definition at line 781 of file ql4_fw.h.

#define CF_HEAD_TAG   0x03

Definition at line 1024 of file ql4_fw.h.

#define CF_NO_DATA   0x00

Definition at line 1021 of file ql4_fw.h.

#define CF_ORDERED_TAG   0x02

Definition at line 1025 of file ql4_fw.h.

#define CF_READ   0x40

Definition at line 1020 of file ql4_fw.h.

#define CF_SIMPLE_TAG   0x01

Definition at line 1026 of file ql4_fw.h.

#define CF_WRITE   0x20

Definition at line 1019 of file ql4_fw.h.

#define CHAP_INVALID_COOKIE   0xFFEE

Definition at line 761 of file ql4_fw.h.

#define CHAP_VALID_COOKIE   0x4092

Definition at line 760 of file ql4_fw.h.

#define COMMAND_SEG   COMMAND_SEG_A64

Definition at line 1056 of file ql4_fw.h.

#define COMMAND_SEG_A64   1

Definition at line 991 of file ql4_fw.h.

#define CONTINUE_SEG   CONTINUE_SEG_A64

Definition at line 1057 of file ql4_fw.h.

#define CONTINUE_SEG_A64   5

Definition at line 992 of file ql4_fw.h.

#define CSR_BOOT_ENABLE   0x00000080

Definition at line 218 of file ql4_fw.h.

#define CSR_FATAL_ERROR   0x00004000

Definition at line 223 of file ql4_fw.h.

#define CSR_FORCE_SOFT_RESET   0x00002000 /* 4022 */

Definition at line 222 of file ql4_fw.h.

#define CSR_FUNC_NUM   0x00000700 /* 4022 */

Definition at line 220 of file ql4_fw.h.

#define CSR_INTR_RISC   0x00000040

Definition at line 217 of file ql4_fw.h.

#define CSR_NET_PAGE_SELECT   0x00000300 /* 4010 */

Definition at line 219 of file ql4_fw.h.

#define CSR_NET_RESET_INTR   0x00000800 /* 4010 */

Definition at line 221 of file ql4_fw.h.

#define CSR_SCSI_COMPLETION_INTR   0x00000010

Definition at line 215 of file ql4_fw.h.

#define CSR_SCSI_INTR_ENABLE   0x00000004 /* 4010 */

Definition at line 213 of file ql4_fw.h.

#define CSR_SCSI_PAGE_SELECT   0x00000003

Definition at line 212 of file ql4_fw.h.

#define CSR_SCSI_PROCESSOR_INTR   0x00000020

Definition at line 216 of file ql4_fw.h.

#define CSR_SCSI_RESET_INTR   0x00000008

Definition at line 214 of file ql4_fw.h.

#define CSR_SOFT_RESET   0x00008000

Definition at line 224 of file ql4_fw.h.

#define DDB_DS_DISCOVERY   0x02

Definition at line 404 of file ql4_fw.h.

#define DDB_DS_LOGIN_IN_PROCESS   0x07

Definition at line 407 of file ql4_fw.h.

#define DDB_DS_NO_CONNECTION_ACTIVE   0x01

Definition at line 403 of file ql4_fw.h.

#define DDB_DS_SESSION_ACTIVE   0x04

Definition at line 405 of file ql4_fw.h.

#define DDB_DS_SESSION_FAILED   0x06

Definition at line 406 of file ql4_fw.h.

#define DDB_DS_UNASSIGNED   0x00

Definition at line 402 of file ql4_fw.h.

#define DDB_OPT_AUTO_SENDTGTS_DISABLE   0x40

Definition at line 770 of file ql4_fw.h.

#define DDB_OPT_DISC_SESSION   0x10

Definition at line 767 of file ql4_fw.h.

#define DDB_OPT_IPV6_DEVICE   0x100

Definition at line 769 of file ql4_fw.h.

#define DDB_OPT_IPV6_FW_DEFINED_LINK_LOCAL   0x800 /* pre connection */

Definition at line 772 of file ql4_fw.h.

#define DDB_OPT_IPV6_NULL_LINK_LOCAL   0x800 /* post connection */

Definition at line 771 of file ql4_fw.h.

#define DDB_OPT_TARGET   0x02 /* device is a target */

Definition at line 768 of file ql4_fw.h.

#define DDB_VALID_COOKIE   0x9034

Definition at line 819 of file ql4_fw.h.

#define ET_CMND_T3   0x19

Definition at line 968 of file ql4_fw.h.

#define ET_COMMAND   ET_CMND_T3

Definition at line 1059 of file ql4_fw.h.

#define ET_CONT_T1   0x0A

Definition at line 966 of file ql4_fw.h.

#define ET_CONTINUE   ET_CONT_T1

Definition at line 1060 of file ql4_fw.h.

#define ET_MARKER   0x04

Definition at line 965 of file ql4_fw.h.

#define ET_MBOX_CMD   0x38

Definition at line 971 of file ql4_fw.h.

#define ET_MBOX_STATUS   0x39

Definition at line 972 of file ql4_fw.h.

#define ET_PASSTHRU0   0x3A

Definition at line 969 of file ql4_fw.h.

#define ET_PASSTHRU_STATUS   0x3C

Definition at line 970 of file ql4_fw.h.

#define ET_STATUS   0x03

Definition at line 964 of file ql4_fw.h.

#define ET_STATUS_CONTINUATION   0x10

Definition at line 967 of file ql4_fw.h.

#define FA_BOOT_CODE_ADDR_82   0x20000

Definition at line 286 of file ql4_fw.h.

#define FA_BOOT_LOAD_ADDR_82   0x04000

Definition at line 285 of file ql4_fw.h.

#define FA_FLASH_CHAP_SIZE   0xC0000

Definition at line 290 of file ql4_fw.h.

#define FA_FLASH_DESCR_ADDR_82   0xFC000

Definition at line 284 of file ql4_fw.h.

#define FA_FLASH_ISCSI_CHAP   0x540000

Definition at line 289 of file ql4_fw.h.

#define FA_FLASH_LAYOUT_ADDR_82   0xFC400

Definition at line 283 of file ql4_fw.h.

#define FA_GOLD_RISC_CODE_ADDR_82   0x80000

Definition at line 288 of file ql4_fw.h.

#define FA_RISC_CODE_ADDR_82   0x40000

Definition at line 287 of file ql4_fw.h.

#define FLASH_CHAP_OFFSET   0x06000000

Definition at line 748 of file ql4_fw.h.

#define FLASH_DEFAULTBLOCKSIZE   0x20000

Definition at line 829 of file ql4_fw.h.

#define FLASH_EOF_OFFSET
Value:
(FLASH_DEFAULTBLOCKSIZE-8) /* 4 bytes
* for EOF
* signature */

Definition at line 830 of file ql4_fw.h.

#define FLASH_OFFSET_DB_END   (FLASH_OFFSET_DB_INFO + 0x7fff)

Definition at line 837 of file ql4_fw.h.

#define FLASH_OFFSET_DB_INFO   0x05000000

Definition at line 836 of file ql4_fw.h.

#define FLASH_OFFSET_SYS_INFO   0x02000000

Definition at line 828 of file ql4_fw.h.

#define FLASH_OPT_COMMIT   2

Definition at line 522 of file ql4_fw.h.

#define FLASH_OPT_RMW_COMMIT   3

Definition at line 523 of file ql4_fw.h.

#define FLASH_OPT_RMW_HOLD   0

Definition at line 520 of file ql4_fw.h.

#define FLASH_OPT_RMW_INIT   1

Definition at line 521 of file ql4_fw.h.

#define FLASH_RAW_ACCESS_ADDR   0x8e000000

Definition at line 831 of file ql4_fw.h.

#define FLASH_SEGMENT_IFCB   0x04000000

Definition at line 518 of file ql4_fw.h.

#define FLT_REG_BOOT_CODE_82   0x78

Definition at line 348 of file ql4_fw.h.

#define FLT_REG_BOOTLOAD_82   0x72

Definition at line 344 of file ql4_fw.h.

#define FLT_REG_FDT   0x1a

Definition at line 342 of file ql4_fw.h.

#define FLT_REG_FLT   0x1c

Definition at line 343 of file ql4_fw.h.

#define FLT_REG_FW_82   0x74

Definition at line 345 of file ql4_fw.h.

#define FLT_REG_FW_82_1   0x97

Definition at line 346 of file ql4_fw.h.

#define FLT_REG_GOLD_FW_82   0x75

Definition at line 347 of file ql4_fw.h.

#define FLT_REG_ISCSI_CHAP   0x63

Definition at line 350 of file ql4_fw.h.

#define FLT_REG_ISCSI_PARAM   0x65

Definition at line 349 of file ql4_fw.h.

#define FW_ADDSTATE_DHCPv4_ENABLED   0x0002

Definition at line 440 of file ql4_fw.h.

#define FW_ADDSTATE_DHCPv4_LEASE_ACQUIRED   0x0004

Definition at line 441 of file ql4_fw.h.

#define FW_ADDSTATE_DHCPv4_LEASE_EXPIRED   0x0008

Definition at line 442 of file ql4_fw.h.

#define FW_ADDSTATE_ISNS_SVC_ENABLED   0x0020

Definition at line 444 of file ql4_fw.h.

#define FW_ADDSTATE_LINK_SPEED_100MBPS   0x0200

Definition at line 446 of file ql4_fw.h.

#define FW_ADDSTATE_LINK_SPEED_10GBPS   0x0800

Definition at line 448 of file ql4_fw.h.

#define FW_ADDSTATE_LINK_SPEED_10MBPS   0x0100

Definition at line 445 of file ql4_fw.h.

#define FW_ADDSTATE_LINK_SPEED_1GBPS   0x0400

Definition at line 447 of file ql4_fw.h.

#define FW_ADDSTATE_LINK_UP   0x0010

Definition at line 443 of file ql4_fw.h.

#define FW_ADDSTATE_OPTICAL_MEDIA   0x0001

Definition at line 439 of file ql4_fw.h.

#define FW_STATE_CONFIG_WAIT   0x0001

Definition at line 433 of file ql4_fw.h.

#define FW_STATE_CONFIGURING_IP   0x0008

Definition at line 436 of file ql4_fw.h.

#define FW_STATE_ERROR   0x0004

Definition at line 435 of file ql4_fw.h.

#define FW_STATE_READY   0x0000

Definition at line 432 of file ql4_fw.h.

#define FW_STATE_WAIT_AUTOCONNECT   0x0002

Definition at line 434 of file ql4_fw.h.

#define FWOPT_ENABLE_CRBDB   0x8000

Definition at line 539 of file ql4_fw.h.

#define FWOPT_HEARTBEAT_ENABLE   0x1000

Definition at line 535 of file ql4_fw.h.

#define FWOPT_INITIATOR_MODE   0x0020

Definition at line 537 of file ql4_fw.h.

#define FWOPT_SESSION_MODE   0x0040

Definition at line 536 of file ql4_fw.h.

#define FWOPT_TARGET_MODE   0x0010

Definition at line 538 of file ql4_fw.h.

#define GPOR_TOPCAT_RESET   0x00000004

Definition at line 247 of file ql4_fw.h.

#define HINT_MBX_INT_PENDING   BIT_0

Definition at line 55 of file ql4_fw.h.

#define HOST_MEM_CFG_PAGE   1 /* 4022 */

Definition at line 195 of file ql4_fw.h.

#define HSRX_RISC_IOCB_INT   BIT_1 /* RISC to Host IOCB interrupt */

Definition at line 62 of file ql4_fw.h.

#define HSRX_RISC_MB_INT   BIT_0 /* RISC to Host Mailbox interrupt */

Definition at line 61 of file ql4_fw.h.

#define IFCB_VER_MAX   0x02

Definition at line 531 of file ql4_fw.h.

#define IFCB_VER_MIN   0x01

Definition at line 530 of file ql4_fw.h.

#define IMR_SCSI_INTR_ENABLE   0x00000004 /* 4022 */

Definition at line 234 of file ql4_fw.h.

#define INT_ENABLE_FW_MB   (1 << 2)

Definition at line 99 of file ql4_fw.h.

#define INT_MASK_FW_MB   (1 << 2)

Definition at line 100 of file ql4_fw.h.

#define INTR_DISABLE   0

Definition at line 373 of file ql4_fw.h.

#define INTR_ENABLE   1

Definition at line 374 of file ql4_fw.h.

#define INTR_PENDING
Value:
CSR_SCSI_PROCESSOR_INTR |\
CSR_SCSI_RESET_INTR)

Definition at line 229 of file ql4_fw.h.

#define IOCB_MAX_CDB_LEN   16 /* Bytes in a CBD */

Definition at line 957 of file ql4_fw.h.

#define IOCB_MAX_EXT_SENSEDATA_LEN   60 /* Bytes of extended sense data */

Definition at line 959 of file ql4_fw.h.

#define IOCB_MAX_SENSEDATA_LEN   32 /* Bytes of sense data */

Definition at line 958 of file ql4_fw.h.

#define IP_ADDR_COUNT
Value:
4 /* Total 4 IP address supported in one interface
* One IPv4, one IPv6 link local and 2 IPv6
*/

Definition at line 662 of file ql4_fw.h.

#define IP_ADDRSTATE_ACQUIRING   2

Definition at line 635 of file ql4_fw.h.

#define IP_ADDRSTATE_DEPRICATED   4

Definition at line 637 of file ql4_fw.h.

#define IP_ADDRSTATE_DISABLING   6

Definition at line 639 of file ql4_fw.h.

#define IP_ADDRSTATE_INVALID   1

Definition at line 634 of file ql4_fw.h.

#define IP_ADDRSTATE_PREFERRED   5

Definition at line 638 of file ql4_fw.h.

#define IP_ADDRSTATE_TENTATIVE   3

Definition at line 636 of file ql4_fw.h.

#define IP_ADDRSTATE_UNCONFIGURED   0

Definition at line 633 of file ql4_fw.h.

#define IP_STATE_MASK   0x0F000000

Definition at line 664 of file ql4_fw.h.

#define IP_STATE_SHIFT   24

Definition at line 665 of file ql4_fw.h.

#define IPOPT_IPV4_PROTOCOL_ENABLE   0x8000

Definition at line 567 of file ql4_fw.h.

#define IPOPT_VLAN_TAGGING_ENABLE   0x2000

Definition at line 568 of file ql4_fw.h.

#define IPV6_ADDOPT_AUTOCONFIG_LINK_LOCAL_ADDR   0x0001

Definition at line 623 of file ql4_fw.h.

#define IPV6_ADDOPT_NEIGHBOR_DISCOVERY_ADDR_ENABLE
Value:
0x0002 /* Pri ACB
Only */

Definition at line 622 of file ql4_fw.h.

#define IPV6_DEFAULT_DDB_ENTRY   0x0001

Definition at line 451 of file ql4_fw.h.

#define IPV6_OPT_IPV6_PROTOCOL_ENABLE   0x8000

Definition at line 618 of file ql4_fw.h.

#define IPV6_OPT_VLAN_TAGGING_ENABLE   0x2000

Definition at line 619 of file ql4_fw.h.

#define IPV6_RTRSTATE_ADVERTISED   3

Definition at line 644 of file ql4_fw.h.

#define IPV6_RTRSTATE_MANUAL   1

Definition at line 643 of file ql4_fw.h.

#define IPV6_RTRSTATE_STALE   4

Definition at line 645 of file ql4_fw.h.

#define IPV6_RTRSTATE_UNKNOWN   0

Definition at line 642 of file ql4_fw.h.

#define ISCSI_FLAG_RESIDUAL_OVER   0x04

Definition at line 1093 of file ql4_fw.h.

#define ISCSI_FLAG_RESIDUAL_UNDER   0x02

Definition at line 1092 of file ql4_fw.h.

#define ISNS_DEFAULT_SERVER_CONN_ID   ((uint16_t)0x8000)

Definition at line 1135 of file ql4_fw.h.

#define ISNS_DISABLE   0

Definition at line 382 of file ql4_fw.h.

#define ISNS_ENABLE   1

Definition at line 383 of file ql4_fw.h.

#define ISNS_EVENT_CONNECTION_FAILED   0x0002

Definition at line 504 of file ql4_fw.h.

#define ISNS_EVENT_CONNECTION_OPENED   0x0001

Definition at line 503 of file ql4_fw.h.

#define ISNS_EVENT_DATA_RECEIVED   0x0000

Definition at line 502 of file ql4_fw.h.

#define ISP_CONTROL_FN0_SCSI   0x0500

Definition at line 226 of file ql4_fw.h.

#define ISP_CONTROL_FN1_SCSI   0x0700

Definition at line 227 of file ql4_fw.h.

#define ISP_CONTROL_FN_MASK   CSR_FUNC_NUM

Definition at line 225 of file ql4_fw.h.

#define ISRX_82XX_RISC_INT   BIT_0 /* RISC interrupt. */

Definition at line 65 of file ql4_fw.h.

#define LOCAL_RAM_CFG_PAGE   2 /* 4022 */

Definition at line 196 of file ql4_fw.h.

#define LOGOUT_OPTION_CLOSE_SESSION   0x0002

Definition at line 390 of file ql4_fw.h.

#define LOGOUT_OPTION_FREE_DDB   0x0008

Definition at line 392 of file ql4_fw.h.

#define LOGOUT_OPTION_RELOGIN   0x0004

Definition at line 391 of file ql4_fw.h.

#define MAX_CHAP_ENTRIES_40XX   128

Definition at line 745 of file ql4_fw.h.

#define MAX_CHAP_ENTRIES_82XX   1024

Definition at line 746 of file ql4_fw.h.

#define MAX_CHAP_NAME_LEN   256

Definition at line 757 of file ql4_fw.h.

#define MAX_CHAP_SECRET_LEN   100

Definition at line 755 of file ql4_fw.h.

#define MAX_CONN_EVENT_LOG_ENTRIES   100

Definition at line 940 of file ql4_fw.h.

#define MAX_DEV_DB_ENTRIES   512

Definition at line 14 of file ql4_fw.h.

#define MAX_DEV_DB_ENTRIES_40XX   256

Definition at line 15 of file ql4_fw.h.

#define MAX_DRVR_VER_LEN   24

Definition at line 395 of file ql4_fw.h.

#define MAX_PRST_DEV_DB_ENTRIES   64

Definition at line 12 of file ql4_fw.h.

#define MAX_RESRV_CHAP_IDX   3

Definition at line 747 of file ql4_fw.h.

#define MBOX_ASTS_ARP_COMPLETE   0x8026

Definition at line 489 of file ql4_fw.h.

#define MBOX_ASTS_DATABASE_CHANGED   0x8014

Definition at line 476 of file ql4_fw.h.

#define MBOX_ASTS_DHCP_LEASE_ACQUIRED   0x801F

Definition at line 486 of file ql4_fw.h.

#define MBOX_ASTS_DHCP_LEASE_EXPIRED   0x801D

Definition at line 485 of file ql4_fw.h.

#define MBOX_ASTS_DNS   0x8018

Definition at line 480 of file ql4_fw.h.

#define MBOX_ASTS_DUPLICATE_IP   0x8025

Definition at line 488 of file ql4_fw.h.

#define MBOX_ASTS_HEARTBEAT   0x8019

Definition at line 481 of file ql4_fw.h.

#define MBOX_ASTS_ICMPV6_ERROR_MSG_RCVD   0x802E

Definition at line 496 of file ql4_fw.h.

#define MBOX_ASTS_IDC_COMPLETE   0x8100

Definition at line 497 of file ql4_fw.h.

#define MBOX_ASTS_IDC_NOTIFY   0x8101

Definition at line 498 of file ql4_fw.h.

#define MBOX_ASTS_IP_ADDR_STATE_CHANGED   0x8029

Definition at line 492 of file ql4_fw.h.

#define MBOX_ASTS_IP_ADDRESS_CHANGED   0x801C

Definition at line 484 of file ql4_fw.h.

#define MBOX_ASTS_IPSEC_SYSTEM_FATAL_ERROR   0x8022

Definition at line 505 of file ql4_fw.h.

#define MBOX_ASTS_IPV6_LCL_PREFIX_IGNORED   0x802D

Definition at line 495 of file ql4_fw.h.

#define MBOX_ASTS_IPV6_ND_PREFIX_IGNORED   0x802C

Definition at line 494 of file ql4_fw.h.

#define MBOX_ASTS_IPV6_PREFIX_EXPIRED   0x802B

Definition at line 493 of file ql4_fw.h.

#define MBOX_ASTS_ISNS_UNSOLICITED_PDU_RECEIVED   0x8021

Definition at line 487 of file ql4_fw.h.

#define MBOX_ASTS_LINK_DOWN   0x8011

Definition at line 475 of file ql4_fw.h.

#define MBOX_ASTS_LINK_UP   0x8010

Definition at line 474 of file ql4_fw.h.

#define MBOX_ASTS_LOGIN_FAILED   0x8017

Definition at line 479 of file ql4_fw.h.

#define MBOX_ASTS_MAC_ADDRESS_CHANGED   0x801B

Definition at line 483 of file ql4_fw.h.

#define MBOX_ASTS_NVRAM_INVALID   0x801A

Definition at line 482 of file ql4_fw.h.

#define MBOX_ASTS_PROTOCOL_STATISTIC_ALARM   0x8005

Definition at line 472 of file ql4_fw.h.

#define MBOX_ASTS_REQUEST_TRANSFER_ERROR   0x8003

Definition at line 470 of file ql4_fw.h.

#define MBOX_ASTS_RESPONSE_QUEUE_FULL   0x8028

Definition at line 491 of file ql4_fw.h.

#define MBOX_ASTS_RESPONSE_TRANSFER_ERROR   0x8004

Definition at line 471 of file ql4_fw.h.

#define MBOX_ASTS_SCSI_COMMAND_PDU_REJECTED   0x8006

Definition at line 473 of file ql4_fw.h.

#define MBOX_ASTS_SELF_TEST_FAILED   0x8016

Definition at line 478 of file ql4_fw.h.

#define MBOX_ASTS_SUBNET_STATE_CHANGE   0x8027

Definition at line 506 of file ql4_fw.h.

#define MBOX_ASTS_SUBNET_STATE_CHANGE   0x8027

Definition at line 506 of file ql4_fw.h.

#define MBOX_ASTS_SYSTEM_ERROR   0x8002

Definition at line 469 of file ql4_fw.h.

#define MBOX_ASTS_TXSCVR_INSERTED   0x8130

Definition at line 499 of file ql4_fw.h.

#define MBOX_ASTS_TXSCVR_REMOVED   0x8131

Definition at line 500 of file ql4_fw.h.

#define MBOX_ASTS_UNSOLICITED_PDU_RECEIVED   0x8015

Definition at line 477 of file ql4_fw.h.

#define MBOX_ASYNC_EVENT_STATUS   8

Definition at line 468 of file ql4_fw.h.

#define MBOX_CMD_ABORT_TASK   0x0015

Definition at line 376 of file ql4_fw.h.

#define MBOX_CMD_ABOUT_FW   0x0009

Definition at line 366 of file ql4_fw.h.

#define MBOX_CMD_CLEAR_DATABASE_ENTRY   0x0031

Definition at line 387 of file ql4_fw.h.

#define MBOX_CMD_CONN_CLOSE_SESS_LOGOUT   0x0056

Definition at line 389 of file ql4_fw.h.

#define MBOX_CMD_CONN_OPEN   0x0074

Definition at line 388 of file ql4_fw.h.

#define MBOX_CMD_CONN_OPEN_SESS_LOGIN   0x0074

Definition at line 453 of file ql4_fw.h.

#define MBOX_CMD_COPY_FLASH   0x0024

Definition at line 384 of file ql4_fw.h.

#define MBOX_CMD_DISABLE_ACB   0x008A

Definition at line 416 of file ql4_fw.h.

#define MBOX_CMD_ENABLE_INTRS   0x0010

Definition at line 372 of file ql4_fw.h.

#define MBOX_CMD_EXECUTE_IOCB_A64   0x005A

Definition at line 396 of file ql4_fw.h.

#define MBOX_CMD_GET_ACB   0x0089

Definition at line 415 of file ql4_fw.h.

#define MBOX_CMD_GET_CONN_EVENT_LOG   0x0077

Definition at line 455 of file ql4_fw.h.

#define MBOX_CMD_GET_CRASH_RECORD   0x0076 /* 4010 only */

Definition at line 454 of file ql4_fw.h.

#define MBOX_CMD_GET_DATABASE_ENTRY   0x0064

Definition at line 401 of file ql4_fw.h.

#define MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS   0x006B

Definition at line 450 of file ql4_fw.h.

#define MBOX_CMD_GET_DB_ENTRY_CURRENT_IP_ADDR   0x0093

Definition at line 424 of file ql4_fw.h.

#define MBOX_CMD_GET_FW_STATE   0x0069

Definition at line 408 of file ql4_fw.h.

#define MBOX_CMD_GET_FW_STATUS   0x001F

Definition at line 380 of file ql4_fw.h.

#define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK   0x0061

Definition at line 398 of file ql4_fw.h.

#define MBOX_CMD_GET_INIT_FW_CTRL_BLOCK_DEFAULTS   0x006A

Definition at line 409 of file ql4_fw.h.

#define MBOX_CMD_GET_IP_ADDR_STATE   0x0091

Definition at line 422 of file ql4_fw.h.

#define MBOX_CMD_GET_IPV6_DEF_ROUTER_LIST   0x008D

Definition at line 419 of file ql4_fw.h.

#define MBOX_CMD_GET_IPV6_DEST_CACHE   0x008C

Definition at line 418 of file ql4_fw.h.

#define MBOX_CMD_GET_IPV6_LCL_PREFIX_LIST   0x008E

Definition at line 420 of file ql4_fw.h.

#define MBOX_CMD_GET_IPV6_NEIGHBOR_CACHE   0x008B

Definition at line 417 of file ql4_fw.h.

#define MBOX_CMD_GET_MANAGEMENT_DATA   0x001E

Definition at line 379 of file ql4_fw.h.

#define MBOX_CMD_GET_NVRAM   0x0078 /* For 40xx */

Definition at line 411 of file ql4_fw.h.

#define MBOX_CMD_GET_SYS_INFO   0x0078

Definition at line 410 of file ql4_fw.h.

#define MBOX_CMD_IDC_ACK   0x0101

Definition at line 457 of file ql4_fw.h.

#define MBOX_CMD_INITIALIZE_FIRMWARE   0x0060

Definition at line 397 of file ql4_fw.h.

#define MBOX_CMD_LUN_RESET   0x0016

Definition at line 377 of file ql4_fw.h.

#define MBOX_CMD_MINIDUMP   0x0129

Definition at line 425 of file ql4_fw.h.

#define MBOX_CMD_PING   0x000B

Definition at line 367 of file ql4_fw.h.

#define MBOX_CMD_PORT_RESET   0x0120

Definition at line 458 of file ql4_fw.h.

#define MBOX_CMD_READ_FLASH   0x0026

Definition at line 386 of file ql4_fw.h.

#define MBOX_CMD_REQUEST_DATABASE_ENTRY   0x0062

Definition at line 399 of file ql4_fw.h.

#define MBOX_CMD_RESTORE_FACTORY_DEFAULTS   0x0087

Definition at line 413 of file ql4_fw.h.

#define MBOX_CMD_SEND_IPV6_ROUTER_SOL   0x0092

Definition at line 423 of file ql4_fw.h.

#define MBOX_CMD_SET_ACB   0x0088

Definition at line 414 of file ql4_fw.h.

#define MBOX_CMD_SET_DATABASE_ENTRY   0x0063

Definition at line 400 of file ql4_fw.h.

#define MBOX_CMD_SET_IPV6_NEIGHBOR_CACHE   0x0090

Definition at line 421 of file ql4_fw.h.

#define MBOX_CMD_SET_ISNS_SERVICE   0x0021

Definition at line 381 of file ql4_fw.h.

#define MBOX_CMD_SET_NVRAM   0x0079 /* For 40xx */

Definition at line 412 of file ql4_fw.h.

#define MBOX_CMD_SET_PARAM   0x0059

Definition at line 393 of file ql4_fw.h.

#define MBOX_CMD_SET_PORT_CONFIG   0x0122

Definition at line 459 of file ql4_fw.h.

#define MBOX_CMD_STOP_FW   0x0014

Definition at line 375 of file ql4_fw.h.

#define MBOX_CMD_TARGET_WARM_RESET   0x0017

Definition at line 378 of file ql4_fw.h.

#define MBOX_CMD_WRITE_FLASH   0x0025

Definition at line 385 of file ql4_fw.h.

#define MBOX_COMPLETION_STATUS   4

Definition at line 462 of file ql4_fw.h.

#define MBOX_REG_COUNT   8

Definition at line 104 of file ql4_fw.h.

#define MBOX_STS_BUSY   0x0007

Definition at line 463 of file ql4_fw.h.

#define MBOX_STS_COMMAND_COMPLETE   0x4000

Definition at line 465 of file ql4_fw.h.

#define MBOX_STS_COMMAND_ERROR   0x4005

Definition at line 466 of file ql4_fw.h.

#define MBOX_STS_INTERMEDIATE_COMPLETION   0x1000

Definition at line 464 of file ql4_fw.h.

#define MIN_CHAP_SECRET_LEN   12

Definition at line 754 of file ql4_fw.h.

#define MIN_DISC_DEV_DB_ENTRY   MAX_PRST_DEV_DB_ENTRIES

Definition at line 13 of file ql4_fw.h.

#define MINIDUMP_GET_SIZE_SUBCOMMAND   0x00

Definition at line 428 of file ql4_fw.h.

#define MINIDUMP_GET_TMPLT_SUBCOMMAND   0x01

Definition at line 429 of file ql4_fw.h.

#define MM_LUN_RESET   0

Definition at line 1069 of file ql4_fw.h.

#define MM_TGT_WARM_RESET   1

Definition at line 1070 of file ql4_fw.h.

#define NVR_WRITE_ENABLE   0x00000010 /* 4022 */

Definition at line 237 of file ql4_fw.h.

#define NVRAM_PORT0_BOOT_MODE   0x03b1

Definition at line 185 of file ql4_fw.h.

#define NVRAM_PORT0_BOOT_PRI_TGT   0x03b2

Definition at line 186 of file ql4_fw.h.

#define NVRAM_PORT0_BOOT_SEC_TGT   0x03bb

Definition at line 187 of file ql4_fw.h.

#define NVRAM_PORT1_BOOT_MODE   0x07b1

Definition at line 188 of file ql4_fw.h.

#define NVRAM_PORT1_BOOT_PRI_TGT   0x07b2

Definition at line 189 of file ql4_fw.h.

#define NVRAM_PORT1_BOOT_SEC_TGT   0x07bb

Definition at line 190 of file ql4_fw.h.

#define PASSTHRU_STATUS_COMPLETE   0x01

Definition at line 1160 of file ql4_fw.h.

#define PING_IPV6_ADDR0   0x8

Definition at line 370 of file ql4_fw.h.

#define PING_IPV6_ADDR1   0xC

Definition at line 371 of file ql4_fw.h.

#define PING_IPV6_LINKLOCAL_ADDR   0x4

Definition at line 369 of file ql4_fw.h.

#define PING_IPV6_PROTOCOL_ENABLE   0x1

Definition at line 368 of file ql4_fw.h.

#define PORT_CTRL_STAT_PAGE   0 /* 4022 */

Definition at line 194 of file ql4_fw.h.

#define PRIMARI_ACB   0

Definition at line 672 of file ql4_fw.h.

#define PROT_STAT_PAGE   3 /* 4022 */

Definition at line 197 of file ql4_fw.h.

#define PT_DEFAULT_TIMEOUT   30 /* seconds */

Definition at line 1145 of file ql4_fw.h.

#define PT_FLAG_ETHERNET_FRAME   0x8000

Definition at line 1138 of file ql4_fw.h.

#define PT_FLAG_ISCSI_PDU   0x1000

Definition at line 1142 of file ql4_fw.h.

#define PT_FLAG_ISNS_PDU   0x8000

Definition at line 1139 of file ql4_fw.h.

#define PT_FLAG_SEND_BUFFER   0x0200

Definition at line 1140 of file ql4_fw.h.

#define PT_FLAG_WAIT_4_RESPONSE   0x0100

Definition at line 1141 of file ql4_fw.h.

#define QL4010_DRVR_SEM_BITS   0x00000030

Definition at line 159 of file ql4_fw.h.

#define QL4010_DRVR_SEM_MASK   0x00300000

Definition at line 166 of file ql4_fw.h.

#define QL4010_FLASH_SEM_BITS   0x0000c000

Definition at line 164 of file ql4_fw.h.

#define QL4010_FLASH_SEM_MASK   0xc0000000

Definition at line 171 of file ql4_fw.h.

#define QL4010_GPIO_SEM_BITS   0x000000c0

Definition at line 160 of file ql4_fw.h.

#define QL4010_GPIO_SEM_MASK   0x00c00000

Definition at line 167 of file ql4_fw.h.

#define QL4010_NVRAM_SEM_BITS   0x00003000

Definition at line 163 of file ql4_fw.h.

#define QL4010_NVRAM_SEM_MASK   0x30000000

Definition at line 170 of file ql4_fw.h.

#define QL4010_NVRAM_SIZE   0x200

Definition at line 239 of file ql4_fw.h.

#define QL4010_PHY_SEM_BITS   0x00000c00

Definition at line 162 of file ql4_fw.h.

#define QL4010_PHY_SEM_MASK   0x0c000000

Definition at line 169 of file ql4_fw.h.

#define QL4010_SDRAM_SEM_BITS   0x00000300

Definition at line 161 of file ql4_fw.h.

#define QL4010_SDRAM_SEM_MASK   0x03000000

Definition at line 168 of file ql4_fw.h.

#define QL4022_DDR_RAM_SEM_MASK   (QL4022_RESOURCE_MASK_BASE_CODE << (4+16))

Definition at line 179 of file ql4_fw.h.

#define QL4022_DRVR_SEM_MASK   (QL4022_RESOURCE_MASK_BASE_CODE << (1+16))

Definition at line 178 of file ql4_fw.h.

#define QL4022_FLASH_SEM_MASK   (QL4022_RESOURCE_MASK_BASE_CODE << (13+16))

Definition at line 182 of file ql4_fw.h.

#define QL4022_NVRAM_SEM_MASK   (QL4022_RESOURCE_MASK_BASE_CODE << (10+16))

Definition at line 181 of file ql4_fw.h.

#define QL4022_PHY_GIO_SEM_MASK   (QL4022_RESOURCE_MASK_BASE_CODE << (7+16))

Definition at line 180 of file ql4_fw.h.

#define QL4022_RESOURCE_BITS_BASE_CODE   0x4

Definition at line 175 of file ql4_fw.h.

#define QL4022_RESOURCE_MASK_BASE_CODE   0x7

Definition at line 174 of file ql4_fw.h.

#define QL40X2_NVRAM_SIZE   0x800

Definition at line 240 of file ql4_fw.h.

#define QLA83XX_DBG_OCM_WNDREG_ARRAY_LEN   16

Definition at line 1238 of file ql4_fw.h.

#define QLA83XX_SS_OCM_WNDREG_INDEX   3

Definition at line 1239 of file ql4_fw.h.

#define QLA83XX_SS_PCI_INDEX   0

Definition at line 1240 of file ql4_fw.h.

#define QLA8XXX_DBG_CAP_SIZE_ARRAY_LEN   8

Definition at line 1236 of file ql4_fw.h.

#define QLA8XXX_DBG_RSVD_ARRAY_LEN   8

Definition at line 1237 of file ql4_fw.h.

#define QLA8XXX_DBG_STATE_ARRAY_LEN   16

Definition at line 1235 of file ql4_fw.h.

#define RESPONSE_PROCESSED   0xDEADDEAD /* Signature */

Definition at line 1193 of file ql4_fw.h.

#define SCS_ABORTED   0x05

Definition at line 1101 of file ql4_fw.h.

#define SCS_COMPLETE   0x00

Definition at line 1098 of file ql4_fw.h.

#define SCS_DATA_OVERRUN   0x07

Definition at line 1103 of file ql4_fw.h.

#define SCS_DATA_UNDERRUN   0x15

Definition at line 1104 of file ql4_fw.h.

#define SCS_DEVICE_LOGGED_OUT   0x29

Definition at line 1107 of file ql4_fw.h.

#define SCS_DEVICE_UNAVAILABLE   0x28

Definition at line 1106 of file ql4_fw.h.

#define SCS_INCOMPLETE   0x01

Definition at line 1099 of file ql4_fw.h.

#define SCS_QUEUE_FULL   0x1C

Definition at line 1105 of file ql4_fw.h.

#define SCS_RESET_OCCURRED   0x04

Definition at line 1100 of file ql4_fw.h.

#define SCS_TIMEOUT   0x06

Definition at line 1102 of file ql4_fw.h.

#define SCSI_CHECK_CONDITION   0x02

Definition at line 1089 of file ql4_fw.h.

#define SD_ISCSI_PDU   0x01

Definition at line 976 of file ql4_fw.h.

#define SECONDARY_ACB   1

Definition at line 673 of file ql4_fw.h.

#define SET_DRVR_VERSION   0x200

Definition at line 394 of file ql4_fw.h.

#define TCPOPT_DHCP_ENABLE   0x0200

Definition at line 565 of file ql4_fw.h.

Variable Documentation

union { ... }
u16 ext_hw_conf

Definition at line 148 of file ql4_fw.h.

__le32 flow_ctrl

Definition at line 149 of file ql4_fw.h.

__le32 gp_in

Definition at line 160 of file ql4_fw.h.

__le32 gp_out

Definition at line 159 of file ql4_fw.h.

__le32 intr_mask

Definition at line 121 of file ql4_fw.h.

Definition at line 116 of file ql4_fw.h.

Definition at line 155 of file ql4_fw.h.

Definition at line 156 of file ql4_fw.h.

__le32 port_ctrl

Definition at line 150 of file ql4_fw.h.

__le32 port_err_status

Definition at line 164 of file ql4_fw.h.

__le32 port_status

Definition at line 151 of file ql4_fw.h.

__le32 req_q_out

Definition at line 155 of file ql4_fw.h.

__le32 reserved1[2]

Definition at line 117 of file ql4_fw.h.

__le32 reserved3[8]

Definition at line 153 of file ql4_fw.h.

__le32 reserved4[23]

Definition at line 157 of file ql4_fw.h.

__le32 reserved5[5]

Definition at line 162 of file ql4_fw.h.

Definition at line 123 of file ql4_fw.h.