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Linux Kernel
3.7.1
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All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
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Linux Kernel
3.7.1
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#include <linux/kernel.h>#include <linux/module.h>#include <linux/moduleparam.h>#include <linux/string.h>#include <linux/timer.h>#include <linux/errno.h>#include <linux/ioport.h>#include <linux/interrupt.h>#include <linux/pci.h>#include <linux/netdevice.h>#include <linux/etherdevice.h>#include <linux/skbuff.h>#include <linux/init.h>#include <linux/delay.h>#include <linux/mii.h>#include <linux/ethtool.h>#include <linux/crc32.h>#include <linux/spinlock.h>#include <linux/bitops.h>#include <linux/io.h>#include <linux/irq.h>#include <linux/uaccess.h>#include <linux/phy.h>#include <asm/processor.h>Go to the source code of this file.
Data Structures | |
| struct | r6040_descriptor |
| struct | r6040_private |
Macros | |
| #define | DRV_NAME "r6040" |
| #define | DRV_VERSION "0.28" |
| #define | DRV_RELDATE "07Oct2011" |
| #define | TX_TIMEOUT (6000 * HZ / 1000) |
| #define | R6040_IO_SIZE 256 |
| #define | MAX_MAC 2 |
| #define | MCR0 0x00 /* Control register 0 */ |
| #define | MCR0_RCVEN 0x0002 /* Receive enable */ |
| #define | MCR0_PROMISC 0x0020 /* Promiscuous mode */ |
| #define | MCR0_HASH_EN 0x0100 /* Enable multicast hash table function */ |
| #define | MCR0_XMTEN 0x1000 /* Transmission enable */ |
| #define | MCR0_FD 0x8000 /* Full/Half duplex */ |
| #define | MCR1 0x04 /* Control register 1 */ |
| #define | MAC_RST 0x0001 /* Reset the MAC */ |
| #define | MBCR 0x08 /* Bus control */ |
| #define | MT_ICR 0x0C /* TX interrupt control */ |
| #define | MR_ICR 0x10 /* RX interrupt control */ |
| #define | MTPR 0x14 /* TX poll command register */ |
| #define | TM2TX 0x0001 /* Trigger MAC to transmit */ |
| #define | MR_BSR 0x18 /* RX buffer size */ |
| #define | MR_DCR 0x1A /* RX descriptor control */ |
| #define | MLSR 0x1C /* Last status */ |
| #define | TX_FIFO_UNDR 0x0200 /* TX FIFO under-run */ |
| #define | TX_EXCEEDC 0x2000 /* Transmit exceed collision */ |
| #define | TX_LATEC 0x4000 /* Transmit late collision */ |
| #define | MMDIO 0x20 /* MDIO control register */ |
| #define | MDIO_WRITE 0x4000 /* MDIO write */ |
| #define | MDIO_READ 0x2000 /* MDIO read */ |
| #define | MMRD 0x24 /* MDIO read data register */ |
| #define | MMWD 0x28 /* MDIO write data register */ |
| #define | MTD_SA0 0x2C /* TX descriptor start address 0 */ |
| #define | MTD_SA1 0x30 /* TX descriptor start address 1 */ |
| #define | MRD_SA0 0x34 /* RX descriptor start address 0 */ |
| #define | MRD_SA1 0x38 /* RX descriptor start address 1 */ |
| #define | MISR 0x3C /* Status register */ |
| #define | MIER 0x40 /* INT enable register */ |
| #define | MSK_INT 0x0000 /* Mask off interrupts */ |
| #define | RX_FINISH 0x0001 /* RX finished */ |
| #define | RX_NO_DESC 0x0002 /* No RX descriptor available */ |
| #define | RX_FIFO_FULL 0x0004 /* RX FIFO full */ |
| #define | RX_EARLY 0x0008 /* RX early */ |
| #define | TX_FINISH 0x0010 /* TX finished */ |
| #define | TX_EARLY 0x0080 /* TX early */ |
| #define | EVENT_OVRFL 0x0100 /* Event counter overflow */ |
| #define | LINK_CHANGED 0x0200 /* PHY link changed */ |
| #define | ME_CISR 0x44 /* Event counter INT status */ |
| #define | ME_CIER 0x48 /* Event counter INT enable */ |
| #define | MR_CNT 0x50 /* Successfully received packet counter */ |
| #define | ME_CNT0 0x52 /* Event counter 0 */ |
| #define | ME_CNT1 0x54 /* Event counter 1 */ |
| #define | ME_CNT2 0x56 /* Event counter 2 */ |
| #define | ME_CNT3 0x58 /* Event counter 3 */ |
| #define | MT_CNT 0x5A /* Successfully transmit packet counter */ |
| #define | ME_CNT4 0x5C /* Event counter 4 */ |
| #define | MP_CNT 0x5E /* Pause frame counter register */ |
| #define | MAR0 0x60 /* Hash table 0 */ |
| #define | MAR1 0x62 /* Hash table 1 */ |
| #define | MAR2 0x64 /* Hash table 2 */ |
| #define | MAR3 0x66 /* Hash table 3 */ |
| #define | MID_0L 0x68 /* Multicast address MID0 Low */ |
| #define | MID_0M 0x6A /* Multicast address MID0 Medium */ |
| #define | MID_0H 0x6C /* Multicast address MID0 High */ |
| #define | MID_1L 0x70 /* MID1 Low */ |
| #define | MID_1M 0x72 /* MID1 Medium */ |
| #define | MID_1H 0x74 /* MID1 High */ |
| #define | MID_2L 0x78 /* MID2 Low */ |
| #define | MID_2M 0x7A /* MID2 Medium */ |
| #define | MID_2H 0x7C /* MID2 High */ |
| #define | MID_3L 0x80 /* MID3 Low */ |
| #define | MID_3M 0x82 /* MID3 Medium */ |
| #define | MID_3H 0x84 /* MID3 High */ |
| #define | PHY_CC 0x88 /* PHY status change configuration register */ |
| #define | SCEN 0x8000 /* PHY status change enable */ |
| #define | PHYAD_SHIFT 8 /* PHY address shift */ |
| #define | TMRDIV_SHIFT 0 /* Timer divider shift */ |
| #define | PHY_ST 0x8A /* PHY status register */ |
| #define | MAC_SM 0xAC /* MAC status machine */ |
| #define | MAC_SM_RST 0x0002 /* MAC status machine reset */ |
| #define | MAC_ID 0xBE /* Identifier register */ |
| #define | TX_DCNT 0x80 /* TX descriptor count */ |
| #define | RX_DCNT 0x80 /* RX descriptor count */ |
| #define | MAX_BUF_SIZE 0x600 |
| #define | RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor)) |
| #define | TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor)) |
| #define | MBCR_DEFAULT 0x012A /* MAC Bus Control Register */ |
| #define | MCAST_MAX 3 /* Max number multicast addresses to filter */ |
| #define | MAC_DEF_TIMEOUT 2048 /* Default MAC read/write operation timeout */ |
| #define | DSC_OWNER_MAC 0x8000 /* MAC is the owner of this descriptor */ |
| #define | DSC_RX_OK 0x4000 /* RX was successful */ |
| #define | DSC_RX_ERR 0x0800 /* RX PHY error */ |
| #define | DSC_RX_ERR_DRI 0x0400 /* RX dribble packet */ |
| #define | DSC_RX_ERR_BUF 0x0200 /* RX length exceeds buffer size */ |
| #define | DSC_RX_ERR_LONG 0x0100 /* RX length > maximum packet length */ |
| #define | DSC_RX_ERR_RUNT 0x0080 /* RX packet length < 64 byte */ |
| #define | DSC_RX_ERR_CRC 0x0040 /* RX CRC error */ |
| #define | DSC_RX_BCAST 0x0020 /* RX broadcast (no error) */ |
| #define | DSC_RX_MCAST 0x0010 /* RX multicast (no error) */ |
| #define | DSC_RX_MCH_HIT 0x0008 /* RX multicast hit in hash table (no error) */ |
| #define | DSC_RX_MIDH_HIT 0x0004 /* RX MID table hit (no error) */ |
| #define | DSC_RX_IDX_MID_MASK 3 /* RX mask for the index of matched MIDx */ |
| #define | RX_INTS (RX_FIFO_FULL | RX_NO_DESC | RX_FINISH) |
| #define | TX_INTS (TX_FINISH) |
| #define | INT_MASK (RX_INTS | TX_INTS) |
Functions | |
| MODULE_AUTHOR ("Sten Wang <[email protected]>,""Daniel Gimpelevich <[email protected]>,""Florian Fainelli <[email protected]>") | |
| MODULE_LICENSE ("GPL") | |
| MODULE_DESCRIPTION ("RDC R6040 NAPI PCI FastEthernet driver") | |
| MODULE_VERSION (DRV_VERSION" "DRV_RELDATE) | |
| struct r6040_descriptor | __aligned (32) |
| MODULE_DEVICE_TABLE (pci, r6040_pci_tbl) | |
| module_pci_driver (r6040_driver) | |
Variables | |
| u16 | status |
| u16 | len |
| __le32 | buf |
| __le32 | ndesc |
| u32 | rev1 |
| char * | vbufp |
| struct r6040_descriptor * | vndescp |
| struct sk_buff * | skb_ptr |
| u32 | rev2 |
| struct r6040_private | __aligned |
| #define DSC_OWNER_MAC 0x8000 /* MAC is the owner of this descriptor */ |
| #define DSC_RX_ERR_BUF 0x0200 /* RX length exceeds buffer size */ |
| #define DSC_RX_ERR_LONG 0x0100 /* RX length > maximum packet length */ |
| #define DSC_RX_ERR_RUNT 0x0080 /* RX packet length < 64 byte */ |
| #define DSC_RX_MCH_HIT 0x0008 /* RX multicast hit in hash table (no error) */ |
| #define DSC_RX_MIDH_HIT 0x0004 /* RX MID table hit (no error) */ |
| #define MCR0_HASH_EN 0x0100 /* Enable multicast hash table function */ |
| #define MR_CNT 0x50 /* Successfully received packet counter */ |
| #define MT_CNT 0x5A /* Successfully transmit packet counter */ |
| #define PHY_CC 0x88 /* PHY status change configuration register */ |
| #define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor)) |
| #define RX_INTS (RX_FIFO_FULL | RX_NO_DESC | RX_FINISH) |
| #define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor)) |
| struct r6040_descriptor __aligned | ( | 32 | ) |
| MODULE_AUTHOR | ( | "Sten Wang <[email protected]> | , |
| ""Daniel Gimpelevich< daniel @gimpelevich.san-francisco.ca.us > | , | ||
| ""Florian Fainelli< florian @openwrt.org >" | |||
| ) |
| MODULE_DEVICE_TABLE | ( | pci | , |
| r6040_pci_tbl | |||
| ) |
| MODULE_LICENSE | ( | "GPL" | ) |
| module_pci_driver | ( | r6040_driver | ) |
| MODULE_VERSION | ( | DRV_VERSION" " | DRV_RELDATE | ) |
| struct r6040_private __aligned |
| struct r6040_descriptor* vndescp |
1.8.2