ux500_msp_i2s.h File Reference

#include <linux/platform_device.h>
#include <mach/msp.h>

Go to the source code of this file.

Data Structures
struct	msp_multichannel_config
struct	msp_protdesc
struct	i2s_message
struct	i2s_controller
struct	ux500_msp_config
struct	ux500_msp
struct	ux500_msp_dma_params

Macros
#define	MSP_INPUT_FREQ_APB   48000000
#define	MSP_BIG_ENDIAN   0x00000000
#define	MSP_LITTLE_ENDIAN   0x00001000
#define	MSP_UNEXPECTED_FS_ABORT   0x00000000
#define	MSP_UNEXPECTED_FS_IGNORE   0x00008000
#define	MSP_NON_MODE_BIT_MASK   0x00009000
#define	RX_ENABLE   0x00000001
#define	RX_FIFO_ENABLE   0x00000002
#define	RX_SYNC_SRG   0x00000010
#define	RX_CLK_POL_RISING   0x00000020
#define	RX_CLK_SEL_SRG   0x00000040
#define	TX_ENABLE   0x00000100
#define	TX_FIFO_ENABLE   0x00000200
#define	TX_SYNC_SRG_PROG   0x00001800
#define	TX_SYNC_SRG_AUTO   0x00001000
#define	TX_CLK_POL_RISING   0x00002000
#define	TX_CLK_SEL_SRG   0x00004000
#define	TX_EXTRA_DELAY_ENABLE   0x00008000
#define	SRG_ENABLE   0x00010000
#define	FRAME_GEN_ENABLE   0x00100000
#define	SRG_CLK_SEL_APB   0x00000000
#define	RX_FIFO_SYNC_HI   0x00000000
#define	TX_FIFO_SYNC_HI   0x00000000
#define	SPI_CLK_MODE_NORMAL   0x00000000
#define	MSP_FRAME_SIZE_AUTO   -1
#define	MSP_DR   0x00
#define	MSP_GCR   0x04
#define	MSP_TCF   0x08
#define	MSP_RCF   0x0c
#define	MSP_SRG   0x10
#define	MSP_FLR   0x14
#define	MSP_DMACR   0x18
#define	MSP_IMSC   0x20
#define	MSP_RIS   0x24
#define	MSP_MIS   0x28
#define	MSP_ICR   0x2c
#define	MSP_MCR   0x30
#define	MSP_RCV   0x34
#define	MSP_RCM   0x38
#define	MSP_TCE0   0x40
#define	MSP_TCE1   0x44
#define	MSP_TCE2   0x48
#define	MSP_TCE3   0x4c
#define	MSP_RCE0   0x60
#define	MSP_RCE1   0x64
#define	MSP_RCE2   0x68
#define	MSP_RCE3   0x6c
#define	MSP_IODLY   0x70
#define	MSP_ITCR   0x80
#define	MSP_ITIP   0x84
#define	MSP_ITOP   0x88
#define	MSP_TSTDR   0x8c
#define	MSP_PID0   0xfe0
#define	MSP_PID1   0xfe4
#define	MSP_PID2   0xfe8
#define	MSP_PID3   0xfec
#define	MSP_CID0   0xff0
#define	MSP_CID1   0xff4
#define	MSP_CID2   0xff8
#define	MSP_CID3   0xffc
#define	RX_ENABLE_MASK   BIT(0)
#define	RX_FIFO_ENABLE_MASK   BIT(1)
#define	RX_FSYNC_MASK   BIT(2)
#define	DIRECT_COMPANDING_MASK   BIT(3)
#define	RX_SYNC_SEL_MASK   BIT(4)
#define	RX_CLK_POL_MASK   BIT(5)
#define	RX_CLK_SEL_MASK   BIT(6)
#define	LOOPBACK_MASK   BIT(7)
#define	TX_ENABLE_MASK   BIT(8)
#define	TX_FIFO_ENABLE_MASK   BIT(9)
#define	TX_FSYNC_MASK   BIT(10)
#define	TX_MSP_TDR_TSR   BIT(11)
#define	TX_SYNC_SEL_MASK   (BIT(12) | BIT(11))
#define	TX_CLK_POL_MASK   BIT(13)
#define	TX_CLK_SEL_MASK   BIT(14)
#define	TX_EXTRA_DELAY_MASK   BIT(15)
#define	SRG_ENABLE_MASK   BIT(16)
#define	SRG_CLK_POL_MASK   BIT(17)
#define	SRG_CLK_SEL_MASK   (BIT(19) | BIT(18))
#define	FRAME_GEN_EN_MASK   BIT(20)
#define	SPI_CLK_MODE_MASK   (BIT(22) | BIT(21))
#define	SPI_BURST_MODE_MASK   BIT(23)
#define	RXEN_SHIFT   0
#define	RFFEN_SHIFT   1
#define	RFSPOL_SHIFT   2
#define	DCM_SHIFT   3
#define	RFSSEL_SHIFT   4
#define	RCKPOL_SHIFT   5
#define	RCKSEL_SHIFT   6
#define	LBM_SHIFT   7
#define	TXEN_SHIFT   8
#define	TFFEN_SHIFT   9
#define	TFSPOL_SHIFT   10
#define	TFSSEL_SHIFT   11
#define	TCKPOL_SHIFT   13
#define	TCKSEL_SHIFT   14
#define	TXDDL_SHIFT   15
#define	SGEN_SHIFT   16
#define	SCKPOL_SHIFT   17
#define	SCKSEL_SHIFT   18
#define	FGEN_SHIFT   20
#define	SPICKM_SHIFT   21
#define	TBSWAP_SHIFT   28
#define	RCKPOL_MASK   BIT(0)
#define	TCKPOL_MASK   BIT(0)
#define	SPICKM_MASK   (BIT(1) | BIT(0))
#define	MSP_RX_CLKPOL_BIT(n)   ((n & RCKPOL_MASK) << RCKPOL_SHIFT)
#define	MSP_TX_CLKPOL_BIT(n)   ((n & TCKPOL_MASK) << TCKPOL_SHIFT)
#define	P1ELEN_SHIFT   0
#define	P1FLEN_SHIFT   3
#define	DTYP_SHIFT   10
#define	ENDN_SHIFT   12
#define	DDLY_SHIFT   13
#define	FSIG_SHIFT   15
#define	P2ELEN_SHIFT   16
#define	P2FLEN_SHIFT   19
#define	P2SM_SHIFT   26
#define	P2EN_SHIFT   27
#define	FSYNC_SHIFT   15
#define	P1ELEN_MASK   0x00000007
#define	P2ELEN_MASK   0x00070000
#define	P1FLEN_MASK   0x00000378
#define	P2FLEN_MASK   0x03780000
#define	DDLY_MASK   0x00003000
#define	DTYP_MASK   0x00000600
#define	P2SM_MASK   0x04000000
#define	P2EN_MASK   0x08000000
#define	ENDN_MASK   0x00001000
#define	TFSPOL_MASK   0x00000400
#define	TBSWAP_MASK   0x30000000
#define	COMPANDING_MODE_MASK   0x00000c00
#define	FSYNC_MASK   0x00008000
#define	MSP_P1_ELEM_LEN_BITS(n)   (n & P1ELEN_MASK)
#define	MSP_P2_ELEM_LEN_BITS(n)   (((n) << P2ELEN_SHIFT) & P2ELEN_MASK)
#define	MSP_P1_FRAME_LEN_BITS(n)   (((n) << P1FLEN_SHIFT) & P1FLEN_MASK)
#define	MSP_P2_FRAME_LEN_BITS(n)   (((n) << P2FLEN_SHIFT) & P2FLEN_MASK)
#define	MSP_DATA_DELAY_BITS(n)   (((n) << DDLY_SHIFT) & DDLY_MASK)
#define	MSP_DATA_TYPE_BITS(n)   (((n) << DTYP_SHIFT) & DTYP_MASK)
#define	MSP_P2_START_MODE_BIT(n)   ((n << P2SM_SHIFT) & P2SM_MASK)
#define	MSP_P2_ENABLE_BIT(n)   ((n << P2EN_SHIFT) & P2EN_MASK)
#define	MSP_SET_ENDIANNES_BIT(n)   ((n << ENDN_SHIFT) & ENDN_MASK)
#define	MSP_FSYNC_POL(n)   ((n << TFSPOL_SHIFT) & TFSPOL_MASK)
#define	MSP_DATA_WORD_SWAP(n)   ((n << TBSWAP_SHIFT) & TBSWAP_MASK)
#define	MSP_SET_COMPANDING_MODE(n)
#define	MSP_SET_FSYNC_IGNORE(n)   ((n << FSYNC_SHIFT) & FSYNC_MASK)
#define	RX_BUSY   BIT(0)
#define	RX_FIFO_EMPTY   BIT(1)
#define	RX_FIFO_FULL   BIT(2)
#define	TX_BUSY   BIT(3)
#define	TX_FIFO_EMPTY   BIT(4)
#define	TX_FIFO_FULL   BIT(5)
#define	RBUSY_SHIFT   0
#define	RFE_SHIFT   1
#define	RFU_SHIFT   2
#define	TBUSY_SHIFT   3
#define	TFE_SHIFT   4
#define	TFU_SHIFT   5
#define	RMCEN_SHIFT   0
#define	RMCSF_SHIFT   1
#define	RCMPM_SHIFT   3
#define	TMCEN_SHIFT   5
#define	TNCSF_SHIFT   6
#define	SCKDIV_SHIFT   0
#define	FRWID_SHIFT   10
#define	FRPER_SHIFT   16
#define	SCK_DIV_MASK   0x0000003FF
#define	FRAME_WIDTH_BITS(n)   (((n) << FRWID_SHIFT) & 0x0000FC00)
#define	FRAME_PERIOD_BITS(n)   (((n) << FRPER_SHIFT) & 0x1FFF0000)
#define	RX_DMA_ENABLE   BIT(0)
#define	TX_DMA_ENABLE   BIT(1)
#define	RDMAE_SHIFT   0
#define	TDMAE_SHIFT   1
#define	RX_SERVICE_INT   BIT(0)
#define	RX_OVERRUN_ERROR_INT   BIT(1)
#define	RX_FSYNC_ERR_INT   BIT(2)
#define	RX_FSYNC_INT   BIT(3)
#define	TX_SERVICE_INT   BIT(4)
#define	TX_UNDERRUN_ERR_INT   BIT(5)
#define	TX_FSYNC_ERR_INT   BIT(6)
#define	TX_FSYNC_INT   BIT(7)
#define	ALL_INT   0x000000ff
#define	MSP_ITCR_ITEN   BIT(0)
#define	MSP_ITCR_TESTFIFO   BIT(1)
#define	RMCEN_BIT   0
#define	RMCSF_BIT   1
#define	RCMPM_BIT   3
#define	TMCEN_BIT   5
#define	TNCSF_BIT   6
#define	MSP_FRAME_PERIOD_IN_MONO_MODE   256
#define	MSP_FRAME_PERIOD_IN_STEREO_MODE   32
#define	MSP_FRAME_WIDTH_IN_STEREO_MODE   16
#define	MAX_MSP_BACKUP_REGS   36

Enumerations
enum	msp_stereo_mode { MSP_MONO, MSP_STEREO }
enum	msp_direction { MSP_TX = 1, MSP_RX = 2 }
enum	msp_phase_mode { MSP_SINGLE_PHASE, MSP_DUAL_PHASE }
enum	msp_frame_length {   MSP_FRAME_LEN_1 = 0, MSP_FRAME_LEN_2 = 1, MSP_FRAME_LEN_4 = 3, MSP_FRAME_LEN_8 = 7,   MSP_FRAME_LEN_12 = 11, MSP_FRAME_LEN_16 = 15, MSP_FRAME_LEN_20 = 19, MSP_FRAME_LEN_32 = 31,   MSP_FRAME_LEN_48 = 47, MSP_FRAME_LEN_64 = 63 }
enum	msp_elem_length {   MSP_ELEM_LEN_8 = 0, MSP_ELEM_LEN_10 = 1, MSP_ELEM_LEN_12 = 2, MSP_ELEM_LEN_14 = 3,   MSP_ELEM_LEN_16 = 4, MSP_ELEM_LEN_20 = 5, MSP_ELEM_LEN_24 = 6, MSP_ELEM_LEN_32 = 7 }
enum	msp_data_xfer_width { MSP_DATA_TRANSFER_WIDTH_BYTE, MSP_DATA_TRANSFER_WIDTH_HALFWORD, MSP_DATA_TRANSFER_WIDTH_WORD }
enum	msp_frame_sync { MSP_FSYNC_UNIGNORE = 0, MSP_FSYNC_IGNORE = 1 }
enum	msp_phase2_start_mode { MSP_PHASE2_START_MODE_IMEDIATE, MSP_PHASE2_START_MODE_FSYNC }
enum	msp_btf { MSP_BTF_MS_BIT_FIRST = 0, MSP_BTF_LS_BIT_FIRST = 1 }
enum	msp_fsync_pol { MSP_FSYNC_POL_ACT_HI = 0, MSP_FSYNC_POL_ACT_LO = 1 }
enum	msp_delay { MSP_DELAY_0 = 0, MSP_DELAY_1 = 1, MSP_DELAY_2 = 2, MSP_DELAY_3 = 3 }
enum	msp_edge { MSP_FALLING_EDGE = 0, MSP_RISING_EDGE = 1 }
enum	msp_hws { MSP_SWAP_NONE = 0, MSP_SWAP_BYTE_PER_WORD = 1, MSP_SWAP_BYTE_PER_HALF_WORD = 2, MSP_SWAP_HALF_WORD_PER_WORD = 3 }
enum	msp_compress_mode { MSP_COMPRESS_MODE_LINEAR = 0, MSP_COMPRESS_MODE_MU_LAW = 2, MSP_COMPRESS_MODE_A_LAW = 3 }
enum	msp_spi_burst_mode { MSP_SPI_BURST_MODE_DISABLE = 0, MSP_SPI_BURST_MODE_ENABLE = 1 }
enum	msp_expand_mode { MSP_EXPAND_MODE_LINEAR = 0, MSP_EXPAND_MODE_LINEAR_SIGNED = 1, MSP_EXPAND_MODE_MU_LAW = 2, MSP_EXPAND_MODE_A_LAW = 3 }
enum	msp_protocol { MSP_I2S_PROTOCOL, MSP_PCM_PROTOCOL, MSP_PCM_COMPAND_PROTOCOL, MSP_INVALID_PROTOCOL }
enum	enum_i2s_controller { MSP_0_I2S_CONTROLLER = 0, MSP_1_I2S_CONTROLLER, MSP_2_I2S_CONTROLLER, MSP_3_I2S_CONTROLLER }
enum	i2s_direction_t { MSP_DIR_TX = 0x01, MSP_DIR_RX = 0x02 }
enum	msp_data_size {   MSP_DATA_BITS_DEFAULT = -1, MSP_DATA_BITS_8 = 0x00, MSP_DATA_BITS_10, MSP_DATA_BITS_12,   MSP_DATA_BITS_14, MSP_DATA_BITS_16, MSP_DATA_BITS_20, MSP_DATA_BITS_24,   MSP_DATA_BITS_32 }
enum	msp_state { MSP_STATE_IDLE = 0, MSP_STATE_CONFIGURED = 1, MSP_STATE_RUNNING = 2 }
enum	msp_rx_comparison_enable_mode { MSP_COMPARISON_DISABLED = 0, MSP_COMPARISON_NONEQUAL_ENABLED = 2, MSP_COMPARISON_EQUAL_ENABLED = 3 }

Functions
int	ux500_msp_i2s_init_msp (struct platform_device *pdev, struct ux500_msp **msp_p, struct msp_i2s_platform_data *platform_data)
void	ux500_msp_i2s_cleanup_msp (struct platform_device *pdev, struct ux500_msp *msp)
int	ux500_msp_i2s_open (struct ux500_msp *msp, struct ux500_msp_config *config)
int	ux500_msp_i2s_close (struct ux500_msp *msp, unsigned int dir)
int	ux500_msp_i2s_trigger (struct ux500_msp *msp, int cmd, int direction)

Macro Definition Documentation

#define ALL_INT   0x000000ff

Definition at line 249 of file ux500_msp_i2s.h.

#define COMPANDING_MODE_MASK   0x00000c00

Definition at line 184 of file ux500_msp_i2s.h.

#define DCM_SHIFT   3

Definition at line 136 of file ux500_msp_i2s.h.

#define DDLY_MASK   0x00003000

Definition at line 177 of file ux500_msp_i2s.h.

#define DDLY_SHIFT   13

Definition at line 165 of file ux500_msp_i2s.h.

#define DIRECT_COMPANDING_MASK   BIT(3)

Definition at line 113 of file ux500_msp_i2s.h.

#define DTYP_MASK   0x00000600

Definition at line 178 of file ux500_msp_i2s.h.

#define DTYP_SHIFT   10

Definition at line 163 of file ux500_msp_i2s.h.

#define ENDN_MASK   0x00001000

Definition at line 181 of file ux500_msp_i2s.h.

#define ENDN_SHIFT   12

Definition at line 164 of file ux500_msp_i2s.h.

#define FGEN_SHIFT   20

Definition at line 151 of file ux500_msp_i2s.h.

#define FRAME_GEN_EN_MASK   BIT(20)

Definition at line 129 of file ux500_msp_i2s.h.

#define FRAME_GEN_ENABLE   0x00100000

Definition at line 59 of file ux500_msp_i2s.h.

#define FRAME_PERIOD_BITS

(

n

)

(((n) << FRPER_SHIFT) & 0x1FFF0000)

Definition at line 231 of file ux500_msp_i2s.h.

#define FRAME_WIDTH_BITS

(

n

)

(((n) << FRWID_SHIFT) & 0x0000FC00)

Definition at line 230 of file ux500_msp_i2s.h.

#define FRPER_SHIFT   16

Definition at line 227 of file ux500_msp_i2s.h.

#define FRWID_SHIFT   10

Definition at line 226 of file ux500_msp_i2s.h.

#define FSIG_SHIFT   15

Definition at line 166 of file ux500_msp_i2s.h.

#define FSYNC_MASK   0x00008000

Definition at line 185 of file ux500_msp_i2s.h.

#define FSYNC_SHIFT   15

Definition at line 171 of file ux500_msp_i2s.h.

#define LBM_SHIFT   7

Definition at line 140 of file ux500_msp_i2s.h.

#define LOOPBACK_MASK   BIT(7)

Definition at line 117 of file ux500_msp_i2s.h.

#define MAX_MSP_BACKUP_REGS   36

Definition at line 373 of file ux500_msp_i2s.h.

#define MSP_BIG_ENDIAN   0x00000000

Definition at line 39 of file ux500_msp_i2s.h.

#define MSP_CID0   0xff0

Definition at line 104 of file ux500_msp_i2s.h.

#define MSP_CID1   0xff4

Definition at line 105 of file ux500_msp_i2s.h.

#define MSP_CID2   0xff8

Definition at line 106 of file ux500_msp_i2s.h.

#define MSP_CID3   0xffc

Definition at line 107 of file ux500_msp_i2s.h.

#define MSP_DATA_DELAY_BITS

(

n

)

(((n) << DDLY_SHIFT) & DDLY_MASK)

Definition at line 191 of file ux500_msp_i2s.h.

#define MSP_DATA_TYPE_BITS

(

n

)

(((n) << DTYP_SHIFT) & DTYP_MASK)

Definition at line 192 of file ux500_msp_i2s.h.

#define MSP_DATA_WORD_SWAP

(

n

)

((n << TBSWAP_SHIFT) & TBSWAP_MASK)

Definition at line 197 of file ux500_msp_i2s.h.

#define MSP_DMACR   0x18

Definition at line 73 of file ux500_msp_i2s.h.

#define MSP_DR   0x00

Definition at line 67 of file ux500_msp_i2s.h.

#define MSP_FLR   0x14

Definition at line 72 of file ux500_msp_i2s.h.

#define MSP_FRAME_PERIOD_IN_MONO_MODE   256

Definition at line 358 of file ux500_msp_i2s.h.

#define MSP_FRAME_PERIOD_IN_STEREO_MODE   32

Definition at line 359 of file ux500_msp_i2s.h.

#define MSP_FRAME_SIZE_AUTO   -1

Definition at line 65 of file ux500_msp_i2s.h.

#define MSP_FRAME_WIDTH_IN_STEREO_MODE   16

Definition at line 360 of file ux500_msp_i2s.h.

#define MSP_FSYNC_POL

(

n

)

((n << TFSPOL_SHIFT) & TFSPOL_MASK)

Definition at line 196 of file ux500_msp_i2s.h.

#define MSP_GCR   0x04

Definition at line 68 of file ux500_msp_i2s.h.

#define MSP_ICR   0x2c

Definition at line 78 of file ux500_msp_i2s.h.

#define MSP_IMSC   0x20

Definition at line 75 of file ux500_msp_i2s.h.

#define MSP_INPUT_FREQ_APB   48000000

Definition at line 22 of file ux500_msp_i2s.h.

#define MSP_IODLY   0x70

Definition at line 92 of file ux500_msp_i2s.h.

#define MSP_ITCR   0x80

Definition at line 94 of file ux500_msp_i2s.h.

#define MSP_ITCR_ITEN   BIT(0)

Definition at line 252 of file ux500_msp_i2s.h.

#define MSP_ITCR_TESTFIFO   BIT(1)

Definition at line 253 of file ux500_msp_i2s.h.

#define MSP_ITIP   0x84

Definition at line 95 of file ux500_msp_i2s.h.

#define MSP_ITOP   0x88

Definition at line 96 of file ux500_msp_i2s.h.

#define MSP_LITTLE_ENDIAN   0x00001000

Definition at line 40 of file ux500_msp_i2s.h.

#define MSP_MCR   0x30

Definition at line 79 of file ux500_msp_i2s.h.

#define MSP_MIS   0x28

Definition at line 77 of file ux500_msp_i2s.h.

#define MSP_NON_MODE_BIT_MASK   0x00009000

Definition at line 43 of file ux500_msp_i2s.h.

#define MSP_P1_ELEM_LEN_BITS

(

n

)

(n & P1ELEN_MASK)

Definition at line 187 of file ux500_msp_i2s.h.

#define MSP_P1_FRAME_LEN_BITS

(

n

)

(((n) << P1FLEN_SHIFT) & P1FLEN_MASK)

Definition at line 189 of file ux500_msp_i2s.h.

#define MSP_P2_ELEM_LEN_BITS

(

n

)

(((n) << P2ELEN_SHIFT) & P2ELEN_MASK)

Definition at line 188 of file ux500_msp_i2s.h.

#define MSP_P2_ENABLE_BIT

(

n

)

((n << P2EN_SHIFT) & P2EN_MASK)

Definition at line 194 of file ux500_msp_i2s.h.

#define MSP_P2_FRAME_LEN_BITS

(

n

)

(((n) << P2FLEN_SHIFT) & P2FLEN_MASK)

Definition at line 190 of file ux500_msp_i2s.h.

#define MSP_P2_START_MODE_BIT

(

n

)

((n << P2SM_SHIFT) & P2SM_MASK)

Definition at line 193 of file ux500_msp_i2s.h.

#define MSP_PID0   0xfe0

Definition at line 99 of file ux500_msp_i2s.h.

#define MSP_PID1   0xfe4

Definition at line 100 of file ux500_msp_i2s.h.

#define MSP_PID2   0xfe8

Definition at line 101 of file ux500_msp_i2s.h.

#define MSP_PID3   0xfec

Definition at line 102 of file ux500_msp_i2s.h.

#define MSP_RCE0   0x60

Definition at line 88 of file ux500_msp_i2s.h.

#define MSP_RCE1   0x64

Definition at line 89 of file ux500_msp_i2s.h.

#define MSP_RCE2   0x68

Definition at line 90 of file ux500_msp_i2s.h.

#define MSP_RCE3   0x6c

Definition at line 91 of file ux500_msp_i2s.h.

#define MSP_RCF   0x0c

Definition at line 70 of file ux500_msp_i2s.h.

#define MSP_RCM   0x38

Definition at line 81 of file ux500_msp_i2s.h.

#define MSP_RCV   0x34

Definition at line 80 of file ux500_msp_i2s.h.

#define MSP_RIS   0x24

Definition at line 76 of file ux500_msp_i2s.h.

#define MSP_RX_CLKPOL_BIT

(

n

)

((n & RCKPOL_MASK) << RCKPOL_SHIFT)

Definition at line 158 of file ux500_msp_i2s.h.

#define MSP_SET_COMPANDING_MODE

(

n

)

Value:

((n << DTYP_SHIFT) & \
                        COMPANDING_MODE_MASK)

Definition at line 198 of file ux500_msp_i2s.h.

#define MSP_SET_ENDIANNES_BIT

(

n

)

((n << ENDN_SHIFT) & ENDN_MASK)

Definition at line 195 of file ux500_msp_i2s.h.

#define MSP_SET_FSYNC_IGNORE

(

n

)

((n << FSYNC_SHIFT) & FSYNC_MASK)

Definition at line 200 of file ux500_msp_i2s.h.

#define MSP_SRG   0x10

Definition at line 71 of file ux500_msp_i2s.h.

#define MSP_TCE0   0x40

Definition at line 83 of file ux500_msp_i2s.h.

#define MSP_TCE1   0x44

Definition at line 84 of file ux500_msp_i2s.h.

#define MSP_TCE2   0x48

Definition at line 85 of file ux500_msp_i2s.h.

#define MSP_TCE3   0x4c

Definition at line 86 of file ux500_msp_i2s.h.

#define MSP_TCF   0x08

Definition at line 69 of file ux500_msp_i2s.h.

#define MSP_TSTDR   0x8c

Definition at line 97 of file ux500_msp_i2s.h.

#define MSP_TX_CLKPOL_BIT

(

n

)

((n & TCKPOL_MASK) << TCKPOL_SHIFT)

Definition at line 159 of file ux500_msp_i2s.h.

#define MSP_UNEXPECTED_FS_ABORT   0x00000000

Definition at line 41 of file ux500_msp_i2s.h.

#define MSP_UNEXPECTED_FS_IGNORE   0x00008000

Definition at line 42 of file ux500_msp_i2s.h.

#define P1ELEN_MASK   0x00000007

Definition at line 173 of file ux500_msp_i2s.h.

#define P1ELEN_SHIFT   0

Definition at line 161 of file ux500_msp_i2s.h.

#define P1FLEN_MASK   0x00000378

Definition at line 175 of file ux500_msp_i2s.h.

#define P1FLEN_SHIFT   3

Definition at line 162 of file ux500_msp_i2s.h.

#define P2ELEN_MASK   0x00070000

Definition at line 174 of file ux500_msp_i2s.h.

#define P2ELEN_SHIFT   16

Definition at line 167 of file ux500_msp_i2s.h.

#define P2EN_MASK   0x08000000

Definition at line 180 of file ux500_msp_i2s.h.

#define P2EN_SHIFT   27

Definition at line 170 of file ux500_msp_i2s.h.

#define P2FLEN_MASK   0x03780000

Definition at line 176 of file ux500_msp_i2s.h.

#define P2FLEN_SHIFT   19

Definition at line 168 of file ux500_msp_i2s.h.

#define P2SM_MASK   0x04000000

Definition at line 179 of file ux500_msp_i2s.h.

#define P2SM_SHIFT   26

Definition at line 169 of file ux500_msp_i2s.h.

#define RBUSY_SHIFT   0

Definition at line 210 of file ux500_msp_i2s.h.

#define RCKPOL_MASK   BIT(0)

Definition at line 155 of file ux500_msp_i2s.h.

#define RCKPOL_SHIFT   5

Definition at line 138 of file ux500_msp_i2s.h.

#define RCKSEL_SHIFT   6

Definition at line 139 of file ux500_msp_i2s.h.

#define RCMPM_BIT   3

Definition at line 257 of file ux500_msp_i2s.h.

#define RCMPM_SHIFT   3

Definition at line 220 of file ux500_msp_i2s.h.

#define RDMAE_SHIFT   0

Definition at line 237 of file ux500_msp_i2s.h.

#define RFE_SHIFT   1

Definition at line 211 of file ux500_msp_i2s.h.

#define RFFEN_SHIFT   1

Definition at line 134 of file ux500_msp_i2s.h.

#define RFSPOL_SHIFT   2

Definition at line 135 of file ux500_msp_i2s.h.

#define RFSSEL_SHIFT   4

Definition at line 137 of file ux500_msp_i2s.h.

#define RFU_SHIFT   2

Definition at line 212 of file ux500_msp_i2s.h.

#define RMCEN_BIT   0

Definition at line 255 of file ux500_msp_i2s.h.

#define RMCEN_SHIFT   0

Definition at line 218 of file ux500_msp_i2s.h.

#define RMCSF_BIT   1

Definition at line 256 of file ux500_msp_i2s.h.

#define RMCSF_SHIFT   1

Definition at line 219 of file ux500_msp_i2s.h.

#define RX_BUSY   BIT(0)

Definition at line 203 of file ux500_msp_i2s.h.

#define RX_CLK_POL_MASK   BIT(5)

Definition at line 115 of file ux500_msp_i2s.h.

#define RX_CLK_POL_RISING   0x00000020

Definition at line 49 of file ux500_msp_i2s.h.

#define RX_CLK_SEL_MASK   BIT(6)

Definition at line 116 of file ux500_msp_i2s.h.

#define RX_CLK_SEL_SRG   0x00000040

Definition at line 50 of file ux500_msp_i2s.h.

#define RX_DMA_ENABLE   BIT(0)

Definition at line 234 of file ux500_msp_i2s.h.

#define RX_ENABLE   0x00000001

Definition at line 46 of file ux500_msp_i2s.h.

#define RX_ENABLE_MASK   BIT(0)

Definition at line 110 of file ux500_msp_i2s.h.

#define RX_FIFO_EMPTY   BIT(1)

Definition at line 204 of file ux500_msp_i2s.h.

#define RX_FIFO_ENABLE   0x00000002

Definition at line 47 of file ux500_msp_i2s.h.

#define RX_FIFO_ENABLE_MASK   BIT(1)

Definition at line 111 of file ux500_msp_i2s.h.

#define RX_FIFO_FULL   BIT(2)

Definition at line 205 of file ux500_msp_i2s.h.

#define RX_FIFO_SYNC_HI   0x00000000

Definition at line 61 of file ux500_msp_i2s.h.

#define RX_FSYNC_ERR_INT   BIT(2)

Definition at line 243 of file ux500_msp_i2s.h.

#define RX_FSYNC_INT   BIT(3)

Definition at line 244 of file ux500_msp_i2s.h.

#define RX_FSYNC_MASK   BIT(2)

Definition at line 112 of file ux500_msp_i2s.h.

#define RX_OVERRUN_ERROR_INT   BIT(1)

Definition at line 242 of file ux500_msp_i2s.h.

#define RX_SERVICE_INT   BIT(0)

Definition at line 241 of file ux500_msp_i2s.h.

#define RX_SYNC_SEL_MASK   BIT(4)

Definition at line 114 of file ux500_msp_i2s.h.

#define RX_SYNC_SRG   0x00000010

Definition at line 48 of file ux500_msp_i2s.h.

#define RXEN_SHIFT   0

Definition at line 133 of file ux500_msp_i2s.h.

#define SCK_DIV_MASK   0x0000003FF

Definition at line 229 of file ux500_msp_i2s.h.

#define SCKDIV_SHIFT   0

Definition at line 225 of file ux500_msp_i2s.h.

#define SCKPOL_SHIFT   17

Definition at line 149 of file ux500_msp_i2s.h.

#define SCKSEL_SHIFT   18

Definition at line 150 of file ux500_msp_i2s.h.

#define SGEN_SHIFT   16

Definition at line 148 of file ux500_msp_i2s.h.

#define SPI_BURST_MODE_MASK   BIT(23)

Definition at line 131 of file ux500_msp_i2s.h.

#define SPI_CLK_MODE_MASK   (BIT(22) | BIT(21))

Definition at line 130 of file ux500_msp_i2s.h.

#define SPI_CLK_MODE_NORMAL   0x00000000

Definition at line 63 of file ux500_msp_i2s.h.

#define SPICKM_MASK   (BIT(1) | BIT(0))

Definition at line 157 of file ux500_msp_i2s.h.

#define SPICKM_SHIFT   21

Definition at line 152 of file ux500_msp_i2s.h.

#define SRG_CLK_POL_MASK   BIT(17)

Definition at line 127 of file ux500_msp_i2s.h.

#define SRG_CLK_SEL_APB   0x00000000

Definition at line 60 of file ux500_msp_i2s.h.

#define SRG_CLK_SEL_MASK   (BIT(19) | BIT(18))

Definition at line 128 of file ux500_msp_i2s.h.

#define SRG_ENABLE   0x00010000

Definition at line 58 of file ux500_msp_i2s.h.

#define SRG_ENABLE_MASK   BIT(16)

Definition at line 126 of file ux500_msp_i2s.h.

#define TBSWAP_MASK   0x30000000

Definition at line 183 of file ux500_msp_i2s.h.

#define TBSWAP_SHIFT   28

Definition at line 153 of file ux500_msp_i2s.h.

#define TBUSY_SHIFT   3

Definition at line 213 of file ux500_msp_i2s.h.

#define TCKPOL_MASK   BIT(0)

Definition at line 156 of file ux500_msp_i2s.h.

#define TCKPOL_SHIFT   13

Definition at line 145 of file ux500_msp_i2s.h.

#define TCKSEL_SHIFT   14

Definition at line 146 of file ux500_msp_i2s.h.

#define TDMAE_SHIFT   1

Definition at line 238 of file ux500_msp_i2s.h.

#define TFE_SHIFT   4

Definition at line 214 of file ux500_msp_i2s.h.

#define TFFEN_SHIFT   9

Definition at line 142 of file ux500_msp_i2s.h.

#define TFSPOL_MASK   0x00000400

Definition at line 182 of file ux500_msp_i2s.h.

#define TFSPOL_SHIFT   10

Definition at line 143 of file ux500_msp_i2s.h.

#define TFSSEL_SHIFT   11

Definition at line 144 of file ux500_msp_i2s.h.

#define TFU_SHIFT   5

Definition at line 215 of file ux500_msp_i2s.h.

#define TMCEN_BIT   5

Definition at line 258 of file ux500_msp_i2s.h.

#define TMCEN_SHIFT   5

Definition at line 221 of file ux500_msp_i2s.h.

#define TNCSF_BIT   6

Definition at line 259 of file ux500_msp_i2s.h.

#define TNCSF_SHIFT   6

Definition at line 222 of file ux500_msp_i2s.h.

#define TX_BUSY   BIT(3)

Definition at line 206 of file ux500_msp_i2s.h.

#define TX_CLK_POL_MASK   BIT(13)

Definition at line 123 of file ux500_msp_i2s.h.

#define TX_CLK_POL_RISING   0x00002000

Definition at line 55 of file ux500_msp_i2s.h.

#define TX_CLK_SEL_MASK   BIT(14)

Definition at line 124 of file ux500_msp_i2s.h.

#define TX_CLK_SEL_SRG   0x00004000

Definition at line 56 of file ux500_msp_i2s.h.

#define TX_DMA_ENABLE   BIT(1)

Definition at line 235 of file ux500_msp_i2s.h.

#define TX_ENABLE   0x00000100

Definition at line 51 of file ux500_msp_i2s.h.

#define TX_ENABLE_MASK   BIT(8)

Definition at line 118 of file ux500_msp_i2s.h.

#define TX_EXTRA_DELAY_ENABLE   0x00008000

Definition at line 57 of file ux500_msp_i2s.h.

#define TX_EXTRA_DELAY_MASK   BIT(15)

Definition at line 125 of file ux500_msp_i2s.h.

#define TX_FIFO_EMPTY   BIT(4)

Definition at line 207 of file ux500_msp_i2s.h.

#define TX_FIFO_ENABLE   0x00000200

Definition at line 52 of file ux500_msp_i2s.h.

#define TX_FIFO_ENABLE_MASK   BIT(9)

Definition at line 119 of file ux500_msp_i2s.h.

#define TX_FIFO_FULL   BIT(5)

Definition at line 208 of file ux500_msp_i2s.h.

#define TX_FIFO_SYNC_HI   0x00000000

Definition at line 62 of file ux500_msp_i2s.h.

#define TX_FSYNC_ERR_INT   BIT(6)

Definition at line 247 of file ux500_msp_i2s.h.

#define TX_FSYNC_INT   BIT(7)

Definition at line 248 of file ux500_msp_i2s.h.

#define TX_FSYNC_MASK   BIT(10)

Definition at line 120 of file ux500_msp_i2s.h.

#define TX_MSP_TDR_TSR   BIT(11)

Definition at line 121 of file ux500_msp_i2s.h.

#define TX_SERVICE_INT   BIT(4)

Definition at line 245 of file ux500_msp_i2s.h.

#define TX_SYNC_SEL_MASK   (BIT(12) | BIT(11))

Definition at line 122 of file ux500_msp_i2s.h.

#define TX_SYNC_SRG_AUTO   0x00001000

Definition at line 54 of file ux500_msp_i2s.h.

#define TX_SYNC_SRG_PROG   0x00001800

Definition at line 53 of file ux500_msp_i2s.h.

#define TX_UNDERRUN_ERR_INT   BIT(5)

Definition at line 246 of file ux500_msp_i2s.h.

#define TXDDL_SHIFT   15

Definition at line 147 of file ux500_msp_i2s.h.

#define TXEN_SHIFT   8

Definition at line 141 of file ux500_msp_i2s.h.

Enumeration Type Documentation

enum enum_i2s_controller

Enumerator:

MSP_0_I2S_CONTROLLER
MSP_1_I2S_CONTROLLER
MSP_2_I2S_CONTROLLER
MSP_3_I2S_CONTROLLER

Definition at line 375 of file ux500_msp_i2s.h.

enum i2s_direction_t

Enumerator:

MSP_DIR_TX
MSP_DIR_RX

Definition at line 382 of file ux500_msp_i2s.h.

enum msp_btf

Enumerator:

MSP_BTF_MS_BIT_FIRST
MSP_BTF_LS_BIT_FIRST

Definition at line 309 of file ux500_msp_i2s.h.

enum msp_compress_mode

Enumerator:

MSP_COMPRESS_MODE_LINEAR
MSP_COMPRESS_MODE_MU_LAW
MSP_COMPRESS_MODE_A_LAW

Definition at line 340 of file ux500_msp_i2s.h.

enum msp_data_size

Enumerator:

MSP_DATA_BITS_DEFAULT
MSP_DATA_BITS_8
MSP_DATA_BITS_10
MSP_DATA_BITS_12
MSP_DATA_BITS_14
MSP_DATA_BITS_16
MSP_DATA_BITS_20
MSP_DATA_BITS_24
MSP_DATA_BITS_32

Definition at line 387 of file ux500_msp_i2s.h.

enum msp_data_xfer_width

Enumerator:

MSP_DATA_TRANSFER_WIDTH_BYTE
MSP_DATA_TRANSFER_WIDTH_HALFWORD
MSP_DATA_TRANSFER_WIDTH_WORD

Definition at line 293 of file ux500_msp_i2s.h.

enum msp_delay

Enumerator:

MSP_DELAY_0
MSP_DELAY_1
MSP_DELAY_2
MSP_DELAY_3

Definition at line 320 of file ux500_msp_i2s.h.

enum msp_direction

Enumerator:

MSP_TX
MSP_RX

Definition at line 33 of file ux500_msp_i2s.h.

enum msp_edge

Enumerator:

MSP_FALLING_EDGE
MSP_RISING_EDGE

Definition at line 328 of file ux500_msp_i2s.h.

enum msp_elem_length

Enumerator:

MSP_ELEM_LEN_8
MSP_ELEM_LEN_10
MSP_ELEM_LEN_12
MSP_ELEM_LEN_14
MSP_ELEM_LEN_16
MSP_ELEM_LEN_20
MSP_ELEM_LEN_24
MSP_ELEM_LEN_32

Definition at line 282 of file ux500_msp_i2s.h.

enum msp_expand_mode

Enumerator:

MSP_EXPAND_MODE_LINEAR
MSP_EXPAND_MODE_LINEAR_SIGNED
MSP_EXPAND_MODE_MU_LAW
MSP_EXPAND_MODE_A_LAW

Definition at line 351 of file ux500_msp_i2s.h.

enum msp_frame_length

Enumerator:

MSP_FRAME_LEN_1
MSP_FRAME_LEN_2
MSP_FRAME_LEN_4
MSP_FRAME_LEN_8
MSP_FRAME_LEN_12
MSP_FRAME_LEN_16
MSP_FRAME_LEN_20
MSP_FRAME_LEN_32
MSP_FRAME_LEN_48
MSP_FRAME_LEN_64

Definition at line 268 of file ux500_msp_i2s.h.

enum msp_frame_sync

Enumerator:

MSP_FSYNC_UNIGNORE
MSP_FSYNC_IGNORE

Definition at line 299 of file ux500_msp_i2s.h.

enum msp_fsync_pol

Enumerator:

MSP_FSYNC_POL_ACT_HI
MSP_FSYNC_POL_ACT_LO

Definition at line 314 of file ux500_msp_i2s.h.

enum msp_hws

Enumerator:

MSP_SWAP_NONE
MSP_SWAP_BYTE_PER_WORD
MSP_SWAP_BYTE_PER_HALF_WORD
MSP_SWAP_HALF_WORD_PER_WORD

Definition at line 333 of file ux500_msp_i2s.h.

enum msp_phase2_start_mode

Enumerator:

MSP_PHASE2_START_MODE_IMEDIATE
MSP_PHASE2_START_MODE_FSYNC

Definition at line 304 of file ux500_msp_i2s.h.

enum msp_phase_mode

Enumerator:

MSP_SINGLE_PHASE
MSP_DUAL_PHASE

Definition at line 262 of file ux500_msp_i2s.h.

enum msp_protocol

Enumerator:

MSP_I2S_PROTOCOL
MSP_PCM_PROTOCOL
MSP_PCM_COMPAND_PROTOCOL
MSP_INVALID_PROTOCOL

Definition at line 362 of file ux500_msp_i2s.h.

enum msp_rx_comparison_enable_mode

Enumerator:

MSP_COMPARISON_DISABLED
MSP_COMPARISON_NONEQUAL_ENABLED
MSP_COMPARISON_EQUAL_ENABLED

Definition at line 405 of file ux500_msp_i2s.h.

enum msp_spi_burst_mode

Enumerator:

MSP_SPI_BURST_MODE_DISABLE
MSP_SPI_BURST_MODE_ENABLE

Definition at line 346 of file ux500_msp_i2s.h.

enum msp_state

Enumerator:

MSP_STATE_IDLE
MSP_STATE_CONFIGURED
MSP_STATE_RUNNING

Definition at line 399 of file ux500_msp_i2s.h.

enum msp_stereo_mode

Enumerator:

MSP_MONO
MSP_STEREO

Definition at line 27 of file ux500_msp_i2s.h.

Function Documentation

void ux500_msp_i2s_cleanup_msp	(	struct platform_device *	pdev,
		struct ux500_msp *	msp
	)

Definition at line 770 of file ux500_msp_i2s.c.

int ux500_msp_i2s_close	(	struct ux500_msp *	msp,
		unsigned int	dir
	)

Definition at line 633 of file ux500_msp_i2s.c.

int ux500_msp_i2s_init_msp	(	struct platform_device *	pdev,
		struct ux500_msp **	msp_p,
		struct msp_i2s_platform_data *	platform_data
	)

Definition at line 682 of file ux500_msp_i2s.c.

int ux500_msp_i2s_open	(	struct ux500_msp *	msp,
		struct ux500_msp_config *	config
	)

Definition at line 454 of file ux500_msp_i2s.c.

int ux500_msp_i2s_trigger	(	struct ux500_msp *	msp,
		int	cmd,
		int	direction
	)

Definition at line 595 of file ux500_msp_i2s.c.