14 #define MAX_H_POSITION 5
15 #define MAX_V_POSITION 5
25 #define H_TABLE_POS1 6
26 #define H_TABLE_POS2 8
34 #define NTSC_TV_CLOCK_T 233
35 #define NTSC_TV_VFTOTAL 1
36 #define NTSC_TV_LINES_PER_FRAME 525
37 #define NTSC_TV_ZERO_H_SIZE 479166
38 #define NTSC_TV_H_SIZE_UNIT 9478
40 #define PAL_TV_CLOCK_T 188
41 #define PAL_TV_VFTOTAL 3
42 #define PAL_TV_LINES_PER_FRAME 625
43 #define PAL_TV_ZERO_H_SIZE 473200
44 #define PAL_TV_H_SIZE_UNIT 9360
47 #define NTSC_TV_PLL_M_27 22
48 #define NTSC_TV_PLL_N_27 175
49 #define NTSC_TV_PLL_P_27 5
51 #define PAL_TV_PLL_M_27 113
52 #define PAL_TV_PLL_N_27 668
53 #define PAL_TV_PLL_P_27 3
56 #define NTSC_TV_PLL_M_14 33
57 #define NTSC_TV_PLL_N_14 693
58 #define NTSC_TV_PLL_P_14 7
60 #define PAL_TV_PLL_M_14 19
61 #define PAL_TV_PLL_N_14 353
62 #define PAL_TV_PLL_P_14 5
64 #define VERT_LEAD_IN_LINES 2
66 #define FRAC_MASK 0x3fff
232 #define N_AVAILABLE_MODES ARRAY_SIZE(available_tv_modes)
246 pll = &rdev->
clock.p2pll;
248 pll = &rdev->
clock.p1pll;
257 const_ptr = &available_tv_modes[0];
259 const_ptr = &available_tv_modes[2];
262 const_ptr = &available_tv_modes[1];
264 const_ptr = &available_tv_modes[3];
269 static long YCOEF_value[5] = { 2, 2, 0, 4, 0 };
270 static long YCOEF_EN_value[5] = { 1, 1, 0, 1, 0 };
271 static long SLOPE_value[5] = { 1, 2, 2, 4, 8 };
272 static long SLOPE_limit[5] = { 6, 5, 4, 3, 2 };
274 static void radeon_wait_pll_lock(
struct drm_encoder *encoder,
unsigned n_tests,
275 unsigned n_wait_loops,
unsigned cnt_threshold)
287 for (i = 0; i < n_tests; i++) {
289 for (j = 0; j < n_wait_loops; j++)
321 static uint32_t radeon_legacy_tv_read_fifo(
struct radeon_encoder *radeon_encoder,
uint16_t addr)
384 static void radeon_restore_tv_timing_tables(
struct radeon_encoder *radeon_encoder)
394 h_table = radeon_get_htiming_tables_addr(tv_dac->
tv.tv_uv_adr);
395 v_table = radeon_get_vtiming_tables_addr(tv_dac->
tv.tv_uv_adr);
398 tmp = ((
uint32_t)tv_dac->
tv.h_code_timing[i] << 14) | ((
uint32_t)tv_dac->
tv.h_code_timing[i+1]);
399 radeon_legacy_tv_write_fifo(radeon_encoder, h_table, tmp);
400 if (tv_dac->
tv.h_code_timing[i] == 0 || tv_dac->
tv.h_code_timing[i + 1] == 0)
404 tmp = ((
uint32_t)tv_dac->
tv.v_code_timing[i+1] << 14) | ((
uint32_t)tv_dac->
tv.v_code_timing[i]);
405 radeon_legacy_tv_write_fifo(radeon_encoder, v_table, tmp);
406 if (tv_dac->
tv.v_code_timing[i] == 0 || tv_dac->
tv.v_code_timing[i + 1] == 0)
411 static void radeon_legacy_write_tv_restarts(
struct radeon_encoder *radeon_encoder)
421 static bool radeon_legacy_tv_init_restarts(
struct drm_encoder *encoder)
429 unsigned int h_total, v_total, f_total;
430 int v_offset, h_offset;
438 pll = &rdev->
clock.p2pll;
440 pll = &rdev->
clock.p1pll;
442 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder,
NULL);
471 p1 = (
u16)((
int)p1 + h_offset);
472 p2 = (
u16)((
int)p2 - h_offset);
481 h_offset = (h_offset * (
int)(const_ptr->
pix_to_tv)) / 1000;
497 restart -= v_offset + h_offset;
499 DRM_DEBUG_KMS(
"compute_restarts: def = %u h = %d v = %d, p1 = %04x, p2 = %04x, restart = %d\n",
502 tv_dac->
tv.hrestart = restart % h_total;
504 tv_dac->
tv.vrestart = restart % v_total;
506 tv_dac->
tv.frestart = restart % f_total;
508 DRM_DEBUG_KMS(
"compute_restart: F/H/V=%u,%u,%u\n",
509 (
unsigned)tv_dac->
tv.frestart,
510 (
unsigned)tv_dac->
tv.vrestart,
511 (
unsigned)tv_dac->
tv.hrestart);
526 DRM_DEBUG_KMS(
"compute_restart: h_size = %d h_inc = %d\n", tv_dac->
h_size, h_inc);
540 struct radeon_crtc *radeon_crtc;
544 uint32_t tv_master_cntl, tv_rgb_cntl, tv_dac_cntl;
545 uint32_t tv_modulator_cntl1, tv_modulator_cntl2;
546 uint32_t tv_vscaler_cntl1, tv_vscaler_cntl2;
547 uint32_t tv_pll_cntl, tv_pll_cntl1, tv_ftotal;
548 uint32_t tv_y_fall_cntl, tv_y_rise_cntl, tv_y_saw_tooth_cntl;
553 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, &pll_ref_freq);
622 tmp |= (vert_space * (1 <<
FRAC_BITS) / 10000);
623 tv_vscaler_cntl1 =
tmp;
625 if (pll_ref_freq == 2700)
643 flicker_removal = (tmp + 500) / 1000;
645 if (flicker_removal < 3)
648 if (flicker_removal == SLOPE_limit[i])
652 tv_y_saw_tooth_cntl = (vert_space * SLOPE_value[
i] * (1 << (
FRAC_BITS - 1)) +
653 5001) / 10000 / 8 | ((SLOPE_value[i] *
656 (YCOEF_EN_value[
i] << 17) | ((YCOEF_value[i] * (1 << 8) / 8) << 24) |
660 (flicker_removal * 1024 - 272) * SLOPE_value[i] / 8 * (1 << (
FRAC_BITS - 1)) / 1024;
663 tv_vscaler_cntl2 |= (0x10 << 24) |
670 tmp = ((16384 * 256 * 10) / tmp + 5) / 10;
672 tv_dac->
tv.timing_cntl =
tmp;
692 if (pll_ref_freq == 2700) {
702 if (pll_ref_freq == 2700) {
725 tv_dac->
tv.tv_uv_adr = 0xc8;
732 hor_timing = hor_timing_NTSC;
733 vert_timing = vert_timing_NTSC;
735 hor_timing = hor_timing_PAL;
736 vert_timing = vert_timing_PAL;
741 if ((tv_dac->
tv.h_code_timing[i] = hor_timing[i]) == 0)
746 if ((tv_dac->
tv.v_code_timing[i] = vert_timing[i]) == 0)
750 radeon_legacy_tv_init_restarts(encoder);
774 radeon_wait_pll_lock(encoder, 200, 800, 135);
778 radeon_wait_pll_lock(encoder, 300, 160, 27);
779 radeon_wait_pll_lock(encoder, 200, 800, 135);
807 radeon_legacy_write_tv_restarts(radeon_encoder);
810 radeon_restore_tv_timing_tables(radeon_encoder);
845 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder,
NULL);
852 tmp = *h_sync_strt_wid;
856 *h_sync_strt_wid =
tmp;
861 tmp = *v_sync_strt_wid;
864 *v_sync_strt_wid =
tmp;
867 static int get_post_div(
int value)
871 case 1: post_div = 0;
break;
872 case 2: post_div = 1;
break;
873 case 3: post_div = 4;
break;
874 case 4: post_div = 2;
break;
875 case 6: post_div = 6;
break;
876 case 8: post_div = 3;
break;
877 case 12: post_div = 7;
break;
879 default: post_div = 5;
break;
891 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder,
NULL);
911 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder,
NULL);
915 *htotal2_cntl = (const_ptr->
hor_total & 0x7);