#include <linux/firmware.h>
#include <linux/platform_device.h>
#include "radeon_family.h"

Go to the source code of this file.

Data Structures
struct	drm_radeon_freelist

struct	drm_radeon_ring_buffer

struct	drm_radeon_depth_clear_t

struct	drm_radeon_driver_file_fields

struct	mem_block

struct	radeon_surface

struct	radeon_virt_surface

struct	drm_radeon_master_private

struct	drm_radeon_private

struct	drm_radeon_buf_priv

struct	drm_radeon_kcmd_buffer

Macros
#define	DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."

#define	DRIVER_NAME "radeon"

#define	DRIVER_DESC "ATI Radeon"

#define	DRIVER_DATE "20080528"

#define	DRIVER_MAJOR 1

#define	DRIVER_MINOR 33

#define	DRIVER_PATCHLEVEL 0

#define	PCIGART_FILE_PRIV ((void *) -1L)

#define	RADEON_FLUSH_EMITED (1 << 0)

#define	RADEON_PURGE_EMITED (1 << 1)

#define	GET_RING_HEAD(dev_priv) radeon_get_ring_head(dev_priv)

#define	SET_RING_HEAD(dev_priv, val) radeon_set_ring_head(dev_priv, val)

#define	RADEON_BOX_DMA_IDLE 0x1

#define	RADEON_BOX_RING_FULL 0x2

#define	RADEON_BOX_FLIP 0x4

#define	RADEON_BOX_WAIT_IDLE 0x8

#define	RADEON_BOX_TEXTURE_LOAD 0x10

#define	RADEON_MM_INDEX 0x0000

#define	RADEON_MM_DATA 0x0004

#define	RADEON_AGP_COMMAND 0x0f60

#define	RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */

#define	RADEON_AGP_ENABLE (1<<8)

#define	RADEON_AUX_SCISSOR_CNTL 0x26f0

#define	RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)

#define	RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)

#define	RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)

#define	RADEON_SCISSOR_0_ENABLE (1 << 28)

#define	RADEON_SCISSOR_1_ENABLE (1 << 29)

#define	RADEON_SCISSOR_2_ENABLE (1 << 30)

#define	RADEON_BUS_CNTL 0x0030

#define	RADEON_BUS_MASTER_DIS (1 << 6)

#define	RS600_BUS_MASTER_DIS (1 << 14)

#define	RS600_MSI_REARM (1 << 20)

#define	RADEON_BUS_CNTL1 0x0034

#define	RADEON_PMI_BM_DIS (1 << 2)

#define	RADEON_PMI_INT_DIS (1 << 3)

#define	RV370_BUS_CNTL 0x004c

#define	RV370_PMI_BM_DIS (1 << 5)

#define	RV370_PMI_INT_DIS (1 << 6)

#define	RADEON_MSI_REARM_EN 0x0160

#define	RV370_MSI_REARM_EN (1 << 0)

#define	RADEON_CLOCK_CNTL_DATA 0x000c

#define	RADEON_PLL_WR_EN (1 << 7)

#define	RADEON_CLOCK_CNTL_INDEX 0x0008

#define	RADEON_CONFIG_APER_SIZE 0x0108

#define	RADEON_CONFIG_MEMSIZE 0x00f8

#define	RADEON_CRTC_OFFSET 0x0224

#define	RADEON_CRTC_OFFSET_CNTL 0x0228

#define	RADEON_CRTC_TILE_EN (1 << 15)

#define	RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)

#define	RADEON_CRTC2_OFFSET 0x0324

#define	RADEON_CRTC2_OFFSET_CNTL 0x0328

#define	RADEON_PCIE_INDEX 0x0030

#define	RADEON_PCIE_DATA 0x0034

#define	RADEON_PCIE_TX_GART_CNTL 0x10

#define	RADEON_PCIE_TX_GART_EN (1 << 0)

#define	RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)

#define	RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)

#define	RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)

#define	RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)

#define	RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)

#define	RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)

#define	RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)

#define	RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11

#define	RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12

#define	RADEON_PCIE_TX_GART_BASE 0x13

#define	RADEON_PCIE_TX_GART_START_LO 0x14

#define	RADEON_PCIE_TX_GART_START_HI 0x15

#define	RADEON_PCIE_TX_GART_END_LO 0x16

#define	RADEON_PCIE_TX_GART_END_HI 0x17

#define	RS480_NB_MC_INDEX 0x168

#define	RS480_NB_MC_IND_WR_EN (1 << 8)

#define	RS480_NB_MC_DATA 0x16c

#define	RS690_MC_INDEX 0x78

#define	RS690_MC_INDEX_MASK 0x1ff

#define	RS690_MC_INDEX_WR_EN (1 << 9)

#define	RS690_MC_INDEX_WR_ACK 0x7f

#define	RS690_MC_DATA 0x7c

#define	RS480_MC_MISC_CNTL 0x18

#define	RS480_DISABLE_GTW (1 << 1)

#define	RS480_GART_INDEX_REG_EN (1 << 12)

#define	RS690_BLOCK_GFX_D3_EN (1 << 14)

#define	RS480_K8_FB_LOCATION 0x1e

#define	RS480_GART_FEATURE_ID 0x2b

#define	RS480_HANG_EN (1 << 11)

#define	RS480_TLB_ENABLE (1 << 18)

#define	RS480_P2P_ENABLE (1 << 19)

#define	RS480_GTW_LAC_EN (1 << 25)

#define	RS480_2LEVEL_GART (0 << 30)

#define	RS480_1LEVEL_GART (1 << 30)

#define	RS480_PDC_EN (1 << 31)

#define	RS480_GART_BASE 0x2c

#define	RS480_GART_CACHE_CNTRL 0x2e

#define	RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */

#define	RS480_AGP_ADDRESS_SPACE_SIZE 0x38

#define	RS480_GART_EN (1 << 0)

#define	RS480_VA_SIZE_32MB (0 << 1)

#define	RS480_VA_SIZE_64MB (1 << 1)

#define	RS480_VA_SIZE_128MB (2 << 1)

#define	RS480_VA_SIZE_256MB (3 << 1)

#define	RS480_VA_SIZE_512MB (4 << 1)

#define	RS480_VA_SIZE_1GB (5 << 1)

#define	RS480_VA_SIZE_2GB (6 << 1)

#define	RS480_AGP_MODE_CNTL 0x39

#define	RS480_POST_GART_Q_SIZE (1 << 18)

#define	RS480_NONGART_SNOOP (1 << 19)

#define	RS480_AGP_RD_BUF_SIZE (1 << 20)

#define	RS480_REQ_TYPE_SNOOP_SHIFT 22

#define	RS480_REQ_TYPE_SNOOP_MASK 0x3

#define	RS480_REQ_TYPE_SNOOP_DIS (1 << 24)

#define	RS480_MC_MISC_UMA_CNTL 0x5f

#define	RS480_MC_MCLK_CNTL 0x7a

#define	RS480_MC_UMA_DUALCH_CNTL 0x86

#define	RS690_MC_FB_LOCATION 0x100

#define	RS690_MC_AGP_LOCATION 0x101

#define	RS690_MC_AGP_BASE 0x102

#define	RS690_MC_AGP_BASE_2 0x103

#define	RS600_MC_INDEX 0x70

#define	RS600_MC_ADDR_MASK 0xffff

#define	RS600_MC_IND_SEQ_RBS_0 (1 << 16)

#define	RS600_MC_IND_SEQ_RBS_1 (1 << 17)

#define	RS600_MC_IND_SEQ_RBS_2 (1 << 18)

#define	RS600_MC_IND_SEQ_RBS_3 (1 << 19)

#define	RS600_MC_IND_AIC_RBS (1 << 20)

#define	RS600_MC_IND_CITF_ARB0 (1 << 21)

#define	RS600_MC_IND_CITF_ARB1 (1 << 22)

#define	RS600_MC_IND_WR_EN (1 << 23)

#define	RS600_MC_DATA 0x74

#define	RS600_MC_STATUS 0x0

#define	RS600_MC_IDLE (1 << 1)

#define	RS600_MC_FB_LOCATION 0x4

#define	RS600_MC_AGP_LOCATION 0x5

#define	RS600_AGP_BASE 0x6

#define	RS600_AGP_BASE_2 0x7

#define	RS600_MC_CNTL1 0x9

#define	RS600_ENABLE_PAGE_TABLES (1 << 26)

#define	RS600_MC_PT0_CNTL 0x100

#define	RS600_ENABLE_PT (1 << 0)

#define	RS600_EFFECTIVE_L2_CACHE_SIZE(x) ((x) << 15)

#define	RS600_EFFECTIVE_L2_QUEUE_SIZE(x) ((x) << 21)

#define	RS600_INVALIDATE_ALL_L1_TLBS (1 << 28)

#define	RS600_INVALIDATE_L2_CACHE (1 << 29)

#define	RS600_MC_PT0_CONTEXT0_CNTL 0x102

#define	RS600_ENABLE_PAGE_TABLE (1 << 0)

#define	RS600_PAGE_TABLE_TYPE_FLAT (0 << 1)

#define	RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x112

#define	RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x114

#define	RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x11c

#define	RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x12c

#define	RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x13c

#define	RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x14c

#define	RS600_MC_PT0_CLIENT0_CNTL 0x16c

#define	RS600_ENABLE_TRANSLATION_MODE_OVERRIDE (1 << 0)

#define	RS600_TRANSLATION_MODE_OVERRIDE (1 << 1)

#define	RS600_SYSTEM_ACCESS_MODE_MASK (3 << 8)

#define	RS600_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 8)

#define	RS600_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 8)

#define	RS600_SYSTEM_ACCESS_MODE_IN_SYS (2 << 8)

#define	RS600_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 8)

#define	RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH (0 << 10)

#define	RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 10)

#define	RS600_EFFECTIVE_L1_CACHE_SIZE(x) ((x) << 11)

#define	RS600_ENABLE_FRAGMENT_PROCESSING (1 << 14)

#define	RS600_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15)

#define	RS600_INVALIDATE_L1_TLB (1 << 20)

#define	R520_MC_IND_INDEX 0x70

#define	R520_MC_IND_WR_EN (1 << 24)

#define	R520_MC_IND_DATA 0x74

#define	RV515_MC_FB_LOCATION 0x01

#define	RV515_MC_AGP_LOCATION 0x02

#define	RV515_MC_AGP_BASE 0x03

#define	RV515_MC_AGP_BASE_2 0x04

#define	R520_MC_FB_LOCATION 0x04

#define	R520_MC_AGP_LOCATION 0x05

#define	R520_MC_AGP_BASE 0x06

#define	R520_MC_AGP_BASE_2 0x07

#define	RADEON_MPP_TB_CONFIG 0x01c0

#define	RADEON_MEM_CNTL 0x0140

#define	RADEON_MEM_SDRAM_MODE_REG 0x0158

#define	RADEON_AGP_BASE_2 0x015c /* r200+ only */

#define	RS480_AGP_BASE_2 0x0164

#define	RADEON_AGP_BASE 0x0170

#define	R400_GB_PIPE_SELECT 0x402c

#define	RV530_GB_PIPE_SELECT2 0x4124

#define	R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */

#define	R300_GB_TILE_CONFIG 0x4018

#define	R300_ENABLE_TILING (1 << 0)

#define	R300_PIPE_COUNT_RV350 (0 << 1)

#define	R300_PIPE_COUNT_R300 (3 << 1)

#define	R300_PIPE_COUNT_R420_3P (6 << 1)

#define	R300_PIPE_COUNT_R420 (7 << 1)

#define	R300_TILE_SIZE_8 (0 << 4)

#define	R300_TILE_SIZE_16 (1 << 4)

#define	R300_TILE_SIZE_32 (2 << 4)

#define	R300_SUBPIXEL_1_12 (0 << 16)

#define	R300_SUBPIXEL_1_16 (1 << 16)

#define	R300_DST_PIPE_CONFIG 0x170c

#define	R300_PIPE_AUTO_CONFIG (1 << 31)

#define	R300_RB2D_DSTCACHE_MODE 0x3428

#define	R300_DC_AUTOFLUSH_ENABLE (1 << 8)

#define	R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)

#define	RADEON_RB3D_COLOROFFSET 0x1c40

#define	RADEON_RB3D_COLORPITCH 0x1c48

#define	RADEON_SRC_X_Y 0x1590

#define	RADEON_DP_GUI_MASTER_CNTL 0x146c

#define	RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)

#define	RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)

#define	RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)

#define	RADEON_GMC_BRUSH_NONE (15 << 4)

#define	RADEON_GMC_DST_16BPP (4 << 8)

#define	RADEON_GMC_DST_24BPP (5 << 8)

#define	RADEON_GMC_DST_32BPP (6 << 8)

#define	RADEON_GMC_DST_DATATYPE_SHIFT 8

#define	RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)

#define	RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)

#define	RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)

#define	RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)

#define	RADEON_GMC_WR_MSK_DIS (1 << 30)

#define	RADEON_ROP3_S 0x00cc0000

#define	RADEON_ROP3_P 0x00f00000

#define	RADEON_DP_WRITE_MASK 0x16cc

#define	RADEON_SRC_PITCH_OFFSET 0x1428

#define	RADEON_DST_PITCH_OFFSET 0x142c

#define	RADEON_DST_PITCH_OFFSET_C 0x1c80

#define	RADEON_DST_TILE_LINEAR (0 << 30)

#define	RADEON_DST_TILE_MACRO (1 << 30)

#define	RADEON_DST_TILE_MICRO (2 << 30)

#define	RADEON_DST_TILE_BOTH (3 << 30)

#define	RADEON_SCRATCH_REG0 0x15e0

#define	RADEON_SCRATCH_REG1 0x15e4

#define	RADEON_SCRATCH_REG2 0x15e8

#define	RADEON_SCRATCH_REG3 0x15ec

#define	RADEON_SCRATCH_REG4 0x15f0

#define	RADEON_SCRATCH_REG5 0x15f4

#define	RADEON_SCRATCH_UMSK 0x0770

#define	RADEON_SCRATCH_ADDR 0x0774

#define	RADEON_SCRATCHOFF(x) (RADEON_SCRATCH_REG_OFFSET + 4*(x))

#define	GET_SCRATCH(dev_priv, x) radeon_get_scratch(dev_priv, x)

#define	R600_SCRATCH_REG0 0x8500

#define	R600_SCRATCH_REG1 0x8504

#define	R600_SCRATCH_REG2 0x8508

#define	R600_SCRATCH_REG3 0x850c

#define	R600_SCRATCH_REG4 0x8510

#define	R600_SCRATCH_REG5 0x8514

#define	R600_SCRATCH_REG6 0x8518

#define	R600_SCRATCH_REG7 0x851c

#define	R600_SCRATCH_UMSK 0x8540

#define	R600_SCRATCH_ADDR 0x8544

#define	R600_SCRATCHOFF(x) (R600_SCRATCH_REG_OFFSET + 4*(x))

#define	RADEON_GEN_INT_CNTL 0x0040

#define	RADEON_CRTC_VBLANK_MASK (1 << 0)

#define	RADEON_CRTC2_VBLANK_MASK (1 << 9)

#define	RADEON_GUI_IDLE_INT_ENABLE (1 << 19)

#define	RADEON_SW_INT_ENABLE (1 << 25)

#define	RADEON_GEN_INT_STATUS 0x0044

#define	RADEON_CRTC_VBLANK_STAT (1 << 0)

#define	RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)

#define	RADEON_CRTC2_VBLANK_STAT (1 << 9)

#define	RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)

#define	RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)

#define	RADEON_SW_INT_TEST (1 << 25)

#define	RADEON_SW_INT_TEST_ACK (1 << 25)

#define	RADEON_SW_INT_FIRE (1 << 26)

#define	R500_DISPLAY_INT_STATUS (1 << 0)

#define	RADEON_HOST_PATH_CNTL 0x0130

#define	RADEON_HDP_SOFT_RESET (1 << 26)

#define	RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)

#define	RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)

#define	RADEON_ISYNC_CNTL 0x1724

#define	RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)

#define	RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)

#define	RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)

#define	RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)

#define	RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)

#define	RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)

#define	RADEON_RBBM_GUICNTL 0x172c

#define	RADEON_HOST_DATA_SWAP_NONE (0 << 0)

#define	RADEON_HOST_DATA_SWAP_16BIT (1 << 0)

#define	RADEON_HOST_DATA_SWAP_32BIT (2 << 0)

#define	RADEON_HOST_DATA_SWAP_HDW (3 << 0)

#define	RADEON_MC_AGP_LOCATION 0x014c

#define	RADEON_MC_FB_LOCATION 0x0148

#define	RADEON_MCLK_CNTL 0x0012

#define	RADEON_FORCEON_MCLKA (1 << 16)

#define	RADEON_FORCEON_MCLKB (1 << 17)

#define	RADEON_FORCEON_YCLKA (1 << 18)

#define	RADEON_FORCEON_YCLKB (1 << 19)

#define	RADEON_FORCEON_MC (1 << 20)

#define	RADEON_FORCEON_AIC (1 << 21)

#define	RADEON_PP_BORDER_COLOR_0 0x1d40

#define	RADEON_PP_BORDER_COLOR_1 0x1d44

#define	RADEON_PP_BORDER_COLOR_2 0x1d48

#define	RADEON_PP_CNTL 0x1c38

#define	RADEON_SCISSOR_ENABLE (1 << 1)

#define	RADEON_PP_LUM_MATRIX 0x1d00

#define	RADEON_PP_MISC 0x1c14

#define	RADEON_PP_ROT_MATRIX_0 0x1d58

#define	RADEON_PP_TXFILTER_0 0x1c54

#define	RADEON_PP_TXOFFSET_0 0x1c5c

#define	RADEON_PP_TXFILTER_1 0x1c6c

#define	RADEON_PP_TXFILTER_2 0x1c84

#define	R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */

#define	R300_DSTCACHE_CTLSTAT 0x1714

#define	R300_RB2D_DC_FLUSH (3 << 0)

#define	R300_RB2D_DC_FREE (3 << 2)

#define	R300_RB2D_DC_FLUSH_ALL 0xf

#define	R300_RB2D_DC_BUSY (1 << 31)

#define	RADEON_RB3D_CNTL 0x1c3c

#define	RADEON_ALPHA_BLEND_ENABLE (1 << 0)

#define	RADEON_PLANE_MASK_ENABLE (1 << 1)

#define	RADEON_DITHER_ENABLE (1 << 2)

#define	RADEON_ROUND_ENABLE (1 << 3)

#define	RADEON_SCALE_DITHER_ENABLE (1 << 4)

#define	RADEON_DITHER_INIT (1 << 5)

#define	RADEON_ROP_ENABLE (1 << 6)

#define	RADEON_STENCIL_ENABLE (1 << 7)

#define	RADEON_Z_ENABLE (1 << 8)

#define	RADEON_ZBLOCK16 (1 << 15)

#define	RADEON_RB3D_DEPTHOFFSET 0x1c24

#define	RADEON_RB3D_DEPTHCLEARVALUE 0x3230

#define	RADEON_RB3D_DEPTHPITCH 0x1c28

#define	RADEON_RB3D_PLANEMASK 0x1d84

#define	RADEON_RB3D_STENCILREFMASK 0x1d7c

#define	RADEON_RB3D_ZCACHE_MODE 0x3250

#define	RADEON_RB3D_ZCACHE_CTLSTAT 0x3254

#define	RADEON_RB3D_ZC_FLUSH (1 << 0)

#define	RADEON_RB3D_ZC_FREE (1 << 2)

#define	RADEON_RB3D_ZC_FLUSH_ALL 0x5

#define	RADEON_RB3D_ZC_BUSY (1 << 31)

#define	R300_ZB_ZCACHE_CTLSTAT 0x4f18

#define	R300_ZC_FLUSH (1 << 0)

#define	R300_ZC_FREE (1 << 1)

#define	R300_ZC_BUSY (1 << 31)

#define	RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c

#define	RADEON_RB3D_DC_FLUSH (3 << 0)

#define	RADEON_RB3D_DC_FREE (3 << 2)

#define	RADEON_RB3D_DC_FLUSH_ALL 0xf

#define	RADEON_RB3D_DC_BUSY (1 << 31)

#define	R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c

#define	R300_RB3D_DC_FLUSH (2 << 0)

#define	R300_RB3D_DC_FREE (2 << 2)

#define	R300_RB3D_DC_FINISH (1 << 4)

#define	RADEON_RB3D_ZSTENCILCNTL 0x1c2c

#define	RADEON_Z_TEST_MASK (7 << 4)

#define	RADEON_Z_TEST_ALWAYS (7 << 4)

#define	RADEON_Z_HIERARCHY_ENABLE (1 << 8)

#define	RADEON_STENCIL_TEST_ALWAYS (7 << 12)

#define	RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)

#define	RADEON_STENCIL_ZPASS_REPLACE (2 << 20)

#define	RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)

#define	RADEON_Z_COMPRESSION_ENABLE (1 << 28)

#define	RADEON_FORCE_Z_DIRTY (1 << 29)

#define	RADEON_Z_WRITE_ENABLE (1 << 30)

#define	RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)

#define	RADEON_RBBM_SOFT_RESET 0x00f0

#define	RADEON_SOFT_RESET_CP (1 << 0)

#define	RADEON_SOFT_RESET_HI (1 << 1)

#define	RADEON_SOFT_RESET_SE (1 << 2)

#define	RADEON_SOFT_RESET_RE (1 << 3)

#define	RADEON_SOFT_RESET_PP (1 << 4)

#define	RADEON_SOFT_RESET_E2 (1 << 5)

#define	RADEON_SOFT_RESET_RB (1 << 6)

#define	RADEON_SOFT_RESET_HDP (1 << 7)

#define	RADEON_RBBM_STATUS 0x0e40

#define	RADEON_RBBM_FIFOCNT_MASK 0x007f

#define	RADEON_HIRQ_ON_RBB (1 << 8)

#define	RADEON_CPRQ_ON_RBB (1 << 9)

#define	RADEON_CFRQ_ON_RBB (1 << 10)

#define	RADEON_HIRQ_IN_RTBUF (1 << 11)

#define	RADEON_CPRQ_IN_RTBUF (1 << 12)

#define	RADEON_CFRQ_IN_RTBUF (1 << 13)

#define	RADEON_PIPE_BUSY (1 << 14)

#define	RADEON_ENG_EV_BUSY (1 << 15)

#define	RADEON_CP_CMDSTRM_BUSY (1 << 16)

#define	RADEON_E2_BUSY (1 << 17)

#define	RADEON_RB2D_BUSY (1 << 18)

#define	RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */

#define	RADEON_VAP_BUSY (1 << 20)

#define	RADEON_RE_BUSY (1 << 21) /* not used on r300 */

#define	RADEON_TAM_BUSY (1 << 22) /* not used on r300 */

#define	RADEON_TDM_BUSY (1 << 23) /* not used on r300 */

#define	RADEON_PB_BUSY (1 << 24) /* not used on r300 */

#define	RADEON_TIM_BUSY (1 << 25) /* not used on r300 */

#define	RADEON_GA_BUSY (1 << 26)

#define	RADEON_CBA2D_BUSY (1 << 27)

#define	RADEON_RBBM_ACTIVE (1 << 31)

#define	RADEON_RE_LINE_PATTERN 0x1cd0

#define	RADEON_RE_MISC 0x26c4

#define	RADEON_RE_TOP_LEFT 0x26c0

#define	RADEON_RE_WIDTH_HEIGHT 0x1c44

#define	RADEON_RE_STIPPLE_ADDR 0x1cc8

#define	RADEON_RE_STIPPLE_DATA 0x1ccc

#define	RADEON_SCISSOR_TL_0 0x1cd8

#define	RADEON_SCISSOR_BR_0 0x1cdc

#define	RADEON_SCISSOR_TL_1 0x1ce0

#define	RADEON_SCISSOR_BR_1 0x1ce4

#define	RADEON_SCISSOR_TL_2 0x1ce8

#define	RADEON_SCISSOR_BR_2 0x1cec

#define	RADEON_SE_COORD_FMT 0x1c50

#define	RADEON_SE_CNTL 0x1c4c

#define	RADEON_FFACE_CULL_CW (0 << 0)

#define	RADEON_BFACE_SOLID (3 << 1)

#define	RADEON_FFACE_SOLID (3 << 3)

#define	RADEON_FLAT_SHADE_VTX_LAST (3 << 6)

#define	RADEON_DIFFUSE_SHADE_FLAT (1 << 8)

#define	RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)

#define	RADEON_ALPHA_SHADE_FLAT (1 << 10)

#define	RADEON_ALPHA_SHADE_GOURAUD (2 << 10)

#define	RADEON_SPECULAR_SHADE_FLAT (1 << 12)

#define	RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)

#define	RADEON_FOG_SHADE_FLAT (1 << 14)

#define	RADEON_FOG_SHADE_GOURAUD (2 << 14)

#define	RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)

#define	RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)

#define	RADEON_VTX_PIX_CENTER_OGL (1 << 27)

#define	RADEON_ROUND_MODE_TRUNC (0 << 28)

#define	RADEON_ROUND_PREC_8TH_PIX (1 << 30)

#define	RADEON_SE_CNTL_STATUS 0x2140

#define	RADEON_SE_LINE_WIDTH 0x1db8

#define	RADEON_SE_VPORT_XSCALE 0x1d98

#define	RADEON_SE_ZBIAS_FACTOR 0x1db0

#define	RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210

#define	RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254

#define	RADEON_SE_TCL_VECTOR_INDX_REG 0x2200

#define	RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16

#define	RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28

#define	RADEON_SE_TCL_VECTOR_DATA_REG 0x2204

#define	RADEON_SE_TCL_SCALAR_INDX_REG 0x2208

#define	RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16

#define	RADEON_SE_TCL_SCALAR_DATA_REG 0x220C

#define	RADEON_SURFACE_ACCESS_FLAGS 0x0bf8

#define	RADEON_SURFACE_ACCESS_CLR 0x0bfc

#define	RADEON_SURFACE_CNTL 0x0b00

#define	RADEON_SURF_TRANSLATION_DIS (1 << 8)

#define	RADEON_NONSURF_AP0_SWP_MASK (3 << 20)

#define	RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)

#define	RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)

#define	RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)

#define	RADEON_NONSURF_AP1_SWP_MASK (3 << 22)

#define	RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)

#define	RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)

#define	RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)

#define	RADEON_SURFACE0_INFO 0x0b0c

#define	RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)

#define	RADEON_SURF_TILE_MODE_MASK (3 << 16)

#define	RADEON_SURF_TILE_MODE_MACRO (0 << 16)

#define	RADEON_SURF_TILE_MODE_MICRO (1 << 16)

#define	RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)

#define	RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)

#define	RADEON_SURFACE0_LOWER_BOUND 0x0b04

#define	RADEON_SURFACE0_UPPER_BOUND 0x0b08

#define	RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)

#define	RADEON_SURFACE1_INFO 0x0b1c

#define	RADEON_SURFACE1_LOWER_BOUND 0x0b14

#define	RADEON_SURFACE1_UPPER_BOUND 0x0b18

#define	RADEON_SURFACE2_INFO 0x0b2c

#define	RADEON_SURFACE2_LOWER_BOUND 0x0b24

#define	RADEON_SURFACE2_UPPER_BOUND 0x0b28

#define	RADEON_SURFACE3_INFO 0x0b3c

#define	RADEON_SURFACE3_LOWER_BOUND 0x0b34

#define	RADEON_SURFACE3_UPPER_BOUND 0x0b38

#define	RADEON_SURFACE4_INFO 0x0b4c

#define	RADEON_SURFACE4_LOWER_BOUND 0x0b44

#define	RADEON_SURFACE4_UPPER_BOUND 0x0b48

#define	RADEON_SURFACE5_INFO 0x0b5c

#define	RADEON_SURFACE5_LOWER_BOUND 0x0b54

#define	RADEON_SURFACE5_UPPER_BOUND 0x0b58

#define	RADEON_SURFACE6_INFO 0x0b6c

#define	RADEON_SURFACE6_LOWER_BOUND 0x0b64

#define	RADEON_SURFACE6_UPPER_BOUND 0x0b68

#define	RADEON_SURFACE7_INFO 0x0b7c

#define	RADEON_SURFACE7_LOWER_BOUND 0x0b74

#define	RADEON_SURFACE7_UPPER_BOUND 0x0b78

#define	RADEON_SW_SEMAPHORE 0x013c

#define	RADEON_WAIT_UNTIL 0x1720

#define	RADEON_WAIT_CRTC_PFLIP (1 << 0)

#define	RADEON_WAIT_2D_IDLE (1 << 14)

#define	RADEON_WAIT_3D_IDLE (1 << 15)

#define	RADEON_WAIT_2D_IDLECLEAN (1 << 16)

#define	RADEON_WAIT_3D_IDLECLEAN (1 << 17)

#define	RADEON_WAIT_HOST_IDLECLEAN (1 << 18)

#define	RADEON_RB3D_ZMASKOFFSET 0x3234

#define	RADEON_RB3D_ZSTENCILCNTL 0x1c2c

#define	RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)

#define	RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)

#define	RADEON_CP_ME_RAM_ADDR 0x07d4

#define	RADEON_CP_ME_RAM_RADDR 0x07d8

#define	RADEON_CP_ME_RAM_DATAH 0x07dc

#define	RADEON_CP_ME_RAM_DATAL 0x07e0

#define	RADEON_CP_RB_BASE 0x0700

#define	RADEON_CP_RB_CNTL 0x0704

#define	RADEON_BUF_SWAP_32BIT (2 << 16)

#define	RADEON_RB_NO_UPDATE (1 << 27)

#define	RADEON_RB_RPTR_WR_ENA (1 << 31)

#define	RADEON_CP_RB_RPTR_ADDR 0x070c

#define	RADEON_CP_RB_RPTR 0x0710

#define	RADEON_CP_RB_WPTR 0x0714

#define	RADEON_CP_RB_WPTR_DELAY 0x0718

#define	RADEON_PRE_WRITE_TIMER_SHIFT 0

#define	RADEON_PRE_WRITE_LIMIT_SHIFT 23

#define	RADEON_CP_IB_BASE 0x0738

#define	RADEON_CP_CSQ_CNTL 0x0740

#define	RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)

#define	RADEON_CSQ_PRIDIS_INDDIS (0 << 28)

#define	RADEON_CSQ_PRIPIO_INDDIS (1 << 28)

#define	RADEON_CSQ_PRIBM_INDDIS (2 << 28)

#define	RADEON_CSQ_PRIPIO_INDBM (3 << 28)

#define	RADEON_CSQ_PRIBM_INDBM (4 << 28)

#define	RADEON_CSQ_PRIPIO_INDPIO (15 << 28)

#define	R300_CP_RESYNC_ADDR 0x0778

#define	R300_CP_RESYNC_DATA 0x077c

#define	RADEON_AIC_CNTL 0x01d0

#define	RADEON_PCIGART_TRANSLATE_EN (1 << 0)

#define	RS400_MSI_REARM (1 << 3)

#define	RADEON_AIC_STAT 0x01d4

#define	RADEON_AIC_PT_BASE 0x01d8

#define	RADEON_AIC_LO_ADDR 0x01dc

#define	RADEON_AIC_HI_ADDR 0x01e0

#define	RADEON_AIC_TLB_ADDR 0x01e4

#define	RADEON_AIC_TLB_DATA 0x01e8

#define	RADEON_CP_PACKET0 0x00000000

#define	RADEON_ONE_REG_WR (1 << 15)

#define	RADEON_CP_PACKET1 0x40000000

#define	RADEON_CP_PACKET2 0x80000000

#define	RADEON_CP_PACKET3 0xC0000000

#define	RADEON_CP_NOP 0x00001000

#define	RADEON_CP_NEXT_CHAR 0x00001900

#define	RADEON_CP_PLY_NEXTSCAN 0x00001D00

#define	RADEON_CP_SET_SCISSORS 0x00001E00

#define	RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300

#define	RADEON_WAIT_FOR_IDLE 0x00002600

#define	RADEON_3D_DRAW_VBUF 0x00002800

#define	RADEON_3D_DRAW_IMMD 0x00002900

#define	RADEON_3D_DRAW_INDX 0x00002A00

#define	RADEON_CP_LOAD_PALETTE 0x00002C00

#define	RADEON_3D_LOAD_VBPNTR 0x00002F00

#define	RADEON_MPEG_IDCT_MACROBLOCK 0x00003000

#define	RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100

#define	RADEON_3D_CLEAR_ZMASK 0x00003200

#define	RADEON_CP_INDX_BUFFER 0x00003300

#define	RADEON_CP_3D_DRAW_VBUF_2 0x00003400

#define	RADEON_CP_3D_DRAW_IMMD_2 0x00003500

#define	RADEON_CP_3D_DRAW_INDX_2 0x00003600

#define	RADEON_3D_CLEAR_HIZ 0x00003700

#define	RADEON_CP_3D_CLEAR_CMASK 0x00003802

#define	RADEON_CNTL_HOSTDATA_BLT 0x00009400

#define	RADEON_CNTL_PAINT_MULTI 0x00009A00

#define	RADEON_CNTL_BITBLT_MULTI 0x00009B00

#define	RADEON_CNTL_SET_SCISSORS 0xC0001E00

#define	R600_IT_INDIRECT_BUFFER_END 0x00001700

#define	R600_IT_SET_PREDICATION 0x00002000

#define	R600_IT_REG_RMW 0x00002100

#define	R600_IT_COND_EXEC 0x00002200

#define	R600_IT_PRED_EXEC 0x00002300

#define	R600_IT_START_3D_CMDBUF 0x00002400

#define	R600_IT_DRAW_INDEX_2 0x00002700

#define	R600_IT_CONTEXT_CONTROL 0x00002800

#define	R600_IT_DRAW_INDEX_IMMD_BE 0x00002900

#define	R600_IT_INDEX_TYPE 0x00002A00

#define	R600_IT_DRAW_INDEX 0x00002B00

#define	R600_IT_DRAW_INDEX_AUTO 0x00002D00

#define	R600_IT_DRAW_INDEX_IMMD 0x00002E00

#define	R600_IT_NUM_INSTANCES 0x00002F00

#define	R600_IT_STRMOUT_BUFFER_UPDATE 0x00003400

#define	R600_IT_INDIRECT_BUFFER_MP 0x00003800

#define	R600_IT_MEM_SEMAPHORE 0x00003900

#define	R600_IT_MPEG_INDEX 0x00003A00

#define	R600_IT_WAIT_REG_MEM 0x00003C00

#define	R600_IT_MEM_WRITE 0x00003D00

#define	R600_IT_INDIRECT_BUFFER 0x00003200

#define	R600_IT_SURFACE_SYNC 0x00004300

#define	R600_CB0_DEST_BASE_ENA (1 << 6)

#define	R600_TC_ACTION_ENA (1 << 23)

#define	R600_VC_ACTION_ENA (1 << 24)

#define	R600_CB_ACTION_ENA (1 << 25)

#define	R600_DB_ACTION_ENA (1 << 26)

#define	R600_SH_ACTION_ENA (1 << 27)

#define	R600_SMX_ACTION_ENA (1 << 28)

#define	R600_IT_ME_INITIALIZE 0x00004400

#define	R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)

#define	R600_IT_COND_WRITE 0x00004500

#define	R600_IT_EVENT_WRITE 0x00004600

#define	R600_IT_EVENT_WRITE_EOP 0x00004700

#define	R600_IT_ONE_REG_WRITE 0x00005700

#define	R600_IT_SET_CONFIG_REG 0x00006800

#define	R600_SET_CONFIG_REG_OFFSET 0x00008000

#define	R600_SET_CONFIG_REG_END 0x0000ac00

#define	R600_IT_SET_CONTEXT_REG 0x00006900

#define	R600_SET_CONTEXT_REG_OFFSET 0x00028000

#define	R600_SET_CONTEXT_REG_END 0x00029000

#define	R600_IT_SET_ALU_CONST 0x00006A00

#define	R600_SET_ALU_CONST_OFFSET 0x00030000

#define	R600_SET_ALU_CONST_END 0x00032000

#define	R600_IT_SET_BOOL_CONST 0x00006B00

#define	R600_SET_BOOL_CONST_OFFSET 0x0003e380

#define	R600_SET_BOOL_CONST_END 0x00040000

#define	R600_IT_SET_LOOP_CONST 0x00006C00

#define	R600_SET_LOOP_CONST_OFFSET 0x0003e200

#define	R600_SET_LOOP_CONST_END 0x0003e380

#define	R600_IT_SET_RESOURCE 0x00006D00

#define	R600_SET_RESOURCE_OFFSET 0x00038000

#define	R600_SET_RESOURCE_END 0x0003c000

#define	R600_SQ_TEX_VTX_INVALID_TEXTURE 0x0

#define	R600_SQ_TEX_VTX_INVALID_BUFFER 0x1

#define	R600_SQ_TEX_VTX_VALID_TEXTURE 0x2

#define	R600_SQ_TEX_VTX_VALID_BUFFER 0x3

#define	R600_IT_SET_SAMPLER 0x00006E00

#define	R600_SET_SAMPLER_OFFSET 0x0003c000

#define	R600_SET_SAMPLER_END 0x0003cff0

#define	R600_IT_SET_CTL_CONST 0x00006F00

#define	R600_SET_CTL_CONST_OFFSET 0x0003cff0

#define	R600_SET_CTL_CONST_END 0x0003e200

#define	R600_IT_SURFACE_BASE_UPDATE 0x00007300

#define	RADEON_CP_PACKET_MASK 0xC0000000

#define	RADEON_CP_PACKET_COUNT_MASK 0x3fff0000

#define	RADEON_CP_PACKET0_REG_MASK 0x000007ff

#define	RADEON_CP_PACKET1_REG0_MASK 0x000007ff

#define	RADEON_CP_PACKET1_REG1_MASK 0x003ff800

#define	RADEON_VTX_Z_PRESENT (1 << 31)

#define	RADEON_VTX_PKCOLOR_PRESENT (1 << 3)

#define	RADEON_PRIM_TYPE_NONE (0 << 0)

#define	RADEON_PRIM_TYPE_POINT (1 << 0)

#define	RADEON_PRIM_TYPE_LINE (2 << 0)

#define	RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)

#define	RADEON_PRIM_TYPE_TRI_LIST (4 << 0)

#define	RADEON_PRIM_TYPE_TRI_FAN (5 << 0)

#define	RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)

#define	RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)

#define	RADEON_PRIM_TYPE_RECT_LIST (8 << 0)

#define	RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)

#define	RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)

#define	RADEON_PRIM_TYPE_MASK 0xf

#define	RADEON_PRIM_WALK_IND (1 << 4)

#define	RADEON_PRIM_WALK_LIST (2 << 4)

#define	RADEON_PRIM_WALK_RING (3 << 4)

#define	RADEON_COLOR_ORDER_BGRA (0 << 6)

#define	RADEON_COLOR_ORDER_RGBA (1 << 6)

#define	RADEON_MAOS_ENABLE (1 << 7)

#define	RADEON_VTX_FMT_R128_MODE (0 << 8)

#define	RADEON_VTX_FMT_RADEON_MODE (1 << 8)

#define	RADEON_NUM_VERTICES_SHIFT 16

#define	RADEON_COLOR_FORMAT_CI8 2

#define	RADEON_COLOR_FORMAT_ARGB1555 3

#define	RADEON_COLOR_FORMAT_RGB565 4

#define	RADEON_COLOR_FORMAT_ARGB8888 6

#define	RADEON_COLOR_FORMAT_RGB332 7

#define	RADEON_COLOR_FORMAT_RGB8 9

#define	RADEON_COLOR_FORMAT_ARGB4444 15

#define	RADEON_TXFORMAT_I8 0

#define	RADEON_TXFORMAT_AI88 1

#define	RADEON_TXFORMAT_RGB332 2

#define	RADEON_TXFORMAT_ARGB1555 3

#define	RADEON_TXFORMAT_RGB565 4

#define	RADEON_TXFORMAT_ARGB4444 5

#define	RADEON_TXFORMAT_ARGB8888 6

#define	RADEON_TXFORMAT_RGBA8888 7

#define	RADEON_TXFORMAT_Y8 8

#define	RADEON_TXFORMAT_VYUY422 10

#define	RADEON_TXFORMAT_YVYU422 11

#define	RADEON_TXFORMAT_DXT1 12

#define	RADEON_TXFORMAT_DXT23 14

#define	RADEON_TXFORMAT_DXT45 15

#define	R200_PP_TXCBLEND_0 0x2f00

#define	R200_PP_TXCBLEND_1 0x2f10

#define	R200_PP_TXCBLEND_2 0x2f20

#define	R200_PP_TXCBLEND_3 0x2f30

#define	R200_PP_TXCBLEND_4 0x2f40

#define	R200_PP_TXCBLEND_5 0x2f50

#define	R200_PP_TXCBLEND_6 0x2f60

#define	R200_PP_TXCBLEND_7 0x2f70

#define	R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268

#define	R200_PP_TFACTOR_0 0x2ee0

#define	R200_SE_VTX_FMT_0 0x2088

#define	R200_SE_VAP_CNTL 0x2080

#define	R200_SE_TCL_MATRIX_SEL_0 0x2230

#define	R200_SE_TCL_TEX_PROC_CTL_2 0x22a8

#define	R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0

#define	R200_PP_TXFILTER_5 0x2ca0

#define	R200_PP_TXFILTER_4 0x2c80

#define	R200_PP_TXFILTER_3 0x2c60

#define	R200_PP_TXFILTER_2 0x2c40

#define	R200_PP_TXFILTER_1 0x2c20

#define	R200_PP_TXFILTER_0 0x2c00

#define	R200_PP_TXOFFSET_5 0x2d78

#define	R200_PP_TXOFFSET_4 0x2d60

#define	R200_PP_TXOFFSET_3 0x2d48

#define	R200_PP_TXOFFSET_2 0x2d30

#define	R200_PP_TXOFFSET_1 0x2d18

#define	R200_PP_TXOFFSET_0 0x2d00

#define	R200_PP_CUBIC_FACES_0 0x2c18

#define	R200_PP_CUBIC_FACES_1 0x2c38

#define	R200_PP_CUBIC_FACES_2 0x2c58

#define	R200_PP_CUBIC_FACES_3 0x2c78

#define	R200_PP_CUBIC_FACES_4 0x2c98

#define	R200_PP_CUBIC_FACES_5 0x2cb8

#define	R200_PP_CUBIC_OFFSET_F1_0 0x2d04

#define	R200_PP_CUBIC_OFFSET_F2_0 0x2d08

#define	R200_PP_CUBIC_OFFSET_F3_0 0x2d0c

#define	R200_PP_CUBIC_OFFSET_F4_0 0x2d10

#define	R200_PP_CUBIC_OFFSET_F5_0 0x2d14

#define	R200_PP_CUBIC_OFFSET_F1_1 0x2d1c

#define	R200_PP_CUBIC_OFFSET_F2_1 0x2d20

#define	R200_PP_CUBIC_OFFSET_F3_1 0x2d24

#define	R200_PP_CUBIC_OFFSET_F4_1 0x2d28

#define	R200_PP_CUBIC_OFFSET_F5_1 0x2d2c

#define	R200_PP_CUBIC_OFFSET_F1_2 0x2d34

#define	R200_PP_CUBIC_OFFSET_F2_2 0x2d38

#define	R200_PP_CUBIC_OFFSET_F3_2 0x2d3c

#define	R200_PP_CUBIC_OFFSET_F4_2 0x2d40

#define	R200_PP_CUBIC_OFFSET_F5_2 0x2d44

#define	R200_PP_CUBIC_OFFSET_F1_3 0x2d4c

#define	R200_PP_CUBIC_OFFSET_F2_3 0x2d50

#define	R200_PP_CUBIC_OFFSET_F3_3 0x2d54

#define	R200_PP_CUBIC_OFFSET_F4_3 0x2d58

#define	R200_PP_CUBIC_OFFSET_F5_3 0x2d5c

#define	R200_PP_CUBIC_OFFSET_F1_4 0x2d64

#define	R200_PP_CUBIC_OFFSET_F2_4 0x2d68

#define	R200_PP_CUBIC_OFFSET_F3_4 0x2d6c

#define	R200_PP_CUBIC_OFFSET_F4_4 0x2d70

#define	R200_PP_CUBIC_OFFSET_F5_4 0x2d74

#define	R200_PP_CUBIC_OFFSET_F1_5 0x2d7c

#define	R200_PP_CUBIC_OFFSET_F2_5 0x2d80

#define	R200_PP_CUBIC_OFFSET_F3_5 0x2d84

#define	R200_PP_CUBIC_OFFSET_F4_5 0x2d88

#define	R200_PP_CUBIC_OFFSET_F5_5 0x2d8c

#define	R200_RE_AUX_SCISSOR_CNTL 0x26f0

#define	R200_SE_VTE_CNTL 0x20b0

#define	R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250

#define	R200_PP_TAM_DEBUG3 0x2d9c

#define	R200_PP_CNTL_X 0x2cc4

#define	R200_SE_VAP_CNTL_STATUS 0x2140

#define	R200_RE_SCISSOR_TL_0 0x1cd8

#define	R200_RE_SCISSOR_TL_1 0x1ce0

#define	R200_RE_SCISSOR_TL_2 0x1ce8

#define	R200_RB3D_DEPTHXY_OFFSET 0x1d60

#define	R200_RE_AUX_SCISSOR_CNTL 0x26f0

#define	R200_SE_VTX_STATE_CNTL 0x2180

#define	R200_RE_POINTSIZE 0x2648

#define	R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254

#define	RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */

#define	RADEON_PP_TEX_SIZE_1 0x1d0c

#define	RADEON_PP_TEX_SIZE_2 0x1d14

#define	RADEON_PP_CUBIC_FACES_0 0x1d24

#define	RADEON_PP_CUBIC_FACES_1 0x1d28

#define	RADEON_PP_CUBIC_FACES_2 0x1d2c

#define	RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */

#define	RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00

#define	RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14

#define	RADEON_SE_TCL_STATE_FLUSH 0x2284

#define	SE_VAP_CNTL__TCL_ENA_MASK 0x00000001

#define	SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000

#define	SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012

#define	SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100

#define	SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200

#define	SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001

#define	SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002

#define	SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b

#define	R200_3D_DRAW_IMMD_2 0xC0003500

#define	R200_SE_VTX_FMT_1 0x208c

#define	R200_RE_CNTL 0x1c50

#define	R200_RB3D_BLENDCOLOR 0x3218

#define	R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4

#define	R200_PP_TRI_PERF 0x2cf8

#define	R200_PP_AFS_0 0x2f80

#define	R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */

#define	R200_VAP_PVS_CNTL_1 0x22D0

#define	RADEON_CRTC_CRNT_FRAME 0x0214

#define	RADEON_CRTC2_CRNT_FRAME 0x0314

#define	R500_D1CRTC_STATUS 0x609c

#define	R500_D2CRTC_STATUS 0x689c

#define	R500_CRTC_V_BLANK (1<<0)

#define	R500_D1CRTC_FRAME_COUNT 0x60a4

#define	R500_D2CRTC_FRAME_COUNT 0x68a4

#define	R500_D1MODE_V_COUNTER 0x6530

#define	R500_D2MODE_V_COUNTER 0x6d30

#define	R500_D1MODE_VBLANK_STATUS 0x6534

#define	R500_D2MODE_VBLANK_STATUS 0x6d34

#define	R500_VBLANK_OCCURED (1<<0)

#define	R500_VBLANK_ACK (1<<4)

#define	R500_VBLANK_STAT (1<<12)

#define	R500_VBLANK_INT (1<<16)

#define	R500_DxMODE_INT_MASK 0x6540

#define	R500_D1MODE_INT_MASK (1<<0)

#define	R500_D2MODE_INT_MASK (1<<8)

#define	R500_DISP_INTERRUPT_STATUS 0x7edc

#define	R500_D1_VBLANK_INTERRUPT (1 << 4)

#define	R500_D2_VBLANK_INTERRUPT (1 << 5)

#define	R600_MC_VM_FB_LOCATION 0x2180

#define	R600_MC_VM_AGP_TOP 0x2184

#define	R600_MC_VM_AGP_BOT 0x2188

#define	R600_MC_VM_AGP_BASE 0x218c

#define	R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190

#define	R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194

#define	R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198

#define	R700_MC_VM_FB_LOCATION 0x2024

#define	R700_MC_VM_AGP_TOP 0x2028

#define	R700_MC_VM_AGP_BOT 0x202c

#define	R700_MC_VM_AGP_BASE 0x2030

#define	R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034

#define	R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038

#define	R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c

#define	R600_MCD_RD_A_CNTL 0x219c

#define	R600_MCD_RD_B_CNTL 0x21a0

#define	R600_MCD_WR_A_CNTL 0x21a4

#define	R600_MCD_WR_B_CNTL 0x21a8

#define	R600_MCD_RD_SYS_CNTL 0x2200

#define	R600_MCD_WR_SYS_CNTL 0x2214

#define	R600_MCD_RD_GFX_CNTL 0x21fc

#define	R600_MCD_RD_HDP_CNTL 0x2204

#define	R600_MCD_RD_PDMA_CNTL 0x2208

#define	R600_MCD_RD_SEM_CNTL 0x220c

#define	R600_MCD_WR_GFX_CNTL 0x2210

#define	R600_MCD_WR_HDP_CNTL 0x2218

#define	R600_MCD_WR_PDMA_CNTL 0x221c

#define	R600_MCD_WR_SEM_CNTL 0x2220

#define	R600_MCD_L1_TLB (1 << 0)

#define	R600_MCD_L1_FRAG_PROC (1 << 1)

#define	R600_MCD_L1_STRICT_ORDERING (1 << 2)

#define	R600_MCD_SYSTEM_ACCESS_MODE_MASK (3 << 6)

#define	R600_MCD_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6)

#define	R600_MCD_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6)

#define	R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS (2 << 6)

#define	R600_MCD_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6)

#define	R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8)

#define	R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8)

#define	R600_MCD_SEMAPHORE_MODE (1 << 10)

#define	R600_MCD_WAIT_L2_QUERY (1 << 11)

#define	R600_MCD_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 12)

#define	R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15)

#define	R700_MC_VM_MD_L1_TLB0_CNTL 0x2654

#define	R700_MC_VM_MD_L1_TLB1_CNTL 0x2658

#define	R700_MC_VM_MD_L1_TLB2_CNTL 0x265c

#define	R700_MC_VM_MB_L1_TLB0_CNTL 0x2234

#define	R700_MC_VM_MB_L1_TLB1_CNTL 0x2238

#define	R700_MC_VM_MB_L1_TLB2_CNTL 0x223c

#define	R700_MC_VM_MB_L1_TLB3_CNTL 0x2240

#define	R700_ENABLE_L1_TLB (1 << 0)

#define	R700_ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)

#define	R700_SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)

#define	R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)

#define	R700_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 15)

#define	R700_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 18)

#define	R700_MC_ARB_RAMCFG 0x2760

#define	R700_NOOFBANK_SHIFT 0

#define	R700_NOOFBANK_MASK 0x3

#define	R700_NOOFRANK_SHIFT 2

#define	R700_NOOFRANK_MASK 0x1

#define	R700_NOOFROWS_SHIFT 3

#define	R700_NOOFROWS_MASK 0x7

#define	R700_NOOFCOLS_SHIFT 6

#define	R700_NOOFCOLS_MASK 0x3

#define	R700_CHANSIZE_SHIFT 8

#define	R700_CHANSIZE_MASK 0x1

#define	R700_BURSTLENGTH_SHIFT 9

#define	R700_BURSTLENGTH_MASK 0x1

#define	R600_RAMCFG 0x2408

#define	R600_NOOFBANK_SHIFT 0

#define	R600_NOOFBANK_MASK 0x1

#define	R600_NOOFRANK_SHIFT 1

#define	R600_NOOFRANK_MASK 0x1

#define	R600_NOOFROWS_SHIFT 2

#define	R600_NOOFROWS_MASK 0x7

#define	R600_NOOFCOLS_SHIFT 5

#define	R600_NOOFCOLS_MASK 0x3

#define	R600_CHANSIZE_SHIFT 7

#define	R600_CHANSIZE_MASK 0x1

#define	R600_BURSTLENGTH_SHIFT 8

#define	R600_BURSTLENGTH_MASK 0x1

#define	R600_VM_L2_CNTL 0x1400

#define	R600_VM_L2_CACHE_EN (1 << 0)

#define	R600_VM_L2_FRAG_PROC (1 << 1)

#define	R600_VM_ENABLE_PTE_CACHE_LRU_W (1 << 9)

#define	R600_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 13)

#define	R700_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 14)

#define	R600_VM_L2_CNTL2 0x1404

#define	R600_VM_L2_CNTL2_INVALIDATE_ALL_L1_TLBS (1 << 0)

#define	R600_VM_L2_CNTL2_INVALIDATE_L2_CACHE (1 << 1)

#define	R600_VM_L2_CNTL3 0x1408

#define	R600_VM_L2_CNTL3_BANK_SELECT_0(x) ((x) << 0)

#define	R600_VM_L2_CNTL3_BANK_SELECT_1(x) ((x) << 5)

#define	R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 10)

#define	R700_VM_L2_CNTL3_BANK_SELECT(x) ((x) << 0)

#define	R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 6)

#define	R600_VM_L2_STATUS 0x140c

#define	R600_VM_CONTEXT0_CNTL 0x1410

#define	R600_VM_ENABLE_CONTEXT (1 << 0)

#define	R600_VM_PAGE_TABLE_DEPTH_FLAT (0 << 1)

#define	R600_VM_CONTEXT0_CNTL2 0x1430

#define	R600_VM_CONTEXT0_REQUEST_RESPONSE 0x1470

#define	R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490

#define	R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14b0

#define	R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574

#define	R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594

#define	R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15b4

#define	R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c

#define	R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c

#define	R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157c

#define	R600_HDP_HOST_PATH_CNTL 0x2c00

#define	R600_GRBM_CNTL 0x8000

#define	R600_GRBM_READ_TIMEOUT(x) ((x) << 0)

#define	R600_GRBM_STATUS 0x8010

#define	R600_CMDFIFO_AVAIL_MASK 0x1f

#define	R700_CMDFIFO_AVAIL_MASK 0xf

#define	R600_GUI_ACTIVE (1 << 31)

#define	R600_GRBM_STATUS2 0x8014

#define	R600_GRBM_SOFT_RESET 0x8020

#define	R600_SOFT_RESET_CP (1 << 0)

#define	R600_WAIT_UNTIL 0x8040

#define	R600_CP_SEM_WAIT_TIMER 0x85bc

#define	R600_CP_ME_CNTL 0x86d8

#define	R600_CP_ME_HALT (1 << 28)

#define	R600_CP_QUEUE_THRESHOLDS 0x8760

#define	R600_ROQ_IB1_START(x) ((x) << 0)

#define	R600_ROQ_IB2_START(x) ((x) << 8)

#define	R600_CP_MEQ_THRESHOLDS 0x8764

#define	R700_STQ_SPLIT(x) ((x) << 0)

#define	R600_MEQ_END(x) ((x) << 16)

#define	R600_ROQ_END(x) ((x) << 24)

#define	R600_CP_PERFMON_CNTL 0x87fc

#define	R600_CP_RB_BASE 0xc100

#define	R600_CP_RB_CNTL 0xc104

#define	R600_RB_BUFSZ(x) ((x) << 0)

#define	R600_RB_BLKSZ(x) ((x) << 8)

#define	R600_BUF_SWAP_32BIT (2 << 16)

#define	R600_RB_NO_UPDATE (1 << 27)

#define	R600_RB_RPTR_WR_ENA (1 << 31)

#define	R600_CP_RB_RPTR_WR 0xc108

#define	R600_CP_RB_RPTR_ADDR 0xc10c

#define	R600_CP_RB_RPTR_ADDR_HI 0xc110

#define	R600_CP_RB_WPTR 0xc114

#define	R600_CP_RB_WPTR_ADDR 0xc118

#define	R600_CP_RB_WPTR_ADDR_HI 0xc11c

#define	R600_CP_RB_RPTR 0x8700

#define	R600_CP_RB_WPTR_DELAY 0x8704

#define	R600_CP_PFP_UCODE_ADDR 0xc150

#define	R600_CP_PFP_UCODE_DATA 0xc154

#define	R600_CP_ME_RAM_RADDR 0xc158

#define	R600_CP_ME_RAM_WADDR 0xc15c

#define	R600_CP_ME_RAM_DATA 0xc160

#define	R600_CP_DEBUG 0xc1fc

#define	R600_PA_CL_ENHANCE 0x8a14

#define	R600_CLIP_VTX_REORDER_ENA (1 << 0)

#define	R600_NUM_CLIP_SEQ(x) ((x) << 1)

#define	R600_PA_SC_LINE_STIPPLE_STATE 0x8b10

#define	R600_PA_SC_MULTI_CHIP_CNTL 0x8b20

#define	R700_PA_SC_FORCE_EOV_MAX_CNTS 0x8b24

#define	R700_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)

#define	R700_FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)

#define	R600_PA_SC_AA_SAMPLE_LOCS_2S 0x8b40

#define	R600_PA_SC_AA_SAMPLE_LOCS_4S 0x8b44

#define	R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8b48

#define	R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8b4c

#define	R600_S0_X(x) ((x) << 0)

#define	R600_S0_Y(x) ((x) << 4)

#define	R600_S1_X(x) ((x) << 8)

#define	R600_S1_Y(x) ((x) << 12)

#define	R600_S2_X(x) ((x) << 16)

#define	R600_S2_Y(x) ((x) << 20)

#define	R600_S3_X(x) ((x) << 24)

#define	R600_S3_Y(x) ((x) << 28)

#define	R600_S4_X(x) ((x) << 0)

#define	R600_S4_Y(x) ((x) << 4)

#define	R600_S5_X(x) ((x) << 8)

#define	R600_S5_Y(x) ((x) << 12)

#define	R600_S6_X(x) ((x) << 16)

#define	R600_S6_Y(x) ((x) << 20)

#define	R600_S7_X(x) ((x) << 24)

#define	R600_S7_Y(x) ((x) << 28)

#define	R600_PA_SC_FIFO_SIZE 0x8bd0

#define	R600_SC_PRIM_FIFO_SIZE(x) ((x) << 0)

#define	R600_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 8)

#define	R600_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 16)

#define	R700_PA_SC_FIFO_SIZE_R7XX 0x8bcc

#define	R700_SC_PRIM_FIFO_SIZE(x) ((x) << 0)

#define	R700_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)

#define	R700_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)

#define	R600_PA_SC_ENHANCE 0x8bf0

#define	R600_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)

#define	R600_FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12)

#define	R600_PA_SC_CLIPRECT_RULE 0x2820c

#define	R700_PA_SC_EDGERULE 0x28230

#define	R600_PA_SC_LINE_STIPPLE 0x28a0c

#define	R600_PA_SC_MODE_CNTL 0x28a4c

#define	R600_PA_SC_AA_CONFIG 0x28c04

#define	R600_SX_EXPORT_BUFFER_SIZES 0x900c

#define	R600_COLOR_BUFFER_SIZE(x) ((x) << 0)

#define	R600_POSITION_BUFFER_SIZE(x) ((x) << 8)

#define	R600_SMX_BUFFER_SIZE(x) ((x) << 16)

#define	R600_SX_DEBUG_1 0x9054

#define	R600_SMX_EVENT_RELEASE (1 << 0)

#define	R600_ENABLE_NEW_SMX_ADDRESS (1 << 16)

#define	R700_SX_DEBUG_1 0x9058

#define	R700_ENABLE_NEW_SMX_ADDRESS (1 << 16)

#define	R600_SX_MISC 0x28350

#define	R600_DB_DEBUG 0x9830

#define	R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)

#define	R600_DB_WATERMARKS 0x9838

#define	R600_DEPTH_FREE(x) ((x) << 0)

#define	R600_DEPTH_FLUSH(x) ((x) << 5)

#define	R600_DEPTH_PENDING_FREE(x) ((x) << 15)

#define	R600_DEPTH_CACHELINE_FREE(x) ((x) << 20)

#define	R700_DB_DEBUG3 0x98b0

#define	R700_DB_CLK_OFF_DELAY(x) ((x) << 11)

#define	RV700_DB_DEBUG4 0x9b8c

#define	RV700_DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6)

#define	R600_VGT_CACHE_INVALIDATION 0x88c4

#define	R600_CACHE_INVALIDATION(x) ((x) << 0)

#define	R600_VC_ONLY 0

#define	R600_TC_ONLY 1

#define	R600_VC_AND_TC 2

#define	R700_AUTO_INVLD_EN(x) ((x) << 6)

#define	R700_NO_AUTO 0

#define	R700_ES_AUTO 1

#define	R700_GS_AUTO 2

#define	R700_ES_AND_GS_AUTO 3

#define	R600_VGT_GS_PER_ES 0x88c8

#define	R600_VGT_ES_PER_GS 0x88cc

#define	R600_VGT_GS_PER_VS 0x88e8

#define	R600_VGT_GS_VERTEX_REUSE 0x88d4

#define	R600_VGT_NUM_INSTANCES 0x8974

#define	R600_VGT_STRMOUT_EN 0x28ab0

#define	R600_VGT_EVENT_INITIATOR 0x28a90

#define	R600_CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)

#define	R600_VGT_VERTEX_REUSE_BLOCK_CNTL 0x28c58

#define	R600_VTX_REUSE_DEPTH_MASK 0xff

#define	R600_VGT_OUT_DEALLOC_CNTL 0x28c5c

#define	R600_DEALLOC_DIST_MASK 0x7f

#define	R600_CB_COLOR0_BASE 0x28040

#define	R600_CB_COLOR1_BASE 0x28044

#define	R600_CB_COLOR2_BASE 0x28048

#define	R600_CB_COLOR3_BASE 0x2804c

#define	R600_CB_COLOR4_BASE 0x28050

#define	R600_CB_COLOR5_BASE 0x28054

#define	R600_CB_COLOR6_BASE 0x28058

#define	R600_CB_COLOR7_BASE 0x2805c

#define	R600_CB_COLOR7_FRAG 0x280fc

#define	R600_CB_COLOR0_SIZE 0x28060

#define	R600_CB_COLOR0_VIEW 0x28080

#define	R600_CB_COLOR0_INFO 0x280a0

#define	R600_CB_COLOR0_TILE 0x280c0

#define	R600_CB_COLOR0_FRAG 0x280e0

#define	R600_CB_COLOR0_MASK 0x28100

#define	AVIVO_D1MODE_VLINE_START_END 0x6538

#define	AVIVO_D2MODE_VLINE_START_END 0x6d38

#define	R600_CP_COHER_BASE 0x85f8

#define	R600_DB_DEPTH_BASE 0x2800c

#define	R600_SQ_PGM_START_FS 0x28894

#define	R600_SQ_PGM_START_ES 0x28880

#define	R600_SQ_PGM_START_VS 0x28858

#define	R600_SQ_PGM_RESOURCES_VS 0x28868

#define	R600_SQ_PGM_CF_OFFSET_VS 0x288d0

#define	R600_SQ_PGM_START_GS 0x2886c

#define	R600_SQ_PGM_START_PS 0x28840

#define	R600_SQ_PGM_RESOURCES_PS 0x28850

#define	R600_SQ_PGM_EXPORTS_PS 0x28854

#define	R600_SQ_PGM_CF_OFFSET_PS 0x288cc

#define	R600_VGT_DMA_BASE 0x287e8

#define	R600_VGT_DMA_BASE_HI 0x287e4

#define	R600_VGT_STRMOUT_BASE_OFFSET_0 0x28b10

#define	R600_VGT_STRMOUT_BASE_OFFSET_1 0x28b14

#define	R600_VGT_STRMOUT_BASE_OFFSET_2 0x28b18

#define	R600_VGT_STRMOUT_BASE_OFFSET_3 0x28b1c

#define	R600_VGT_STRMOUT_BASE_OFFSET_HI_0 0x28b44

#define	R600_VGT_STRMOUT_BASE_OFFSET_HI_1 0x28b48

#define	R600_VGT_STRMOUT_BASE_OFFSET_HI_2 0x28b4c

#define	R600_VGT_STRMOUT_BASE_OFFSET_HI_3 0x28b50

#define	R600_VGT_STRMOUT_BUFFER_BASE_0 0x28ad8

#define	R600_VGT_STRMOUT_BUFFER_BASE_1 0x28ae8

#define	R600_VGT_STRMOUT_BUFFER_BASE_2 0x28af8

#define	R600_VGT_STRMOUT_BUFFER_BASE_3 0x28b08

#define	R600_VGT_STRMOUT_BUFFER_OFFSET_0 0x28adc

#define	R600_VGT_STRMOUT_BUFFER_OFFSET_1 0x28aec

#define	R600_VGT_STRMOUT_BUFFER_OFFSET_2 0x28afc

#define	R600_VGT_STRMOUT_BUFFER_OFFSET_3 0x28b0c

#define	R600_VGT_PRIMITIVE_TYPE 0x8958

#define	R600_PA_SC_SCREEN_SCISSOR_TL 0x28030

#define	R600_PA_SC_GENERIC_SCISSOR_TL 0x28240

#define	R600_PA_SC_WINDOW_SCISSOR_TL 0x28204

#define	R600_TC_CNTL 0x9608

#define	R600_TC_L2_SIZE(x) ((x) << 5)

#define	R600_L2_DISABLE_LATE_HIT (1 << 9)

#define	R600_ARB_POP 0x2418

#define	R600_ENABLE_TC128 (1 << 30)

#define	R600_ARB_GDEC_RD_CNTL 0x246c

#define	R600_TA_CNTL_AUX 0x9508

#define	R600_DISABLE_CUBE_WRAP (1 << 0)

#define	R600_DISABLE_CUBE_ANISO (1 << 1)

#define	R700_GETLOD_SELECT(x) ((x) << 2)

#define	R600_SYNC_GRADIENT (1 << 24)

#define	R600_SYNC_WALKER (1 << 25)

#define	R600_SYNC_ALIGNER (1 << 26)

#define	R600_BILINEAR_PRECISION_6_BIT (0 << 31)

#define	R600_BILINEAR_PRECISION_8_BIT (1 << 31)

#define	R700_TCP_CNTL 0x9610

#define	R600_SMX_DC_CTL0 0xa020

#define	R700_USE_HASH_FUNCTION (1 << 0)

#define	R700_CACHE_DEPTH(x) ((x) << 1)

#define	R700_FLUSH_ALL_ON_EVENT (1 << 10)

#define	R700_STALL_ON_EVENT (1 << 11)

#define	R700_SMX_EVENT_CTL 0xa02c

#define	R700_ES_FLUSH_CTL(x) ((x) << 0)

#define	R700_GS_FLUSH_CTL(x) ((x) << 3)

#define	R700_ACK_FLUSH_CTL(x) ((x) << 6)

#define	R700_SYNC_FLUSH_CTL (1 << 8)

#define	R600_SQ_CONFIG 0x8c00

#define	R600_VC_ENABLE (1 << 0)

#define	R600_EXPORT_SRC_C (1 << 1)

#define	R600_DX9_CONSTS (1 << 2)

#define	R600_ALU_INST_PREFER_VECTOR (1 << 3)

#define	R600_DX10_CLAMP (1 << 4)

#define	R600_CLAUSE_SEQ_PRIO(x) ((x) << 8)

#define	R600_PS_PRIO(x) ((x) << 24)

#define	R600_VS_PRIO(x) ((x) << 26)

#define	R600_GS_PRIO(x) ((x) << 28)

#define	R600_ES_PRIO(x) ((x) << 30)

#define	R600_SQ_GPR_RESOURCE_MGMT_1 0x8c04

#define	R600_NUM_PS_GPRS(x) ((x) << 0)

#define	R600_NUM_VS_GPRS(x) ((x) << 16)

#define	R700_DYN_GPR_ENABLE (1 << 27)

#define	R600_NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)

#define	R600_SQ_GPR_RESOURCE_MGMT_2 0x8c08

#define	R600_NUM_GS_GPRS(x) ((x) << 0)

#define	R600_NUM_ES_GPRS(x) ((x) << 16)

#define	R600_SQ_THREAD_RESOURCE_MGMT 0x8c0c

#define	R600_NUM_PS_THREADS(x) ((x) << 0)

#define	R600_NUM_VS_THREADS(x) ((x) << 8)

#define	R600_NUM_GS_THREADS(x) ((x) << 16)

#define	R600_NUM_ES_THREADS(x) ((x) << 24)

#define	R600_SQ_STACK_RESOURCE_MGMT_1 0x8c10

#define	R600_NUM_PS_STACK_ENTRIES(x) ((x) << 0)

#define	R600_NUM_VS_STACK_ENTRIES(x) ((x) << 16)

#define	R600_SQ_STACK_RESOURCE_MGMT_2 0x8c14

#define	R600_NUM_GS_STACK_ENTRIES(x) ((x) << 0)

#define	R600_NUM_ES_STACK_ENTRIES(x) ((x) << 16)

#define	R600_SQ_MS_FIFO_SIZES 0x8cf0

#define	R600_CACHE_FIFO_SIZE(x) ((x) << 0)

#define	R600_FETCH_FIFO_HIWATER(x) ((x) << 8)

#define	R600_DONE_FIFO_HIWATER(x) ((x) << 16)

#define	R600_ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)

#define	R700_SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8db0

#define	R700_SIMDA_RING0(x) ((x) << 0)

#define	R700_SIMDA_RING1(x) ((x) << 8)

#define	R700_SIMDB_RING0(x) ((x) << 16)

#define	R700_SIMDB_RING1(x) ((x) << 24)

#define	R700_SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8db4

#define	R700_SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8db8

#define	R700_SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8dbc

#define	R700_SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8dc0

#define	R700_SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8dc4

#define	R700_SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8dc8

#define	R700_SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8dcc

#define	R600_SPI_PS_IN_CONTROL_0 0x286cc

#define	R600_NUM_INTERP(x) ((x) << 0)

#define	R600_POSITION_ENA (1 << 8)

#define	R600_POSITION_CENTROID (1 << 9)

#define	R600_POSITION_ADDR(x) ((x) << 10)

#define	R600_PARAM_GEN(x) ((x) << 15)

#define	R600_PARAM_GEN_ADDR(x) ((x) << 19)

#define	R600_BARYC_SAMPLE_CNTL(x) ((x) << 26)

#define	R600_PERSP_GRADIENT_ENA (1 << 28)

#define	R600_LINEAR_GRADIENT_ENA (1 << 29)

#define	R600_POSITION_SAMPLE (1 << 30)

#define	R600_BARYC_AT_SAMPLE_ENA (1 << 31)

#define	R600_SPI_PS_IN_CONTROL_1 0x286d0

#define	R600_GEN_INDEX_PIX (1 << 0)

#define	R600_GEN_INDEX_PIX_ADDR(x) ((x) << 1)

#define	R600_FRONT_FACE_ENA (1 << 8)

#define	R600_FRONT_FACE_CHAN(x) ((x) << 9)

#define	R600_FRONT_FACE_ALL_BITS (1 << 11)

#define	R600_FRONT_FACE_ADDR(x) ((x) << 12)

#define	R600_FOG_ADDR(x) ((x) << 17)

#define	R600_FIXED_PT_POSITION_ENA (1 << 24)

#define	R600_FIXED_PT_POSITION_ADDR(x) ((x) << 25)

#define	R700_POSITION_ULC (1 << 30)

#define	R600_SPI_INPUT_Z 0x286d8

#define	R600_SPI_CONFIG_CNTL 0x9100

#define	R600_GPR_WRITE_PRIORITY(x) ((x) << 0)

#define	R600_DISABLE_INTERP_1 (1 << 5)

#define	R600_SPI_CONFIG_CNTL_1 0x913c

#define	R600_VTX_DONE_DELAY(x) ((x) << 0)

#define	R600_INTERP_ONE_PRIM_PER_ROW (1 << 4)

#define	R600_GB_TILING_CONFIG 0x98f0

#define	R600_PIPE_TILING(x) ((x) << 1)

#define	R600_BANK_TILING(x) ((x) << 4)

#define	R600_GROUP_SIZE(x) ((x) << 6)

#define	R600_ROW_TILING(x) ((x) << 8)

#define	R600_BANK_SWAPS(x) ((x) << 11)

#define	R600_SAMPLE_SPLIT(x) ((x) << 14)

#define	R600_BACKEND_MAP(x) ((x) << 16)

#define	R600_DCP_TILING_CONFIG 0x6ca0

#define	R600_HDP_TILING_CONFIG 0x2f3c

#define	R600_CC_RB_BACKEND_DISABLE 0x98f4

#define	R700_CC_SYS_RB_BACKEND_DISABLE 0x3f88

#define	R600_BACKEND_DISABLE(x) ((x) << 16)

#define	R600_CC_GC_SHADER_PIPE_CONFIG 0x8950

#define	R600_GC_USER_SHADER_PIPE_CONFIG 0x8954

#define	R600_INACTIVE_QD_PIPES(x) ((x) << 8)

#define	R600_INACTIVE_QD_PIPES_MASK (0xff << 8)

#define	R600_INACTIVE_SIMDS(x) ((x) << 16)

#define	R600_INACTIVE_SIMDS_MASK (0xff << 16)

#define	R700_CGTS_SYS_TCC_DISABLE 0x3f90

#define	R700_CGTS_USER_SYS_TCC_DISABLE 0x3f94

#define	R700_CGTS_TCC_DISABLE 0x9148

#define	R700_CGTS_USER_TCC_DISABLE 0x914c

#define	RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */

#define	RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0

#define	RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1

#define	RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2

#define	RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3

#define	RADEON_LAST_DISPATCH 1

#define	R600_LAST_FRAME_REG R600_SCRATCH_REG0

#define	R600_LAST_DISPATCH_REG R600_SCRATCH_REG1

#define	R600_LAST_CLEAR_REG R600_SCRATCH_REG2

#define	R600_LAST_SWI_REG R600_SCRATCH_REG3

#define	RADEON_MAX_VB_AGE 0x7fffffff

#define	RADEON_MAX_VB_VERTS (0xffff)

#define	RADEON_RING_HIGH_MARK 128

#define	RADEON_PCIGART_TABLE_SIZE (32*1024)

#define	RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )

#define	RADEON_WRITE(reg, val)

#define	RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )

#define	RADEON_WRITE8(reg, val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )

#define	RADEON_WRITE_PLL(addr, val)

#define	RADEON_WRITE_PCIE(addr, val)

#define	R500_WRITE_MCIND(addr, val)

#define	RS480_WRITE_MCIND(addr, val)

#define	RS690_WRITE_MCIND(addr, val)

#define	RS600_WRITE_MCIND(addr, val)

#define	IGP_WRITE_MCIND(addr, val)

#define	CP_PACKET0(reg, n) (RADEON_CP_PACKET0 \| ((n) << 16) \| ((reg) >> 2))

#define	CP_PACKET0_TABLE(reg, n) (RADEON_CP_PACKET0 \| RADEON_ONE_REG_WR \| ((n) << 16) \| ((reg) >> 2))

#define	CP_PACKET1(reg0, reg1) (RADEON_CP_PACKET1 \| (((reg1) >> 2) << 15) \| ((reg0) >> 2))

#define	CP_PACKET2() (RADEON_CP_PACKET2)

#define	CP_PACKET3(pkt, n) (RADEON_CP_PACKET3 \| (pkt) \| ((n) << 16))

#define	RADEON_WAIT_UNTIL_2D_IDLE()

#define	RADEON_WAIT_UNTIL_3D_IDLE()

#define	RADEON_WAIT_UNTIL_IDLE()

#define	RADEON_WAIT_UNTIL_PAGE_FLIPPED()

#define	RADEON_FLUSH_CACHE()

#define	RADEON_PURGE_CACHE()

#define	RADEON_FLUSH_ZCACHE()

#define	RADEON_PURGE_ZCACHE()

#define	RING_SPACE_TEST_WITH_RETURN(dev_priv)

#define	VB_AGE_TEST_WITH_RETURN(dev_priv)

#define	RADEON_DISPATCH_AGE(age)

#define	RADEON_FRAME_AGE(age)

#define	RADEON_CLEAR_AGE(age)

#define	R600_DISPATCH_AGE(age)

#define	R600_FRAME_AGE(age)

#define	R600_CLEAR_AGE(age)

#define	RADEON_VERBOSE 0

#define	RING_LOCALS int write, _nr, _align_nr; unsigned int mask; u32 *ring;

#define	RADEON_RING_ALIGN 16

#define	BEGIN_RING(n)

#define	ADVANCE_RING()

#define	COMMIT_RING()

#define	OUT_RING(x)

#define	OUT_RING_REG(reg, val)

#define	OUT_RING_TABLE(tab, sz)

#define	OUT_RING_DRM_BUFFER(buf, sz)

Typedefs
typedef struct drm_radeon_freelist	drm_radeon_freelist_t

typedef struct drm_radeon_ring_buffer	drm_radeon_ring_buffer_t

typedef struct drm_radeon_depth_clear_t	drm_radeon_depth_clear_t

typedef struct drm_radeon_private	drm_radeon_private_t

typedef struct drm_radeon_buf_priv	drm_radeon_buf_priv_t

typedef struct drm_radeon_kcmd_buffer	drm_radeon_kcmd_buffer_t

Enumerations
enum	radeon_cp_microcode_version { UCODE_R100, UCODE_R200, UCODE_R300 }

Functions
u32	radeon_get_ring_head (drm_radeon_private_t *dev_priv)

void	radeon_set_ring_head (drm_radeon_private_t *dev_priv, u32 val)

void	radeon_cp_discard_buffer (struct drm_device dev, struct drm_master master, struct drm_buf *buf)

int	radeon_cp_init (struct drm_device dev, void data, struct drm_file *file_priv)

int	radeon_cp_start (struct drm_device dev, void data, struct drm_file *file_priv)

int	radeon_cp_stop (struct drm_device dev, void data, struct drm_file *file_priv)

int	radeon_cp_reset (struct drm_device dev, void data, struct drm_file *file_priv)

int	radeon_cp_idle (struct drm_device dev, void data, struct drm_file *file_priv)

int	radeon_cp_resume (struct drm_device dev, void data, struct drm_file *file_priv)

int	radeon_engine_reset (struct drm_device dev, void data, struct drm_file *file_priv)

int	radeon_fullscreen (struct drm_device dev, void data, struct drm_file *file_priv)

int	radeon_cp_buffers (struct drm_device dev, void data, struct drm_file *file_priv)

u32	radeon_read_fb_location (drm_radeon_private_t *dev_priv)

void	radeon_write_agp_location (drm_radeon_private_t *dev_priv, u32 agp_loc)

void	radeon_write_agp_base (drm_radeon_private_t *dev_priv, u64 agp_base)

u32	RADEON_READ_MM (drm_radeon_private_t *dev_priv, int addr)

void	radeon_freelist_reset (struct drm_device *dev)

struct drm_buf *	radeon_freelist_get (struct drm_device *dev)

int	radeon_wait_ring (drm_radeon_private_t *dev_priv, int n)

int	radeon_do_cp_idle (drm_radeon_private_t *dev_priv)

int	radeon_driver_preinit (struct drm_device *dev, unsigned long flags)

int	radeon_presetup (struct drm_device *dev)

int	radeon_driver_postcleanup (struct drm_device *dev)

int	radeon_mem_alloc (struct drm_device dev, void data, struct drm_file *file_priv)

int	radeon_mem_free (struct drm_device dev, void data, struct drm_file *file_priv)

int	radeon_mem_init_heap (struct drm_device dev, void data, struct drm_file *file_priv)

void	radeon_mem_takedown (struct mem_block **heap)

void	radeon_mem_release (struct drm_file file_priv, struct mem_block heap)

void	radeon_enable_bm (struct drm_radeon_private *dev_priv)

u32	radeon_read_ring_rptr (drm_radeon_private_t *dev_priv, u32 off)

void	radeon_write_ring_rptr (drm_radeon_private_t *dev_priv, u32 off, u32 val)

void	radeon_irq_set_state (struct drm_device *dev, u32 mask, int state)

int	radeon_irq_emit (struct drm_device dev, void data, struct drm_file *file_priv)

int	radeon_irq_wait (struct drm_device dev, void data, struct drm_file *file_priv)

void	radeon_do_release (struct drm_device *dev)

u32	radeon_get_vblank_counter (struct drm_device *dev, int crtc)

int	radeon_enable_vblank (struct drm_device *dev, int crtc)

void	radeon_disable_vblank (struct drm_device *dev, int crtc)

irqreturn_t	radeon_driver_irq_handler (DRM_IRQ_ARGS)

void	radeon_driver_irq_preinstall (struct drm_device *dev)

int	radeon_driver_irq_postinstall (struct drm_device *dev)

void	radeon_driver_irq_uninstall (struct drm_device *dev)

void	radeon_enable_interrupt (struct drm_device *dev)

int	radeon_vblank_crtc_get (struct drm_device *dev)

int	radeon_vblank_crtc_set (struct drm_device *dev, int64_t value)

int	radeon_driver_load (struct drm_device *dev, unsigned long flags)

int	radeon_driver_unload (struct drm_device *dev)

int	radeon_driver_firstopen (struct drm_device *dev)

void	radeon_driver_preclose (struct drm_device dev, struct drm_file file_priv)

void	radeon_driver_postclose (struct drm_device dev, struct drm_file file_priv)

void	radeon_driver_lastclose (struct drm_device *dev)

int	radeon_driver_open (struct drm_device dev, struct drm_file file_priv)

long	radeon_compat_ioctl (struct file *filp, unsigned int cmd, unsigned long arg)

long	radeon_kms_compat_ioctl (struct file *filp, unsigned int cmd, unsigned long arg)

int	radeon_master_create (struct drm_device dev, struct drm_master master)

void	radeon_master_destroy (struct drm_device dev, struct drm_master master)

void	radeon_cp_dispatch_flip (struct drm_device dev, struct drm_master master)

void	r300_init_reg_flags (struct drm_device *dev)

int	r300_do_cp_cmdbuf (struct drm_device dev, struct drm_file file_priv, drm_radeon_kcmd_buffer_t *cmdbuf)

int	r600_do_engine_reset (struct drm_device *dev)

int	r600_do_cleanup_cp (struct drm_device *dev)

int	r600_do_init_cp (struct drm_device dev, drm_radeon_init_t init, struct drm_file *file_priv)

int	r600_do_resume_cp (struct drm_device dev, struct drm_file file_priv)

int	r600_do_cp_idle (drm_radeon_private_t *dev_priv)

void	r600_do_cp_start (drm_radeon_private_t *dev_priv)

void	r600_do_cp_reset (drm_radeon_private_t *dev_priv)

void	r600_do_cp_stop (drm_radeon_private_t *dev_priv)

int	r600_cp_dispatch_indirect (struct drm_device dev, struct drm_buf buf, int start, int end)

int	r600_page_table_init (struct drm_device *dev)

void	r600_page_table_cleanup (struct drm_device dev, struct drm_ati_pcigart_info gart_info)

int	r600_cs_legacy_ioctl (struct drm_device dev, void data, struct drm_file *fpriv)

void	r600_cp_dispatch_swap (struct drm_device dev, struct drm_file file_priv)

int	r600_cp_dispatch_texture (struct drm_device dev, struct drm_file file_priv, drm_radeon_texture_t tex, drm_radeon_tex_image_t image)

int	r600_prepare_blit_copy (struct drm_device dev, struct drm_file file_priv)

void	r600_done_blit_copy (struct drm_device *dev)

void	r600_blit_copy (struct drm_device *dev, uint64_t src_gpu_addr, uint64_t dst_gpu_addr, int size_bytes)

void	r600_blit_swap (struct drm_device *dev, uint64_t src_gpu_addr, uint64_t dst_gpu_addr, int sx, int sy, int dx, int dy, int w, int h, int src_pitch, int dst_pitch, int cpp)

u32	radeon_get_scratch (drm_radeon_private_t *dev_priv, int index)

void	radeon_commit_ring (drm_radeon_private_t *dev_priv)

Variables
int	radeon_no_wb

struct drm_ioctl_desc	radeon_ioctls []

int	radeon_max_ioctl

Macro Definition Documentation

#define ADVANCE_RING ( )

Value:

do {                        \
    if ( RADEON_VERBOSE ) {                     \
        DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
              write, dev_priv->ring.tail );         \
    }                               \
    if (((dev_priv->ring.tail + _nr) & mask) != write) {        \
        DRM_ERROR(                      \
            "ADVANCE_RING(): mismatch: nr: %x write: %x line: %d\n",    \
            ((dev_priv->ring.tail + _nr) & mask),       \
            write, __LINE__);               \
    } else                              \
        dev_priv->ring.tail = write;                \
} while (0)

Definition at line 2086 of file radeon_drv.h.

#define AVIVO_D1MODE_VLINE_START_END 0x6538

Definition at line 1653 of file radeon_drv.h.

#define AVIVO_D2MODE_VLINE_START_END 0x6d38

Definition at line 1654 of file radeon_drv.h.

#define BEGIN_RING ( n )

Value:

do {                        \
    if ( RADEON_VERBOSE ) {                     \
        DRM_INFO( "BEGIN_RING( %d )\n", (n));           \
    }                               \
    _align_nr = RADEON_RING_ALIGN - ((dev_priv->ring.tail + n) & (RADEON_RING_ALIGN-1));    \
    _align_nr += n;                         \
    if (dev_priv->ring.space <= (_align_nr * sizeof(u32))) {    \
                COMMIT_RING();                      \
        radeon_wait_ring( dev_priv, _align_nr * sizeof(u32));   \
    }                               \
    _nr = n; dev_priv->ring.space -= (n) * sizeof(u32);     \
	ring = dev_priv->ring.start;                   \
    write = dev_priv->ring.tail;                    \
    mask = dev_priv->ring.tail_mask;                \
} while (0)

Definition at line 2070 of file radeon_drv.h.

#define COMMIT_RING ( )

Value:

do {                        \
        radeon_commit_ring(dev_priv);               \
    } while(0)

Definition at line 2102 of file radeon_drv.h.

#define CP_PACKET0	(	reg,
		n
	)	(RADEON_CP_PACKET0 \| ((n) << 16) \| ((reg) >> 2))

Definition at line 1917 of file radeon_drv.h.

#define CP_PACKET0_TABLE	(	reg,
		n
	)	(RADEON_CP_PACKET0 \| RADEON_ONE_REG_WR \| ((n) << 16) \| ((reg) >> 2))

Definition at line 1919 of file radeon_drv.h.

#define CP_PACKET1	(	reg0,
		reg1
	)	(RADEON_CP_PACKET1 \| (((reg1) >> 2) << 15) \| ((reg0) >> 2))

Definition at line 1921 of file radeon_drv.h.

#define CP_PACKET2 ( ) (RADEON_CP_PACKET2)

Definition at line 1923 of file radeon_drv.h.

#define CP_PACKET3	(	pkt,
		n
	)	(RADEON_CP_PACKET3 \| (pkt) \| ((n) << 16))

Definition at line 1925 of file radeon_drv.h.

#define DRIVER_AUTHOR "Gareth Hughes, Keith Whitwell, others."

Definition at line 42 of file radeon_drv.h.

#define DRIVER_DATE "20080528"

Definition at line 46 of file radeon_drv.h.

#define DRIVER_DESC "ATI Radeon"

Definition at line 45 of file radeon_drv.h.

#define DRIVER_MAJOR 1

Definition at line 112 of file radeon_drv.h.

#define DRIVER_MINOR 33

Definition at line 113 of file radeon_drv.h.

#define DRIVER_NAME "radeon"

Definition at line 44 of file radeon_drv.h.

#define DRIVER_PATCHLEVEL 0

Definition at line 114 of file radeon_drv.h.

#define GET_RING_HEAD ( dev_priv ) radeon_get_ring_head(dev_priv)

Definition at line 335 of file radeon_drv.h.

#define GET_SCRATCH	(	dev_priv,
		x
	)	radeon_get_scratch(dev_priv, x)

Definition at line 745 of file radeon_drv.h.

#define IGP_WRITE_MCIND	(	addr,
		val
	)

Value:

do {                                    \
    if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||   \
        ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))      \
        RS690_WRITE_MCIND(addr, val);               \
    else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)  \
        RS600_WRITE_MCIND(addr, val);               \
	else								\
		RS480_WRITE_MCIND(addr, val);             \
} while (0)

Definition at line 1906 of file radeon_drv.h.

#define OUT_RING ( x )

Value:

do {                        \
    if ( RADEON_VERBOSE ) {                     \
        DRM_INFO( "   OUT_RING( 0x%08x ) at 0x%x\n",        \
               (unsigned int)(x), write );          \
    }                               \
	ring[write++] = (x);                       \
    write &= mask;                          \
} while (0)

Definition at line 2106 of file radeon_drv.h.

#define OUT_RING_DRM_BUFFER	(	buf,
		sz
	)

Value:

do {                \
    int _size = (sz) * 4;                       \
	struct drm_buffer *_buf = (buf);               \
    int _part_size;                         \
    while (_size > 0) {                     \
        _part_size = _size;                 \
									\
		if (write + _part_size/4 > mask)          \
            _part_size = ((mask + 1) - write)*4;        \
									\
		if (drm_buffer_index(_buf) + _part_size > PAGE_SIZE)  \
            _part_size = PAGE_SIZE - drm_buffer_index(_buf);\
									\
									\
									\
		memcpy(ring + write, &_buf->data[drm_buffer_page(_buf)]   \
            [drm_buffer_index(_buf)], _part_size);      \
                                    \
        _size -= _part_size;                    \
        write = (write + _part_size/4) & mask;          \
        drm_buffer_advance(_buf, _part_size);           \
    }                               \
} while (0)

Copy given number of dwords from drm buffer to the ring buffer.

Definition at line 2146 of file radeon_drv.h.

#define OUT_RING_REG	(	reg,
		val
	)

Value:

do {                    \
    OUT_RING( CP_PACKET0( reg, 0 ) );               \
    OUT_RING( val );                        \
} while (0)

Definition at line 2115 of file radeon_drv.h.

#define OUT_RING_TABLE	(	tab,
		sz
	)

Value:

do {                    \
    int _size = (sz);                   \
    int *_tab = (int *)(tab);               \
								\
	if (write + _size > mask) {                \
        int _i = (mask+1) - write;          \
        _size -= _i;                    \
        while (_i > 0 ) {               \
            *(int *)(ring + write) = *_tab++;   \
            write++;                \
            _i--;                   \
        }                       \
        write = 0;                  \
        _tab += _i;                 \
    }                           \
    while (_size > 0) {                 \
        *(ring + write) = *_tab++;          \
        write++;                    \
        _size--;                    \
    }                           \
    write &= mask;                      \
} while (0)

Definition at line 2120 of file radeon_drv.h.

#define PCIGART_FILE_PRIV ((void *) -1L)

Definition at line 179 of file radeon_drv.h.

#define R200_3D_DRAW_IMMD_2 0xC0003500

Definition at line 1324 of file radeon_drv.h.

#define R200_PP_AFS_0 0x2f80

Definition at line 1334 of file radeon_drv.h.

#define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */

Definition at line 1335 of file radeon_drv.h.

#define R200_PP_CNTL_X 0x2cc4

Definition at line 1292 of file radeon_drv.h.

#define R200_PP_CUBIC_FACES_0 0x2c18

Definition at line 1251 of file radeon_drv.h.

#define R200_PP_CUBIC_FACES_1 0x2c38

Definition at line 1252 of file radeon_drv.h.

#define R200_PP_CUBIC_FACES_2 0x2c58

Definition at line 1253 of file radeon_drv.h.

#define R200_PP_CUBIC_FACES_3 0x2c78

Definition at line 1254 of file radeon_drv.h.

#define R200_PP_CUBIC_FACES_4 0x2c98

Definition at line 1255 of file radeon_drv.h.

#define R200_PP_CUBIC_FACES_5 0x2cb8

Definition at line 1256 of file radeon_drv.h.

#define R200_PP_CUBIC_OFFSET_F1_0 0x2d04

Definition at line 1257 of file radeon_drv.h.

#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c

Definition at line 1262 of file radeon_drv.h.

#define R200_PP_CUBIC_OFFSET_F1_2 0x2d34

Definition at line 1267 of file radeon_drv.h.

#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c

Definition at line 1272 of file radeon_drv.h.

#define R200_PP_CUBIC_OFFSET_F1_4 0x2d64

Definition at line 1277 of file radeon_drv.h.

#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c

Definition at line 1282 of file radeon_drv.h.

#define R200_PP_CUBIC_OFFSET_F2_0 0x2d08

Definition at line 1258 of file radeon_drv.h.

#define R200_PP_CUBIC_OFFSET_F2_1 0x2d20

Definition at line 1263 of file radeon_drv.h.

#define R200_PP_CUBIC_OFFSET_F2_2 0x2d38

Definition at line 1268 of file radeon_drv.h.

#define R200_PP_CUBIC_OFFSET_F2_3 0x2d50

Definition at line 1273 of file radeon_drv.h.

#define R200_PP_CUBIC_OFFSET_F2_4 0x2d68

Definition at line 1278 of file radeon_drv.h.

#define R200_PP_CUBIC_OFFSET_F2_5 0x2d80

Definition at line 1283 of file radeon_drv.h.

#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c

Definition at line 1259 of file radeon_drv.h.

#define R200_PP_CUBIC_OFFSET_F3_1 0x2d24

Definition at line 1264 of file radeon_drv.h.

#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c

Definition at line 1269 of file radeon_drv.h.

#define R200_PP_CUBIC_OFFSET_F3_3 0x2d54

Definition at line 1274 of file radeon_drv.h.

#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c

Definition at line 1279 of file radeon_drv.h.

#define R200_PP_CUBIC_OFFSET_F3_5 0x2d84

Definition at line 1284 of file radeon_drv.h.

#define R200_PP_CUBIC_OFFSET_F4_0 0x2d10

Definition at line 1260 of file radeon_drv.h.

#define R200_PP_CUBIC_OFFSET_F4_1 0x2d28

Definition at line 1265 of file radeon_drv.h.

#define R200_PP_CUBIC_OFFSET_F4_2 0x2d40

Definition at line 1270 of file radeon_drv.h.

#define R200_PP_CUBIC_OFFSET_F4_3 0x2d58

Definition at line 1275 of file radeon_drv.h.

#define R200_PP_CUBIC_OFFSET_F4_4 0x2d70

Definition at line 1280 of file radeon_drv.h.

#define R200_PP_CUBIC_OFFSET_F4_5 0x2d88

Definition at line 1285 of file radeon_drv.h.

#define R200_PP_CUBIC_OFFSET_F5_0 0x2d14

Definition at line 1261 of file radeon_drv.h.

#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c

Definition at line 1266 of file radeon_drv.h.

#define R200_PP_CUBIC_OFFSET_F5_2 0x2d44

Definition at line 1271 of file radeon_drv.h.

#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c

Definition at line 1276 of file radeon_drv.h.

#define R200_PP_CUBIC_OFFSET_F5_4 0x2d74

Definition at line 1281 of file radeon_drv.h.

#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c

Definition at line 1286 of file radeon_drv.h.

#define R200_PP_TAM_DEBUG3 0x2d9c

Definition at line 1291 of file radeon_drv.h.

#define R200_PP_TFACTOR_0 0x2ee0

Definition at line 1232 of file radeon_drv.h.

#define R200_PP_TRI_PERF 0x2cf8

Definition at line 1332 of file radeon_drv.h.

#define R200_PP_TXCBLEND_0 0x2f00

Definition at line 1223 of file radeon_drv.h.

#define R200_PP_TXCBLEND_1 0x2f10

Definition at line 1224 of file radeon_drv.h.

#define R200_PP_TXCBLEND_2 0x2f20

Definition at line 1225 of file radeon_drv.h.

#define R200_PP_TXCBLEND_3 0x2f30

Definition at line 1226 of file radeon_drv.h.

#define R200_PP_TXCBLEND_4 0x2f40

Definition at line 1227 of file radeon_drv.h.

#define R200_PP_TXCBLEND_5 0x2f50

Definition at line 1228 of file radeon_drv.h.

#define R200_PP_TXCBLEND_6 0x2f60

Definition at line 1229 of file radeon_drv.h.

#define R200_PP_TXCBLEND_7 0x2f70

Definition at line 1230 of file radeon_drv.h.

#define R200_PP_TXFILTER_0 0x2c00

Definition at line 1243 of file radeon_drv.h.

#define R200_PP_TXFILTER_1 0x2c20

Definition at line 1242 of file radeon_drv.h.

#define R200_PP_TXFILTER_2 0x2c40

Definition at line 1241 of file radeon_drv.h.

#define R200_PP_TXFILTER_3 0x2c60

Definition at line 1240 of file radeon_drv.h.

#define R200_PP_TXFILTER_4 0x2c80

Definition at line 1239 of file radeon_drv.h.

#define R200_PP_TXFILTER_5 0x2ca0

Definition at line 1238 of file radeon_drv.h.

#define R200_PP_TXOFFSET_0 0x2d00

Definition at line 1249 of file radeon_drv.h.

#define R200_PP_TXOFFSET_1 0x2d18

Definition at line 1248 of file radeon_drv.h.

#define R200_PP_TXOFFSET_2 0x2d30

Definition at line 1247 of file radeon_drv.h.

#define R200_PP_TXOFFSET_3 0x2d48

Definition at line 1246 of file radeon_drv.h.

#define R200_PP_TXOFFSET_4 0x2d60

Definition at line 1245 of file radeon_drv.h.

#define R200_PP_TXOFFSET_5 0x2d78

Definition at line 1244 of file radeon_drv.h.

#define R200_RB3D_BLENDCOLOR 0x3218

Definition at line 1328 of file radeon_drv.h.

#define R200_RB3D_DEPTHXY_OFFSET 0x1d60

Definition at line 1297 of file radeon_drv.h.

#define R200_RE_AUX_SCISSOR_CNTL 0x26f0

Definition at line 1298 of file radeon_drv.h.

#define R200_RE_AUX_SCISSOR_CNTL 0x26f0

Definition at line 1298 of file radeon_drv.h.

#define R200_RE_CNTL 0x1c50

Definition at line 1326 of file radeon_drv.h.

#define R200_RE_POINTSIZE 0x2648

Definition at line 1300 of file radeon_drv.h.

#define R200_RE_SCISSOR_TL_0 0x1cd8

Definition at line 1294 of file radeon_drv.h.

#define R200_RE_SCISSOR_TL_1 0x1ce0

Definition at line 1295 of file radeon_drv.h.

#define R200_RE_SCISSOR_TL_2 0x1ce8

Definition at line 1296 of file radeon_drv.h.

#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254

Definition at line 1301 of file radeon_drv.h.

#define R200_SE_TCL_LIGHT_MODEL_CTL_0 0x2268

Definition at line 1231 of file radeon_drv.h.

#define R200_SE_TCL_MATRIX_SEL_0 0x2230

Definition at line 1235 of file radeon_drv.h.

#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250

Definition at line 1290 of file radeon_drv.h.

#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4

Definition at line 1330 of file radeon_drv.h.

#define R200_SE_TCL_TEX_PROC_CTL_2 0x22a8

Definition at line 1236 of file radeon_drv.h.

#define R200_SE_TCL_UCP_VERT_BLEND_CTL 0x22c0

Definition at line 1237 of file radeon_drv.h.

#define R200_SE_VAP_CNTL 0x2080

Definition at line 1234 of file radeon_drv.h.

#define R200_SE_VAP_CNTL_STATUS 0x2140

Definition at line 1293 of file radeon_drv.h.

#define R200_SE_VTE_CNTL 0x20b0

Definition at line 1289 of file radeon_drv.h.

#define R200_SE_VTX_FMT_0 0x2088

Definition at line 1233 of file radeon_drv.h.

#define R200_SE_VTX_FMT_1 0x208c

Definition at line 1325 of file radeon_drv.h.

#define R200_SE_VTX_STATE_CNTL 0x2180

Definition at line 1299 of file radeon_drv.h.

#define R200_VAP_PVS_CNTL_1 0x22D0

Definition at line 1337 of file radeon_drv.h.

#define R300_CP_RESYNC_ADDR 0x0778

Definition at line 1059 of file radeon_drv.h.

#define R300_CP_RESYNC_DATA 0x077c

Definition at line 1060 of file radeon_drv.h.

#define R300_DC_AUTOFLUSH_ENABLE (1 << 8)

Definition at line 699 of file radeon_drv.h.

#define R300_DC_DC_DISABLE_IGNORE_PE (1 << 17)

Definition at line 700 of file radeon_drv.h.

#define R300_DST_PIPE_CONFIG 0x170c

Definition at line 696 of file radeon_drv.h.

#define R300_DSTCACHE_CTLSTAT 0x1714

Definition at line 820 of file radeon_drv.h.

#define R300_ENABLE_TILING (1 << 0)

Definition at line 686 of file radeon_drv.h.

#define R300_GB_TILE_CONFIG 0x4018

Definition at line 685 of file radeon_drv.h.

#define R300_PIPE_AUTO_CONFIG (1 << 31)

Definition at line 697 of file radeon_drv.h.

#define R300_PIPE_COUNT_R300 (3 << 1)

Definition at line 688 of file radeon_drv.h.

#define R300_PIPE_COUNT_R420 (7 << 1)

Definition at line 690 of file radeon_drv.h.

#define R300_PIPE_COUNT_R420_3P (6 << 1)

Definition at line 689 of file radeon_drv.h.

#define R300_PIPE_COUNT_RV350 (0 << 1)

Definition at line 687 of file radeon_drv.h.

#define R300_RB2D_DC_BUSY (1 << 31)

Definition at line 824 of file radeon_drv.h.

#define R300_RB2D_DC_FLUSH (3 << 0)

Definition at line 821 of file radeon_drv.h.

#define R300_RB2D_DC_FLUSH_ALL 0xf

Definition at line 823 of file radeon_drv.h.

#define R300_RB2D_DC_FREE (3 << 2)

Definition at line 822 of file radeon_drv.h.

#define R300_RB2D_DSTCACHE_CTLSTAT 0x342c /* use R300_DSTCACHE_CTLSTAT */

Definition at line 819 of file radeon_drv.h.

#define R300_RB2D_DSTCACHE_MODE 0x3428

Definition at line 698 of file radeon_drv.h.

#define R300_RB3D_DC_FINISH (1 << 4)

Definition at line 859 of file radeon_drv.h.

#define R300_RB3D_DC_FLUSH (2 << 0)

Definition at line 857 of file radeon_drv.h.

#define R300_RB3D_DC_FREE (2 << 2)

Definition at line 858 of file radeon_drv.h.

#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c

Definition at line 856 of file radeon_drv.h.

#define R300_SUBPIXEL_1_12 (0 << 16)

Definition at line 694 of file radeon_drv.h.

#define R300_SUBPIXEL_1_16 (1 << 16)

Definition at line 695 of file radeon_drv.h.

#define R300_TILE_SIZE_16 (1 << 4)

Definition at line 692 of file radeon_drv.h.

#define R300_TILE_SIZE_32 (2 << 4)

Definition at line 693 of file radeon_drv.h.

#define R300_TILE_SIZE_8 (0 << 4)

Definition at line 691 of file radeon_drv.h.

#define R300_ZB_ZCACHE_CTLSTAT 0x4f18

Definition at line 847 of file radeon_drv.h.

#define R300_ZC_BUSY (1 << 31)

Definition at line 850 of file radeon_drv.h.

#define R300_ZC_FLUSH (1 << 0)

Definition at line 848 of file radeon_drv.h.

#define R300_ZC_FREE (1 << 1)

Definition at line 849 of file radeon_drv.h.

#define R400_GB_PIPE_SELECT 0x402c

Definition at line 682 of file radeon_drv.h.

#define R500_CRTC_V_BLANK (1<<0)

Definition at line 1344 of file radeon_drv.h.

#define R500_D1_VBLANK_INTERRUPT (1 << 4)

Definition at line 1364 of file radeon_drv.h.

#define R500_D1CRTC_FRAME_COUNT 0x60a4

Definition at line 1346 of file radeon_drv.h.

#define R500_D1CRTC_STATUS 0x609c

Definition at line 1342 of file radeon_drv.h.

#define R500_D1MODE_INT_MASK (1<<0)

Definition at line 1360 of file radeon_drv.h.

#define R500_D1MODE_V_COUNTER 0x6530

Definition at line 1349 of file radeon_drv.h.

#define R500_D1MODE_VBLANK_STATUS 0x6534

Definition at line 1352 of file radeon_drv.h.

#define R500_D2_VBLANK_INTERRUPT (1 << 5)

Definition at line 1365 of file radeon_drv.h.

#define R500_D2CRTC_FRAME_COUNT 0x68a4

Definition at line 1347 of file radeon_drv.h.

#define R500_D2CRTC_STATUS 0x689c

Definition at line 1343 of file radeon_drv.h.

#define R500_D2MODE_INT_MASK (1<<8)

Definition at line 1361 of file radeon_drv.h.

#define R500_D2MODE_V_COUNTER 0x6d30

Definition at line 1350 of file radeon_drv.h.

#define R500_D2MODE_VBLANK_STATUS 0x6d34

Definition at line 1353 of file radeon_drv.h.

#define R500_DISP_INTERRUPT_STATUS 0x7edc

Definition at line 1363 of file radeon_drv.h.

#define R500_DISPLAY_INT_STATUS (1 << 0)

Definition at line 775 of file radeon_drv.h.

#define R500_DxMODE_INT_MASK 0x6540

Definition at line 1359 of file radeon_drv.h.

#define R500_DYN_SCLK_PWMEM_PIPE 0x000d /* PLL */

Definition at line 684 of file radeon_drv.h.

#define R500_VBLANK_ACK (1<<4)

Definition at line 1355 of file radeon_drv.h.

#define R500_VBLANK_INT (1<<16)

Definition at line 1357 of file radeon_drv.h.

#define R500_VBLANK_OCCURED (1<<0)

Definition at line 1354 of file radeon_drv.h.

#define R500_VBLANK_STAT (1<<12)

Definition at line 1356 of file radeon_drv.h.

#define R500_WRITE_MCIND	(	addr,
		val
	)

Value:

do {                                \
    RADEON_WRITE(R520_MC_IND_INDEX, 0xff0000 | ((addr) & 0xff));    \
    RADEON_WRITE(R520_MC_IND_DATA, (val));          \
    RADEON_WRITE(R520_MC_IND_INDEX, 0); \
} while (0)

Definition at line 1878 of file radeon_drv.h.

#define R520_MC_AGP_BASE 0x06

Definition at line 671 of file radeon_drv.h.

#define R520_MC_AGP_BASE_2 0x07

Definition at line 672 of file radeon_drv.h.

#define R520_MC_AGP_LOCATION 0x05

Definition at line 670 of file radeon_drv.h.

#define R520_MC_FB_LOCATION 0x04

Definition at line 669 of file radeon_drv.h.

#define R520_MC_IND_DATA 0x74

Definition at line 662 of file radeon_drv.h.

#define R520_MC_IND_INDEX 0x70

Definition at line 660 of file radeon_drv.h.

#define R520_MC_IND_WR_EN (1 << 24)

Definition at line 661 of file radeon_drv.h.

#define R600_ALU_INST_PREFER_VECTOR (1 << 3)

Definition at line 1727 of file radeon_drv.h.

#define R600_ALU_UPDATE_FIFO_HIWATER ( x ) ((x) << 24)

Definition at line 1757 of file radeon_drv.h.

#define R600_ARB_GDEC_RD_CNTL 0x246c

Definition at line 1698 of file radeon_drv.h.

#define R600_ARB_POP 0x2418

Definition at line 1696 of file radeon_drv.h.

#define R600_BACKEND_DISABLE ( x ) ((x) << 16)

Definition at line 1816 of file radeon_drv.h.

#define R600_BACKEND_MAP ( x ) ((x) << 16)

Definition at line 1810 of file radeon_drv.h.

#define R600_BANK_SWAPS ( x ) ((x) << 11)

Definition at line 1808 of file radeon_drv.h.

#define R600_BANK_TILING ( x ) ((x) << 4)

Definition at line 1805 of file radeon_drv.h.

#define R600_BARYC_AT_SAMPLE_ENA (1 << 31)

Definition at line 1782 of file radeon_drv.h.

#define R600_BARYC_SAMPLE_CNTL ( x ) ((x) << 26)

Definition at line 1778 of file radeon_drv.h.

#define R600_BILINEAR_PRECISION_6_BIT (0 << 31)

Definition at line 1707 of file radeon_drv.h.

#define R600_BILINEAR_PRECISION_8_BIT (1 << 31)

Definition at line 1708 of file radeon_drv.h.

#define R600_BUF_SWAP_32BIT (2 << 16)

Definition at line 1527 of file radeon_drv.h.

#define R600_BURSTLENGTH_MASK 0x1

Definition at line 1461 of file radeon_drv.h.

#define R600_BURSTLENGTH_SHIFT 8

Definition at line 1460 of file radeon_drv.h.

#define R600_CACHE_FIFO_SIZE ( x ) ((x) << 0)

Definition at line 1754 of file radeon_drv.h.

#define R600_CACHE_FLUSH_AND_INV_EVENT (0x16 << 0)

Definition at line 1630 of file radeon_drv.h.

#define R600_CACHE_INVALIDATION ( x ) ((x) << 0)

Definition at line 1614 of file radeon_drv.h.

#define R600_CB0_DEST_BASE_ENA (1 << 6)

Definition at line 1126 of file radeon_drv.h.

#define R600_CB_ACTION_ENA (1 << 25)

Definition at line 1129 of file radeon_drv.h.

#define R600_CB_COLOR0_BASE 0x28040

Definition at line 1636 of file radeon_drv.h.

#define R600_CB_COLOR0_FRAG 0x280e0

Definition at line 1650 of file radeon_drv.h.

#define R600_CB_COLOR0_INFO 0x280a0

Definition at line 1648 of file radeon_drv.h.

#define R600_CB_COLOR0_MASK 0x28100

Definition at line 1651 of file radeon_drv.h.

#define R600_CB_COLOR0_SIZE 0x28060

Definition at line 1646 of file radeon_drv.h.

#define R600_CB_COLOR0_TILE 0x280c0

Definition at line 1649 of file radeon_drv.h.

#define R600_CB_COLOR0_VIEW 0x28080

Definition at line 1647 of file radeon_drv.h.

#define R600_CB_COLOR1_BASE 0x28044

Definition at line 1637 of file radeon_drv.h.

#define R600_CB_COLOR2_BASE 0x28048

Definition at line 1638 of file radeon_drv.h.

#define R600_CB_COLOR3_BASE 0x2804c

Definition at line 1639 of file radeon_drv.h.

#define R600_CB_COLOR4_BASE 0x28050

Definition at line 1640 of file radeon_drv.h.

#define R600_CB_COLOR5_BASE 0x28054

Definition at line 1641 of file radeon_drv.h.

#define R600_CB_COLOR6_BASE 0x28058

Definition at line 1642 of file radeon_drv.h.

#define R600_CB_COLOR7_BASE 0x2805c

Definition at line 1643 of file radeon_drv.h.

#define R600_CB_COLOR7_FRAG 0x280fc

Definition at line 1644 of file radeon_drv.h.

#define R600_CC_GC_SHADER_PIPE_CONFIG 0x8950

Definition at line 1818 of file radeon_drv.h.

#define R600_CC_RB_BACKEND_DISABLE 0x98f4

Definition at line 1814 of file radeon_drv.h.

#define R600_CHANSIZE_MASK 0x1

Definition at line 1459 of file radeon_drv.h.

#define R600_CHANSIZE_SHIFT 7

Definition at line 1458 of file radeon_drv.h.

#define R600_CLAUSE_SEQ_PRIO ( x ) ((x) << 8)

Definition at line 1729 of file radeon_drv.h.

#define R600_CLEAR_AGE ( age )

Value:

do {                    \
    OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));        \
    OUT_RING((R600_LAST_CLEAR_REG - R600_SET_CONFIG_REG_OFFSET) >> 2);  \
    OUT_RING(age);                          \
} while (0)

Definition at line 2054 of file radeon_drv.h.

#define R600_CLIP_VTX_REORDER_ENA (1 << 0)

Definition at line 1546 of file radeon_drv.h.

#define R600_CMDFIFO_AVAIL_MASK 0x1f

Definition at line 1504 of file radeon_drv.h.

#define R600_COLOR_BUFFER_SIZE ( x ) ((x) << 0)

Definition at line 1591 of file radeon_drv.h.

#define R600_CP_COHER_BASE 0x85f8

Definition at line 1655 of file radeon_drv.h.

#define R600_CP_DEBUG 0xc1fc

Definition at line 1543 of file radeon_drv.h.

#define R600_CP_ME_CNTL 0x86d8

Definition at line 1513 of file radeon_drv.h.

#define R600_CP_ME_HALT (1 << 28)

Definition at line 1514 of file radeon_drv.h.

#define R600_CP_ME_RAM_DATA 0xc160

Definition at line 1542 of file radeon_drv.h.

#define R600_CP_ME_RAM_RADDR 0xc158

Definition at line 1540 of file radeon_drv.h.

#define R600_CP_ME_RAM_WADDR 0xc15c

Definition at line 1541 of file radeon_drv.h.

#define R600_CP_MEQ_THRESHOLDS 0x8764

Definition at line 1518 of file radeon_drv.h.

#define R600_CP_PERFMON_CNTL 0x87fc

Definition at line 1522 of file radeon_drv.h.

#define R600_CP_PFP_UCODE_ADDR 0xc150

Definition at line 1538 of file radeon_drv.h.

#define R600_CP_PFP_UCODE_DATA 0xc154

Definition at line 1539 of file radeon_drv.h.

#define R600_CP_QUEUE_THRESHOLDS 0x8760

Definition at line 1515 of file radeon_drv.h.

#define R600_CP_RB_BASE 0xc100

Definition at line 1523 of file radeon_drv.h.

#define R600_CP_RB_CNTL 0xc104

Definition at line 1524 of file radeon_drv.h.

#define R600_CP_RB_RPTR 0x8700

Definition at line 1536 of file radeon_drv.h.

#define R600_CP_RB_RPTR_ADDR 0xc10c

Definition at line 1531 of file radeon_drv.h.

#define R600_CP_RB_RPTR_ADDR_HI 0xc110

Definition at line 1532 of file radeon_drv.h.

#define R600_CP_RB_RPTR_WR 0xc108

Definition at line 1530 of file radeon_drv.h.

#define R600_CP_RB_WPTR 0xc114

Definition at line 1533 of file radeon_drv.h.

#define R600_CP_RB_WPTR_ADDR 0xc118

Definition at line 1534 of file radeon_drv.h.

#define R600_CP_RB_WPTR_ADDR_HI 0xc11c

Definition at line 1535 of file radeon_drv.h.

#define R600_CP_RB_WPTR_DELAY 0x8704

Definition at line 1537 of file radeon_drv.h.

#define R600_CP_SEM_WAIT_TIMER 0x85bc

Definition at line 1512 of file radeon_drv.h.

#define R600_DB_ACTION_ENA (1 << 26)

Definition at line 1130 of file radeon_drv.h.

#define R600_DB_DEBUG 0x9830

Definition at line 1601 of file radeon_drv.h.

#define R600_DB_DEPTH_BASE 0x2800c

Definition at line 1656 of file radeon_drv.h.

#define R600_DB_WATERMARKS 0x9838

Definition at line 1603 of file radeon_drv.h.

#define R600_DCP_TILING_CONFIG 0x6ca0

Definition at line 1811 of file radeon_drv.h.

#define R600_DEALLOC_DIST_MASK 0x7f

Definition at line 1634 of file radeon_drv.h.

#define R600_DEPTH_CACHELINE_FREE ( x ) ((x) << 20)

Definition at line 1607 of file radeon_drv.h.

#define R600_DEPTH_FLUSH ( x ) ((x) << 5)

Definition at line 1605 of file radeon_drv.h.

#define R600_DEPTH_FREE ( x ) ((x) << 0)

Definition at line 1604 of file radeon_drv.h.

#define R600_DEPTH_PENDING_FREE ( x ) ((x) << 15)

Definition at line 1606 of file radeon_drv.h.

#define R600_DISABLE_CUBE_ANISO (1 << 1)

Definition at line 1702 of file radeon_drv.h.

#define R600_DISABLE_CUBE_WRAP (1 << 0)

Definition at line 1701 of file radeon_drv.h.

#define R600_DISABLE_INTERP_1 (1 << 5)

Definition at line 1798 of file radeon_drv.h.

#define R600_DISPATCH_AGE ( age )

Value:

do {                    \
    OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));        \
    OUT_RING((R600_LAST_DISPATCH_REG - R600_SET_CONFIG_REG_OFFSET) >> 2);  \
    OUT_RING(age);                          \
} while (0)

Definition at line 2042 of file radeon_drv.h.

#define R600_DONE_FIFO_HIWATER ( x ) ((x) << 16)

Definition at line 1756 of file radeon_drv.h.

#define R600_DX10_CLAMP (1 << 4)

Definition at line 1728 of file radeon_drv.h.

#define R600_DX9_CONSTS (1 << 2)

Definition at line 1726 of file radeon_drv.h.

#define R600_ENABLE_NEW_SMX_ADDRESS (1 << 16)

Definition at line 1596 of file radeon_drv.h.

#define R600_ENABLE_TC128 (1 << 30)

Definition at line 1697 of file radeon_drv.h.

#define R600_ES_PRIO ( x ) ((x) << 30)

Definition at line 1733 of file radeon_drv.h.

#define R600_EXPORT_SRC_C (1 << 1)

Definition at line 1725 of file radeon_drv.h.

#define R600_FETCH_FIFO_HIWATER ( x ) ((x) << 8)

Definition at line 1755 of file radeon_drv.h.

#define R600_FIXED_PT_POSITION_ADDR ( x ) ((x) << 25)

Definition at line 1792 of file radeon_drv.h.

#define R600_FIXED_PT_POSITION_ENA (1 << 24)

Definition at line 1791 of file radeon_drv.h.

#define R600_FOG_ADDR ( x ) ((x) << 17)

Definition at line 1790 of file radeon_drv.h.

#define R600_FORCE_EOV_MAX_CLK_CNT ( x ) ((x) << 0)

Definition at line 1582 of file radeon_drv.h.

#define R600_FORCE_EOV_MAX_TILE_CNT ( x ) ((x) << 12)

Definition at line 1583 of file radeon_drv.h.

#define R600_FRAME_AGE ( age )

Value:

do {                    \
    OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));        \
    OUT_RING((R600_LAST_FRAME_REG - R600_SET_CONFIG_REG_OFFSET) >> 2);  \
    OUT_RING(age);                          \
} while (0)

Definition at line 2048 of file radeon_drv.h.

#define R600_FRONT_FACE_ADDR ( x ) ((x) << 12)

Definition at line 1789 of file radeon_drv.h.

#define R600_FRONT_FACE_ALL_BITS (1 << 11)

Definition at line 1788 of file radeon_drv.h.

#define R600_FRONT_FACE_CHAN ( x ) ((x) << 9)

Definition at line 1787 of file radeon_drv.h.

#define R600_FRONT_FACE_ENA (1 << 8)

Definition at line 1786 of file radeon_drv.h.

#define R600_GB_TILING_CONFIG 0x98f0

Definition at line 1803 of file radeon_drv.h.

#define R600_GC_USER_SHADER_PIPE_CONFIG 0x8954

Definition at line 1819 of file radeon_drv.h.

#define R600_GEN_INDEX_PIX (1 << 0)

Definition at line 1784 of file radeon_drv.h.

#define R600_GEN_INDEX_PIX_ADDR ( x ) ((x) << 1)

Definition at line 1785 of file radeon_drv.h.

#define R600_GPR_WRITE_PRIORITY ( x ) ((x) << 0)

Definition at line 1797 of file radeon_drv.h.

#define R600_GRBM_CNTL 0x8000

Definition at line 1500 of file radeon_drv.h.

#define R600_GRBM_READ_TIMEOUT ( x ) ((x) << 0)

Definition at line 1501 of file radeon_drv.h.

#define R600_GRBM_SOFT_RESET 0x8020

Definition at line 1508 of file radeon_drv.h.

#define R600_GRBM_STATUS 0x8010

Definition at line 1503 of file radeon_drv.h.

#define R600_GRBM_STATUS2 0x8014

Definition at line 1507 of file radeon_drv.h.

#define R600_GROUP_SIZE ( x ) ((x) << 6)

Definition at line 1806 of file radeon_drv.h.

#define R600_GS_PRIO ( x ) ((x) << 28)

Definition at line 1732 of file radeon_drv.h.

#define R600_GUI_ACTIVE (1 << 31)

Definition at line 1506 of file radeon_drv.h.

#define R600_HDP_HOST_PATH_CNTL 0x2c00

Definition at line 1498 of file radeon_drv.h.

#define R600_HDP_TILING_CONFIG 0x2f3c

Definition at line 1812 of file radeon_drv.h.

#define R600_INACTIVE_QD_PIPES ( x ) ((x) << 8)

Definition at line 1820 of file radeon_drv.h.

#define R600_INACTIVE_QD_PIPES_MASK (0xff << 8)

Definition at line 1821 of file radeon_drv.h.

#define R600_INACTIVE_SIMDS ( x ) ((x) << 16)

Definition at line 1822 of file radeon_drv.h.

#define R600_INACTIVE_SIMDS_MASK (0xff << 16)

Definition at line 1823 of file radeon_drv.h.

#define R600_INTERP_ONE_PRIM_PER_ROW (1 << 4)

Definition at line 1801 of file radeon_drv.h.

#define R600_IT_COND_EXEC 0x00002200

Definition at line 1107 of file radeon_drv.h.

#define R600_IT_COND_WRITE 0x00004500

Definition at line 1135 of file radeon_drv.h.

#define R600_IT_CONTEXT_CONTROL 0x00002800

Definition at line 1111 of file radeon_drv.h.

#define R600_IT_DRAW_INDEX 0x00002B00

Definition at line 1114 of file radeon_drv.h.

#define R600_IT_DRAW_INDEX_2 0x00002700

Definition at line 1110 of file radeon_drv.h.

#define R600_IT_DRAW_INDEX_AUTO 0x00002D00

Definition at line 1115 of file radeon_drv.h.

#define R600_IT_DRAW_INDEX_IMMD 0x00002E00

Definition at line 1116 of file radeon_drv.h.

#define R600_IT_DRAW_INDEX_IMMD_BE 0x00002900

Definition at line 1112 of file radeon_drv.h.

#define R600_IT_EVENT_WRITE 0x00004600

Definition at line 1136 of file radeon_drv.h.

#define R600_IT_EVENT_WRITE_EOP 0x00004700

Definition at line 1137 of file radeon_drv.h.

#define R600_IT_INDEX_TYPE 0x00002A00

Definition at line 1113 of file radeon_drv.h.

#define R600_IT_INDIRECT_BUFFER 0x00003200

Definition at line 1124 of file radeon_drv.h.

#define R600_IT_INDIRECT_BUFFER_END 0x00001700

Definition at line 1104 of file radeon_drv.h.

#define R600_IT_INDIRECT_BUFFER_MP 0x00003800

Definition at line 1119 of file radeon_drv.h.

#define R600_IT_ME_INITIALIZE 0x00004400

Definition at line 1133 of file radeon_drv.h.

#define R600_IT_MEM_SEMAPHORE 0x00003900

Definition at line 1120 of file radeon_drv.h.

#define R600_IT_MEM_WRITE 0x00003D00

Definition at line 1123 of file radeon_drv.h.

#define R600_IT_MPEG_INDEX 0x00003A00

Definition at line 1121 of file radeon_drv.h.

#define R600_IT_NUM_INSTANCES 0x00002F00

Definition at line 1117 of file radeon_drv.h.

#define R600_IT_ONE_REG_WRITE 0x00005700

Definition at line 1138 of file radeon_drv.h.

#define R600_IT_PRED_EXEC 0x00002300

Definition at line 1108 of file radeon_drv.h.

#define R600_IT_REG_RMW 0x00002100

Definition at line 1106 of file radeon_drv.h.

#define R600_IT_SET_ALU_CONST 0x00006A00

Definition at line 1145 of file radeon_drv.h.

#define R600_IT_SET_BOOL_CONST 0x00006B00

Definition at line 1148 of file radeon_drv.h.

#define R600_IT_SET_CONFIG_REG 0x00006800

Definition at line 1139 of file radeon_drv.h.

#define R600_IT_SET_CONTEXT_REG 0x00006900

Definition at line 1142 of file radeon_drv.h.

#define R600_IT_SET_CTL_CONST 0x00006F00

Definition at line 1164 of file radeon_drv.h.

#define R600_IT_SET_LOOP_CONST 0x00006C00

Definition at line 1151 of file radeon_drv.h.

#define R600_IT_SET_PREDICATION 0x00002000

Definition at line 1105 of file radeon_drv.h.

#define R600_IT_SET_RESOURCE 0x00006D00

Definition at line 1154 of file radeon_drv.h.

#define R600_IT_SET_SAMPLER 0x00006E00

Definition at line 1161 of file radeon_drv.h.

#define R600_IT_START_3D_CMDBUF 0x00002400

Definition at line 1109 of file radeon_drv.h.

#define R600_IT_STRMOUT_BUFFER_UPDATE 0x00003400

Definition at line 1118 of file radeon_drv.h.

#define R600_IT_SURFACE_BASE_UPDATE 0x00007300

Definition at line 1167 of file radeon_drv.h.

#define R600_IT_SURFACE_SYNC 0x00004300

Definition at line 1125 of file radeon_drv.h.

#define R600_IT_WAIT_REG_MEM 0x00003C00

Definition at line 1122 of file radeon_drv.h.

#define R600_L2_DISABLE_LATE_HIT (1 << 9)

Definition at line 1694 of file radeon_drv.h.

#define R600_LAST_CLEAR_REG R600_SCRATCH_REG2

Definition at line 1841 of file radeon_drv.h.

#define R600_LAST_DISPATCH_REG R600_SCRATCH_REG1

Definition at line 1840 of file radeon_drv.h.

#define R600_LAST_FRAME_REG R600_SCRATCH_REG0

Definition at line 1839 of file radeon_drv.h.

#define R600_LAST_SWI_REG R600_SCRATCH_REG3

Definition at line 1842 of file radeon_drv.h.

#define R600_LINEAR_GRADIENT_ENA (1 << 29)

Definition at line 1780 of file radeon_drv.h.

#define R600_MC_VM_AGP_BASE 0x218c

Definition at line 1371 of file radeon_drv.h.

#define R600_MC_VM_AGP_BOT 0x2188

Definition at line 1370 of file radeon_drv.h.

#define R600_MC_VM_AGP_TOP 0x2184

Definition at line 1369 of file radeon_drv.h.

#define R600_MC_VM_FB_LOCATION 0x2180

Definition at line 1368 of file radeon_drv.h.

#define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198

Definition at line 1374 of file radeon_drv.h.

#define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194

Definition at line 1373 of file radeon_drv.h.

#define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190

Definition at line 1372 of file radeon_drv.h.

#define R600_MCD_EFFECTIVE_L1_QUEUE_SIZE ( x ) ((x) << 15)

Definition at line 1418 of file radeon_drv.h.

#define R600_MCD_EFFECTIVE_L1_TLB_SIZE ( x ) ((x) << 12)

Definition at line 1417 of file radeon_drv.h.

#define R600_MCD_L1_FRAG_PROC (1 << 1)

Definition at line 1403 of file radeon_drv.h.

#define R600_MCD_L1_STRICT_ORDERING (1 << 2)

Definition at line 1404 of file radeon_drv.h.

#define R600_MCD_L1_TLB (1 << 0)

Definition at line 1402 of file radeon_drv.h.

#define R600_MCD_RD_A_CNTL 0x219c

Definition at line 1384 of file radeon_drv.h.

#define R600_MCD_RD_B_CNTL 0x21a0

Definition at line 1385 of file radeon_drv.h.

#define R600_MCD_RD_GFX_CNTL 0x21fc

Definition at line 1393 of file radeon_drv.h.

#define R600_MCD_RD_HDP_CNTL 0x2204

Definition at line 1394 of file radeon_drv.h.

#define R600_MCD_RD_PDMA_CNTL 0x2208

Definition at line 1395 of file radeon_drv.h.

#define R600_MCD_RD_SEM_CNTL 0x220c

Definition at line 1396 of file radeon_drv.h.

#define R600_MCD_RD_SYS_CNTL 0x2200

Definition at line 1390 of file radeon_drv.h.

#define R600_MCD_SEMAPHORE_MODE (1 << 10)

Definition at line 1415 of file radeon_drv.h.

#define R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS (2 << 6)

Definition at line 1409 of file radeon_drv.h.

#define R600_MCD_SYSTEM_ACCESS_MODE_MASK (3 << 6)

Definition at line 1406 of file radeon_drv.h.

#define R600_MCD_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6)

Definition at line 1410 of file radeon_drv.h.

#define R600_MCD_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6)

Definition at line 1407 of file radeon_drv.h.

#define R600_MCD_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6)

Definition at line 1408 of file radeon_drv.h.

#define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8)

Definition at line 1413 of file radeon_drv.h.

#define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8)

Definition at line 1412 of file radeon_drv.h.

#define R600_MCD_WAIT_L2_QUERY (1 << 11)

Definition at line 1416 of file radeon_drv.h.

#define R600_MCD_WR_A_CNTL 0x21a4

Definition at line 1387 of file radeon_drv.h.

#define R600_MCD_WR_B_CNTL 0x21a8

Definition at line 1388 of file radeon_drv.h.

#define R600_MCD_WR_GFX_CNTL 0x2210

Definition at line 1397 of file radeon_drv.h.

#define R600_MCD_WR_HDP_CNTL 0x2218

Definition at line 1398 of file radeon_drv.h.

#define R600_MCD_WR_PDMA_CNTL 0x221c

Definition at line 1399 of file radeon_drv.h.

#define R600_MCD_WR_SEM_CNTL 0x2220

Definition at line 1400 of file radeon_drv.h.

#define R600_MCD_WR_SYS_CNTL 0x2214

Definition at line 1391 of file radeon_drv.h.

#define R600_ME_INITIALIZE_DEVICE_ID ( x ) ((x) << 16)

Definition at line 1134 of file radeon_drv.h.

#define R600_MEQ_END ( x ) ((x) << 16)

Definition at line 1520 of file radeon_drv.h.

#define R600_NOOFBANK_MASK 0x1

Definition at line 1451 of file radeon_drv.h.

#define R600_NOOFBANK_SHIFT 0

Definition at line 1450 of file radeon_drv.h.

#define R600_NOOFCOLS_MASK 0x3

Definition at line 1457 of file radeon_drv.h.

#define R600_NOOFCOLS_SHIFT 5

Definition at line 1456 of file radeon_drv.h.

#define R600_NOOFRANK_MASK 0x1

Definition at line 1453 of file radeon_drv.h.

#define R600_NOOFRANK_SHIFT 1

Definition at line 1452 of file radeon_drv.h.

#define R600_NOOFROWS_MASK 0x7

Definition at line 1455 of file radeon_drv.h.

#define R600_NOOFROWS_SHIFT 2

Definition at line 1454 of file radeon_drv.h.

#define R600_NUM_CLAUSE_TEMP_GPRS ( x ) ((x) << 28)

Definition at line 1738 of file radeon_drv.h.

#define R600_NUM_CLIP_SEQ ( x ) ((x) << 1)

Definition at line 1547 of file radeon_drv.h.

#define R600_NUM_ES_GPRS ( x ) ((x) << 16)

Definition at line 1741 of file radeon_drv.h.

#define R600_NUM_ES_STACK_ENTRIES ( x ) ((x) << 16)

Definition at line 1752 of file radeon_drv.h.

#define R600_NUM_ES_THREADS ( x ) ((x) << 24)

Definition at line 1746 of file radeon_drv.h.

#define R600_NUM_GS_GPRS ( x ) ((x) << 0)

Definition at line 1740 of file radeon_drv.h.

#define R600_NUM_GS_STACK_ENTRIES ( x ) ((x) << 0)

Definition at line 1751 of file radeon_drv.h.

#define R600_NUM_GS_THREADS ( x ) ((x) << 16)

Definition at line 1745 of file radeon_drv.h.

#define R600_NUM_INTERP ( x ) ((x) << 0)

Definition at line 1772 of file radeon_drv.h.

#define R600_NUM_PS_GPRS ( x ) ((x) << 0)

Definition at line 1735 of file radeon_drv.h.

#define R600_NUM_PS_STACK_ENTRIES ( x ) ((x) << 0)

Definition at line 1748 of file radeon_drv.h.

#define R600_NUM_PS_THREADS ( x ) ((x) << 0)

Definition at line 1743 of file radeon_drv.h.

#define R600_NUM_VS_GPRS ( x ) ((x) << 16)

Definition at line 1736 of file radeon_drv.h.

#define R600_NUM_VS_STACK_ENTRIES ( x ) ((x) << 16)

Definition at line 1749 of file radeon_drv.h.

#define R600_NUM_VS_THREADS ( x ) ((x) << 8)

Definition at line 1744 of file radeon_drv.h.

#define R600_PA_CL_ENHANCE 0x8a14

Definition at line 1545 of file radeon_drv.h.

#define R600_PA_SC_AA_CONFIG 0x28c04

Definition at line 1588 of file radeon_drv.h.

#define R600_PA_SC_AA_SAMPLE_LOCS_2S 0x8b40

Definition at line 1553 of file radeon_drv.h.

#define R600_PA_SC_AA_SAMPLE_LOCS_4S 0x8b44

Definition at line 1554 of file radeon_drv.h.

#define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8b48

Definition at line 1555 of file radeon_drv.h.

#define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8b4c

Definition at line 1556 of file radeon_drv.h.

#define R600_PA_SC_CLIPRECT_RULE 0x2820c

Definition at line 1584 of file radeon_drv.h.

#define R600_PA_SC_ENHANCE 0x8bf0

Definition at line 1581 of file radeon_drv.h.

#define R600_PA_SC_FIFO_SIZE 0x8bd0

Definition at line 1573 of file radeon_drv.h.

#define R600_PA_SC_GENERIC_SCISSOR_TL 0x28240

Definition at line 1689 of file radeon_drv.h.

#define R600_PA_SC_LINE_STIPPLE 0x28a0c

Definition at line 1586 of file radeon_drv.h.

#define R600_PA_SC_LINE_STIPPLE_STATE 0x8b10

Definition at line 1548 of file radeon_drv.h.

#define R600_PA_SC_MODE_CNTL 0x28a4c

Definition at line 1587 of file radeon_drv.h.

#define R600_PA_SC_MULTI_CHIP_CNTL 0x8b20

Definition at line 1549 of file radeon_drv.h.

#define R600_PA_SC_SCREEN_SCISSOR_TL 0x28030

Definition at line 1688 of file radeon_drv.h.

#define R600_PA_SC_WINDOW_SCISSOR_TL 0x28204

Definition at line 1690 of file radeon_drv.h.

#define R600_PARAM_GEN ( x ) ((x) << 15)

Definition at line 1776 of file radeon_drv.h.

#define R600_PARAM_GEN_ADDR ( x ) ((x) << 19)

Definition at line 1777 of file radeon_drv.h.

#define R600_PERSP_GRADIENT_ENA (1 << 28)

Definition at line 1779 of file radeon_drv.h.

#define R600_PIPE_TILING ( x ) ((x) << 1)

Definition at line 1804 of file radeon_drv.h.

#define R600_POSITION_ADDR ( x ) ((x) << 10)

Definition at line 1775 of file radeon_drv.h.

#define R600_POSITION_BUFFER_SIZE ( x ) ((x) << 8)

Definition at line 1592 of file radeon_drv.h.

#define R600_POSITION_CENTROID (1 << 9)

Definition at line 1774 of file radeon_drv.h.

#define R600_POSITION_ENA (1 << 8)

Definition at line 1773 of file radeon_drv.h.

#define R600_POSITION_SAMPLE (1 << 30)

Definition at line 1781 of file radeon_drv.h.

#define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31)

Definition at line 1602 of file radeon_drv.h.

#define R600_PS_PRIO ( x ) ((x) << 24)

Definition at line 1730 of file radeon_drv.h.

#define R600_RAMCFG 0x2408

Definition at line 1449 of file radeon_drv.h.

#define R600_RB_BLKSZ ( x ) ((x) << 8)

Definition at line 1526 of file radeon_drv.h.

#define R600_RB_BUFSZ ( x ) ((x) << 0)

Definition at line 1525 of file radeon_drv.h.

#define R600_RB_NO_UPDATE (1 << 27)

Definition at line 1528 of file radeon_drv.h.

#define R600_RB_RPTR_WR_ENA (1 << 31)

Definition at line 1529 of file radeon_drv.h.

#define R600_ROQ_END ( x ) ((x) << 24)

Definition at line 1521 of file radeon_drv.h.

#define R600_ROQ_IB1_START ( x ) ((x) << 0)

Definition at line 1516 of file radeon_drv.h.

#define R600_ROQ_IB2_START ( x ) ((x) << 8)

Definition at line 1517 of file radeon_drv.h.

#define R600_ROW_TILING ( x ) ((x) << 8)

Definition at line 1807 of file radeon_drv.h.

#define R600_S0_X ( x ) ((x) << 0)

Definition at line 1557 of file radeon_drv.h.

#define R600_S0_Y ( x ) ((x) << 4)

Definition at line 1558 of file radeon_drv.h.

#define R600_S1_X ( x ) ((x) << 8)

Definition at line 1559 of file radeon_drv.h.

#define R600_S1_Y ( x ) ((x) << 12)

Definition at line 1560 of file radeon_drv.h.

#define R600_S2_X ( x ) ((x) << 16)

Definition at line 1561 of file radeon_drv.h.

#define R600_S2_Y ( x ) ((x) << 20)

Definition at line 1562 of file radeon_drv.h.

#define R600_S3_X ( x ) ((x) << 24)

Definition at line 1563 of file radeon_drv.h.

#define R600_S3_Y ( x ) ((x) << 28)

Definition at line 1564 of file radeon_drv.h.

#define R600_S4_X ( x ) ((x) << 0)

Definition at line 1565 of file radeon_drv.h.

#define R600_S4_Y ( x ) ((x) << 4)

Definition at line 1566 of file radeon_drv.h.

#define R600_S5_X ( x ) ((x) << 8)

Definition at line 1567 of file radeon_drv.h.

#define R600_S5_Y ( x ) ((x) << 12)

Definition at line 1568 of file radeon_drv.h.

#define R600_S6_X ( x ) ((x) << 16)

Definition at line 1569 of file radeon_drv.h.

#define R600_S6_Y ( x ) ((x) << 20)

Definition at line 1570 of file radeon_drv.h.

#define R600_S7_X ( x ) ((x) << 24)

Definition at line 1571 of file radeon_drv.h.

#define R600_S7_Y ( x ) ((x) << 28)

Definition at line 1572 of file radeon_drv.h.

#define R600_SAMPLE_SPLIT ( x ) ((x) << 14)

Definition at line 1809 of file radeon_drv.h.

#define R600_SC_EARLYZ_TILE_FIFO_SIZE ( x ) ((x) << 16)

Definition at line 1576 of file radeon_drv.h.

#define R600_SC_HIZ_TILE_FIFO_SIZE ( x ) ((x) << 8)

Definition at line 1575 of file radeon_drv.h.

#define R600_SC_PRIM_FIFO_SIZE ( x ) ((x) << 0)

Definition at line 1574 of file radeon_drv.h.

#define R600_SCRATCH_ADDR 0x8544

Definition at line 756 of file radeon_drv.h.

#define R600_SCRATCH_REG0 0x8500

Definition at line 747 of file radeon_drv.h.

#define R600_SCRATCH_REG1 0x8504

Definition at line 748 of file radeon_drv.h.

#define R600_SCRATCH_REG2 0x8508

Definition at line 749 of file radeon_drv.h.

#define R600_SCRATCH_REG3 0x850c

Definition at line 750 of file radeon_drv.h.

#define R600_SCRATCH_REG4 0x8510

Definition at line 751 of file radeon_drv.h.

#define R600_SCRATCH_REG5 0x8514

Definition at line 752 of file radeon_drv.h.

#define R600_SCRATCH_REG6 0x8518

Definition at line 753 of file radeon_drv.h.

#define R600_SCRATCH_REG7 0x851c

Definition at line 754 of file radeon_drv.h.

#define R600_SCRATCH_UMSK 0x8540

Definition at line 755 of file radeon_drv.h.

#define R600_SCRATCHOFF ( x ) (R600_SCRATCH_REG_OFFSET + 4*(x))

Definition at line 758 of file radeon_drv.h.

#define R600_SET_ALU_CONST_END 0x00032000

Definition at line 1147 of file radeon_drv.h.

#define R600_SET_ALU_CONST_OFFSET 0x00030000

Definition at line 1146 of file radeon_drv.h.

#define R600_SET_BOOL_CONST_END 0x00040000

Definition at line 1150 of file radeon_drv.h.

#define R600_SET_BOOL_CONST_OFFSET 0x0003e380

Definition at line 1149 of file radeon_drv.h.

#define R600_SET_CONFIG_REG_END 0x0000ac00

Definition at line 1141 of file radeon_drv.h.

#define R600_SET_CONFIG_REG_OFFSET 0x00008000

Definition at line 1140 of file radeon_drv.h.

#define R600_SET_CONTEXT_REG_END 0x00029000

Definition at line 1144 of file radeon_drv.h.

#define R600_SET_CONTEXT_REG_OFFSET 0x00028000

Definition at line 1143 of file radeon_drv.h.

#define R600_SET_CTL_CONST_END 0x0003e200

Definition at line 1166 of file radeon_drv.h.

#define R600_SET_CTL_CONST_OFFSET 0x0003cff0

Definition at line 1165 of file radeon_drv.h.

#define R600_SET_LOOP_CONST_END 0x0003e380

Definition at line 1153 of file radeon_drv.h.

#define R600_SET_LOOP_CONST_OFFSET 0x0003e200

Definition at line 1152 of file radeon_drv.h.

#define R600_SET_RESOURCE_END 0x0003c000

Definition at line 1156 of file radeon_drv.h.

#define R600_SET_RESOURCE_OFFSET 0x00038000

Definition at line 1155 of file radeon_drv.h.

#define R600_SET_SAMPLER_END 0x0003cff0

Definition at line 1163 of file radeon_drv.h.

#define R600_SET_SAMPLER_OFFSET 0x0003c000

Definition at line 1162 of file radeon_drv.h.

#define R600_SH_ACTION_ENA (1 << 27)

Definition at line 1131 of file radeon_drv.h.

#define R600_SMX_ACTION_ENA (1 << 28)

Definition at line 1132 of file radeon_drv.h.

#define R600_SMX_BUFFER_SIZE ( x ) ((x) << 16)

Definition at line 1593 of file radeon_drv.h.

#define R600_SMX_DC_CTL0 0xa020

Definition at line 1712 of file radeon_drv.h.

#define R600_SMX_EVENT_RELEASE (1 << 0)

Definition at line 1595 of file radeon_drv.h.

#define R600_SOFT_RESET_CP (1 << 0)

Definition at line 1509 of file radeon_drv.h.

#define R600_SPI_CONFIG_CNTL 0x9100

Definition at line 1796 of file radeon_drv.h.

#define R600_SPI_CONFIG_CNTL_1 0x913c

Definition at line 1799 of file radeon_drv.h.

#define R600_SPI_INPUT_Z 0x286d8

Definition at line 1794 of file radeon_drv.h.

#define R600_SPI_PS_IN_CONTROL_0 0x286cc

Definition at line 1771 of file radeon_drv.h.

#define R600_SPI_PS_IN_CONTROL_1 0x286d0

Definition at line 1783 of file radeon_drv.h.

#define R600_SQ_CONFIG 0x8c00

Definition at line 1723 of file radeon_drv.h.

#define R600_SQ_GPR_RESOURCE_MGMT_1 0x8c04

Definition at line 1734 of file radeon_drv.h.

#define R600_SQ_GPR_RESOURCE_MGMT_2 0x8c08

Definition at line 1739 of file radeon_drv.h.

#define R600_SQ_MS_FIFO_SIZES 0x8cf0

Definition at line 1753 of file radeon_drv.h.

#define R600_SQ_PGM_CF_OFFSET_PS 0x288cc

Definition at line 1666 of file radeon_drv.h.

#define R600_SQ_PGM_CF_OFFSET_VS 0x288d0

Definition at line 1661 of file radeon_drv.h.

#define R600_SQ_PGM_EXPORTS_PS 0x28854

Definition at line 1665 of file radeon_drv.h.

#define R600_SQ_PGM_RESOURCES_PS 0x28850

Definition at line 1664 of file radeon_drv.h.

#define R600_SQ_PGM_RESOURCES_VS 0x28868

Definition at line 1660 of file radeon_drv.h.

#define R600_SQ_PGM_START_ES 0x28880

Definition at line 1658 of file radeon_drv.h.

#define R600_SQ_PGM_START_FS 0x28894

Definition at line 1657 of file radeon_drv.h.

#define R600_SQ_PGM_START_GS 0x2886c

Definition at line 1662 of file radeon_drv.h.

#define R600_SQ_PGM_START_PS 0x28840

Definition at line 1663 of file radeon_drv.h.

#define R600_SQ_PGM_START_VS 0x28858

Definition at line 1659 of file radeon_drv.h.

#define R600_SQ_STACK_RESOURCE_MGMT_1 0x8c10

Definition at line 1747 of file radeon_drv.h.

#define R600_SQ_STACK_RESOURCE_MGMT_2 0x8c14

Definition at line 1750 of file radeon_drv.h.

#define R600_SQ_TEX_VTX_INVALID_BUFFER 0x1

Definition at line 1158 of file radeon_drv.h.

#define R600_SQ_TEX_VTX_INVALID_TEXTURE 0x0

Definition at line 1157 of file radeon_drv.h.

#define R600_SQ_TEX_VTX_VALID_BUFFER 0x3

Definition at line 1160 of file radeon_drv.h.

#define R600_SQ_TEX_VTX_VALID_TEXTURE 0x2

Definition at line 1159 of file radeon_drv.h.

#define R600_SQ_THREAD_RESOURCE_MGMT 0x8c0c

Definition at line 1742 of file radeon_drv.h.

#define R600_SX_DEBUG_1 0x9054

Definition at line 1594 of file radeon_drv.h.

#define R600_SX_EXPORT_BUFFER_SIZES 0x900c

Definition at line 1590 of file radeon_drv.h.

#define R600_SX_MISC 0x28350

Definition at line 1599 of file radeon_drv.h.

#define R600_SYNC_ALIGNER (1 << 26)

Definition at line 1706 of file radeon_drv.h.

#define R600_SYNC_GRADIENT (1 << 24)

Definition at line 1704 of file radeon_drv.h.

#define R600_SYNC_WALKER (1 << 25)

Definition at line 1705 of file radeon_drv.h.

#define R600_TA_CNTL_AUX 0x9508

Definition at line 1700 of file radeon_drv.h.

#define R600_TC_ACTION_ENA (1 << 23)

Definition at line 1127 of file radeon_drv.h.

#define R600_TC_CNTL 0x9608

Definition at line 1692 of file radeon_drv.h.

#define R600_TC_L2_SIZE ( x ) ((x) << 5)

Definition at line 1693 of file radeon_drv.h.

#define R600_TC_ONLY 1

Definition at line 1616 of file radeon_drv.h.

#define R600_VC_ACTION_ENA (1 << 24)

Definition at line 1128 of file radeon_drv.h.

#define R600_VC_AND_TC 2

Definition at line 1617 of file radeon_drv.h.

#define R600_VC_ENABLE (1 << 0)

Definition at line 1724 of file radeon_drv.h.

#define R600_VC_ONLY 0

Definition at line 1615 of file radeon_drv.h.

#define R600_VGT_CACHE_INVALIDATION 0x88c4

Definition at line 1613 of file radeon_drv.h.

#define R600_VGT_DMA_BASE 0x287e8

Definition at line 1667 of file radeon_drv.h.

#define R600_VGT_DMA_BASE_HI 0x287e4

Definition at line 1668 of file radeon_drv.h.

#define R600_VGT_ES_PER_GS 0x88cc

Definition at line 1624 of file radeon_drv.h.

#define R600_VGT_EVENT_INITIATOR 0x28a90

Definition at line 1629 of file radeon_drv.h.

#define R600_VGT_GS_PER_ES 0x88c8

Definition at line 1623 of file radeon_drv.h.

#define R600_VGT_GS_PER_VS 0x88e8

Definition at line 1625 of file radeon_drv.h.

#define R600_VGT_GS_VERTEX_REUSE 0x88d4

Definition at line 1626 of file radeon_drv.h.

#define R600_VGT_NUM_INSTANCES 0x8974

Definition at line 1627 of file radeon_drv.h.

#define R600_VGT_OUT_DEALLOC_CNTL 0x28c5c

Definition at line 1633 of file radeon_drv.h.

#define R600_VGT_PRIMITIVE_TYPE 0x8958

Definition at line 1686 of file radeon_drv.h.

#define R600_VGT_STRMOUT_BASE_OFFSET_0 0x28b10

Definition at line 1669 of file radeon_drv.h.

#define R600_VGT_STRMOUT_BASE_OFFSET_1 0x28b14

Definition at line 1670 of file radeon_drv.h.

#define R600_VGT_STRMOUT_BASE_OFFSET_2 0x28b18

Definition at line 1671 of file radeon_drv.h.

#define R600_VGT_STRMOUT_BASE_OFFSET_3 0x28b1c

Definition at line 1672 of file radeon_drv.h.

#define R600_VGT_STRMOUT_BASE_OFFSET_HI_0 0x28b44

Definition at line 1673 of file radeon_drv.h.

#define R600_VGT_STRMOUT_BASE_OFFSET_HI_1 0x28b48

Definition at line 1674 of file radeon_drv.h.

#define R600_VGT_STRMOUT_BASE_OFFSET_HI_2 0x28b4c

Definition at line 1675 of file radeon_drv.h.

#define R600_VGT_STRMOUT_BASE_OFFSET_HI_3 0x28b50

Definition at line 1676 of file radeon_drv.h.

#define R600_VGT_STRMOUT_BUFFER_BASE_0 0x28ad8

Definition at line 1677 of file radeon_drv.h.

#define R600_VGT_STRMOUT_BUFFER_BASE_1 0x28ae8

Definition at line 1678 of file radeon_drv.h.

#define R600_VGT_STRMOUT_BUFFER_BASE_2 0x28af8

Definition at line 1679 of file radeon_drv.h.

#define R600_VGT_STRMOUT_BUFFER_BASE_3 0x28b08

Definition at line 1680 of file radeon_drv.h.

#define R600_VGT_STRMOUT_BUFFER_OFFSET_0 0x28adc

Definition at line 1681 of file radeon_drv.h.

#define R600_VGT_STRMOUT_BUFFER_OFFSET_1 0x28aec

Definition at line 1682 of file radeon_drv.h.

#define R600_VGT_STRMOUT_BUFFER_OFFSET_2 0x28afc

Definition at line 1683 of file radeon_drv.h.

#define R600_VGT_STRMOUT_BUFFER_OFFSET_3 0x28b0c

Definition at line 1684 of file radeon_drv.h.

#define R600_VGT_STRMOUT_EN 0x28ab0

Definition at line 1628 of file radeon_drv.h.

#define R600_VGT_VERTEX_REUSE_BLOCK_CNTL 0x28c58

Definition at line 1631 of file radeon_drv.h.

#define R600_VM_CONTEXT0_CNTL 0x1410

Definition at line 1482 of file radeon_drv.h.

#define R600_VM_CONTEXT0_CNTL2 0x1430

Definition at line 1486 of file radeon_drv.h.

#define R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14b0

Definition at line 1489 of file radeon_drv.h.

#define R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490

Definition at line 1488 of file radeon_drv.h.

#define R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574

Definition at line 1490 of file radeon_drv.h.

#define R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15b4

Definition at line 1492 of file radeon_drv.h.

#define R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594

Definition at line 1491 of file radeon_drv.h.

#define R600_VM_CONTEXT0_REQUEST_RESPONSE 0x1470

Definition at line 1487 of file radeon_drv.h.

#define R600_VM_ENABLE_CONTEXT (1 << 0)

Definition at line 1483 of file radeon_drv.h.

#define R600_VM_ENABLE_PTE_CACHE_LRU_W (1 << 9)

Definition at line 1466 of file radeon_drv.h.

#define R600_VM_L2_CACHE_EN (1 << 0)

Definition at line 1464 of file radeon_drv.h.

#define R600_VM_L2_CNTL 0x1400

Definition at line 1463 of file radeon_drv.h.

#define R600_VM_L2_CNTL2 0x1404

Definition at line 1470 of file radeon_drv.h.

#define R600_VM_L2_CNTL2_INVALIDATE_ALL_L1_TLBS (1 << 0)

Definition at line 1471 of file radeon_drv.h.

#define R600_VM_L2_CNTL2_INVALIDATE_L2_CACHE (1 << 1)

Definition at line 1472 of file radeon_drv.h.

#define R600_VM_L2_CNTL3 0x1408

Definition at line 1473 of file radeon_drv.h.

#define R600_VM_L2_CNTL3_BANK_SELECT_0 ( x ) ((x) << 0)

Definition at line 1474 of file radeon_drv.h.

#define R600_VM_L2_CNTL3_BANK_SELECT_1 ( x ) ((x) << 5)

Definition at line 1475 of file radeon_drv.h.

#define R600_VM_L2_CNTL3_CACHE_UPDATE_MODE ( x ) ((x) << 10)

Definition at line 1476 of file radeon_drv.h.

#define R600_VM_L2_CNTL_QUEUE_SIZE ( x ) ((x) << 13)

Definition at line 1467 of file radeon_drv.h.

#define R600_VM_L2_FRAG_PROC (1 << 1)

Definition at line 1465 of file radeon_drv.h.

#define R600_VM_L2_STATUS 0x140c

Definition at line 1480 of file radeon_drv.h.

#define R600_VM_PAGE_TABLE_DEPTH_FLAT (0 << 1)

Definition at line 1484 of file radeon_drv.h.

#define R600_VS_PRIO ( x ) ((x) << 26)

Definition at line 1731 of file radeon_drv.h.

#define R600_VTX_DONE_DELAY ( x ) ((x) << 0)

Definition at line 1800 of file radeon_drv.h.

#define R600_VTX_REUSE_DEPTH_MASK 0xff

Definition at line 1632 of file radeon_drv.h.

#define R600_WAIT_UNTIL 0x8040

Definition at line 1510 of file radeon_drv.h.

#define R700_ACK_FLUSH_CTL ( x ) ((x) << 6)

Definition at line 1720 of file radeon_drv.h.

#define R700_AUTO_INVLD_EN ( x ) ((x) << 6)

Definition at line 1618 of file radeon_drv.h.

#define R700_BURSTLENGTH_MASK 0x1

Definition at line 1448 of file radeon_drv.h.

#define R700_BURSTLENGTH_SHIFT 9

Definition at line 1447 of file radeon_drv.h.

#define R700_CACHE_DEPTH ( x ) ((x) << 1)

Definition at line 1714 of file radeon_drv.h.

#define R700_CC_SYS_RB_BACKEND_DISABLE 0x3f88

Definition at line 1815 of file radeon_drv.h.

#define R700_CGTS_SYS_TCC_DISABLE 0x3f90

Definition at line 1825 of file radeon_drv.h.

#define R700_CGTS_TCC_DISABLE 0x9148

Definition at line 1827 of file radeon_drv.h.

#define R700_CGTS_USER_SYS_TCC_DISABLE 0x3f94

Definition at line 1826 of file radeon_drv.h.

#define R700_CGTS_USER_TCC_DISABLE 0x914c

Definition at line 1828 of file radeon_drv.h.

#define R700_CHANSIZE_MASK 0x1

Definition at line 1446 of file radeon_drv.h.

#define R700_CHANSIZE_SHIFT 8

Definition at line 1445 of file radeon_drv.h.

#define R700_CMDFIFO_AVAIL_MASK 0xf

Definition at line 1505 of file radeon_drv.h.

#define R700_DB_CLK_OFF_DELAY ( x ) ((x) << 11)

Definition at line 1609 of file radeon_drv.h.

#define R700_DB_DEBUG3 0x98b0

Definition at line 1608 of file radeon_drv.h.

#define R700_DYN_GPR_ENABLE (1 << 27)

Definition at line 1737 of file radeon_drv.h.

#define R700_EFFECTIVE_L1_QUEUE_SIZE ( x ) ((x) << 18)

Definition at line 1434 of file radeon_drv.h.

#define R700_EFFECTIVE_L1_TLB_SIZE ( x ) ((x) << 15)

Definition at line 1433 of file radeon_drv.h.

#define R700_ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)

Definition at line 1430 of file radeon_drv.h.

#define R700_ENABLE_L1_TLB (1 << 0)

Definition at line 1429 of file radeon_drv.h.

#define R700_ENABLE_NEW_SMX_ADDRESS (1 << 16)

Definition at line 1598 of file radeon_drv.h.

#define R700_ES_AND_GS_AUTO 3

Definition at line 1622 of file radeon_drv.h.

#define R700_ES_AUTO 1

Definition at line 1620 of file radeon_drv.h.

#define R700_ES_FLUSH_CTL ( x ) ((x) << 0)

Definition at line 1718 of file radeon_drv.h.

#define R700_FLUSH_ALL_ON_EVENT (1 << 10)

Definition at line 1715 of file radeon_drv.h.

#define R700_FORCE_EOV_MAX_CLK_CNT ( x ) ((x) << 0)

Definition at line 1551 of file radeon_drv.h.

#define R700_FORCE_EOV_MAX_REZ_CNT ( x ) ((x) << 16)

Definition at line 1552 of file radeon_drv.h.

#define R700_GETLOD_SELECT ( x ) ((x) << 2)

Definition at line 1703 of file radeon_drv.h.

#define R700_GS_AUTO 2

Definition at line 1621 of file radeon_drv.h.

#define R700_GS_FLUSH_CTL ( x ) ((x) << 3)

Definition at line 1719 of file radeon_drv.h.

#define R700_MC_ARB_RAMCFG 0x2760

Definition at line 1436 of file radeon_drv.h.

#define R700_MC_VM_AGP_BASE 0x2030

Definition at line 1379 of file radeon_drv.h.

#define R700_MC_VM_AGP_BOT 0x202c

Definition at line 1378 of file radeon_drv.h.

#define R700_MC_VM_AGP_TOP 0x2028

Definition at line 1377 of file radeon_drv.h.

#define R700_MC_VM_FB_LOCATION 0x2024

Definition at line 1376 of file radeon_drv.h.

#define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234

Definition at line 1424 of file radeon_drv.h.

#define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238

Definition at line 1425 of file radeon_drv.h.

#define R700_MC_VM_MB_L1_TLB2_CNTL 0x223c

Definition at line 1426 of file radeon_drv.h.

#define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240

Definition at line 1427 of file radeon_drv.h.

#define R700_MC_VM_MD_L1_TLB0_CNTL 0x2654

Definition at line 1420 of file radeon_drv.h.

#define R700_MC_VM_MD_L1_TLB1_CNTL 0x2658

Definition at line 1421 of file radeon_drv.h.

#define R700_MC_VM_MD_L1_TLB2_CNTL 0x265c

Definition at line 1422 of file radeon_drv.h.

#define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c

Definition at line 1382 of file radeon_drv.h.

#define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038

Definition at line 1381 of file radeon_drv.h.

#define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034

Definition at line 1380 of file radeon_drv.h.

#define R700_NO_AUTO 0

Definition at line 1619 of file radeon_drv.h.

#define R700_NOOFBANK_MASK 0x3

Definition at line 1438 of file radeon_drv.h.

#define R700_NOOFBANK_SHIFT 0

Definition at line 1437 of file radeon_drv.h.

#define R700_NOOFCOLS_MASK 0x3

Definition at line 1444 of file radeon_drv.h.

#define R700_NOOFCOLS_SHIFT 6

Definition at line 1443 of file radeon_drv.h.

#define R700_NOOFRANK_MASK 0x1

Definition at line 1440 of file radeon_drv.h.

#define R700_NOOFRANK_SHIFT 2

Definition at line 1439 of file radeon_drv.h.

#define R700_NOOFROWS_MASK 0x7

Definition at line 1442 of file radeon_drv.h.

#define R700_NOOFROWS_SHIFT 3

Definition at line 1441 of file radeon_drv.h.

#define R700_PA_SC_EDGERULE 0x28230

Definition at line 1585 of file radeon_drv.h.

#define R700_PA_SC_FIFO_SIZE_R7XX 0x8bcc

Definition at line 1577 of file radeon_drv.h.

#define R700_PA_SC_FORCE_EOV_MAX_CNTS 0x8b24

Definition at line 1550 of file radeon_drv.h.

#define R700_POSITION_ULC (1 << 30)

Definition at line 1793 of file radeon_drv.h.

#define R700_SC_EARLYZ_TILE_FIFO_SIZE ( x ) ((x) << 20)

Definition at line 1580 of file radeon_drv.h.

#define R700_SC_HIZ_TILE_FIFO_SIZE ( x ) ((x) << 12)

Definition at line 1579 of file radeon_drv.h.

#define R700_SC_PRIM_FIFO_SIZE ( x ) ((x) << 0)

Definition at line 1578 of file radeon_drv.h.

#define R700_SIMDA_RING0 ( x ) ((x) << 0)

Definition at line 1759 of file radeon_drv.h.

#define R700_SIMDA_RING1 ( x ) ((x) << 8)

Definition at line 1760 of file radeon_drv.h.

#define R700_SIMDB_RING0 ( x ) ((x) << 16)

Definition at line 1761 of file radeon_drv.h.

#define R700_SIMDB_RING1 ( x ) ((x) << 24)

Definition at line 1762 of file radeon_drv.h.

#define R700_SMX_EVENT_CTL 0xa02c

Definition at line 1717 of file radeon_drv.h.

#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8db0

Definition at line 1758 of file radeon_drv.h.

#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8db4

Definition at line 1763 of file radeon_drv.h.

#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8db8

Definition at line 1764 of file radeon_drv.h.

#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8dbc

Definition at line 1765 of file radeon_drv.h.

#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8dc0

Definition at line 1766 of file radeon_drv.h.

#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8dc4

Definition at line 1767 of file radeon_drv.h.

#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8dc8

Definition at line 1768 of file radeon_drv.h.

#define R700_SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8dcc

Definition at line 1769 of file radeon_drv.h.

#define R700_STALL_ON_EVENT (1 << 11)

Definition at line 1716 of file radeon_drv.h.

#define R700_STQ_SPLIT ( x ) ((x) << 0)

Definition at line 1519 of file radeon_drv.h.

#define R700_SX_DEBUG_1 0x9058

Definition at line 1597 of file radeon_drv.h.

#define R700_SYNC_FLUSH_CTL (1 << 8)

Definition at line 1721 of file radeon_drv.h.

#define R700_SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)

Definition at line 1431 of file radeon_drv.h.

#define R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)

Definition at line 1432 of file radeon_drv.h.

#define R700_TCP_CNTL 0x9610

Definition at line 1710 of file radeon_drv.h.

#define R700_USE_HASH_FUNCTION (1 << 0)

Definition at line 1713 of file radeon_drv.h.

#define R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c

Definition at line 1494 of file radeon_drv.h.

#define R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157c

Definition at line 1496 of file radeon_drv.h.

#define R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c

Definition at line 1495 of file radeon_drv.h.

#define R700_VM_L2_CNTL3_BANK_SELECT ( x ) ((x) << 0)

Definition at line 1477 of file radeon_drv.h.

#define R700_VM_L2_CNTL3_CACHE_UPDATE_MODE ( x ) ((x) << 6)

Definition at line 1478 of file radeon_drv.h.

#define R700_VM_L2_CNTL_QUEUE_SIZE ( x ) ((x) << 14)

Definition at line 1468 of file radeon_drv.h.

#define RADEON_3D_CLEAR_HIZ 0x00003700

Definition at line 1097 of file radeon_drv.h.

#define RADEON_3D_CLEAR_ZMASK 0x00003200

Definition at line 1092 of file radeon_drv.h.

#define RADEON_3D_DRAW_IMMD 0x00002900

Definition at line 1086 of file radeon_drv.h.

#define RADEON_3D_DRAW_INDX 0x00002A00

Definition at line 1087 of file radeon_drv.h.

#define RADEON_3D_DRAW_VBUF 0x00002800

Definition at line 1085 of file radeon_drv.h.

#define RADEON_3D_LOAD_VBPNTR 0x00002F00

Definition at line 1089 of file radeon_drv.h.

#define RADEON_3D_RNDR_GEN_INDX_PRIM 0x00002300

Definition at line 1083 of file radeon_drv.h.

#define RADEON_AGP_BASE 0x0170

Definition at line 679 of file radeon_drv.h.

#define RADEON_AGP_BASE_2 0x015c /* r200+ only */

Definition at line 677 of file radeon_drv.h.

#define RADEON_AGP_COMMAND 0x0f60

Definition at line 489 of file radeon_drv.h.

#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */

Definition at line 490 of file radeon_drv.h.

#define RADEON_AGP_ENABLE (1<<8)

Definition at line 491 of file radeon_drv.h.

#define RADEON_AIC_CNTL 0x01d0

Definition at line 1062 of file radeon_drv.h.

#define RADEON_AIC_HI_ADDR 0x01e0

Definition at line 1068 of file radeon_drv.h.

#define RADEON_AIC_LO_ADDR 0x01dc

Definition at line 1067 of file radeon_drv.h.

#define RADEON_AIC_PT_BASE 0x01d8

Definition at line 1066 of file radeon_drv.h.

#define RADEON_AIC_STAT 0x01d4

Definition at line 1065 of file radeon_drv.h.

#define RADEON_AIC_TLB_ADDR 0x01e4

Definition at line 1069 of file radeon_drv.h.

#define RADEON_AIC_TLB_DATA 0x01e8

Definition at line 1070 of file radeon_drv.h.

#define RADEON_ALPHA_BLEND_ENABLE (1 << 0)

Definition at line 826 of file radeon_drv.h.

#define RADEON_ALPHA_SHADE_FLAT (1 << 10)

Definition at line 947 of file radeon_drv.h.

#define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)

Definition at line 948 of file radeon_drv.h.

#define RADEON_AUX_SCISSOR_CNTL 0x26f0

Definition at line 492 of file radeon_drv.h.

#define RADEON_BFACE_SOLID (3 << 1)

Definition at line 942 of file radeon_drv.h.

#define RADEON_BOX_DMA_IDLE 0x1

Definition at line 477 of file radeon_drv.h.

#define RADEON_BOX_FLIP 0x4

Definition at line 479 of file radeon_drv.h.

#define RADEON_BOX_RING_FULL 0x2

Definition at line 478 of file radeon_drv.h.

#define RADEON_BOX_TEXTURE_LOAD 0x10

Definition at line 481 of file radeon_drv.h.

#define RADEON_BOX_WAIT_IDLE 0x8

Definition at line 480 of file radeon_drv.h.

#define RADEON_BUF_SWAP_32BIT (2 << 16)

Definition at line 1037 of file radeon_drv.h.

#define RADEON_BUS_CNTL 0x0030

Definition at line 506 of file radeon_drv.h.

#define RADEON_BUS_CNTL1 0x0034

Definition at line 514 of file radeon_drv.h.

#define RADEON_BUS_MASTER_DIS (1 << 6)

Definition at line 508 of file radeon_drv.h.

#define RADEON_CBA2D_BUSY (1 << 27)

Definition at line 924 of file radeon_drv.h.

#define RADEON_CFRQ_IN_RTBUF (1 << 13)

Definition at line 910 of file radeon_drv.h.

#define RADEON_CFRQ_ON_RBB (1 << 10)

Definition at line 907 of file radeon_drv.h.

#define RADEON_CLEAR_AGE ( age )

Value:

do {                    \
    OUT_RING( CP_PACKET0( RADEON_LAST_CLEAR_REG, 0 ) );     \
    OUT_RING( age );                        \
} while (0)

Definition at line 2037 of file radeon_drv.h.

#define RADEON_CLOCK_CNTL_DATA 0x000c

Definition at line 526 of file radeon_drv.h.

#define RADEON_CLOCK_CNTL_INDEX 0x0008

Definition at line 528 of file radeon_drv.h.

#define RADEON_CNTL_BITBLT_MULTI 0x00009B00

Definition at line 1101 of file radeon_drv.h.

#define RADEON_CNTL_HOSTDATA_BLT 0x00009400

Definition at line 1099 of file radeon_drv.h.

#define RADEON_CNTL_PAINT_MULTI 0x00009A00

Definition at line 1100 of file radeon_drv.h.

#define RADEON_CNTL_SET_SCISSORS 0xC0001E00

Definition at line 1102 of file radeon_drv.h.

#define RADEON_COLOR_FORMAT_ARGB1555 3

Definition at line 1201 of file radeon_drv.h.

#define RADEON_COLOR_FORMAT_ARGB4444 15

Definition at line 1206 of file radeon_drv.h.

#define RADEON_COLOR_FORMAT_ARGB8888 6

Definition at line 1203 of file radeon_drv.h.

#define RADEON_COLOR_FORMAT_CI8 2

Definition at line 1200 of file radeon_drv.h.

#define RADEON_COLOR_FORMAT_RGB332 7

Definition at line 1204 of file radeon_drv.h.

#define RADEON_COLOR_FORMAT_RGB565 4

Definition at line 1202 of file radeon_drv.h.

#define RADEON_COLOR_FORMAT_RGB8 9

Definition at line 1205 of file radeon_drv.h.

#define RADEON_COLOR_ORDER_BGRA (0 << 6)

Definition at line 1193 of file radeon_drv.h.

#define RADEON_COLOR_ORDER_RGBA (1 << 6)

Definition at line 1194 of file radeon_drv.h.

#define RADEON_CONFIG_APER_SIZE 0x0108

Definition at line 529 of file radeon_drv.h.

#define RADEON_CONFIG_MEMSIZE 0x00f8

Definition at line 530 of file radeon_drv.h.

#define RADEON_CP_3D_CLEAR_CMASK 0x00003802

Definition at line 1098 of file radeon_drv.h.

#define RADEON_CP_3D_DRAW_IMMD_2 0x00003500

Definition at line 1095 of file radeon_drv.h.

#define RADEON_CP_3D_DRAW_INDX_2 0x00003600

Definition at line 1096 of file radeon_drv.h.

#define RADEON_CP_3D_DRAW_VBUF_2 0x00003400

Definition at line 1094 of file radeon_drv.h.

#define RADEON_CP_CMDSTRM_BUSY (1 << 16)

Definition at line 913 of file radeon_drv.h.

#define RADEON_CP_CSQ_CNTL 0x0740

Definition at line 1050 of file radeon_drv.h.

#define RADEON_CP_IB_BASE 0x0738

Definition at line 1048 of file radeon_drv.h.

#define RADEON_CP_INDX_BUFFER 0x00003300

Definition at line 1093 of file radeon_drv.h.

#define RADEON_CP_LOAD_PALETTE 0x00002C00

Definition at line 1088 of file radeon_drv.h.

#define RADEON_CP_ME_RAM_ADDR 0x07d4

Definition at line 1030 of file radeon_drv.h.

#define RADEON_CP_ME_RAM_DATAH 0x07dc

Definition at line 1032 of file radeon_drv.h.

#define RADEON_CP_ME_RAM_DATAL 0x07e0

Definition at line 1033 of file radeon_drv.h.

#define RADEON_CP_ME_RAM_RADDR 0x07d8

Definition at line 1031 of file radeon_drv.h.

#define RADEON_CP_NEXT_CHAR 0x00001900

Definition at line 1079 of file radeon_drv.h.

#define RADEON_CP_NOP 0x00001000

Definition at line 1078 of file radeon_drv.h.

#define RADEON_CP_PACKET0 0x00000000

Definition at line 1073 of file radeon_drv.h.

#define RADEON_CP_PACKET0_REG_MASK 0x000007ff

Definition at line 1171 of file radeon_drv.h.

#define RADEON_CP_PACKET1 0x40000000

Definition at line 1075 of file radeon_drv.h.

#define RADEON_CP_PACKET1_REG0_MASK 0x000007ff

Definition at line 1172 of file radeon_drv.h.

#define RADEON_CP_PACKET1_REG1_MASK 0x003ff800

Definition at line 1173 of file radeon_drv.h.

#define RADEON_CP_PACKET2 0x80000000

Definition at line 1076 of file radeon_drv.h.

#define RADEON_CP_PACKET3 0xC0000000

Definition at line 1077 of file radeon_drv.h.

#define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000

Definition at line 1170 of file radeon_drv.h.

#define RADEON_CP_PACKET_MASK 0xC0000000

Definition at line 1169 of file radeon_drv.h.

#define RADEON_CP_PLY_NEXTSCAN 0x00001D00

Definition at line 1080 of file radeon_drv.h.

#define RADEON_CP_RB_BASE 0x0700

Definition at line 1035 of file radeon_drv.h.

#define RADEON_CP_RB_CNTL 0x0704

Definition at line 1036 of file radeon_drv.h.

#define RADEON_CP_RB_RPTR 0x0710

Definition at line 1041 of file radeon_drv.h.

#define RADEON_CP_RB_RPTR_ADDR 0x070c

Definition at line 1040 of file radeon_drv.h.

#define RADEON_CP_RB_WPTR 0x0714

Definition at line 1042 of file radeon_drv.h.

#define RADEON_CP_RB_WPTR_DELAY 0x0718

Definition at line 1044 of file radeon_drv.h.

#define RADEON_CP_SET_SCISSORS 0x00001E00

Definition at line 1081 of file radeon_drv.h.

#define RADEON_CPRQ_IN_RTBUF (1 << 12)

Definition at line 909 of file radeon_drv.h.

#define RADEON_CPRQ_ON_RBB (1 << 9)

Definition at line 906 of file radeon_drv.h.

#define RADEON_CRTC2_CRNT_FRAME 0x0314

Definition at line 1340 of file radeon_drv.h.

#define RADEON_CRTC2_OFFSET 0x0324

Definition at line 535 of file radeon_drv.h.

#define RADEON_CRTC2_OFFSET_CNTL 0x0328

Definition at line 536 of file radeon_drv.h.

#define RADEON_CRTC2_VBLANK_MASK (1 << 9)

Definition at line 762 of file radeon_drv.h.

#define RADEON_CRTC2_VBLANK_STAT (1 << 9)

Definition at line 769 of file radeon_drv.h.

#define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)

Definition at line 770 of file radeon_drv.h.

#define RADEON_CRTC_CRNT_FRAME 0x0214

Definition at line 1339 of file radeon_drv.h.

#define RADEON_CRTC_OFFSET 0x0224

Definition at line 531 of file radeon_drv.h.

#define RADEON_CRTC_OFFSET_CNTL 0x0228

Definition at line 532 of file radeon_drv.h.

#define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)

Definition at line 534 of file radeon_drv.h.

#define RADEON_CRTC_TILE_EN (1 << 15)

Definition at line 533 of file radeon_drv.h.

#define RADEON_CRTC_VBLANK_MASK (1 << 0)

Definition at line 761 of file radeon_drv.h.

#define RADEON_CRTC_VBLANK_STAT (1 << 0)

Definition at line 767 of file radeon_drv.h.

#define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)

Definition at line 768 of file radeon_drv.h.

#define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)

Definition at line 1051 of file radeon_drv.h.

#define RADEON_CSQ_PRIBM_INDBM (4 << 28)

Definition at line 1056 of file radeon_drv.h.

#define RADEON_CSQ_PRIBM_INDDIS (2 << 28)

Definition at line 1054 of file radeon_drv.h.

#define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)

Definition at line 1052 of file radeon_drv.h.

#define RADEON_CSQ_PRIPIO_INDBM (3 << 28)

Definition at line 1055 of file radeon_drv.h.

#define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)

Definition at line 1053 of file radeon_drv.h.

#define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)

Definition at line 1057 of file radeon_drv.h.

#define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)

Definition at line 1026 of file radeon_drv.h.

#define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)

Definition at line 1027 of file radeon_drv.h.

#define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)

Definition at line 945 of file radeon_drv.h.

#define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)

Definition at line 946 of file radeon_drv.h.

#define RADEON_DISPATCH_AGE ( age )

Value:

do {                    \
    OUT_RING( CP_PACKET0( RADEON_LAST_DISPATCH_REG, 0 ) );      \
    OUT_RING( age );                        \
} while (0)

Definition at line 2027 of file radeon_drv.h.

#define RADEON_DITHER_ENABLE (1 << 2)

Definition at line 828 of file radeon_drv.h.

#define RADEON_DITHER_INIT (1 << 5)

Definition at line 831 of file radeon_drv.h.

#define RADEON_DP_GUI_MASTER_CNTL 0x146c

Definition at line 707 of file radeon_drv.h.

#define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)

Definition at line 718 of file radeon_drv.h.

#define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)

Definition at line 717 of file radeon_drv.h.

#define RADEON_DP_WRITE_MASK 0x16cc

Definition at line 723 of file radeon_drv.h.

#define RADEON_DST_PITCH_OFFSET 0x142c

Definition at line 725 of file radeon_drv.h.

#define RADEON_DST_PITCH_OFFSET_C 0x1c80

Definition at line 726 of file radeon_drv.h.

#define RADEON_DST_TILE_BOTH (3 << 30)

Definition at line 730 of file radeon_drv.h.

#define RADEON_DST_TILE_LINEAR (0 << 30)

Definition at line 727 of file radeon_drv.h.

#define RADEON_DST_TILE_MACRO (1 << 30)

Definition at line 728 of file radeon_drv.h.

#define RADEON_DST_TILE_MICRO (2 << 30)

Definition at line 729 of file radeon_drv.h.

#define RADEON_E2_BUSY (1 << 17)

Definition at line 914 of file radeon_drv.h.

#define RADEON_ENG_EV_BUSY (1 << 15)

Definition at line 912 of file radeon_drv.h.

#define RADEON_EXCLUSIVE_SCISSOR_0 (1 << 24)

Definition at line 493 of file radeon_drv.h.

#define RADEON_EXCLUSIVE_SCISSOR_1 (1 << 25)

Definition at line 494 of file radeon_drv.h.

#define RADEON_EXCLUSIVE_SCISSOR_2 (1 << 26)

Definition at line 495 of file radeon_drv.h.

#define RADEON_FFACE_CULL_CW (0 << 0)

Definition at line 941 of file radeon_drv.h.

#define RADEON_FFACE_SOLID (3 << 3)

Definition at line 943 of file radeon_drv.h.

#define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)

Definition at line 944 of file radeon_drv.h.

#define RADEON_FLUSH_CACHE ( )

Value:

do {                    \
    if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
        OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));  \
        OUT_RING(RADEON_RB3D_DC_FLUSH);             \
    } else {                                                        \
        OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));    \
        OUT_RING(R300_RB3D_DC_FLUSH);               \
    }                                                               \
} while (0)

Definition at line 1956 of file radeon_drv.h.

#define RADEON_FLUSH_EMITED (1 << 0)

Definition at line 182 of file radeon_drv.h.

#define RADEON_FLUSH_ZCACHE ( )

Value:

do {                    \
    if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
        OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));    \
        OUT_RING(RADEON_RB3D_ZC_FLUSH);             \
    } else {                                                        \
        OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0));    \
        OUT_RING(R300_ZC_FLUSH);                \
    }                                                               \
} while (0)

Definition at line 1976 of file radeon_drv.h.

#define RADEON_FOG_SHADE_FLAT (1 << 14)

Definition at line 951 of file radeon_drv.h.

#define RADEON_FOG_SHADE_GOURAUD (2 << 14)

Definition at line 952 of file radeon_drv.h.

#define RADEON_FORCE_Z_DIRTY (1 << 29)

Definition at line 869 of file radeon_drv.h.

#define RADEON_FORCEON_AIC (1 << 21)

Definition at line 804 of file radeon_drv.h.

#define RADEON_FORCEON_MC (1 << 20)

Definition at line 803 of file radeon_drv.h.

#define RADEON_FORCEON_MCLKA (1 << 16)

Definition at line 799 of file radeon_drv.h.

#define RADEON_FORCEON_MCLKB (1 << 17)

Definition at line 800 of file radeon_drv.h.

#define RADEON_FORCEON_YCLKA (1 << 18)

Definition at line 801 of file radeon_drv.h.

#define RADEON_FORCEON_YCLKB (1 << 19)

Definition at line 802 of file radeon_drv.h.

#define RADEON_FRAME_AGE ( age )

Value:

do {                    \
    OUT_RING( CP_PACKET0( RADEON_LAST_FRAME_REG, 0 ) );     \
    OUT_RING( age );                        \
} while (0)

Definition at line 2032 of file radeon_drv.h.

#define RADEON_GA_BUSY (1 << 26)

Definition at line 923 of file radeon_drv.h.

#define RADEON_GEN_INT_CNTL 0x0040

Definition at line 760 of file radeon_drv.h.

#define RADEON_GEN_INT_STATUS 0x0044

Definition at line 766 of file radeon_drv.h.

#define RADEON_GMC_BRUSH_NONE (15 << 4)

Definition at line 711 of file radeon_drv.h.

#define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)

Definition at line 710 of file radeon_drv.h.

#define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)

Definition at line 719 of file radeon_drv.h.

#define RADEON_GMC_DST_16BPP (4 << 8)

Definition at line 712 of file radeon_drv.h.

#define RADEON_GMC_DST_24BPP (5 << 8)

Definition at line 713 of file radeon_drv.h.

#define RADEON_GMC_DST_32BPP (6 << 8)

Definition at line 714 of file radeon_drv.h.

#define RADEON_GMC_DST_DATATYPE_SHIFT 8

Definition at line 715 of file radeon_drv.h.

#define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)

Definition at line 709 of file radeon_drv.h.

#define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)

Definition at line 716 of file radeon_drv.h.

#define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)

Definition at line 708 of file radeon_drv.h.

#define RADEON_GMC_WR_MSK_DIS (1 << 30)

Definition at line 720 of file radeon_drv.h.

#define RADEON_GUI_IDLE_INT_ENABLE (1 << 19)

Definition at line 763 of file radeon_drv.h.

#define RADEON_GUI_IDLE_INT_TEST_ACK (1 << 19)

Definition at line 771 of file radeon_drv.h.

#define RADEON_HDP_SOFT_RESET (1 << 26)

Definition at line 778 of file radeon_drv.h.

#define RADEON_HDP_WC_TIMEOUT_28BCLK (7 << 28)

Definition at line 780 of file radeon_drv.h.

#define RADEON_HDP_WC_TIMEOUT_MASK (7 << 28)

Definition at line 779 of file radeon_drv.h.

#define RADEON_HIRQ_IN_RTBUF (1 << 11)

Definition at line 908 of file radeon_drv.h.

#define RADEON_HIRQ_ON_RBB (1 << 8)

Definition at line 905 of file radeon_drv.h.

#define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)

Definition at line 792 of file radeon_drv.h.

#define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)

Definition at line 793 of file radeon_drv.h.

#define RADEON_HOST_DATA_SWAP_HDW (3 << 0)

Definition at line 794 of file radeon_drv.h.

#define RADEON_HOST_DATA_SWAP_NONE (0 << 0)

Definition at line 791 of file radeon_drv.h.

#define RADEON_HOST_PATH_CNTL 0x0130

Definition at line 777 of file radeon_drv.h.

#define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)

Definition at line 783 of file radeon_drv.h.

#define RADEON_ISYNC_ANY3D_IDLE2D (1 << 1)

Definition at line 784 of file radeon_drv.h.

#define RADEON_ISYNC_CNTL 0x1724

Definition at line 782 of file radeon_drv.h.

#define RADEON_ISYNC_CPSCRATCH_IDLEGUI (1 << 5)

Definition at line 788 of file radeon_drv.h.

#define RADEON_ISYNC_TRIG2D_IDLE3D (1 << 2)

Definition at line 785 of file radeon_drv.h.

#define RADEON_ISYNC_TRIG3D_IDLE2D (1 << 3)

Definition at line 786 of file radeon_drv.h.

#define RADEON_ISYNC_WAIT_IDLEGUI (1 << 4)

Definition at line 787 of file radeon_drv.h.

#define RADEON_LAST_CLEAR_REG RADEON_SCRATCH_REG2

Definition at line 1835 of file radeon_drv.h.

#define RADEON_LAST_DISPATCH 1

Definition at line 1837 of file radeon_drv.h.

#define RADEON_LAST_DISPATCH_REG RADEON_SCRATCH_REG1

Definition at line 1834 of file radeon_drv.h.

#define RADEON_LAST_FRAME_REG RADEON_SCRATCH_REG0

Definition at line 1833 of file radeon_drv.h.

#define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3

Definition at line 1836 of file radeon_drv.h.

#define RADEON_MAOS_ENABLE (1 << 7)

Definition at line 1195 of file radeon_drv.h.

#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */

Definition at line 1831 of file radeon_drv.h.

#define RADEON_MAX_VB_AGE 0x7fffffff

Definition at line 1844 of file radeon_drv.h.

#define RADEON_MAX_VB_VERTS (0xffff)

Definition at line 1845 of file radeon_drv.h.

#define RADEON_MC_AGP_LOCATION 0x014c

Definition at line 796 of file radeon_drv.h.

#define RADEON_MC_FB_LOCATION 0x0148

Definition at line 797 of file radeon_drv.h.

#define RADEON_MCLK_CNTL 0x0012

Definition at line 798 of file radeon_drv.h.

#define RADEON_MEM_CNTL 0x0140

Definition at line 675 of file radeon_drv.h.

#define RADEON_MEM_SDRAM_MODE_REG 0x0158

Definition at line 676 of file radeon_drv.h.

#define RADEON_MM_DATA 0x0004

Definition at line 487 of file radeon_drv.h.

#define RADEON_MM_INDEX 0x0000

Definition at line 486 of file radeon_drv.h.

#define RADEON_MPEG_IDCT_MACROBLOCK 0x00003000

Definition at line 1090 of file radeon_drv.h.

#define RADEON_MPEG_IDCT_MACROBLOCK_REV 0x00003100

Definition at line 1091 of file radeon_drv.h.

#define RADEON_MPP_TB_CONFIG 0x01c0

Definition at line 674 of file radeon_drv.h.

#define RADEON_MSI_REARM_EN 0x0160

Definition at line 522 of file radeon_drv.h.

#define RADEON_NONSURF_AP0_SWP_BIG16 (1 << 20)

Definition at line 977 of file radeon_drv.h.

#define RADEON_NONSURF_AP0_SWP_BIG32 (2 << 20)

Definition at line 978 of file radeon_drv.h.

#define RADEON_NONSURF_AP0_SWP_LITTLE (0 << 20)

Definition at line 976 of file radeon_drv.h.

#define RADEON_NONSURF_AP0_SWP_MASK (3 << 20)

Definition at line 975 of file radeon_drv.h.

#define RADEON_NONSURF_AP1_SWP_BIG16 (1 << 22)

Definition at line 981 of file radeon_drv.h.

#define RADEON_NONSURF_AP1_SWP_BIG32 (2 << 22)

Definition at line 982 of file radeon_drv.h.

#define RADEON_NONSURF_AP1_SWP_LITTLE (0 << 22)

Definition at line 980 of file radeon_drv.h.

#define RADEON_NONSURF_AP1_SWP_MASK (3 << 22)

Definition at line 979 of file radeon_drv.h.

#define RADEON_NUM_VERTICES_SHIFT 16

Definition at line 1198 of file radeon_drv.h.

#define RADEON_ONE_REG_WR (1 << 15)

Definition at line 1074 of file radeon_drv.h.

#define RADEON_PB_BUSY (1 << 24) /* not used on r300 */

Definition at line 921 of file radeon_drv.h.

#define RADEON_PCIE_DATA 0x0034

Definition at line 539 of file radeon_drv.h.

#define RADEON_PCIE_INDEX 0x0030

Definition at line 538 of file radeon_drv.h.

#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12

Definition at line 550 of file radeon_drv.h.

#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11

Definition at line 549 of file radeon_drv.h.

#define RADEON_PCIE_TX_GART_BASE 0x13

Definition at line 551 of file radeon_drv.h.

#define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)

Definition at line 547 of file radeon_drv.h.

#define RADEON_PCIE_TX_GART_CNTL 0x10

Definition at line 540 of file radeon_drv.h.

#define RADEON_PCIE_TX_GART_EN (1 << 0)

Definition at line 541 of file radeon_drv.h.

#define RADEON_PCIE_TX_GART_END_HI 0x17

Definition at line 555 of file radeon_drv.h.

#define RADEON_PCIE_TX_GART_END_LO 0x16

Definition at line 554 of file radeon_drv.h.

#define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)

Definition at line 548 of file radeon_drv.h.

#define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)

Definition at line 545 of file radeon_drv.h.

#define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)

Definition at line 546 of file radeon_drv.h.

#define RADEON_PCIE_TX_GART_START_HI 0x15

Definition at line 553 of file radeon_drv.h.

#define RADEON_PCIE_TX_GART_START_LO 0x14

Definition at line 552 of file radeon_drv.h.

#define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)

Definition at line 543 of file radeon_drv.h.

#define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)

Definition at line 544 of file radeon_drv.h.

#define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)

Definition at line 542 of file radeon_drv.h.

#define RADEON_PCIGART_TABLE_SIZE (32*1024)

Definition at line 1849 of file radeon_drv.h.

#define RADEON_PCIGART_TRANSLATE_EN (1 << 0)

Definition at line 1063 of file radeon_drv.h.

#define RADEON_PIPE_BUSY (1 << 14)

Definition at line 911 of file radeon_drv.h.

#define RADEON_PLANE_MASK_ENABLE (1 << 1)

Definition at line 827 of file radeon_drv.h.

#define RADEON_PLL_WR_EN (1 << 7)

Definition at line 527 of file radeon_drv.h.

#define RADEON_PMI_BM_DIS (1 << 2)

Definition at line 515 of file radeon_drv.h.

#define RADEON_PMI_INT_DIS (1 << 3)

Definition at line 516 of file radeon_drv.h.

#define RADEON_PP_BORDER_COLOR_0 0x1d40

Definition at line 806 of file radeon_drv.h.

#define RADEON_PP_BORDER_COLOR_1 0x1d44

Definition at line 807 of file radeon_drv.h.

#define RADEON_PP_BORDER_COLOR_2 0x1d48

Definition at line 808 of file radeon_drv.h.

#define RADEON_PP_CNTL 0x1c38

Definition at line 809 of file radeon_drv.h.

#define RADEON_PP_CUBIC_FACES_0 0x1d24

Definition at line 1307 of file radeon_drv.h.

#define RADEON_PP_CUBIC_FACES_1 0x1d28

Definition at line 1308 of file radeon_drv.h.

#define RADEON_PP_CUBIC_FACES_2 0x1d2c

Definition at line 1309 of file radeon_drv.h.

#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */

Definition at line 1310 of file radeon_drv.h.

#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00

Definition at line 1311 of file radeon_drv.h.

#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14

Definition at line 1312 of file radeon_drv.h.

#define RADEON_PP_LUM_MATRIX 0x1d00

Definition at line 811 of file radeon_drv.h.

#define RADEON_PP_MISC 0x1c14

Definition at line 812 of file radeon_drv.h.

#define RADEON_PP_ROT_MATRIX_0 0x1d58

Definition at line 813 of file radeon_drv.h.

#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */

Definition at line 1303 of file radeon_drv.h.

#define RADEON_PP_TEX_SIZE_1 0x1d0c

Definition at line 1304 of file radeon_drv.h.

#define RADEON_PP_TEX_SIZE_2 0x1d14

Definition at line 1305 of file radeon_drv.h.

#define RADEON_PP_TXFILTER_0 0x1c54

Definition at line 814 of file radeon_drv.h.

#define RADEON_PP_TXFILTER_1 0x1c6c

Definition at line 816 of file radeon_drv.h.

#define RADEON_PP_TXFILTER_2 0x1c84

Definition at line 817 of file radeon_drv.h.

#define RADEON_PP_TXOFFSET_0 0x1c5c

Definition at line 815 of file radeon_drv.h.

#define RADEON_PRE_WRITE_LIMIT_SHIFT 23

Definition at line 1046 of file radeon_drv.h.

#define RADEON_PRE_WRITE_TIMER_SHIFT 0

Definition at line 1045 of file radeon_drv.h.

#define RADEON_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)

Definition at line 1188 of file radeon_drv.h.

#define RADEON_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)

Definition at line 1187 of file radeon_drv.h.

#define RADEON_PRIM_TYPE_LINE (2 << 0)

Definition at line 1180 of file radeon_drv.h.

#define RADEON_PRIM_TYPE_LINE_STRIP (3 << 0)

Definition at line 1181 of file radeon_drv.h.

#define RADEON_PRIM_TYPE_MASK 0xf

Definition at line 1189 of file radeon_drv.h.

#define RADEON_PRIM_TYPE_NONE (0 << 0)

Definition at line 1178 of file radeon_drv.h.

#define RADEON_PRIM_TYPE_POINT (1 << 0)

Definition at line 1179 of file radeon_drv.h.

#define RADEON_PRIM_TYPE_RECT_LIST (8 << 0)

Definition at line 1186 of file radeon_drv.h.

#define RADEON_PRIM_TYPE_TRI_FAN (5 << 0)

Definition at line 1183 of file radeon_drv.h.

#define RADEON_PRIM_TYPE_TRI_LIST (4 << 0)

Definition at line 1182 of file radeon_drv.h.

#define RADEON_PRIM_TYPE_TRI_STRIP (6 << 0)

Definition at line 1184 of file radeon_drv.h.

#define RADEON_PRIM_TYPE_TRI_TYPE2 (7 << 0)

Definition at line 1185 of file radeon_drv.h.

#define RADEON_PRIM_WALK_IND (1 << 4)

Definition at line 1190 of file radeon_drv.h.

#define RADEON_PRIM_WALK_LIST (2 << 4)

Definition at line 1191 of file radeon_drv.h.

#define RADEON_PRIM_WALK_RING (3 << 4)

Definition at line 1192 of file radeon_drv.h.

#define RADEON_PURGE_CACHE ( )

Value:

do {                    \
    if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
        OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));  \
        OUT_RING(RADEON_RB3D_DC_FLUSH | RADEON_RB3D_DC_FREE);   \
    } else {                                                        \
        OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));    \
        OUT_RING(R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);   \
    }                                                               \
} while (0)

Definition at line 1966 of file radeon_drv.h.

#define RADEON_PURGE_EMITED (1 << 1)

Definition at line 183 of file radeon_drv.h.

#define RADEON_PURGE_ZCACHE ( )

Value:

do {                    \
    if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
        OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));    \
        OUT_RING(RADEON_RB3D_ZC_FLUSH | RADEON_RB3D_ZC_FREE);           \
    } else {                                                        \
        OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0));    \
        OUT_RING(R300_ZC_FLUSH | R300_ZC_FREE);             \
    }                                                               \
} while (0)

Definition at line 1986 of file radeon_drv.h.

#define RADEON_RB2D_BUSY (1 << 18)

Definition at line 915 of file radeon_drv.h.

#define RADEON_RB3D_BUSY (1 << 19) /* not used on r300 */

Definition at line 916 of file radeon_drv.h.

#define RADEON_RB3D_CNTL 0x1c3c

Definition at line 825 of file radeon_drv.h.

#define RADEON_RB3D_COLOROFFSET 0x1c40

Definition at line 702 of file radeon_drv.h.

#define RADEON_RB3D_COLORPITCH 0x1c48

Definition at line 703 of file radeon_drv.h.

#define RADEON_RB3D_DC_BUSY (1 << 31)

Definition at line 855 of file radeon_drv.h.

#define RADEON_RB3D_DC_FLUSH (3 << 0)

Definition at line 852 of file radeon_drv.h.

#define RADEON_RB3D_DC_FLUSH_ALL 0xf

Definition at line 854 of file radeon_drv.h.

#define RADEON_RB3D_DC_FREE (3 << 2)

Definition at line 853 of file radeon_drv.h.

#define RADEON_RB3D_DEPTHCLEARVALUE 0x3230

Definition at line 837 of file radeon_drv.h.

#define RADEON_RB3D_DEPTHOFFSET 0x1c24

Definition at line 836 of file radeon_drv.h.

#define RADEON_RB3D_DEPTHPITCH 0x1c28

Definition at line 838 of file radeon_drv.h.

#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c

Definition at line 851 of file radeon_drv.h.

#define RADEON_RB3D_PLANEMASK 0x1d84

Definition at line 839 of file radeon_drv.h.

#define RADEON_RB3D_STENCILREFMASK 0x1d7c

Definition at line 840 of file radeon_drv.h.

#define RADEON_RB3D_ZC_BUSY (1 << 31)

Definition at line 846 of file radeon_drv.h.

#define RADEON_RB3D_ZC_FLUSH (1 << 0)

Definition at line 843 of file radeon_drv.h.

#define RADEON_RB3D_ZC_FLUSH_ALL 0x5

Definition at line 845 of file radeon_drv.h.

#define RADEON_RB3D_ZC_FREE (1 << 2)

Definition at line 844 of file radeon_drv.h.

#define RADEON_RB3D_ZCACHE_CTLSTAT 0x3254

Definition at line 842 of file radeon_drv.h.

#define RADEON_RB3D_ZCACHE_MODE 0x3250

Definition at line 841 of file radeon_drv.h.

#define RADEON_RB3D_ZMASKOFFSET 0x3234

Definition at line 1024 of file radeon_drv.h.

#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c

Definition at line 1025 of file radeon_drv.h.

#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c

Definition at line 1025 of file radeon_drv.h.

#define RADEON_RB_NO_UPDATE (1 << 27)

Definition at line 1038 of file radeon_drv.h.

#define RADEON_RB_RPTR_WR_ENA (1 << 31)

Definition at line 1039 of file radeon_drv.h.

#define RADEON_RBBM_ACTIVE (1 << 31)

Definition at line 925 of file radeon_drv.h.

#define RADEON_RBBM_FIFOCNT_MASK 0x007f

Definition at line 904 of file radeon_drv.h.

#define RADEON_RBBM_GUICNTL 0x172c

Definition at line 790 of file radeon_drv.h.

#define RADEON_RBBM_SOFT_RESET 0x00f0

Definition at line 872 of file radeon_drv.h.

#define RADEON_RBBM_STATUS 0x0e40

Definition at line 900 of file radeon_drv.h.

#define RADEON_RE_BUSY (1 << 21) /* not used on r300 */

Definition at line 918 of file radeon_drv.h.

#define RADEON_RE_LINE_PATTERN 0x1cd0

Definition at line 926 of file radeon_drv.h.

#define RADEON_RE_MISC 0x26c4

Definition at line 927 of file radeon_drv.h.

#define RADEON_RE_STIPPLE_ADDR 0x1cc8

Definition at line 930 of file radeon_drv.h.

#define RADEON_RE_STIPPLE_DATA 0x1ccc

Definition at line 931 of file radeon_drv.h.

#define RADEON_RE_TOP_LEFT 0x26c0

Definition at line 928 of file radeon_drv.h.

#define RADEON_RE_WIDTH_HEIGHT 0x1c44

Definition at line 929 of file radeon_drv.h.

#define RADEON_READ ( reg ) DRM_READ32( dev_priv->mmio, (reg) )

Definition at line 1851 of file radeon_drv.h.

#define RADEON_READ8 ( reg ) DRM_READ8( dev_priv->mmio, (reg) )

Definition at line 1861 of file radeon_drv.h.

#define RADEON_RING_ALIGN 16

Definition at line 2068 of file radeon_drv.h.

#define RADEON_RING_HIGH_MARK 128

Definition at line 1847 of file radeon_drv.h.

#define RADEON_ROP3_P 0x00f00000

Definition at line 722 of file radeon_drv.h.

#define RADEON_ROP3_S 0x00cc0000

Definition at line 721 of file radeon_drv.h.

#define RADEON_ROP_ENABLE (1 << 6)

Definition at line 832 of file radeon_drv.h.

#define RADEON_ROUND_ENABLE (1 << 3)

Definition at line 829 of file radeon_drv.h.

#define RADEON_ROUND_MODE_TRUNC (0 << 28)

Definition at line 956 of file radeon_drv.h.

#define RADEON_ROUND_PREC_8TH_PIX (1 << 30)

Definition at line 957 of file radeon_drv.h.

#define RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT 16

Definition at line 969 of file radeon_drv.h.

#define RADEON_SCALE_DITHER_ENABLE (1 << 4)

Definition at line 830 of file radeon_drv.h.

#define RADEON_SCISSOR_0_ENABLE (1 << 28)

Definition at line 496 of file radeon_drv.h.

#define RADEON_SCISSOR_1_ENABLE (1 << 29)

Definition at line 497 of file radeon_drv.h.

#define RADEON_SCISSOR_2_ENABLE (1 << 30)

Definition at line 498 of file radeon_drv.h.

#define RADEON_SCISSOR_BR_0 0x1cdc

Definition at line 934 of file radeon_drv.h.

#define RADEON_SCISSOR_BR_1 0x1ce4

Definition at line 936 of file radeon_drv.h.

#define RADEON_SCISSOR_BR_2 0x1cec

Definition at line 938 of file radeon_drv.h.

#define RADEON_SCISSOR_ENABLE (1 << 1)

Definition at line 810 of file radeon_drv.h.

#define RADEON_SCISSOR_TL_0 0x1cd8

Definition at line 933 of file radeon_drv.h.

#define RADEON_SCISSOR_TL_1 0x1ce0

Definition at line 935 of file radeon_drv.h.

#define RADEON_SCISSOR_TL_2 0x1ce8

Definition at line 937 of file radeon_drv.h.

#define RADEON_SCRATCH_ADDR 0x0774

Definition at line 739 of file radeon_drv.h.

#define RADEON_SCRATCH_REG0 0x15e0

Definition at line 732 of file radeon_drv.h.

#define RADEON_SCRATCH_REG1 0x15e4

Definition at line 733 of file radeon_drv.h.

#define RADEON_SCRATCH_REG2 0x15e8

Definition at line 734 of file radeon_drv.h.

#define RADEON_SCRATCH_REG3 0x15ec

Definition at line 735 of file radeon_drv.h.

#define RADEON_SCRATCH_REG4 0x15f0

Definition at line 736 of file radeon_drv.h.

#define RADEON_SCRATCH_REG5 0x15f4

Definition at line 737 of file radeon_drv.h.

#define RADEON_SCRATCH_UMSK 0x0770

Definition at line 738 of file radeon_drv.h.

#define RADEON_SCRATCHOFF ( x ) (RADEON_SCRATCH_REG_OFFSET + 4*(x))

Definition at line 741 of file radeon_drv.h.

#define RADEON_SE_CNTL 0x1c4c

Definition at line 940 of file radeon_drv.h.

#define RADEON_SE_CNTL_STATUS 0x2140

Definition at line 958 of file radeon_drv.h.

#define RADEON_SE_COORD_FMT 0x1c50

Definition at line 939 of file radeon_drv.h.

#define RADEON_SE_LINE_WIDTH 0x1db8

Definition at line 959 of file radeon_drv.h.

#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210

Definition at line 962 of file radeon_drv.h.

#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x2254

Definition at line 963 of file radeon_drv.h.

#define RADEON_SE_TCL_SCALAR_DATA_REG 0x220C

Definition at line 970 of file radeon_drv.h.

#define RADEON_SE_TCL_SCALAR_INDX_REG 0x2208

Definition at line 968 of file radeon_drv.h.

#define RADEON_SE_TCL_STATE_FLUSH 0x2284

Definition at line 1314 of file radeon_drv.h.

#define RADEON_SE_TCL_VECTOR_DATA_REG 0x2204

Definition at line 967 of file radeon_drv.h.

#define RADEON_SE_TCL_VECTOR_INDX_REG 0x2200

Definition at line 964 of file radeon_drv.h.

#define RADEON_SE_VPORT_XSCALE 0x1d98

Definition at line 960 of file radeon_drv.h.

#define RADEON_SE_ZBIAS_FACTOR 0x1db0

Definition at line 961 of file radeon_drv.h.

#define RADEON_SOFT_RESET_CP (1 << 0)

Definition at line 873 of file radeon_drv.h.

#define RADEON_SOFT_RESET_E2 (1 << 5)

Definition at line 878 of file radeon_drv.h.

#define RADEON_SOFT_RESET_HDP (1 << 7)

Definition at line 880 of file radeon_drv.h.

#define RADEON_SOFT_RESET_HI (1 << 1)

Definition at line 874 of file radeon_drv.h.

#define RADEON_SOFT_RESET_PP (1 << 4)

Definition at line 877 of file radeon_drv.h.

#define RADEON_SOFT_RESET_RB (1 << 6)

Definition at line 879 of file radeon_drv.h.

#define RADEON_SOFT_RESET_RE (1 << 3)

Definition at line 876 of file radeon_drv.h.

#define RADEON_SOFT_RESET_SE (1 << 2)

Definition at line 875 of file radeon_drv.h.

#define RADEON_SPECULAR_SHADE_FLAT (1 << 12)

Definition at line 949 of file radeon_drv.h.

#define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)

Definition at line 950 of file radeon_drv.h.

#define RADEON_SRC_PITCH_OFFSET 0x1428

Definition at line 724 of file radeon_drv.h.

#define RADEON_SRC_X_Y 0x1590

Definition at line 705 of file radeon_drv.h.

#define RADEON_STENCIL_ENABLE (1 << 7)

Definition at line 833 of file radeon_drv.h.

#define RADEON_STENCIL_S_FAIL_REPLACE (2 << 16)

Definition at line 865 of file radeon_drv.h.

#define RADEON_STENCIL_TEST_ALWAYS (7 << 12)

Definition at line 864 of file radeon_drv.h.

#define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)

Definition at line 867 of file radeon_drv.h.

#define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)

Definition at line 866 of file radeon_drv.h.

#define RADEON_SURF_ADDRESS_FIXED_MASK (0x3ff << 0)

Definition at line 992 of file radeon_drv.h.

#define RADEON_SURF_PITCHSEL_MASK (0x1ff << 0)

Definition at line 984 of file radeon_drv.h.

#define RADEON_SURF_TILE_MODE_16BIT_Z (3 << 16)

Definition at line 989 of file radeon_drv.h.

#define RADEON_SURF_TILE_MODE_32BIT_Z (2 << 16)

Definition at line 988 of file radeon_drv.h.

#define RADEON_SURF_TILE_MODE_MACRO (0 << 16)

Definition at line 986 of file radeon_drv.h.

#define RADEON_SURF_TILE_MODE_MASK (3 << 16)

Definition at line 985 of file radeon_drv.h.

#define RADEON_SURF_TILE_MODE_MICRO (1 << 16)

Definition at line 987 of file radeon_drv.h.

#define RADEON_SURF_TRANSLATION_DIS (1 << 8)

Definition at line 974 of file radeon_drv.h.

#define RADEON_SURFACE0_INFO 0x0b0c

Definition at line 983 of file radeon_drv.h.

#define RADEON_SURFACE0_LOWER_BOUND 0x0b04

Definition at line 990 of file radeon_drv.h.

#define RADEON_SURFACE0_UPPER_BOUND 0x0b08

Definition at line 991 of file radeon_drv.h.

#define RADEON_SURFACE1_INFO 0x0b1c

Definition at line 993 of file radeon_drv.h.

#define RADEON_SURFACE1_LOWER_BOUND 0x0b14

Definition at line 994 of file radeon_drv.h.

#define RADEON_SURFACE1_UPPER_BOUND 0x0b18

Definition at line 995 of file radeon_drv.h.

#define RADEON_SURFACE2_INFO 0x0b2c

Definition at line 996 of file radeon_drv.h.

#define RADEON_SURFACE2_LOWER_BOUND 0x0b24

Definition at line 997 of file radeon_drv.h.

#define RADEON_SURFACE2_UPPER_BOUND 0x0b28

Definition at line 998 of file radeon_drv.h.

#define RADEON_SURFACE3_INFO 0x0b3c

Definition at line 999 of file radeon_drv.h.

#define RADEON_SURFACE3_LOWER_BOUND 0x0b34

Definition at line 1000 of file radeon_drv.h.

#define RADEON_SURFACE3_UPPER_BOUND 0x0b38

Definition at line 1001 of file radeon_drv.h.

#define RADEON_SURFACE4_INFO 0x0b4c

Definition at line 1002 of file radeon_drv.h.

#define RADEON_SURFACE4_LOWER_BOUND 0x0b44

Definition at line 1003 of file radeon_drv.h.

#define RADEON_SURFACE4_UPPER_BOUND 0x0b48

Definition at line 1004 of file radeon_drv.h.

#define RADEON_SURFACE5_INFO 0x0b5c

Definition at line 1005 of file radeon_drv.h.

#define RADEON_SURFACE5_LOWER_BOUND 0x0b54

Definition at line 1006 of file radeon_drv.h.

#define RADEON_SURFACE5_UPPER_BOUND 0x0b58

Definition at line 1007 of file radeon_drv.h.

#define RADEON_SURFACE6_INFO 0x0b6c

Definition at line 1008 of file radeon_drv.h.

#define RADEON_SURFACE6_LOWER_BOUND 0x0b64

Definition at line 1009 of file radeon_drv.h.

#define RADEON_SURFACE6_UPPER_BOUND 0x0b68

Definition at line 1010 of file radeon_drv.h.

#define RADEON_SURFACE7_INFO 0x0b7c

Definition at line 1011 of file radeon_drv.h.

#define RADEON_SURFACE7_LOWER_BOUND 0x0b74

Definition at line 1012 of file radeon_drv.h.

#define RADEON_SURFACE7_UPPER_BOUND 0x0b78

Definition at line 1013 of file radeon_drv.h.

#define RADEON_SURFACE_ACCESS_CLR 0x0bfc

Definition at line 972 of file radeon_drv.h.

#define RADEON_SURFACE_ACCESS_FLAGS 0x0bf8

Definition at line 971 of file radeon_drv.h.

#define RADEON_SURFACE_CNTL 0x0b00

Definition at line 973 of file radeon_drv.h.

#define RADEON_SW_INT_ENABLE (1 << 25)

Definition at line 764 of file radeon_drv.h.

#define RADEON_SW_INT_FIRE (1 << 26)

Definition at line 774 of file radeon_drv.h.

#define RADEON_SW_INT_TEST (1 << 25)

Definition at line 772 of file radeon_drv.h.

#define RADEON_SW_INT_TEST_ACK (1 << 25)

Definition at line 773 of file radeon_drv.h.

#define RADEON_SW_SEMAPHORE 0x013c

Definition at line 1014 of file radeon_drv.h.

#define RADEON_TAM_BUSY (1 << 22) /* not used on r300 */

Definition at line 919 of file radeon_drv.h.

#define RADEON_TDM_BUSY (1 << 23) /* not used on r300 */

Definition at line 920 of file radeon_drv.h.

#define RADEON_TIM_BUSY (1 << 25) /* not used on r300 */

Definition at line 922 of file radeon_drv.h.

#define RADEON_TXFORMAT_AI88 1

Definition at line 1209 of file radeon_drv.h.

#define RADEON_TXFORMAT_ARGB1555 3

Definition at line 1211 of file radeon_drv.h.

#define RADEON_TXFORMAT_ARGB4444 5

Definition at line 1213 of file radeon_drv.h.

#define RADEON_TXFORMAT_ARGB8888 6

Definition at line 1214 of file radeon_drv.h.

#define RADEON_TXFORMAT_DXT1 12

Definition at line 1219 of file radeon_drv.h.

#define RADEON_TXFORMAT_DXT23 14

Definition at line 1220 of file radeon_drv.h.

#define RADEON_TXFORMAT_DXT45 15

Definition at line 1221 of file radeon_drv.h.

#define RADEON_TXFORMAT_I8 0

Definition at line 1208 of file radeon_drv.h.

#define RADEON_TXFORMAT_RGB332 2

Definition at line 1210 of file radeon_drv.h.

#define RADEON_TXFORMAT_RGB565 4

Definition at line 1212 of file radeon_drv.h.

#define RADEON_TXFORMAT_RGBA8888 7

Definition at line 1215 of file radeon_drv.h.

#define RADEON_TXFORMAT_VYUY422 10

Definition at line 1217 of file radeon_drv.h.

#define RADEON_TXFORMAT_Y8 8

Definition at line 1216 of file radeon_drv.h.

#define RADEON_TXFORMAT_YVYU422 11

Definition at line 1218 of file radeon_drv.h.

#define RADEON_VAP_BUSY (1 << 20)

Definition at line 917 of file radeon_drv.h.

#define RADEON_VEC_INDX_DWORD_COUNT_SHIFT 28

Definition at line 966 of file radeon_drv.h.

#define RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT 16

Definition at line 965 of file radeon_drv.h.

#define RADEON_VERBOSE 0

Definition at line 2064 of file radeon_drv.h.

#define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)

Definition at line 953 of file radeon_drv.h.

#define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)

Definition at line 954 of file radeon_drv.h.

#define RADEON_VTX_FMT_R128_MODE (0 << 8)

Definition at line 1196 of file radeon_drv.h.

#define RADEON_VTX_FMT_RADEON_MODE (1 << 8)

Definition at line 1197 of file radeon_drv.h.

#define RADEON_VTX_PIX_CENTER_OGL (1 << 27)

Definition at line 955 of file radeon_drv.h.

#define RADEON_VTX_PKCOLOR_PRESENT (1 << 3)

Definition at line 1176 of file radeon_drv.h.

#define RADEON_VTX_Z_PRESENT (1 << 31)

Definition at line 1175 of file radeon_drv.h.

#define RADEON_WAIT_2D_IDLE (1 << 14)

Definition at line 1018 of file radeon_drv.h.

#define RADEON_WAIT_2D_IDLECLEAN (1 << 16)

Definition at line 1020 of file radeon_drv.h.

#define RADEON_WAIT_3D_IDLE (1 << 15)

Definition at line 1019 of file radeon_drv.h.

#define RADEON_WAIT_3D_IDLECLEAN (1 << 17)

Definition at line 1021 of file radeon_drv.h.

#define RADEON_WAIT_CRTC_PFLIP (1 << 0)

Definition at line 1017 of file radeon_drv.h.

#define RADEON_WAIT_FOR_IDLE 0x00002600

Definition at line 1084 of file radeon_drv.h.

#define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)

Definition at line 1022 of file radeon_drv.h.

#define RADEON_WAIT_UNTIL 0x1720

Definition at line 1016 of file radeon_drv.h.

#define RADEON_WAIT_UNTIL_2D_IDLE ( )

Value:

do {                \
    OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) );         \
    OUT_RING( (RADEON_WAIT_2D_IDLECLEAN |               \
           RADEON_WAIT_HOST_IDLECLEAN) );           \
} while (0)

Definition at line 1932 of file radeon_drv.h.

#define RADEON_WAIT_UNTIL_3D_IDLE ( )

Value:

do {                \
    OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) );         \
    OUT_RING( (RADEON_WAIT_3D_IDLECLEAN |               \
           RADEON_WAIT_HOST_IDLECLEAN) );           \
} while (0)

Definition at line 1938 of file radeon_drv.h.

#define RADEON_WAIT_UNTIL_IDLE ( )

Value:

do {                    \
    OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) );         \
    OUT_RING( (RADEON_WAIT_2D_IDLECLEAN |               \
           RADEON_WAIT_3D_IDLECLEAN |               \
           RADEON_WAIT_HOST_IDLECLEAN) );           \
} while (0)

Definition at line 1944 of file radeon_drv.h.

#define RADEON_WAIT_UNTIL_PAGE_FLIPPED ( )

Value:

do {                \
    OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) );         \
    OUT_RING( RADEON_WAIT_CRTC_PFLIP );             \
} while (0)

Definition at line 1951 of file radeon_drv.h.

#define RADEON_WRITE	(	reg,
		val
	)

Value:

do {                                    \
    if (reg < 0x10000) {                                \
        DRM_WRITE32(dev_priv->mmio, (reg), (val));      \
    } else {                                                        \
        DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, (reg));    \
        DRM_WRITE32(dev_priv->mmio, RADEON_MM_DATA, (val)); \
    }                                                               \
} while (0)

Definition at line 1852 of file radeon_drv.h.

#define RADEON_WRITE8	(	reg,
		val
	)	DRM_WRITE8( dev_priv->mmio, (reg), (val) )

Definition at line 1862 of file radeon_drv.h.

#define RADEON_WRITE_PCIE	(	addr,
		val
	)

Value:

do {                                    \
    RADEON_WRITE8(RADEON_PCIE_INDEX,                \
            ((addr) & 0xff));               \
    RADEON_WRITE(RADEON_PCIE_DATA, (val));          \
} while (0)

Definition at line 1871 of file radeon_drv.h.

#define RADEON_WRITE_PLL	(	addr,
		val
	)

Value:

do {                                    \
    RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX,              \
               ((addr) & 0x1f) | RADEON_PLL_WR_EN );        \
    RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val));            \
} while (0)

Definition at line 1864 of file radeon_drv.h.

#define RADEON_Z_COMPRESSION_ENABLE (1 << 28)

Definition at line 868 of file radeon_drv.h.

#define RADEON_Z_DECOMPRESSION_ENABLE (1 << 31)

Definition at line 871 of file radeon_drv.h.

#define RADEON_Z_ENABLE (1 << 8)

Definition at line 834 of file radeon_drv.h.

#define RADEON_Z_HIERARCHY_ENABLE (1 << 8)

Definition at line 863 of file radeon_drv.h.

#define RADEON_Z_TEST_ALWAYS (7 << 4)

Definition at line 862 of file radeon_drv.h.

#define RADEON_Z_TEST_MASK (7 << 4)

Definition at line 861 of file radeon_drv.h.

#define RADEON_Z_WRITE_ENABLE (1 << 30)

Definition at line 870 of file radeon_drv.h.

#define RADEON_ZBLOCK16 (1 << 15)

Definition at line 835 of file radeon_drv.h.

#define RING_LOCALS int write, _nr, _align_nr; unsigned int mask; u32 *ring;

Definition at line 2066 of file radeon_drv.h.

#define RING_SPACE_TEST_WITH_RETURN ( dev_priv )

Value:

do {                                    \
    if (!(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE)) {       \
		u32 head = GET_RING_HEAD( dev_priv );         \
        if (head == dev_priv->ring.tail)            \
			dev_priv->stats.boxes |= RADEON_BOX_DMA_IDLE;    \
    }                               \
} while (0)

Definition at line 2002 of file radeon_drv.h.

#define RS400_MSI_REARM (1 << 3)

Definition at line 1064 of file radeon_drv.h.

#define RS480_1LEVEL_GART (1 << 30)

Definition at line 580 of file radeon_drv.h.

#define RS480_2LEVEL_GART (0 << 30)

Definition at line 579 of file radeon_drv.h.

#define RS480_AGP_ADDRESS_SPACE_SIZE 0x38

Definition at line 585 of file radeon_drv.h.

#define RS480_AGP_BASE_2 0x0164

Definition at line 678 of file radeon_drv.h.

#define RS480_AGP_MODE_CNTL 0x39

Definition at line 594 of file radeon_drv.h.

#define RS480_AGP_RD_BUF_SIZE (1 << 20)

Definition at line 597 of file radeon_drv.h.

#define RS480_DISABLE_GTW (1 << 1)

Definition at line 569 of file radeon_drv.h.

#define RS480_GART_BASE 0x2c

Definition at line 582 of file radeon_drv.h.

#define RS480_GART_CACHE_CNTRL 0x2e

Definition at line 583 of file radeon_drv.h.

#define RS480_GART_CACHE_INVALIDATE (1 << 0) /* wait for it to clear */

Definition at line 584 of file radeon_drv.h.

#define RS480_GART_EN (1 << 0)

Definition at line 586 of file radeon_drv.h.

#define RS480_GART_FEATURE_ID 0x2b

Definition at line 574 of file radeon_drv.h.

#define RS480_GART_INDEX_REG_EN (1 << 12)

Definition at line 571 of file radeon_drv.h.

#define RS480_GTW_LAC_EN (1 << 25)

Definition at line 578 of file radeon_drv.h.

#define RS480_HANG_EN (1 << 11)

Definition at line 575 of file radeon_drv.h.

#define RS480_K8_FB_LOCATION 0x1e

Definition at line 573 of file radeon_drv.h.

#define RS480_MC_MCLK_CNTL 0x7a

Definition at line 602 of file radeon_drv.h.

#define RS480_MC_MISC_CNTL 0x18

Definition at line 568 of file radeon_drv.h.

#define RS480_MC_MISC_UMA_CNTL 0x5f

Definition at line 601 of file radeon_drv.h.

#define RS480_MC_UMA_DUALCH_CNTL 0x86

Definition at line 603 of file radeon_drv.h.

#define RS480_NB_MC_DATA 0x16c

Definition at line 559 of file radeon_drv.h.

#define RS480_NB_MC_IND_WR_EN (1 << 8)

Definition at line 558 of file radeon_drv.h.

#define RS480_NB_MC_INDEX 0x168

Definition at line 557 of file radeon_drv.h.

#define RS480_NONGART_SNOOP (1 << 19)

Definition at line 596 of file radeon_drv.h.

#define RS480_P2P_ENABLE (1 << 19)

Definition at line 577 of file radeon_drv.h.

#define RS480_PDC_EN (1 << 31)

Definition at line 581 of file radeon_drv.h.

#define RS480_POST_GART_Q_SIZE (1 << 18)

Definition at line 595 of file radeon_drv.h.

#define RS480_REQ_TYPE_SNOOP_DIS (1 << 24)

Definition at line 600 of file radeon_drv.h.

#define RS480_REQ_TYPE_SNOOP_MASK 0x3

Definition at line 599 of file radeon_drv.h.

#define RS480_REQ_TYPE_SNOOP_SHIFT 22

Definition at line 598 of file radeon_drv.h.

#define RS480_TLB_ENABLE (1 << 18)

Definition at line 576 of file radeon_drv.h.

#define RS480_VA_SIZE_128MB (2 << 1)

Definition at line 589 of file radeon_drv.h.

#define RS480_VA_SIZE_1GB (5 << 1)

Definition at line 592 of file radeon_drv.h.

#define RS480_VA_SIZE_256MB (3 << 1)

Definition at line 590 of file radeon_drv.h.

#define RS480_VA_SIZE_2GB (6 << 1)

Definition at line 593 of file radeon_drv.h.

#define RS480_VA_SIZE_32MB (0 << 1)

Definition at line 587 of file radeon_drv.h.

#define RS480_VA_SIZE_512MB (4 << 1)

Definition at line 591 of file radeon_drv.h.

#define RS480_VA_SIZE_64MB (1 << 1)

Definition at line 588 of file radeon_drv.h.

#define RS480_WRITE_MCIND	(	addr,
		val
	)

Value:

do {                                    \
    RADEON_WRITE(RS480_NB_MC_INDEX,             \
            ((addr) & 0xff) | RS480_NB_MC_IND_WR_EN);   \
    RADEON_WRITE(RS480_NB_MC_DATA, (val));          \
    RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);          \
} while (0)

Definition at line 1885 of file radeon_drv.h.

#define RS600_AGP_BASE 0x6

Definition at line 626 of file radeon_drv.h.

#define RS600_AGP_BASE_2 0x7

Definition at line 627 of file radeon_drv.h.

#define RS600_BUS_MASTER_DIS (1 << 14)

Definition at line 510 of file radeon_drv.h.

#define RS600_EFFECTIVE_L1_CACHE_SIZE ( x ) ((x) << 11)

Definition at line 655 of file radeon_drv.h.

#define RS600_EFFECTIVE_L1_QUEUE_SIZE ( x ) ((x) << 15)

Definition at line 657 of file radeon_drv.h.

#define RS600_EFFECTIVE_L2_CACHE_SIZE ( x ) ((x) << 15)

Definition at line 632 of file radeon_drv.h.

#define RS600_EFFECTIVE_L2_QUEUE_SIZE ( x ) ((x) << 21)

Definition at line 633 of file radeon_drv.h.

#define RS600_ENABLE_FRAGMENT_PROCESSING (1 << 14)

Definition at line 656 of file radeon_drv.h.

#define RS600_ENABLE_PAGE_TABLE (1 << 0)

Definition at line 637 of file radeon_drv.h.

#define RS600_ENABLE_PAGE_TABLES (1 << 26)

Definition at line 629 of file radeon_drv.h.

#define RS600_ENABLE_PT (1 << 0)

Definition at line 631 of file radeon_drv.h.

#define RS600_ENABLE_TRANSLATION_MODE_OVERRIDE (1 << 0)

Definition at line 646 of file radeon_drv.h.

#define RS600_INVALIDATE_ALL_L1_TLBS (1 << 28)

Definition at line 634 of file radeon_drv.h.

#define RS600_INVALIDATE_L1_TLB (1 << 20)

Definition at line 658 of file radeon_drv.h.

#define RS600_INVALIDATE_L2_CACHE (1 << 29)

Definition at line 635 of file radeon_drv.h.

#define RS600_MC_ADDR_MASK 0xffff

Definition at line 611 of file radeon_drv.h.

#define RS600_MC_AGP_LOCATION 0x5

Definition at line 625 of file radeon_drv.h.

#define RS600_MC_CNTL1 0x9

Definition at line 628 of file radeon_drv.h.

#define RS600_MC_DATA 0x74

Definition at line 620 of file radeon_drv.h.

#define RS600_MC_FB_LOCATION 0x4

Definition at line 624 of file radeon_drv.h.

#define RS600_MC_IDLE (1 << 1)

Definition at line 623 of file radeon_drv.h.

#define RS600_MC_IND_AIC_RBS (1 << 20)

Definition at line 616 of file radeon_drv.h.

#define RS600_MC_IND_CITF_ARB0 (1 << 21)

Definition at line 617 of file radeon_drv.h.

#define RS600_MC_IND_CITF_ARB1 (1 << 22)

Definition at line 618 of file radeon_drv.h.

#define RS600_MC_IND_SEQ_RBS_0 (1 << 16)

Definition at line 612 of file radeon_drv.h.

#define RS600_MC_IND_SEQ_RBS_1 (1 << 17)

Definition at line 613 of file radeon_drv.h.

#define RS600_MC_IND_SEQ_RBS_2 (1 << 18)

Definition at line 614 of file radeon_drv.h.

#define RS600_MC_IND_SEQ_RBS_3 (1 << 19)

Definition at line 615 of file radeon_drv.h.

#define RS600_MC_IND_WR_EN (1 << 23)

Definition at line 619 of file radeon_drv.h.

#define RS600_MC_INDEX 0x70

Definition at line 610 of file radeon_drv.h.

#define RS600_MC_PT0_CLIENT0_CNTL 0x16c

Definition at line 645 of file radeon_drv.h.

#define RS600_MC_PT0_CNTL 0x100

Definition at line 630 of file radeon_drv.h.

#define RS600_MC_PT0_CONTEXT0_CNTL 0x102

Definition at line 636 of file radeon_drv.h.

#define RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x11c

Definition at line 641 of file radeon_drv.h.

#define RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x12c

Definition at line 642 of file radeon_drv.h.

#define RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x14c

Definition at line 644 of file radeon_drv.h.

#define RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x13c

Definition at line 643 of file radeon_drv.h.

#define RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x114

Definition at line 640 of file radeon_drv.h.

#define RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x112

Definition at line 639 of file radeon_drv.h.

#define RS600_MC_STATUS 0x0

Definition at line 622 of file radeon_drv.h.

#define RS600_MSI_REARM (1 << 20)

Definition at line 511 of file radeon_drv.h.

#define RS600_PAGE_TABLE_TYPE_FLAT (0 << 1)

Definition at line 638 of file radeon_drv.h.

#define RS600_SYSTEM_ACCESS_MODE_IN_SYS (2 << 8)

Definition at line 651 of file radeon_drv.h.

#define RS600_SYSTEM_ACCESS_MODE_MASK (3 << 8)

Definition at line 648 of file radeon_drv.h.

#define RS600_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 8)

Definition at line 652 of file radeon_drv.h.

#define RS600_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 8)

Definition at line 649 of file radeon_drv.h.

#define RS600_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 8)

Definition at line 650 of file radeon_drv.h.

#define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 10)

Definition at line 654 of file radeon_drv.h.

#define RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH (0 << 10)

Definition at line 653 of file radeon_drv.h.

#define RS600_TRANSLATION_MODE_OVERRIDE (1 << 1)

Definition at line 647 of file radeon_drv.h.

#define RS600_WRITE_MCIND	(	addr,
		val
	)

Value:

do {                                    \
    RADEON_WRITE(RS600_MC_INDEX, RS600_MC_IND_WR_EN | RS600_MC_IND_CITF_ARB0 | ((addr) & RS600_MC_ADDR_MASK)); \
    RADEON_WRITE(RS600_MC_DATA, val);                       \
} while (0)

Definition at line 1900 of file radeon_drv.h.

#define RS690_BLOCK_GFX_D3_EN (1 << 14)

Definition at line 572 of file radeon_drv.h.

#define RS690_MC_AGP_BASE 0x102

Definition at line 607 of file radeon_drv.h.

#define RS690_MC_AGP_BASE_2 0x103

Definition at line 608 of file radeon_drv.h.

#define RS690_MC_AGP_LOCATION 0x101

Definition at line 606 of file radeon_drv.h.

#define RS690_MC_DATA 0x7c

Definition at line 565 of file radeon_drv.h.

#define RS690_MC_FB_LOCATION 0x100

Definition at line 605 of file radeon_drv.h.

#define RS690_MC_INDEX 0x78

Definition at line 561 of file radeon_drv.h.

#define RS690_MC_INDEX_MASK 0x1ff

Definition at line 562 of file radeon_drv.h.

#define RS690_MC_INDEX_WR_ACK 0x7f

Definition at line 564 of file radeon_drv.h.

#define RS690_MC_INDEX_WR_EN (1 << 9)

Definition at line 563 of file radeon_drv.h.

#define RS690_WRITE_MCIND	(	addr,
		val
	)

Value:

do {                                \
    RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_EN | ((addr) & RS690_MC_INDEX_MASK));    \
    RADEON_WRITE(RS690_MC_DATA, val);           \
    RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK);    \
} while (0)

Definition at line 1893 of file radeon_drv.h.

#define RV370_BUS_CNTL 0x004c

Definition at line 518 of file radeon_drv.h.

#define RV370_MSI_REARM_EN (1 << 0)

Definition at line 524 of file radeon_drv.h.

#define RV370_PMI_BM_DIS (1 << 5)

Definition at line 519 of file radeon_drv.h.

#define RV370_PMI_INT_DIS (1 << 6)

Definition at line 520 of file radeon_drv.h.

#define RV515_MC_AGP_BASE 0x03

Definition at line 666 of file radeon_drv.h.

#define RV515_MC_AGP_BASE_2 0x04

Definition at line 667 of file radeon_drv.h.

#define RV515_MC_AGP_LOCATION 0x02

Definition at line 665 of file radeon_drv.h.

#define RV515_MC_FB_LOCATION 0x01

Definition at line 664 of file radeon_drv.h.

#define RV530_GB_PIPE_SELECT2 0x4124

Definition at line 683 of file radeon_drv.h.

#define RV700_DB_DEBUG4 0x9b8c

Definition at line 1610 of file radeon_drv.h.

#define RV700_DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6)

Definition at line 1611 of file radeon_drv.h.

#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000

Definition at line 1317 of file radeon_drv.h.

#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001

Definition at line 1316 of file radeon_drv.h.

#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012

Definition at line 1318 of file radeon_drv.h.

#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100

Definition at line 1319 of file radeon_drv.h.

#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200

Definition at line 1320 of file radeon_drv.h.

#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b

Definition at line 1323 of file radeon_drv.h.

#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002

Definition at line 1322 of file radeon_drv.h.

#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001

Definition at line 1321 of file radeon_drv.h.

#define SET_RING_HEAD	(	dev_priv,
		val
	)	radeon_set_ring_head(dev_priv, val)

Definition at line 336 of file radeon_drv.h.

#define VB_AGE_TEST_WITH_RETURN ( dev_priv )

Value:

do {                                \
	struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;    \
	drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;  \
    if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) {     \
        int __ret;                      \
        if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) \
            __ret = r600_do_cp_idle(dev_priv);      \
        else                            \
            __ret = radeon_do_cp_idle(dev_priv);        \
        if ( __ret ) return __ret;              \
        sarea_priv->last_dispatch = 0;              \
        radeon_freelist_reset( dev );               \
    }                               \
} while (0)

Definition at line 2011 of file radeon_drv.h.

Typedef Documentation

typedef struct drm_radeon_buf_priv drm_radeon_buf_priv_t

typedef struct drm_radeon_depth_clear_t drm_radeon_depth_clear_t

typedef struct drm_radeon_freelist drm_radeon_freelist_t

typedef struct drm_radeon_kcmd_buffer drm_radeon_kcmd_buffer_t

typedef struct drm_radeon_private drm_radeon_private_t

typedef struct drm_radeon_ring_buffer drm_radeon_ring_buffer_t

Enumeration Type Documentation

enum radeon_cp_microcode_version

Enumerator:

UCODE_R100
UCODE_R200
UCODE_R300

Definition at line 116 of file radeon_drv.h.

Function Documentation

int r300_do_cp_cmdbuf	(	struct drm_device *	dev,
		struct drm_file *	file_priv,
		drm_radeon_kcmd_buffer_t *	cmdbuf
	)

Parses and validates a user-supplied command buffer and emits appropriate commands on the DMA ring buffer. Called by the ioctl handler function radeon_cp_cmdbuf.

Definition at line 1010 of file r300_cmdbuf.c.

void r300_init_reg_flags ( struct drm_device * dev )

Definition at line 161 of file r300_cmdbuf.c.

void r600_blit_copy	(	struct drm_device *	dev,
		uint64_t	src_gpu_addr,
		uint64_t	dst_gpu_addr,
		int	size_bytes
	)

Definition at line 590 of file r600_blit.c.

void r600_blit_swap	(	struct drm_device *	dev,
		uint64_t	src_gpu_addr,
		uint64_t	dst_gpu_addr,
		int	sx,
		int	sy,
		int	dx,
		int	dy,
		int	w,
		int	h,
		int	src_pitch,
		int	dst_pitch,
		int	cpp
	)

Definition at line 784 of file r600_blit.c.

int r600_cp_dispatch_indirect	(	struct drm_device *	dev,
		struct drm_buf *	buf,
		int	start,
		int	end
	)

Definition at line 2383 of file r600_cp.c.

void r600_cp_dispatch_swap	(	struct drm_device *	dev,
		struct drm_file *	file_priv
	)

Definition at line 2420 of file r600_cp.c.

int r600_cp_dispatch_texture	(	struct drm_device *	dev,
		struct drm_file *	file_priv,
		drm_radeon_texture_t *	tex,
		drm_radeon_tex_image_t *	image
	)

Definition at line 2480 of file r600_cp.c.

int r600_cs_legacy_ioctl	(	struct drm_device *	dev,
		void *	data,
		struct drm_file *	fpriv
	)

Definition at line 2615 of file r600_cp.c.

int r600_do_cleanup_cp ( struct drm_device * dev )

Definition at line 1940 of file r600_cp.c.

int r600_do_cp_idle ( drm_radeon_private_t * dev_priv )

Definition at line 2310 of file r600_cp.c.

void r600_do_cp_reset ( drm_radeon_private_t * dev_priv )

Definition at line 2359 of file r600_cp.c.

void r600_do_cp_start ( drm_radeon_private_t * dev_priv )

Definition at line 2331 of file r600_cp.c.

void r600_do_cp_stop ( drm_radeon_private_t * dev_priv )

Definition at line 2370 of file r600_cp.c.

int r600_do_engine_reset ( struct drm_device * dev )

Definition at line 570 of file r600_cp.c.

int r600_do_init_cp	(	struct drm_device *	dev,
		drm_radeon_init_t *	init,
		struct drm_file *	file_priv
	)

Definition at line 1984 of file r600_cp.c.

int r600_do_resume_cp	(	struct drm_device *	dev,
		struct drm_file *	file_priv
	)

Definition at line 2290 of file r600_cp.c.

void r600_done_blit_copy ( struct drm_device * dev )

Definition at line 569 of file r600_blit.c.

void r600_page_table_cleanup	(	struct drm_device *	dev,
		struct drm_ati_pcigart_info *	gart_info
	)

Definition at line 149 of file r600_cp.c.

int r600_page_table_init ( struct drm_device * dev )

Definition at line 176 of file r600_cp.c.

int r600_prepare_blit_copy	(	struct drm_device *	dev,
		struct drm_file *	file_priv
	)

Definition at line 549 of file r600_blit.c.

void radeon_commit_ring ( drm_radeon_private_t * dev_priv )

Definition at line 2219 of file radeon_cp.c.

long radeon_compat_ioctl	(	struct file *	filp,
		unsigned int	cmd,
		unsigned long	arg
	)

Called whenever a 32-bit process running under a 64-bit kernel performs an ioctl on /dev/dri/card<n>.

Parameters

filp	file pointer.
cmd	command.
arg	user argument.

Returns: zero on success or negative number on failure.

Definition at line 393 of file radeon_ioc32.c.

int radeon_cp_buffers	(	struct drm_device *	dev,
		void *	data,
		struct drm_file *	file_priv
	)

Definition at line 2047 of file radeon_cp.c.

void radeon_cp_discard_buffer	(	struct drm_device *	dev,
		struct drm_master *	master,
		struct drm_buf *	buf
	)

Definition at line 1576 of file radeon_state.c.

void radeon_cp_dispatch_flip	(	struct drm_device *	dev,
		struct drm_master *	master
	)

Definition at line 1449 of file radeon_state.c.

int radeon_cp_idle	(	struct drm_device *	dev,
		void *	data,
		struct drm_file *	file_priv
	)

Definition at line 1860 of file radeon_cp.c.

int radeon_cp_init	(	struct drm_device *	dev,
		void *	data,
		struct drm_file *	file_priv
	)

Definition at line 1663 of file radeon_cp.c.

int radeon_cp_reset	(	struct drm_device *	dev,
		void *	data,
		struct drm_file *	file_priv
	)

Definition at line 1837 of file radeon_cp.c.

int radeon_cp_resume	(	struct drm_device *	dev,
		void *	data,
		struct drm_file *	file_priv
	)

Definition at line 1875 of file radeon_cp.c.

int radeon_cp_start	(	struct drm_device *	dev,
		void *	data,
		struct drm_file *	file_priv
	)

Definition at line 1690 of file radeon_cp.c.

int radeon_cp_stop	(	struct drm_device *	dev,
		void *	data,
		struct drm_file *	file_priv
	)

Definition at line 1718 of file radeon_cp.c.

void radeon_disable_vblank	(	struct drm_device *	dev,
		int	crtc
	)

Definition at line 98 of file radeon_irq.c.

int radeon_do_cp_idle ( drm_radeon_private_t * dev_priv )

Definition at line 596 of file radeon_cp.c.

void radeon_do_release ( struct drm_device * dev )

Definition at line 1767 of file radeon_cp.c.

int radeon_driver_firstopen ( struct drm_device * dev )

Definition at line 2187 of file radeon_cp.c.

irqreturn_t radeon_driver_irq_handler ( DRM_IRQ_ARGS )

Definition at line 182 of file radeon_irq.c.

int radeon_driver_irq_postinstall ( struct drm_device * dev )

Definition at line 349 of file radeon_irq.c.

void radeon_driver_irq_preinstall ( struct drm_device * dev )

Definition at line 331 of file radeon_irq.c.

void radeon_driver_irq_uninstall ( struct drm_device * dev )

Definition at line 367 of file radeon_irq.c.

void radeon_driver_lastclose ( struct drm_device * dev )

Definition at line 3194 of file radeon_state.c.

int radeon_driver_load	(	struct drm_device *	dev,
		unsigned long	flags
	)

Definition at line 2080 of file radeon_cp.c.

int radeon_driver_open	(	struct drm_device *	dev,
		struct drm_file *	file_priv
	)

Definition at line 3200 of file radeon_state.c.

int radeon_driver_postcleanup ( struct drm_device * dev )

void radeon_driver_postclose	(	struct drm_device *	dev,
		struct drm_file *	file_priv
	)

Definition at line 3220 of file radeon_state.c.

void radeon_driver_preclose	(	struct drm_device *	dev,
		struct drm_file *	file_priv
	)

Definition at line 3183 of file radeon_state.c.

int radeon_driver_preinit	(	struct drm_device *	dev,
		unsigned long	flags
	)

int radeon_driver_unload ( struct drm_device * dev )

Definition at line 2205 of file radeon_cp.c.

void radeon_enable_bm ( struct drm_radeon_private * dev_priv )

Definition at line 276 of file radeon_cp.c.

void radeon_enable_interrupt ( struct drm_device * dev )

int radeon_enable_vblank	(	struct drm_device *	dev,
		int	crtc
	)

Definition at line 63 of file radeon_irq.c.

int radeon_engine_reset	(	struct drm_device *	dev,
		void *	data,
		struct drm_file *	file_priv
	)

Definition at line 1886 of file radeon_cp.c.

struct drm_buf* radeon_freelist_get ( struct drm_device * dev )

read

Definition at line 1931 of file radeon_cp.c.

void radeon_freelist_reset ( struct drm_device * dev )

Definition at line 1971 of file radeon_cp.c.

int radeon_fullscreen	(	struct drm_device *	dev,
		void *	data,
		struct drm_file *	file_priv
	)

Definition at line 1905 of file radeon_cp.c.

u32 radeon_get_ring_head ( drm_radeon_private_t * dev_priv )

Definition at line 76 of file radeon_cp.c.

u32 radeon_get_scratch	(	drm_radeon_private_t *	dev_priv,
		int	index
	)

Definition at line 102 of file radeon_cp.c.

u32 radeon_get_vblank_counter	(	struct drm_device *	dev,
		int	crtc
	)

Definition at line 256 of file radeon_irq.c.

int radeon_irq_emit	(	struct drm_device *	dev,
		void *	data,
		struct drm_file *	file_priv
	)

Definition at line 285 of file radeon_irq.c.

void radeon_irq_set_state	(	struct drm_device *	dev,
		u32	mask,
		int	state
	)

Definition at line 37 of file radeon_irq.c.

int radeon_irq_wait	(	struct drm_device *	dev,
		void *	data,
		struct drm_file *	file_priv
	)

Definition at line 313 of file radeon_irq.c.

long radeon_kms_compat_ioctl	(	struct file *	filp,
		unsigned int	cmd,
		unsigned long	arg
	)

Definition at line 413 of file radeon_ioc32.c.

int radeon_master_create	(	struct drm_device *	dev,
		struct drm_master *	master
	)

Definition at line 2138 of file radeon_cp.c.

void radeon_master_destroy	(	struct drm_device *	dev,
		struct drm_master *	master
	)

Definition at line 2164 of file radeon_cp.c.

int radeon_mem_alloc	(	struct drm_device *	dev,
		void *	data,
		struct drm_file *	file_priv
	)

Definition at line 218 of file radeon_mem.c.

int radeon_mem_free	(	struct drm_device *	dev,
		void *	data,
		struct drm_file *	file_priv
	)

Definition at line 253 of file radeon_mem.c.

int radeon_mem_init_heap	(	struct drm_device *	dev,
		void *	data,
		struct drm_file *	file_priv
	)

Definition at line 279 of file radeon_mem.c.

void radeon_mem_release	(	struct drm_file *	file_priv,
		struct mem_block *	heap
	)

Definition at line 159 of file radeon_mem.c.

void radeon_mem_takedown ( struct mem_block ** heap )

Definition at line 187 of file radeon_mem.c.

int radeon_presetup ( struct drm_device * dev )

u32 radeon_read_fb_location ( drm_radeon_private_t * dev_priv )

Definition at line 180 of file radeon_cp.c.

u32 RADEON_READ_MM	(	drm_radeon_private_t *	dev_priv,
		int	addr
	)

Definition at line 119 of file radeon_cp.c.

u32 radeon_read_ring_rptr	(	drm_radeon_private_t *	dev_priv,
		u32	off
	)

Definition at line 61 of file radeon_cp.c.

void radeon_set_ring_head	(	drm_radeon_private_t *	dev_priv,
		u32	val
	)

Definition at line 97 of file radeon_cp.c.

int radeon_vblank_crtc_get ( struct drm_device * dev )

Definition at line 384 of file radeon_irq.c.

int radeon_vblank_crtc_set	(	struct drm_device *	dev,
		int64_t	value
	)

Definition at line 391 of file radeon_irq.c.

int radeon_wait_ring	(	drm_radeon_private_t *	dev_priv,
		int	n
	)

Definition at line 1989 of file radeon_cp.c.

void radeon_write_agp_base	(	drm_radeon_private_t *	dev_priv,
		u64	agp_base
	)

Definition at line 241 of file radeon_cp.c.

void radeon_write_agp_location	(	drm_radeon_private_t *	dev_priv,
		u32	agp_loc
	)

Definition at line 219 of file radeon_cp.c.

void radeon_write_ring_rptr	(	drm_radeon_private_t *	dev_priv,
		u32	off,
		u32	val
	)

Definition at line 88 of file radeon_cp.c.

Variable Documentation

struct drm_ioctl_desc radeon_ioctls[]

Definition at line 3228 of file radeon_state.c.

int radeon_max_ioctl

Definition at line 3259 of file radeon_state.c.

int radeon_no_wb

Definition at line 128 of file radeon_drv.c.

Data Structures

Macros

Typedefs

Enumerations

Functions

Variables

Macro Definition Documentation

Typedef Documentation

Enumeration Type Documentation

Function Documentation

Variable Documentation