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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Macros | |
| #define | KS8695_WAN_OFFSET (0xF0000 + 0x6000) |
| #define | KS8695_WAN_VA (KS8695_IO_VA + KS8695_WAN_OFFSET) |
| #define | KS8695_WAN_PA (KS8695_IO_PA + KS8695_WAN_OFFSET) |
| #define | KS8695_WMDTXC (0x00) /* DMA Transmit Control */ |
| #define | KS8695_WMDRXC (0x04) /* DMA Receive Control */ |
| #define | KS8695_WMDTSC (0x08) /* DMA Transmit Start Command */ |
| #define | KS8695_WMDRSC (0x0c) /* DMA Receive Start Command */ |
| #define | KS8695_WTDLB (0x10) /* Transmit Descriptor List Base Address */ |
| #define | KS8695_WRDLB (0x14) /* Receive Descriptor List Base Address */ |
| #define | KS8695_WMAL (0x18) /* MAC Station Address Low */ |
| #define | KS8695_WMAH (0x1c) /* MAC Station Address High */ |
| #define | KS8695_WMAAL(n) (0x80 + ((n)*8)) /* MAC Additional Station Address (0..15) Low */ |
| #define | KS8695_WMAAH(n) (0x84 + ((n)*8)) /* MAC Additional Station Address (0..15) High */ |
| #define | WMDTXC_WMTRST (1 << 31) /* Soft Reset */ |
| #define | WMDTXC_WMTBS (0x3f << 24) /* Transmit Burst Size */ |
| #define | WMDTXC_WMTUCG (1 << 18) /* Transmit UDP Checksum Generate */ |
| #define | WMDTXC_WMTTCG (1 << 17) /* Transmit TCP Checksum Generate */ |
| #define | WMDTXC_WMTICG (1 << 16) /* Transmit IP Checksum Generate */ |
| #define | WMDTXC_WMTFCE (1 << 9) /* Transmit Flow Control Enable */ |
| #define | WMDTXC_WMTLB (1 << 8) /* Loopback mode */ |
| #define | WMDTXC_WMTEP (1 << 2) /* Transmit Enable Padding */ |
| #define | WMDTXC_WMTAC (1 << 1) /* Transmit Add CRC */ |
| #define | WMDTXC_WMTE (1 << 0) /* TX Enable */ |
| #define | WMDRXC_WMRBS (0x3f << 24) /* Receive Burst Size */ |
| #define | WMDRXC_WMRUCC (1 << 18) /* Receive UDP Checksum check */ |
| #define | WMDRXC_WMRTCG (1 << 17) /* Receive TCP Checksum check */ |
| #define | WMDRXC_WMRICG (1 << 16) /* Receive IP Checksum check */ |
| #define | WMDRXC_WMRFCE (1 << 9) /* Receive Flow Control Enable */ |
| #define | WMDRXC_WMRB (1 << 6) /* Receive Broadcast */ |
| #define | WMDRXC_WMRM (1 << 5) /* Receive Multicast */ |
| #define | WMDRXC_WMRU (1 << 4) /* Receive Unicast */ |
| #define | WMDRXC_WMRERR (1 << 3) /* Receive Error Frame */ |
| #define | WMDRXC_WMRA (1 << 2) /* Receive All */ |
| #define | WMDRXC_WMRE (1 << 0) /* RX Enable */ |
| #define | WMAAH_E (1 << 31) /* Address Enabled */ |
| #define KS8695_WAN_OFFSET (0xF0000 + 0x6000) |
Definition at line 16 of file regs-wan.h.
| #define KS8695_WAN_PA (KS8695_IO_PA + KS8695_WAN_OFFSET) |
Definition at line 18 of file regs-wan.h.
| #define KS8695_WAN_VA (KS8695_IO_VA + KS8695_WAN_OFFSET) |
Definition at line 17 of file regs-wan.h.
| #define KS8695_WMAAH | ( | n | ) | (0x84 + ((n)*8)) /* MAC Additional Station Address (0..15) High */ |
Definition at line 33 of file regs-wan.h.
| #define KS8695_WMAAL | ( | n | ) | (0x80 + ((n)*8)) /* MAC Additional Station Address (0..15) Low */ |
Definition at line 32 of file regs-wan.h.
| #define KS8695_WMAH (0x1c) /* MAC Station Address High */ |
Definition at line 31 of file regs-wan.h.
| #define KS8695_WMAL (0x18) /* MAC Station Address Low */ |
Definition at line 30 of file regs-wan.h.
| #define KS8695_WMDRSC (0x0c) /* DMA Receive Start Command */ |
Definition at line 27 of file regs-wan.h.
| #define KS8695_WMDRXC (0x04) /* DMA Receive Control */ |
Definition at line 25 of file regs-wan.h.
| #define KS8695_WMDTSC (0x08) /* DMA Transmit Start Command */ |
Definition at line 26 of file regs-wan.h.
| #define KS8695_WMDTXC (0x00) /* DMA Transmit Control */ |
Definition at line 24 of file regs-wan.h.
| #define KS8695_WRDLB (0x14) /* Receive Descriptor List Base Address */ |
Definition at line 29 of file regs-wan.h.
| #define KS8695_WTDLB (0x10) /* Transmit Descriptor List Base Address */ |
Definition at line 28 of file regs-wan.h.
Definition at line 62 of file regs-wan.h.
| #define WMDRXC_WMRA (1 << 2) /* Receive All */ |
Definition at line 58 of file regs-wan.h.
| #define WMDRXC_WMRB (1 << 6) /* Receive Broadcast */ |
Definition at line 54 of file regs-wan.h.
| #define WMDRXC_WMRBS (0x3f << 24) /* Receive Burst Size */ |
Definition at line 49 of file regs-wan.h.
| #define WMDRXC_WMRE (1 << 0) /* RX Enable */ |
Definition at line 59 of file regs-wan.h.
| #define WMDRXC_WMRERR (1 << 3) /* Receive Error Frame */ |
Definition at line 57 of file regs-wan.h.
| #define WMDRXC_WMRFCE (1 << 9) /* Receive Flow Control Enable */ |
Definition at line 53 of file regs-wan.h.
Definition at line 52 of file regs-wan.h.
| #define WMDRXC_WMRM (1 << 5) /* Receive Multicast */ |
Definition at line 55 of file regs-wan.h.
Definition at line 51 of file regs-wan.h.
| #define WMDRXC_WMRU (1 << 4) /* Receive Unicast */ |
Definition at line 56 of file regs-wan.h.
Definition at line 50 of file regs-wan.h.
Definition at line 45 of file regs-wan.h.
| #define WMDTXC_WMTBS (0x3f << 24) /* Transmit Burst Size */ |
Definition at line 38 of file regs-wan.h.
| #define WMDTXC_WMTE (1 << 0) /* TX Enable */ |
Definition at line 46 of file regs-wan.h.
| #define WMDTXC_WMTEP (1 << 2) /* Transmit Enable Padding */ |
Definition at line 44 of file regs-wan.h.
Definition at line 42 of file regs-wan.h.
Definition at line 41 of file regs-wan.h.
| #define WMDTXC_WMTLB (1 << 8) /* Loopback mode */ |
Definition at line 43 of file regs-wan.h.
| #define WMDTXC_WMTRST (1 << 31) /* Soft Reset */ |
Definition at line 37 of file regs-wan.h.
Definition at line 40 of file regs-wan.h.
Definition at line 39 of file regs-wan.h.
1.8.2