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Linux Kernel
3.7.1
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All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
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Linux Kernel
3.7.1
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#include <linux/module.h>#include <linux/kernel.h>#include <linux/string.h>#include <linux/timer.h>#include <linux/errno.h>#include <linux/ioport.h>#include <linux/interrupt.h>#include <linux/pci.h>#include <linux/netdevice.h>#include <linux/etherdevice.h>#include <linux/skbuff.h>#include <linux/init.h>#include <linux/mii.h>#include <linux/ethtool.h>#include <linux/crc32.h>#include <linux/delay.h>#include <linux/bitops.h>#include <asm/processor.h>#include <asm/io.h>#include <asm/uaccess.h>#include <asm/byteorder.h>Go to the source code of this file.
Data Structures | |
| struct | chip_info |
| struct | fealnx_desc |
| struct | netdev_private |
Macros | |
| #define | DRV_NAME "fealnx" |
| #define | DRV_VERSION "2.52" |
| #define | DRV_RELDATE "Sep-11-2006" |
| #define | MAX_UNITS 8 /* More are supported, limit only on options */ |
| #define | TX_RING_SIZE 6 |
| #define | RX_RING_SIZE 12 |
| #define | TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct fealnx_desc) |
| #define | RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct fealnx_desc) |
| #define | TX_TIMEOUT (2*HZ) |
| #define | PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */ |
| #define | USE_IO_OPS |
| #define | RUN_AT(x) (jiffies + (x)) |
| #define | MASK_MIIR_MII_READ 0x00000000 |
| #define | MASK_MIIR_MII_WRITE 0x00000008 |
| #define | MASK_MIIR_MII_MDO 0x00000004 |
| #define | MASK_MIIR_MII_MDI 0x00000002 |
| #define | MASK_MIIR_MII_MDC 0x00000001 |
| #define | OP_READ 0x6000 /* ST:01+OP:10+PHYAD+REGAD+TA:Z0 */ |
| #define | OP_WRITE 0x5002 /* ST:01+OP:01+PHYAD+REGAD+TA:10 */ |
| #define | MysonPHYID 0xd0000302 |
| #define | MysonPHYID0 0x0302 |
| #define | StatusRegister 18 |
| #define | SPEED100 0x0400 |
| #define | FULLMODE 0x0800 |
| #define | SeeqPHYID0 0x0016 |
| #define | MIIRegister18 18 |
| #define | SPD_DET_100 0x80 |
| #define | DPLX_DET_FULL 0x40 |
| #define | AhdocPHYID0 0x0022 |
| #define | DiagnosticReg 18 |
| #define | DPLX_FULL 0x0800 |
| #define | Speed_100 0x0400 |
| #define | MarvellPHYID0 0x0141 |
| #define | LevelOnePHYID0 0x0013 |
| #define | MII1000BaseTControlReg 9 |
| #define | MII1000BaseTStatusReg 10 |
| #define | SpecificReg 17 |
| #define | PHYAbletoPerform1000FullDuplex 0x0200 |
| #define | PHYAbletoPerform1000HalfDuplex 0x0100 |
| #define | PHY1000AbilityMask 0x300 |
| #define | SpeedMask 0x0c000 |
| #define | Speed_1000M 0x08000 |
| #define | Speed_100M 0x4000 |
| #define | Speed_10M 0 |
| #define | Full_Duplex 0x2000 |
| #define | LXT1000_100M 0x08000 |
| #define | LXT1000_1000M 0x0c000 |
| #define | LXT1000_Full 0x200 |
| #define | LinkIsUp2 0x00040000 |
| #define | LinkIsUp 0x0004 |
| #define | one_buffer |
| #define | BPT 1022 |
Enumerations | |
| enum | { MIN_REGION_SIZE = 136 } |
| enum | chip_capability_flags { CanHaveMII =1, CanHaveMII =1, HasBrokenTx =2, AlwaysFDX =4, FDXOnNoMII =8, HAS_MII_XCVR, HAS_CHIP_XCVR, MII_PWRDWN =1, TYPE2_INTR =2, NO_MII =4 } |
| enum | phy_type_flags { MysonPHY = 1, AhdocPHY = 2, SeeqPHY = 3, MarvellPHY = 4, Myson981 = 5, LevelOnePHY = 6, OtherPHY = 10 } |
| enum | fealnx_offsets { PAR0 = 0x0, PAR1 = 0x04, MAR0 = 0x08, MAR1 = 0x0C, FAR0 = 0x10, FAR1 = 0x14, TCRRCR = 0x18, BCR = 0x1C, TXPDR = 0x20, RXPDR = 0x24, RXCWP = 0x28, TXLBA = 0x2C, RXLBA = 0x30, ISR = 0x34, IMR = 0x38, FTH = 0x3C, MANAGEMENT = 0x40, TALLY = 0x44, TSR = 0x48, BMCRSR = 0x4c, PHYIDENTIFIER = 0x50, ANARANLPAR = 0x54, ANEROCR = 0x58, BPREMRPSR = 0x5c } |
| enum | intr_status_bits { IntrLinkChange =0xf0000000, IntrStatsMax =0x08000000, IntrAbnormalSummary =0x02000000, IntrGeneralTimer =0x01000000, IntrSoftware =0x800000, IntrRxComplQ1Low =0x400000, IntrTxComplQLow =0x200000, IntrPCI =0x100000, IntrDMAErr =0x080000, IntrTxDataLow =0x040000, IntrRxComplQ2Low =0x020000, IntrRxDescQ1Low =0x010000, IntrNormalSummary =0x8000, IntrTxDone =0x4000, IntrTxDMADone =0x2000, IntrTxEmpty =0x1000, IntrEarlyRxQ2 =0x0800, IntrEarlyRxQ1 =0x0400, IntrRxQ2Done =0x0200, IntrRxQ1Done =0x0100, IntrRxGFPDead =0x80, IntrRxDescQ2Low =0x40, IntrNoTxCsum =0x20, IntrTxBadID =0x10, IntrHiPriTxBadID =0x08, IntrRxGfp =0x04, IntrTxGfp =0x02, IntrPCIPad =0x01, IntrRxDone =IntrRxQ2Done | IntrRxQ1Done, IntrRxEmpty =IntrRxDescQ1Low | IntrRxDescQ2Low, IntrNormalMask =0xff00, IntrAbnormalMask =0x3ff00fe, IntrSummary =0x0001, IntrPCIErr =0x0002, IntrMACCtrl =0x0008, IntrTxDone =0x0004, IntrRxDone =0x0010, IntrRxStart =0x0020, IntrDrvRqst =0x0040, StatsMax =0x0080, LinkChange =0x0100, IntrTxDMADone =0x0200, IntrRxDMADone =0x0400, RFCON = 0x00020000, RFCOFF = 0x00010000, LSCStatus = 0x00008000, ANCStatus = 0x00004000, FBE = 0x00002000, FBEMask = 0x00001800, ParityErr = 0x00000000, TargetErr = 0x00001000, MasterErr = 0x00000800, TUNF = 0x00000400, ROVF = 0x00000200, ETI = 0x00000100, ERI = 0x00000080, CNTOVF = 0x00000040, RBU = 0x00000020, TBU = 0x00000010, TI = 0x00000008, RI = 0x00000004, RxErr = 0x00000002, IntrRxDone =0x01, IntrRxPCIFault =0x02, IntrRxPCIErr =0x04, IntrTxDone =0x100, IntrTxPCIFault =0x200, IntrTxPCIErr =0x400, LinkChange =0x10000, NegotiationChange =0x20000, StatsMax =0x40000, IntrRxDone =0x01, IntrRxInvalid =0x02, IntrRxPCIFault =0x04, IntrRxPCIErr =0x08, IntrTxDone =0x10, IntrTxInvalid =0x20, IntrTxPCIFault =0x40, IntrTxPCIErr =0x80, IntrEarlyRx =0x100, IntrWakeup =0x200, IntrRxDone = 0x0001, IntrTxDone = 0x0002, IntrRxErr = 0x0004, IntrTxError = 0x0008, IntrRxEmpty = 0x0020, IntrPCIErr = 0x0040, IntrStatsMax = 0x0080, IntrRxEarly = 0x0100, IntrTxUnderrun = 0x0210, IntrRxOverflow = 0x0400, IntrRxDropped = 0x0800, IntrRxNoBuf = 0x1000, IntrTxAborted = 0x2000, IntrLinkChange = 0x4000, IntrRxWakeUp = 0x8000, IntrTxDescRace = 0x080000, IntrNormalSummary = IntrRxDone | IntrTxDone, IntrTxErrSummary } |
| enum | rx_mode_bits { AcceptBroadcast =0x04, AcceptAllMulticast =0x02, AcceptAll =0x01, AcceptMulticast =0x10, PerfectFilter =0x40, HashFilter =0x30, PerfectFilterVlan =0x80, MinVLANPrio =0xE000, VlanMode =0x0200, WakeupOnGFP =0x0800, AcceptErr =0x80, RxAcceptBroadcast =0x20, AcceptMulticast =0x10, RxAcceptAllPhys =0x08, AcceptMyPhys =0x02, AcceptAllIPMulti =0x20, AcceptMultiHash =0x10, AcceptAll =0x08, AcceptBroadcast =0x04, AcceptMulticast =0x02, AcceptMyPhys =0x01, CR_W_ENH = 0x02000000, CR_W_FD = 0x00100000, CR_W_PS10 = 0x00080000, CR_W_TXEN = 0x00040000, CR_W_PS1000 = 0x00010000, CR_W_RXMODEMASK = 0x000000e0, CR_W_PROM = 0x00000080, CR_W_AB = 0x00000040, CR_W_AM = 0x00000020, CR_W_ARP = 0x00000008, CR_W_ALP = 0x00000004, CR_W_SEP = 0x00000002, CR_W_RXEN = 0x00000001, CR_R_TXSTOP = 0x04000000, CR_R_FD = 0x00100000, CR_R_PS10 = 0x00080000, CR_R_RXSTOP = 0x00008000, AcceptErr = 0x20, AcceptRunt = 0x10, AcceptBroadcast = 0x08, AcceptMulticast = 0x04, AcceptMyPhys = 0x02, AcceptAllPhys = 0x01 } |
| enum | rx_desc_status_bits { RXOWN = 0x80000000, FLNGMASK = 0x0fff0000, FLNGShift = 16, MARSTATUS = 0x00004000, BARSTATUS = 0x00002000, PHYSTATUS = 0x00001000, RXFSD = 0x00000800, RXLSD = 0x00000400, ErrorSummary = 0x80, RUNT = 0x40, LONG = 0x20, FAE = 0x10, CRC = 0x08, RXER = 0x04 } |
| enum | rx_desc_control_bits { RXIC = 0x00800000, RBSShift = 0 } |
| enum | tx_desc_status_bits { TXOWN = 0x80000000, JABTO = 0x00004000, CSL = 0x00002000, LC = 0x00001000, EC = 0x00000800, UDF = 0x00000400, DFR = 0x00000200, HF = 0x00000100, NCRMask = 0x000000ff, NCRShift = 0 } |
| enum | tx_desc_control_bits { TXIC = 0x80000000, ETIControl = 0x40000000, TXLD = 0x20000000, TXFD = 0x10000000, CRCEnable = 0x08000000, PADEnable = 0x04000000, RetryTxLC = 0x02000000, PKTSMask = 0x3ff800, PKTSShift = 11, TBSMask = 0x000007ff, TBSShift = 0 } |
Functions | |
| MODULE_AUTHOR ("Myson or whoever") | |
| MODULE_DESCRIPTION ("Myson MTD-8xx 100/10M Ethernet PCI Adapter Driver") | |
| MODULE_LICENSE ("GPL") | |
| module_param (max_interrupt_work, int, 0) | |
| module_param (debug, int, 0) | |
| module_param (rx_copybreak, int, 0) | |
| module_param (multicast_filter_limit, int, 0) | |
| module_param_array (options, int, NULL, 0) | |
| module_param_array (full_duplex, int, NULL, 0) | |
| MODULE_PARM_DESC (max_interrupt_work,"fealnx maximum events handled per interrupt") | |
| MODULE_PARM_DESC (debug,"fealnx enable debugging (0-1)") | |
| MODULE_PARM_DESC (rx_copybreak,"fealnx copy breakpoint for copy-only-tiny-frames") | |
| MODULE_PARM_DESC (multicast_filter_limit,"fealnx maximum number of filtered multicast addresses") | |
| MODULE_PARM_DESC (options,"fealnx: Bits 0-3: media type, bit 17: full duplex") | |
| MODULE_PARM_DESC (full_duplex,"fealnx full duplex setting(s) (1)") | |
| MODULE_DEVICE_TABLE (pci, fealnx_pci_tbl) | |
| module_init (fealnx_init) | |
| module_exit (fealnx_exit) | |
Variables | |
| enum { ... } | __attribute__ |
| #define BPT 1022 |
| #define one_buffer |
| #define OP_WRITE 0x5002 /* ST:01+OP:01+PHYAD+REGAD+TA:10 */ |
| #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */ |
| #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct fealnx_desc) |
| #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct fealnx_desc) |
| enum fealnx_offsets |
| enum intr_status_bits |
| enum phy_type_flags |
| enum rx_desc_control_bits |
| enum rx_desc_status_bits |
| enum rx_mode_bits |
| enum tx_desc_control_bits |
| enum tx_desc_status_bits |
| MODULE_AUTHOR | ( | "Myson or whoever" | ) |
| MODULE_DESCRIPTION | ( | "Myson MTD-8xx 100/10M Ethernet PCI Adapter Driver" | ) |
| MODULE_DEVICE_TABLE | ( | pci | , |
| fealnx_pci_tbl | |||
| ) |
| module_exit | ( | fealnx_exit | ) |
| module_init | ( | fealnx_init | ) |
| MODULE_LICENSE | ( | "GPL" | ) |
| module_param | ( | max_interrupt_work | , |
| int | , | ||
| 0 | |||
| ) |
| module_param | ( | rx_copybreak | , |
| int | , | ||
| 0 | |||
| ) |
| module_param | ( | multicast_filter_limit | , |
| int | , | ||
| 0 | |||
| ) |
| MODULE_PARM_DESC | ( | rx_copybreak | , |
| "fealnx copy breakpoint for copy-only-tiny-frames" | |||
| ) |
| MODULE_PARM_DESC | ( | multicast_filter_limit | , |
| "fealnx maximum number of filtered multicast addresses" | |||
| ) |
| enum { ... } __attribute__ |
1.8.2