|
| #define | DRV_NAME "3c59x" |
| |
| #define | TX_RING_SIZE 16 |
| |
| #define | RX_RING_SIZE 32 |
| |
| #define | PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/ |
| |
| #define | tx_interrupt_mitigation 1 |
| |
| #define | vortex_debug debug |
| |
| #define | RUN_AT(x) (jiffies + (x)) |
| |
| #define | VORTEX_TOTAL_SIZE 0x20 |
| |
| #define | BOOMERANG_TOTAL_SIZE 0x40 |
| |
| #define | PFX DRV_NAME ": " |
| |
| #define | EL3_CMD 0x0e |
| |
| #define | EL3_STATUS 0x0e |
| |
| #define | BFEXT(value, offset, bitcount) ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1)) |
| |
| #define | BFINS(lhs, rhs, offset, bitcount) |
| |
| #define | RAM_SIZE(v) BFEXT(v, 0, 3) |
| |
| #define | RAM_WIDTH(v) BFEXT(v, 3, 1) |
| |
| #define | RAM_SPEED(v) BFEXT(v, 4, 2) |
| |
| #define | ROM_SIZE(v) BFEXT(v, 6, 2) |
| |
| #define | RAM_SPLIT(v) BFEXT(v, 16, 2) |
| |
| #define | XCVR(v) BFEXT(v, 20, 4) |
| |
| #define | AUTOSELECT(v) BFEXT(v, 24, 1) |
| |
| #define | LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */ |
| |
| #define | DN_COMPLETE 0x00010000 /* This packet has been downloaded */ |
| |
| #define | DO_ZEROCOPY 0 |
| |
| #define | DEFINE_WINDOW_IO(size) |
| |
| #define | DEVICE_PCI(dev) NULL |
| |
| #define | VORTEX_PCI(vp) ((struct pci_dev *) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL)) |
| |
| #define | DEVICE_EISA(dev) NULL |
| |
| #define | VORTEX_EISA(vp) ((struct eisa_device *) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL)) |
| |
| #define | VORTEX_NUM_STATS 5 |
| |
| #define | MAX_UNITS 8 |
| |
| #define | VORTEX_PM_OPS NULL |
| |
| #define | MDIO_SHIFT_CLK 0x01 |
| |
| #define | MDIO_DIR_WRITE 0x04 |
| |
| #define | MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE) |
| |
| #define | MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE) |
| |
| #define | MDIO_DATA_READ 0x02 |
| |
| #define | MDIO_ENB_IN 0x00 |
| |
|
| enum | pci_flags_bit { PCI_USES_MASTER =4
} |
| |
| enum | {
IS_VORTEX =1,
IS_BOOMERANG =2,
IS_CYCLONE =4,
IS_TORNADO =8,
EEPROM_8BIT =0x10,
HAS_PWR_CTRL =0x20,
HAS_MII =0x40,
HAS_NWAY =0x80,
HAS_CB_FNS =0x100,
INVERT_MII_PWR =0x200,
INVERT_LED_PWR =0x400,
MAX_COLLISION_RESET =0x800,
EEPROM_OFFSET =0x1000,
HAS_HWCKSM =0x2000,
WNO_XCVR_PWR =0x4000,
EXTRA_PREAMBLE =0x8000,
EEPROM_RESET =0x10000
} |
| |
| enum | vortex_chips {
CH_3C590 = 0,
CH_3C592,
CH_3C597,
CH_3C595_1,
CH_3C595_2,
CH_3C595_3,
CH_3C900_1,
CH_3C900_2,
CH_3C900_3,
CH_3C900_4,
CH_3C900_5,
CH_3C900B_FL,
CH_3C905_1,
CH_3C905_2,
CH_3C905B_TX,
CH_3C905B_1,
CH_3C905B_2,
CH_3C905B_FX,
CH_3C905C,
CH_3C9202,
CH_3C980,
CH_3C9805,
CH_3CSOHO100_TX,
CH_3C555,
CH_3C556,
CH_3C556B,
CH_3C575,
CH_3C575_1,
CH_3CCFE575,
CH_3CCFE575CT,
CH_3CCFE656,
CH_3CCFEM656,
CH_3CCFEM656_1,
CH_3C450,
CH_3C920,
CH_3C982A,
CH_3C982B,
CH_905BT4,
CH_920B_EMB_WNM
} |
| |
| enum | vortex_cmd {
TotalReset = 0<<11,
SelectWindow = 1<<11,
StartCoax = 2<<11,
RxDisable = 3<<11,
RxEnable = 4<<11,
RxReset = 5<<11,
UpStall = 6<<11,
UpUnstall = (6<<11)+1,
DownStall = (6<<11)+2,
DownUnstall = (6<<11)+3,
RxDiscard = 8<<11,
TxEnable = 9<<11,
TxDisable = 10<<11,
TxReset = 11<<11,
FakeIntr = 12<<11,
AckIntr = 13<<11,
SetIntrEnb = 14<<11,
SetStatusEnb = 15<<11,
SetRxFilter = 16<<11,
SetRxThreshold = 17<<11,
SetTxThreshold = 18<<11,
SetTxStart = 19<<11,
StartDMAUp = 20<<11,
StartDMADown = (20<<11)+1,
StatsEnable = 21<<11,
StatsDisable = 22<<11,
StopCoax = 23<<11,
SetFilterBit = 25<<11
} |
| |
| enum | RxFilter {
RxStation = 1,
RxMulticast = 2,
RxBroadcast = 4,
RxProm = 8,
RxStation = 1,
RxMulticast = 2,
RxBroadcast = 4,
RxProm = 8,
RxStation = 1,
RxMulticast = 2,
RxBroadcast = 4,
RxProm = 8,
RxStation = 1,
RxMulticast = 2,
RxBroadcast = 4,
RxProm = 8,
RxStation = 1,
RxMulticast = 2,
RxBroadcast = 4,
RxProm = 8
} |
| |
| enum | vortex_status {
IntLatch = 0x0001,
HostError = 0x0002,
TxComplete = 0x0004,
TxAvailable = 0x0008,
RxComplete = 0x0010,
RxEarly = 0x0020,
IntReq = 0x0040,
StatsFull = 0x0080,
DMADone = 1<<8,
DownComplete = 1<<9,
UpComplete = 1<<10,
DMAInProgress = 1<<11,
CmdInProgress = 1<<12
} |
| |
| enum | Window1 {
TX_FIFO = 0x10,
RX_FIFO = 0x10,
RxErrors = 0x14,
RxStatus = 0x18,
Timer = 0x1A,
TxStatus = 0x1B,
TxFree = 0x1C,
TX_FIFO = 0x10,
RX_FIFO = 0x10,
RxErrors = 0x14,
RxStatus = 0x18,
Timer =0x1A,
TxStatus = 0x1B,
TxFree = 0x0C,
RunnerRdCtrl = 0x16,
RunnerWrCtrl = 0x1c,
TX_FIFO = 0x10,
RX_FIFO = 0x10,
RxErrors = 0x14,
RxStatus = 0x18,
Timer =0x1A,
TxStatus = 0x1B,
TxFree = 0x1C
} |
| |
| enum | Window0 {
Wn0IRQ = 0x08,
Wn0EepromCmd = 0x200A,
Wn0EepromData = 0x200C,
Wn0EepromCmd = 10,
Wn0EepromData = 12,
IntrStatus =0x0E,
Wn0EepromCmd = 10,
Wn0EepromData = 12,
IntrStatus =0x0E
} |
| |
| enum | Win0_EEPROM_bits {
EEPROM_Read = 0x80,
EEPROM_WRITE = 0x40,
EEPROM_ERASE = 0xC0,
EEPROM_EWENB = 0x30,
EEPROM_EWDIS = 0x00,
EEPROM_Read = 0x80,
EEPROM_WRITE = 0x40,
EEPROM_ERASE = 0xC0,
EEPROM_EWENB = 0x30,
EEPROM_EWDIS = 0x00
} |
| |
| enum | eeprom_offset {
PhysAddr01 = 0,
PhysAddr23 = 1,
PhysAddr45 = 2,
ModelID = 3,
EtherLink3ID = 7,
PhysAddr01 =0,
PhysAddr23 =1,
PhysAddr45 =2,
ModelID =3,
EtherLink3ID =7,
IFXcvrIO =8,
IRQLine =9,
NodeAddr01 =10,
NodeAddr23 =11,
NodeAddr45 =12,
DriverTune =13,
Checksum =15
} |
| |
| enum | Window2 { Wn2_ResetOptions =12
} |
| |
| enum | Window3 {
Wn3_Config = 0,
Wn3_MAC_Ctrl = 6,
Wn3_Options = 8,
Wn3_Config =0,
Wn3_MAC_Ctrl =6,
Wn3_Options =8,
Wn3_Config =0,
Wn3_MaxPktSize =4,
Wn3_MAC_Ctrl =6,
Wn3_Options =8
} |
| |
| enum | Window4 {
Wn4_NetDiag = 6,
Wn4_Media = 10,
Wn4_FIFODiag = 4,
Wn4_NetDiag = 6,
Wn4_PhysicalMgmt =8,
Wn4_Media = 10,
Wn4_FIFODiag = 4,
Wn4_NetDiag = 6,
Wn4_PhysicalMgmt =8,
Wn4_Media = 10
} |
| |
| enum | Win4_Media_bits {
Media_SQE = 0x0008,
Media_10TP = 0x00C0,
Media_Lnk = 0x0080,
Media_LnkBeat = 0x0800,
Media_SQE = 0x0008,
Media_10TP = 0x00C0,
Media_Lnk = 0x0080,
Media_LnkBeat = 0x0800
} |
| |
| enum | Window7 {
Wn7_MasterAddr = 0,
Wn7_MasterLen = 6,
Wn7_MasterStatus = 12,
Wn7_MasterAddr = 0,
Wn7_VlanEtherType =4,
Wn7_MasterLen = 6,
Wn7_MasterStatus = 12
} |
| |
| enum | MasterCtrl {
PktStatus = 0x400,
DownListPtr = 0x404,
FragAddr = 0x408,
FragLen,
TxFreeThreshold = 0x40f,
UpPktStatus = 0x410,
UpListPtr = 0x418,
PktStatus = 0x20,
DownListPtr = 0x24,
FragAddr = 0x28,
FragLen = 0x2c,
TxFreeThreshold = 0x2f,
UpPktStatus = 0x30,
UpListPtr = 0x38
} |
| |
| enum | rx_desc_status {
RxDComplete = 0x00008000,
RxDError = 0x4000,
RxDComplete =0x00008000,
RxDError =0x4000,
IPChksumErr =1<<25,
TCPChksumErr =1<<26,
UDPChksumErr =1<<27,
IPChksumValid =1<<29,
TCPChksumValid =1<<30,
UDPChksumValid =1<<31
} |
| |
| enum | tx_desc_status {
CRCDisable =0x2000,
TxDComplete =0x8000,
AddIPChksum =0x02000000,
AddTCPChksum =0x04000000,
AddUDPChksum =0x08000000,
TxIntrUploaded =0x80000000
} |
| |
| enum | ChipCaps { CapBusMaster =0x20,
CapPwrMgmt =0x2000
} |
| |
| enum | xcvr_types {
XCVR_10baseT = 0,
XCVR_AUI,
XCVR_10baseTOnly,
XCVR_10base2,
XCVR_100baseTx,
XCVR_100baseFx,
XCVR_MII = 6,
XCVR_Default = 8,
XCVR_10baseT =0,
XCVR_AUI,
XCVR_10baseTOnly,
XCVR_10base2,
XCVR_100baseTx,
XCVR_100baseFx,
XCVR_MII =6,
XCVR_NWAY =8,
XCVR_ExtMII =9,
XCVR_Default =10
} |
| |
|
| | MODULE_AUTHOR ("Donald Becker <[email protected]>") |
| |
| | MODULE_DESCRIPTION ("3Com 3c59x/3c9xx ethernet driver ") |
| |
| | MODULE_LICENSE ("GPL") |
| |
| | MODULE_DEVICE_TABLE (pci, vortex_pci_tbl) |
| |
| | module_param (debug, int, 0) |
| |
| | module_param (global_options, int, 0) |
| |
| | module_param_array (options, int, NULL, 0) |
| |
| | module_param (global_full_duplex, int, 0) |
| |
| | module_param_array (full_duplex, int, NULL, 0) |
| |
| | module_param_array (hw_checksums, int, NULL, 0) |
| |
| | module_param_array (flow_ctrl, int, NULL, 0) |
| |
| | module_param (global_enable_wol, int, 0) |
| |
| | module_param_array (enable_wol, int, NULL, 0) |
| |
| | module_param (rx_copybreak, int, 0) |
| |
| | module_param (max_interrupt_work, int, 0) |
| |
| | module_param (compaq_ioaddr, int, 0) |
| |
| | module_param (compaq_irq, int, 0) |
| |
| | module_param (compaq_device_id, int, 0) |
| |
| | module_param (watchdog, int, 0) |
| |
| | module_param (global_use_mmio, int, 0) |
| |
| | module_param_array (use_mmio, int, NULL, 0) |
| |
| | MODULE_PARM_DESC (debug,"3c59x debug level (0-6)") |
| |
| | MODULE_PARM_DESC (options,"3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex") |
| |
| | MODULE_PARM_DESC (global_options,"3c59x: same as options, but applies to all NICs if options is unset") |
| |
| | MODULE_PARM_DESC (full_duplex,"3c59x full duplex setting(s) (1)") |
| |
| | MODULE_PARM_DESC (global_full_duplex,"3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset") |
| |
| | MODULE_PARM_DESC (hw_checksums,"3c59x Hardware checksum checking by adapter(s) (0-1)") |
| |
| | MODULE_PARM_DESC (flow_ctrl,"3c59x 802.3x flow control usage (PAUSE only) (0-1)") |
| |
| | MODULE_PARM_DESC (enable_wol,"3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)") |
| |
| | MODULE_PARM_DESC (global_enable_wol,"3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset") |
| |
| | MODULE_PARM_DESC (rx_copybreak,"3c59x copy breakpoint for copy-only-tiny-frames") |
| |
| | MODULE_PARM_DESC (max_interrupt_work,"3c59x maximum events handled per interrupt") |
| |
| | MODULE_PARM_DESC (compaq_ioaddr,"3c59x PCI I/O base address (Compaq BIOS problem workaround)") |
| |
| | MODULE_PARM_DESC (compaq_irq,"3c59x PCI IRQ number (Compaq BIOS problem workaround)") |
| |
| | MODULE_PARM_DESC (compaq_device_id,"3c59x PCI device ID (Compaq BIOS problem workaround)") |
| |
| | MODULE_PARM_DESC (watchdog,"3c59x transmit timeout in milliseconds") |
| |
| | MODULE_PARM_DESC (global_use_mmio,"3c59x: same as use_mmio, but applies to all NICs if options is unset") |
| |
| | MODULE_PARM_DESC (use_mmio,"3c59x: use memory-mapped PCI I/O resource (0-1)") |
| |
| | module_init (vortex_init) |
| |
| | module_exit (vortex_cleanup) |
| |
1.8.2