Macros
#define	LAS0_SPARE_00 0x0000 /* - - */

#define	LAS0_SPARE_04 0x0004 /* - - */

#define	LAS0_USER_IO 0x0008 /* Read User Inputs Write User Outputs */

#define	LAS0_SPARE_0C 0x000C /* - - */

#define	LAS0_ADC 0x0010 /* Read FIFO Status Software A/D Start */

#define	LAS0_DAC1 0x0014 /* - Software D/A1 Update */

#define	LAS0_DAC2 0x0018 /* - Software D/A2 Update */

#define	LAS0_SPARE_1C 0x001C /* - - */

#define	LAS0_SPARE_20 0x0020 /* - - */

#define	LAS0_DAC 0x0024 /* - Software Simultaneous D/A1 and D/A2 Update */

#define	LAS0_PACER 0x0028 /* Software Pacer Start Software Pacer Stop */

#define	LAS0_TIMER 0x002C /* Read Timer Counters Status HDIN Software Trigger */

#define	LAS0_IT 0x0030 /* Read Interrupt Status Write Interrupt Enable Mask Register */

#define	LAS0_CLEAR 0x0034 /* Clear ITs set by Clear Mask Set Interrupt Clear Mask */

#define	LAS0_OVERRUN 0x0038 /* Read pending interrupts Clear Overrun Register */

#define	LAS0_SPARE_3C 0x003C /* - - */

#define	LAS0_PCLK 0x0040 /* Pacer Clock value (24bit) Pacer Clock load (24bit) */

#define	LAS0_BCLK 0x0044 /* Burst Clock value (10bit) Burst Clock load (10bit) */

#define	LAS0_ADC_SCNT 0x0048 /* A/D Sample counter value (10bit) A/D Sample counter load (10bit) */

#define	LAS0_DAC1_UCNT 0x004C /* D/A1 Update counter value (10 bit) D/A1 Update counter load (10bit) */

#define	LAS0_DAC2_UCNT 0x0050 /* D/A2 Update counter value (10 bit) D/A2 Update counter load (10bit) */

#define	LAS0_DCNT 0x0054 /* Delay counter value (16 bit) Delay counter load (16bit) */

#define	LAS0_ACNT 0x0058 /* About counter value (16 bit) About counter load (16bit) */

#define	LAS0_DAC_CLK 0x005C /* DAC clock value (16bit) DAC clock load (16bit) */

#define	LAS0_UTC0 0x0060 /* 8254 TC Counter 0 User TC 0 value Load count in TC Counter 0 */

#define	LAS0_UTC1 0x0064 /* 8254 TC Counter 1 User TC 1 value Load count in TC Counter 1 */

#define	LAS0_UTC2 0x0068 /* 8254 TC Counter 2 User TC 2 value Load count in TC Counter 2 */

#define	LAS0_UTC_CTRL 0x006C /* 8254 TC Control Word Program counter mode for TC */

#define	LAS0_DIO0 0x0070 /* Digital I/O Port 0 Read Port Digital I/O Port 0 Write Port */

#define	LAS0_DIO1 0x0074 /* Digital I/O Port 1 Read Port Digital I/O Port 1 Write Port */

#define	LAS0_DIO0_CTRL 0x0078 /* Clear digital IRQ status flag/read Clear digital chip/program Port 0 */

#define	LAS0_DIO_STATUS 0x007C /* Read Digital I/O Status word Program digital control register & */

#define	LAS0_BOARD_RESET 0x0100 /* Board reset */

#define	LAS0_DMA0_SRC 0x0104 /* DMA 0 Sources select */

#define	LAS0_DMA1_SRC 0x0108 /* DMA 1 Sources select */

#define	LAS0_ADC_CONVERSION 0x010C /* A/D Conversion Signal select */

#define	LAS0_BURST_START 0x0110 /* Burst Clock Start Trigger select */

#define	LAS0_PACER_START 0x0114 /* Pacer Clock Start Trigger select */

#define	LAS0_PACER_STOP 0x0118 /* Pacer Clock Stop Trigger select */

#define	LAS0_ACNT_STOP_ENABLE 0x011C /* About Counter Stop Enable */

#define	LAS0_PACER_REPEAT 0x0120 /* Pacer Start Trigger Mode select */

#define	LAS0_DIN_START 0x0124 /* High Speed Digital Input Sampling Signal select */

#define	LAS0_DIN_FIFO_CLEAR 0x0128 /* Digital Input FIFO Clear */

#define	LAS0_ADC_FIFO_CLEAR 0x012C /* A/D FIFO Clear */

#define	LAS0_CGT_WRITE 0x0130 /* Channel Gain Table Write */

#define	LAS0_CGL_WRITE 0x0134 /* Channel Gain Latch Write */

#define	LAS0_CG_DATA 0x0138 /* Digital Table Write */

#define	LAS0_CGT_ENABLE 0x013C /* Channel Gain Table Enable */

#define	LAS0_CG_ENABLE 0x0140 /* Digital Table Enable */

#define	LAS0_CGT_PAUSE 0x0144 /* Table Pause Enable */

#define	LAS0_CGT_RESET 0x0148 /* Reset Channel Gain Table */

#define	LAS0_CGT_CLEAR 0x014C /* Clear Channel Gain Table */

#define	LAS0_DAC1_CTRL 0x0150 /* D/A1 output type/range */

#define	LAS0_DAC1_SRC 0x0154 /* D/A1 update source */

#define	LAS0_DAC1_CYCLE 0x0158 /* D/A1 cycle mode */

#define	LAS0_DAC1_RESET 0x015C /* D/A1 FIFO reset */

#define	LAS0_DAC1_FIFO_CLEAR 0x0160 /* D/A1 FIFO clear */

#define	LAS0_DAC2_CTRL 0x0164 /* D/A2 output type/range */

#define	LAS0_DAC2_SRC 0x0168 /* D/A2 update source */

#define	LAS0_DAC2_CYCLE 0x016C /* D/A2 cycle mode */

#define	LAS0_DAC2_RESET 0x0170 /* D/A2 FIFO reset */

#define	LAS0_DAC2_FIFO_CLEAR 0x0174 /* D/A2 FIFO clear */

#define	LAS0_ADC_SCNT_SRC 0x0178 /* A/D Sample Counter Source select */

#define	LAS0_PACER_SELECT 0x0180 /* Pacer Clock select */

#define	LAS0_SBUS0_SRC 0x0184 /* SyncBus 0 Source select */

#define	LAS0_SBUS0_ENABLE 0x0188 /* SyncBus 0 enable */

#define	LAS0_SBUS1_SRC 0x018C /* SyncBus 1 Source select */

#define	LAS0_SBUS1_ENABLE 0x0190 /* SyncBus 1 enable */

#define	LAS0_SBUS2_SRC 0x0198 /* SyncBus 2 Source select */

#define	LAS0_SBUS2_ENABLE 0x019C /* SyncBus 2 enable */

#define	LAS0_ETRG_POLARITY 0x01A4 /* External Trigger polarity select */

#define	LAS0_EINT_POLARITY 0x01A8 /* External Interrupt polarity select */

#define	LAS0_UTC0_CLOCK 0x01AC /* UTC0 Clock select */

#define	LAS0_UTC0_GATE 0x01B0 /* UTC0 Gate select */

#define	LAS0_UTC1_CLOCK 0x01B4 /* UTC1 Clock select */

#define	LAS0_UTC1_GATE 0x01B8 /* UTC1 Gate select */

#define	LAS0_UTC2_CLOCK 0x01BC /* UTC2 Clock select */

#define	LAS0_UTC2_GATE 0x01C0 /* UTC2 Gate select */

#define	LAS0_UOUT0_SELECT 0x01C4 /* User Output 0 source select */

#define	LAS0_UOUT1_SELECT 0x01C8 /* User Output 1 source select */

#define	LAS0_DMA0_RESET 0x01CC /* DMA0 Request state machine reset */

#define	LAS0_DMA1_RESET 0x01D0 /* DMA1 Request state machine reset */

#define	LAS1_ADC_FIFO 0x0000 /* Read A/D FIFO (16bit) - */

#define	LAS1_HDIO_FIFO 0x0004 /* Read High Speed Digital Input FIFO (16bit) - */

#define	LAS1_DAC1_FIFO 0x0008 /* - Write D/A1 FIFO (16bit) */

#define	LAS1_DAC2_FIFO 0x000C /* - Write D/A2 FIFO (16bit) */

#define	LCFG_ITCSR 0x0068 /* INTCSR, Interrupt Control/Status Register */

#define	LCFG_DMAMODE0 0x0080 /* DMA Channel 0 Mode Register */

#define	LCFG_DMAPADR0 0x0084 /* DMA Channel 0 PCI Address Register */

#define	LCFG_DMALADR0 0x0088 /* DMA Channel 0 Local Address Reg */

#define	LCFG_DMASIZ0 0x008C /* DMA Channel 0 Transfer Size (Bytes) Register */

#define	LCFG_DMADPR0 0x0090 /* DMA Channel 0 Descriptor Pointer Register */

#define	LCFG_DMAMODE1 0x0094 /* DMA Channel 1 Mode Register */

#define	LCFG_DMAPADR1 0x0098 /* DMA Channel 1 PCI Address Register */

#define	LCFG_DMALADR1 0x009C /* DMA Channel 1 Local Address Register */

#define	LCFG_DMASIZ1 0x00A0 /* DMA Channel 1 Transfer Size (Bytes) Register */

#define	LCFG_DMADPR1 0x00A4 /* DMA Channel 1 Descriptor Pointer Register */

#define	LCFG_DMACSR0 0x00A8 /* DMA Channel 0 Command/Status Register */

#define	LCFG_DMACSR1 0x00A9 /* DMA Channel 0 Command/Status Register */

#define	LCFG_DMAARB 0x00AC /* DMA Arbitration Register */

#define	LCFG_DMATHR 0x00B0 /* DMA Threshold Register */

#define	FS_DAC1_NOT_EMPTY 0x0001 /* D0 - DAC1 FIFO not empty */

#define	FS_DAC1_HEMPTY 0x0002 /* D1 - DAC1 FIFO half empty */

#define	FS_DAC1_NOT_FULL 0x0004 /* D2 - DAC1 FIFO not full */

#define	FS_DAC2_NOT_EMPTY 0x0010 /* D4 - DAC2 FIFO not empty */

#define	FS_DAC2_HEMPTY 0x0020 /* D5 - DAC2 FIFO half empty */

#define	FS_DAC2_NOT_FULL 0x0040 /* D6 - DAC2 FIFO not full */

#define	FS_ADC_NOT_EMPTY 0x0100 /* D8 - ADC FIFO not empty */

#define	FS_ADC_HEMPTY 0x0200 /* D9 - ADC FIFO half empty */

#define	FS_ADC_NOT_FULL 0x0400 /* D10 - ADC FIFO not full */

#define	FS_DIN_NOT_EMPTY 0x1000 /* D12 - DIN FIFO not empty */

#define	FS_DIN_HEMPTY 0x2000 /* D13 - DIN FIFO half empty */

#define	FS_DIN_NOT_FULL 0x4000 /* D14 - DIN FIFO not full */

#define	TS_PCLK_GATE 0x0001

#define	TS_BCLK_GATE 0x0002

#define	TS_DCNT_GATE 0x0004

#define	TS_ACNT_GATE 0x0008

#define	TS_PCLK_RUN 0x0010

#define	POL_POSITIVE 0x0 /* positive edge */

#define	POL_NEGATIVE 0x1 /* negative edge */

#define	UOUT_ADC 0x0 /* A/D Conversion Signal */

#define	UOUT_DAC1 0x1 /* D/A1 Update */

#define	UOUT_DAC2 0x2 /* D/A2 Update */

#define	UOUT_SOFTWARE 0x3 /* Software Programmable */

#define	PCLK_INTERNAL 1 /* Internal Pacer Clock */

#define	PCLK_EXTERNAL 0 /* External Pacer Clock */

#define	ADC_SCNT_CGT_RESET 0x0 /* needs restart with StartPacer */

#define	ADC_SCNT_FIFO_WRITE 0x1

#define	ADC_START_SOFTWARE 0x0 /* Software A/D Start */

#define	ADC_START_PCLK 0x1 /* Pacer Clock (Ext. Int. see Func.509) */

#define	ADC_START_BCLK 0x2 /* Burst Clock */

#define	ADC_START_DIGITAL_IT 0x3 /* Digital Interrupt */

#define	ADC_START_DAC1_MARKER1 0x4 /* D/A 1 Data Marker 1 */

#define	ADC_START_DAC2_MARKER1 0x5 /* D/A 2 Data Marker 1 */

#define	ADC_START_SBUS0 0x6 /* SyncBus 0 */

#define	ADC_START_SBUS1 0x7 /* SyncBus 1 */

#define	ADC_START_SBUS2 0x8 /* SyncBus 2 */

#define	BCLK_START_SOFTWARE 0x0 /* Software A/D Start (StartBurst) */

#define	BCLK_START_PCLK 0x1 /* Pacer Clock */

#define	BCLK_START_ETRIG 0x2 /* External Trigger */

#define	BCLK_START_DIGITAL_IT 0x3 /* Digital Interrupt */

#define	BCLK_START_SBUS0 0x4 /* SyncBus 0 */

#define	BCLK_START_SBUS1 0x5 /* SyncBus 1 */

#define	BCLK_START_SBUS2 0x6 /* SyncBus 2 */

#define	PCLK_START_SOFTWARE 0x0 /* Software Pacer Start (StartPacer) */

#define	PCLK_START_ETRIG 0x1 /* External trigger */

#define	PCLK_START_DIGITAL_IT 0x2 /* Digital interrupt */

#define	PCLK_START_UTC2 0x3 /* User TC 2 out */

#define	PCLK_START_SBUS0 0x4 /* SyncBus 0 */

#define	PCLK_START_SBUS1 0x5 /* SyncBus 1 */

#define	PCLK_START_SBUS2 0x6 /* SyncBus 2 */

#define	PCLK_START_D_SOFTWARE 0x8 /* Delayed Software Pacer Start */

#define	PCLK_START_D_ETRIG 0x9 /* Delayed external trigger */

#define	PCLK_START_D_DIGITAL_IT 0xA /* Delayed digital interrupt */

#define	PCLK_START_D_UTC2 0xB /* Delayed User TC 2 out */

#define	PCLK_START_D_SBUS0 0xC /* Delayed SyncBus 0 */

#define	PCLK_START_D_SBUS1 0xD /* Delayed SyncBus 1 */

#define	PCLK_START_D_SBUS2 0xE /* Delayed SyncBus 2 */

#define	PCLK_START_ETRIG_GATED 0xF /* External Trigger Gated controlled mode */

#define	PCLK_STOP_SOFTWARE 0x0 /* Software Pacer Stop (StopPacer) */

#define	PCLK_STOP_ETRIG 0x1 /* External Trigger */

#define	PCLK_STOP_DIGITAL_IT 0x2 /* Digital Interrupt */

#define	PCLK_STOP_ACNT 0x3 /* About Counter */

#define	PCLK_STOP_UTC2 0x4 /* User TC2 out */

#define	PCLK_STOP_SBUS0 0x5 /* SyncBus 0 */

#define	PCLK_STOP_SBUS1 0x6 /* SyncBus 1 */

#define	PCLK_STOP_SBUS2 0x7 /* SyncBus 2 */

#define	PCLK_STOP_A_SOFTWARE 0x8 /* About Software Pacer Stop */

#define	PCLK_STOP_A_ETRIG 0x9 /* About External Trigger */

#define	PCLK_STOP_A_DIGITAL_IT 0xA /* About Digital Interrupt */

#define	PCLK_STOP_A_UTC2 0xC /* About User TC2 out */

#define	PCLK_STOP_A_SBUS0 0xD /* About SyncBus 0 */

#define	PCLK_STOP_A_SBUS1 0xE /* About SyncBus 1 */

#define	PCLK_STOP_A_SBUS2 0xF /* About SyncBus 2 */

#define	ACNT_STOP 0x0 /* stop enable */

#define	ACNT_NO_STOP 0x1 /* stop disabled */

#define	DAC_START_SOFTWARE 0x0 /* Software Update */

#define	DAC_START_CGT 0x1 /* CGT controlled Update */

#define	DAC_START_DAC_CLK 0x2 /* D/A Clock */

#define	DAC_START_EPCLK 0x3 /* External Pacer Clock */

#define	DAC_START_SBUS0 0x4 /* SyncBus 0 */

#define	DAC_START_SBUS1 0x5 /* SyncBus 1 */

#define	DAC_START_SBUS2 0x6 /* SyncBus 2 */

#define	DAC_CYCLE_SINGLE 0x0 /* not cycle */

#define	DAC_CYCLE_MULTI 0x1 /* cycle */

#define	M8254_EVENT_COUNTER 0 /* Event Counter */

#define	M8254_HW_ONE_SHOT 1 /* Hardware-Retriggerable One-Shot */

#define	M8254_RATE_GENERATOR 2 /* Rate Generator */

#define	M8254_SQUARE_WAVE 3 /* Square Wave Mode */

#define	M8254_SW_STROBE 4 /* Software Triggered Strobe */

#define	M8254_HW_STROBE 5 /* Hardware Triggered Strobe (Retriggerable) */

#define	CUTC0_8MHZ 0x0 /* 8MHz */

#define	CUTC0_EXT_TC_CLOCK1 0x1 /* Ext. TC Clock 1 */

#define	CUTC0_EXT_TC_CLOCK2 0x2 /* Ext. TC Clock 2 */

#define	CUTC0_EXT_PCLK 0x3 /* Ext. Pacer Clock */

#define	CUTC1_8MHZ 0x0 /* 8MHz */

#define	CUTC1_EXT_TC_CLOCK1 0x1 /* Ext. TC Clock 1 */

#define	CUTC1_EXT_TC_CLOCK2 0x2 /* Ext. TC Clock 2 */

#define	CUTC1_EXT_PCLK 0x3 /* Ext. Pacer Clock */

#define	CUTC1_UTC0_OUT 0x4 /* User Timer/Counter 0 out */

#define	CUTC1_DIN_SIGNAL 0x5 /* High-Speed Digital Input Sampling signal */

#define	CUTC2_8MHZ 0x0 /* 8MHz */

#define	CUTC2_EXT_TC_CLOCK1 0x1 /* Ext. TC Clock 1 */

#define	CUTC2_EXT_TC_CLOCK2 0x2 /* Ext. TC Clock 2 */

#define	CUTC2_EXT_PCLK 0x3 /* Ext. Pacer Clock */

#define	CUTC2_UTC1_OUT 0x4 /* User Timer/Counter 1 out */

#define	GUTC0_NOT_GATED 0x0 /* Not gated */

#define	GUTC0_GATED 0x1 /* Gated */

#define	GUTC0_EXT_TC_GATE1 0x2 /* Ext. TC Gate 1 */

#define	GUTC0_EXT_TC_GATE2 0x3 /* Ext. TC Gate 2 */

#define	GUTC1_NOT_GATED 0x0 /* Not gated */

#define	GUTC1_GATED 0x1 /* Gated */

#define	GUTC1_EXT_TC_GATE1 0x2 /* Ext. TC Gate 1 */

#define	GUTC1_EXT_TC_GATE2 0x3 /* Ext. TC Gate 2 */

#define	GUTC1_UTC0_OUT 0x4 /* User Timer/Counter 0 out */

#define	GUTC2_NOT_GATED 0x0 /* Not gated */

#define	GUTC2_GATED 0x1 /* Gated */

#define	GUTC2_EXT_TC_GATE1 0x2 /* Ext. TC Gate 1 */

#define	GUTC2_EXT_TC_GATE2 0x3 /* Ext. TC Gate 2 */

#define	GUTC2_UTC1_OUT 0x4 /* User Timer/Counter 1 out */

#define	IRQM_ADC_FIFO_WRITE 0x0001 /* ADC FIFO Write */

#define	IRQM_CGT_RESET 0x0002 /* Reset CGT */

#define	IRQM_CGT_PAUSE 0x0008 /* Pause CGT */

#define	IRQM_ADC_ABOUT_CNT 0x0010 /* About Counter out */

#define	IRQM_ADC_DELAY_CNT 0x0020 /* Delay Counter out */

#define	IRQM_ADC_SAMPLE_CNT 0x0040 /* ADC Sample Counter */

#define	IRQM_DAC1_UCNT 0x0080 /* DAC1 Update Counter */

#define	IRQM_DAC2_UCNT 0x0100 /* DAC2 Update Counter */

#define	IRQM_UTC1 0x0200 /* User TC1 out */

#define	IRQM_UTC1_INV 0x0400 /* User TC1 out, inverted */

#define	IRQM_UTC2 0x0800 /* User TC2 out */

#define	IRQM_DIGITAL_IT 0x1000 /* Digital Interrupt */

#define	IRQM_EXTERNAL_IT 0x2000 /* External Interrupt */

#define	IRQM_ETRIG_RISING 0x4000 /* External Trigger rising-edge */

#define	IRQM_ETRIG_FALLING 0x8000 /* External Trigger falling-edge */

#define	DMAS_DISABLED 0x0 /* DMA Disabled */

#define	DMAS_ADC_SCNT 0x1 /* ADC Sample Counter */

#define	DMAS_DAC1_UCNT 0x2 /* D/A1 Update Counter */

#define	DMAS_DAC2_UCNT 0x3 /* D/A2 Update Counter */

#define	DMAS_UTC1 0x4 /* User TC1 out */

#define	DMAS_ADFIFO_HALF_FULL 0x8 /* A/D FIFO half full */

#define	DMAS_DAC1_FIFO_HALF_EMPTY 0x9 /* D/A1 FIFO half empty */

#define	DMAS_DAC2_FIFO_HALF_EMPTY 0xA /* D/A2 FIFO half empty */

#define	DMALADDR_ADC 0x40000000 /* A/D FIFO */

#define	DMALADDR_HDIN 0x40000004 /* High Speed Digital Input FIFO */

#define	DMALADDR_DAC1 0x40000008 /* D/A1 FIFO */

#define	DMALADDR_DAC2 0x4000000C /* D/A2 FIFO */

#define	DIO_MODE_EVENT 0 /* Event Mode */

#define	DIO_MODE_MATCH 1 /* Match Mode */

#define	DTBL_DISABLE 0 /* Enable Digital Table */

#define	DTBL_ENABLE 1 /* Disable Digital Table */

#define	HDIN_SOFTWARE 0x0 /* Software Trigger */

#define	HDIN_ADC 0x1 /* A/D Conversion Signal */

#define	HDIN_UTC0 0x2 /* User TC out 0 */

#define	HDIN_UTC1 0x3 /* User TC out 1 */

#define	HDIN_UTC2 0x4 /* User TC out 2 */

#define	HDIN_EPCLK 0x5 /* External Pacer Clock */

#define	HDIN_ETRG 0x6 /* External Trigger */

#define	CSC_LATCH 0 /* Channel Gain Latch mode */

#define	CSC_CGT 1 /* Channel Gain Table mode */

#define	CGT_PAUSE_DISABLE 0 /* Channel Gain Table Pause Disable */

#define	CGT_PAUSE_ENABLE 1 /* Channel Gain Table Pause Enable */

#define	AOUT_UNIP5 0 /* 0..+5 Volt */

#define	AOUT_UNIP10 1 /* 0..+10 Volt */

#define	AOUT_BIP5 2 /* -5..+5 Volt */

#define	AOUT_BIP10 3 /* -10..+10 Volt */

#define	GAIN1 0

#define	GAIN2 1

#define	GAIN4 2

#define	GAIN8 3

#define	GAIN16 4

#define	GAIN32 5

#define	GAIN64 6

#define	GAIN128 7

#define	AIN_BIP5 0 /* -5..+5 Volt */

#define	AIN_BIP10 1 /* -10..+10 Volt */

#define	AIN_UNIP10 2 /* 0..+10 Volt */

#define	NRSE_AGND 0 /* AGND referenced SE input */

#define	NRSE_AINS 1 /* AIN SENSE referenced SE input */

#define	GND_SE 0 /* Single-Ended */

#define	GND_DIFF 1 /* Differential */

Macro Definition Documentation

#define ACNT_NO_STOP 0x1 /* stop disabled */

Definition at line 262 of file rtd520.h.

#define ACNT_STOP 0x0 /* stop enable */

Definition at line 261 of file rtd520.h.

#define ADC_SCNT_CGT_RESET 0x0 /* needs restart with StartPacer */

Definition at line 203 of file rtd520.h.

#define ADC_SCNT_FIFO_WRITE 0x1

Definition at line 204 of file rtd520.h.

#define ADC_START_BCLK 0x2 /* Burst Clock */

Definition at line 209 of file rtd520.h.

#define ADC_START_DAC1_MARKER1 0x4 /* D/A 1 Data Marker 1 */

Definition at line 211 of file rtd520.h.

#define ADC_START_DAC2_MARKER1 0x5 /* D/A 2 Data Marker 1 */

Definition at line 212 of file rtd520.h.

#define ADC_START_DIGITAL_IT 0x3 /* Digital Interrupt */

Definition at line 210 of file rtd520.h.

#define ADC_START_PCLK 0x1 /* Pacer Clock (Ext. Int. see Func.509) */

Definition at line 208 of file rtd520.h.

#define ADC_START_SBUS0 0x6 /* SyncBus 0 */

Definition at line 213 of file rtd520.h.

#define ADC_START_SBUS1 0x7 /* SyncBus 1 */

Definition at line 214 of file rtd520.h.

#define ADC_START_SBUS2 0x8 /* SyncBus 2 */

Definition at line 215 of file rtd520.h.

#define ADC_START_SOFTWARE 0x0 /* Software A/D Start */

Definition at line 207 of file rtd520.h.

#define AIN_BIP10 1 /* -10..+10 Volt */

Definition at line 403 of file rtd520.h.

#define AIN_BIP5 0 /* -5..+5 Volt */

Definition at line 402 of file rtd520.h.

#define AIN_UNIP10 2 /* 0..+10 Volt */

Definition at line 404 of file rtd520.h.

#define AOUT_BIP10 3 /* -10..+10 Volt */

Definition at line 388 of file rtd520.h.

#define AOUT_BIP5 2 /* -5..+5 Volt */

Definition at line 387 of file rtd520.h.

#define AOUT_UNIP10 1 /* 0..+10 Volt */

Definition at line 386 of file rtd520.h.

#define AOUT_UNIP5 0 /* 0..+5 Volt */

Definition at line 385 of file rtd520.h.

#define BCLK_START_DIGITAL_IT 0x3 /* Digital Interrupt */

Definition at line 221 of file rtd520.h.

#define BCLK_START_ETRIG 0x2 /* External Trigger */

Definition at line 220 of file rtd520.h.

#define BCLK_START_PCLK 0x1 /* Pacer Clock */

Definition at line 219 of file rtd520.h.

#define BCLK_START_SBUS0 0x4 /* SyncBus 0 */

Definition at line 222 of file rtd520.h.

#define BCLK_START_SBUS1 0x5 /* SyncBus 1 */

Definition at line 223 of file rtd520.h.

#define BCLK_START_SBUS2 0x6 /* SyncBus 2 */

Definition at line 224 of file rtd520.h.

#define BCLK_START_SOFTWARE 0x0 /* Software A/D Start (StartBurst) */

Definition at line 218 of file rtd520.h.

#define CGT_PAUSE_DISABLE 0 /* Channel Gain Table Pause Disable */

Definition at line 381 of file rtd520.h.

#define CGT_PAUSE_ENABLE 1 /* Channel Gain Table Pause Enable */

Definition at line 382 of file rtd520.h.

#define CSC_CGT 1 /* Channel Gain Table mode */

Definition at line 378 of file rtd520.h.

#define CSC_LATCH 0 /* Channel Gain Latch mode */

Definition at line 377 of file rtd520.h.

#define CUTC0_8MHZ 0x0 /* 8MHz */

Definition at line 286 of file rtd520.h.

#define CUTC0_EXT_PCLK 0x3 /* Ext. Pacer Clock */

Definition at line 289 of file rtd520.h.

#define CUTC0_EXT_TC_CLOCK1 0x1 /* Ext. TC Clock 1 */

Definition at line 287 of file rtd520.h.

#define CUTC0_EXT_TC_CLOCK2 0x2 /* Ext. TC Clock 2 */

Definition at line 288 of file rtd520.h.

#define CUTC1_8MHZ 0x0 /* 8MHz */

Definition at line 292 of file rtd520.h.

#define CUTC1_DIN_SIGNAL 0x5 /* High-Speed Digital Input Sampling signal */

Definition at line 297 of file rtd520.h.

#define CUTC1_EXT_PCLK 0x3 /* Ext. Pacer Clock */

Definition at line 295 of file rtd520.h.

#define CUTC1_EXT_TC_CLOCK1 0x1 /* Ext. TC Clock 1 */

Definition at line 293 of file rtd520.h.

#define CUTC1_EXT_TC_CLOCK2 0x2 /* Ext. TC Clock 2 */

Definition at line 294 of file rtd520.h.

#define CUTC1_UTC0_OUT 0x4 /* User Timer/Counter 0 out */

Definition at line 296 of file rtd520.h.

#define CUTC2_8MHZ 0x0 /* 8MHz */

Definition at line 300 of file rtd520.h.

#define CUTC2_EXT_PCLK 0x3 /* Ext. Pacer Clock */

Definition at line 303 of file rtd520.h.

#define CUTC2_EXT_TC_CLOCK1 0x1 /* Ext. TC Clock 1 */

Definition at line 301 of file rtd520.h.

#define CUTC2_EXT_TC_CLOCK2 0x2 /* Ext. TC Clock 2 */

Definition at line 302 of file rtd520.h.

#define CUTC2_UTC1_OUT 0x4 /* User Timer/Counter 1 out */

Definition at line 304 of file rtd520.h.

#define DAC_CYCLE_MULTI 0x1 /* cycle */

Definition at line 275 of file rtd520.h.

#define DAC_CYCLE_SINGLE 0x0 /* not cycle */

Definition at line 274 of file rtd520.h.

#define DAC_START_CGT 0x1 /* CGT controlled Update */

Definition at line 266 of file rtd520.h.

#define DAC_START_DAC_CLK 0x2 /* D/A Clock */

Definition at line 267 of file rtd520.h.

#define DAC_START_EPCLK 0x3 /* External Pacer Clock */

Definition at line 268 of file rtd520.h.

#define DAC_START_SBUS0 0x4 /* SyncBus 0 */

Definition at line 269 of file rtd520.h.

#define DAC_START_SBUS1 0x5 /* SyncBus 1 */

Definition at line 270 of file rtd520.h.

#define DAC_START_SBUS2 0x6 /* SyncBus 2 */

Definition at line 271 of file rtd520.h.

#define DAC_START_SOFTWARE 0x0 /* Software Update */

Definition at line 265 of file rtd520.h.

#define DIO_MODE_EVENT 0 /* Event Mode */

Definition at line 360 of file rtd520.h.

#define DIO_MODE_MATCH 1 /* Match Mode */

Definition at line 361 of file rtd520.h.

#define DMALADDR_ADC 0x40000000 /* A/D FIFO */

Definition at line 354 of file rtd520.h.

#define DMALADDR_DAC1 0x40000008 /* D/A1 FIFO */

Definition at line 356 of file rtd520.h.

#define DMALADDR_DAC2 0x4000000C /* D/A2 FIFO */

Definition at line 357 of file rtd520.h.

#define DMALADDR_HDIN 0x40000004 /* High Speed Digital Input FIFO */

Definition at line 355 of file rtd520.h.

#define DMAS_ADC_SCNT 0x1 /* ADC Sample Counter */

Definition at line 345 of file rtd520.h.

#define DMAS_ADFIFO_HALF_FULL 0x8 /* A/D FIFO half full */

Definition at line 349 of file rtd520.h.

#define DMAS_DAC1_FIFO_HALF_EMPTY 0x9 /* D/A1 FIFO half empty */

Definition at line 350 of file rtd520.h.

#define DMAS_DAC1_UCNT 0x2 /* D/A1 Update Counter */

Definition at line 346 of file rtd520.h.

#define DMAS_DAC2_FIFO_HALF_EMPTY 0xA /* D/A2 FIFO half empty */

Definition at line 351 of file rtd520.h.

#define DMAS_DAC2_UCNT 0x3 /* D/A2 Update Counter */

Definition at line 347 of file rtd520.h.

#define DMAS_DISABLED 0x0 /* DMA Disabled */

Definition at line 344 of file rtd520.h.

#define DMAS_UTC1 0x4 /* User TC1 out */

Definition at line 348 of file rtd520.h.

#define DTBL_DISABLE 0 /* Enable Digital Table */

Definition at line 364 of file rtd520.h.

#define DTBL_ENABLE 1 /* Disable Digital Table */

Definition at line 365 of file rtd520.h.

#define FS_ADC_HEMPTY 0x0200 /* D9 - ADC FIFO half empty */

Definition at line 166 of file rtd520.h.

#define FS_ADC_NOT_EMPTY 0x0100 /* D8 - ADC FIFO not empty */

Definition at line 165 of file rtd520.h.

#define FS_ADC_NOT_FULL 0x0400 /* D10 - ADC FIFO not full */

Definition at line 167 of file rtd520.h.

#define FS_DAC1_HEMPTY 0x0002 /* D1 - DAC1 FIFO half empty */

Definition at line 160 of file rtd520.h.

#define FS_DAC1_NOT_EMPTY 0x0001 /* D0 - DAC1 FIFO not empty */

Definition at line 159 of file rtd520.h.

#define FS_DAC1_NOT_FULL 0x0004 /* D2 - DAC1 FIFO not full */

Definition at line 161 of file rtd520.h.

#define FS_DAC2_HEMPTY 0x0020 /* D5 - DAC2 FIFO half empty */

Definition at line 163 of file rtd520.h.

#define FS_DAC2_NOT_EMPTY 0x0010 /* D4 - DAC2 FIFO not empty */

Definition at line 162 of file rtd520.h.

#define FS_DAC2_NOT_FULL 0x0040 /* D6 - DAC2 FIFO not full */

Definition at line 164 of file rtd520.h.

#define FS_DIN_HEMPTY 0x2000 /* D13 - DIN FIFO half empty */

Definition at line 169 of file rtd520.h.

#define FS_DIN_NOT_EMPTY 0x1000 /* D12 - DIN FIFO not empty */

Definition at line 168 of file rtd520.h.

#define FS_DIN_NOT_FULL 0x4000 /* D14 - DIN FIFO not full */

Definition at line 170 of file rtd520.h.

#define GAIN1 0

Definition at line 392 of file rtd520.h.

#define GAIN128 7

Definition at line 399 of file rtd520.h.

#define GAIN16 4

Definition at line 396 of file rtd520.h.

#define GAIN2 1

Definition at line 393 of file rtd520.h.

#define GAIN32 5

Definition at line 397 of file rtd520.h.

#define GAIN4 2

Definition at line 394 of file rtd520.h.

#define GAIN64 6

Definition at line 398 of file rtd520.h.

#define GAIN8 3

Definition at line 395 of file rtd520.h.

#define GND_DIFF 1 /* Differential */

Definition at line 412 of file rtd520.h.

#define GND_SE 0 /* Single-Ended */

Definition at line 411 of file rtd520.h.

#define GUTC0_EXT_TC_GATE1 0x2 /* Ext. TC Gate 1 */

Definition at line 309 of file rtd520.h.

#define GUTC0_EXT_TC_GATE2 0x3 /* Ext. TC Gate 2 */

Definition at line 310 of file rtd520.h.

#define GUTC0_GATED 0x1 /* Gated */

Definition at line 308 of file rtd520.h.

#define GUTC0_NOT_GATED 0x0 /* Not gated */

Definition at line 307 of file rtd520.h.

#define GUTC1_EXT_TC_GATE1 0x2 /* Ext. TC Gate 1 */

Definition at line 315 of file rtd520.h.

#define GUTC1_EXT_TC_GATE2 0x3 /* Ext. TC Gate 2 */

Definition at line 316 of file rtd520.h.

#define GUTC1_GATED 0x1 /* Gated */

Definition at line 314 of file rtd520.h.

#define GUTC1_NOT_GATED 0x0 /* Not gated */

Definition at line 313 of file rtd520.h.

#define GUTC1_UTC0_OUT 0x4 /* User Timer/Counter 0 out */

Definition at line 317 of file rtd520.h.

#define GUTC2_EXT_TC_GATE1 0x2 /* Ext. TC Gate 1 */

Definition at line 322 of file rtd520.h.

#define GUTC2_EXT_TC_GATE2 0x3 /* Ext. TC Gate 2 */

Definition at line 323 of file rtd520.h.

#define GUTC2_GATED 0x1 /* Gated */

Definition at line 321 of file rtd520.h.

#define GUTC2_NOT_GATED 0x0 /* Not gated */

Definition at line 320 of file rtd520.h.

#define GUTC2_UTC1_OUT 0x4 /* User Timer/Counter 1 out */

Definition at line 324 of file rtd520.h.

#define HDIN_ADC 0x1 /* A/D Conversion Signal */

Definition at line 369 of file rtd520.h.

#define HDIN_EPCLK 0x5 /* External Pacer Clock */

Definition at line 373 of file rtd520.h.

#define HDIN_ETRG 0x6 /* External Trigger */

Definition at line 374 of file rtd520.h.

#define HDIN_SOFTWARE 0x0 /* Software Trigger */

Definition at line 368 of file rtd520.h.

#define HDIN_UTC0 0x2 /* User TC out 0 */

Definition at line 370 of file rtd520.h.

#define HDIN_UTC1 0x3 /* User TC out 1 */

Definition at line 371 of file rtd520.h.

#define HDIN_UTC2 0x4 /* User TC out 2 */

Definition at line 372 of file rtd520.h.

#define IRQM_ADC_ABOUT_CNT 0x0010 /* About Counter out */

Definition at line 330 of file rtd520.h.

#define IRQM_ADC_DELAY_CNT 0x0020 /* Delay Counter out */

Definition at line 331 of file rtd520.h.

#define IRQM_ADC_FIFO_WRITE 0x0001 /* ADC FIFO Write */

Definition at line 327 of file rtd520.h.

#define IRQM_ADC_SAMPLE_CNT 0x0040 /* ADC Sample Counter */

Definition at line 332 of file rtd520.h.

#define IRQM_CGT_PAUSE 0x0008 /* Pause CGT */

Definition at line 329 of file rtd520.h.

#define IRQM_CGT_RESET 0x0002 /* Reset CGT */

Definition at line 328 of file rtd520.h.

#define IRQM_DAC1_UCNT 0x0080 /* DAC1 Update Counter */

Definition at line 333 of file rtd520.h.

#define IRQM_DAC2_UCNT 0x0100 /* DAC2 Update Counter */

Definition at line 334 of file rtd520.h.

#define IRQM_DIGITAL_IT 0x1000 /* Digital Interrupt */

Definition at line 338 of file rtd520.h.

#define IRQM_ETRIG_FALLING 0x8000 /* External Trigger falling-edge */

Definition at line 341 of file rtd520.h.

#define IRQM_ETRIG_RISING 0x4000 /* External Trigger rising-edge */

Definition at line 340 of file rtd520.h.

#define IRQM_EXTERNAL_IT 0x2000 /* External Interrupt */

Definition at line 339 of file rtd520.h.

#define IRQM_UTC1 0x0200 /* User TC1 out */

Definition at line 335 of file rtd520.h.

#define IRQM_UTC1_INV 0x0400 /* User TC1 out, inverted */

Definition at line 336 of file rtd520.h.

#define IRQM_UTC2 0x0800 /* User TC2 out */

Definition at line 337 of file rtd520.h.

#define LAS0_ACNT 0x0058 /* About counter value (16 bit) About counter load (16bit) */

Definition at line 59 of file rtd520.h.

#define LAS0_ACNT_STOP_ENABLE 0x011C /* About Counter Stop Enable */

Definition at line 81 of file rtd520.h.

#define LAS0_ADC 0x0010 /* Read FIFO Status Software A/D Start */

Definition at line 36 of file rtd520.h.

#define LAS0_ADC_CONVERSION 0x010C /* A/D Conversion Signal select */

Definition at line 77 of file rtd520.h.

#define LAS0_ADC_FIFO_CLEAR 0x012C /* A/D FIFO Clear */

Definition at line 85 of file rtd520.h.

#define LAS0_ADC_SCNT 0x0048 /* A/D Sample counter value (10bit) A/D Sample counter load (10bit) */

Definition at line 55 of file rtd520.h.

#define LAS0_ADC_SCNT_SRC 0x0178 /* A/D Sample Counter Source select */

Definition at line 104 of file rtd520.h.

#define LAS0_BCLK 0x0044 /* Burst Clock value (10bit) Burst Clock load (10bit) */

Definition at line 54 of file rtd520.h.

#define LAS0_BOARD_RESET 0x0100 /* Board reset */

Definition at line 74 of file rtd520.h.

#define LAS0_BURST_START 0x0110 /* Burst Clock Start Trigger select */

Definition at line 78 of file rtd520.h.

#define LAS0_CG_DATA 0x0138 /* Digital Table Write */

Definition at line 88 of file rtd520.h.

#define LAS0_CG_ENABLE 0x0140 /* Digital Table Enable */

Definition at line 90 of file rtd520.h.

#define LAS0_CGL_WRITE 0x0134 /* Channel Gain Latch Write */

Definition at line 87 of file rtd520.h.

#define LAS0_CGT_CLEAR 0x014C /* Clear Channel Gain Table */

Definition at line 93 of file rtd520.h.

#define LAS0_CGT_ENABLE 0x013C /* Channel Gain Table Enable */

Definition at line 89 of file rtd520.h.

#define LAS0_CGT_PAUSE 0x0144 /* Table Pause Enable */

Definition at line 91 of file rtd520.h.

#define LAS0_CGT_RESET 0x0148 /* Reset Channel Gain Table */

Definition at line 92 of file rtd520.h.

#define LAS0_CGT_WRITE 0x0130 /* Channel Gain Table Write */

Definition at line 86 of file rtd520.h.

#define LAS0_CLEAR 0x0034 /* Clear ITs set by Clear Mask Set Interrupt Clear Mask */

Definition at line 45 of file rtd520.h.

#define LAS0_DAC 0x0024 /* - Software Simultaneous D/A1 and D/A2 Update */

Definition at line 41 of file rtd520.h.

#define LAS0_DAC1 0x0014 /* - Software D/A1 Update */

Definition at line 37 of file rtd520.h.

#define LAS0_DAC1_CTRL 0x0150 /* D/A1 output type/range */

Definition at line 94 of file rtd520.h.

#define LAS0_DAC1_CYCLE 0x0158 /* D/A1 cycle mode */

Definition at line 96 of file rtd520.h.

#define LAS0_DAC1_FIFO_CLEAR 0x0160 /* D/A1 FIFO clear */

Definition at line 98 of file rtd520.h.

#define LAS0_DAC1_RESET 0x015C /* D/A1 FIFO reset */

Definition at line 97 of file rtd520.h.

#define LAS0_DAC1_SRC 0x0154 /* D/A1 update source */

Definition at line 95 of file rtd520.h.

#define LAS0_DAC1_UCNT 0x004C /* D/A1 Update counter value (10 bit) D/A1 Update counter load (10bit) */

Definition at line 56 of file rtd520.h.

#define LAS0_DAC2 0x0018 /* - Software D/A2 Update */

Definition at line 38 of file rtd520.h.

#define LAS0_DAC2_CTRL 0x0164 /* D/A2 output type/range */

Definition at line 99 of file rtd520.h.

#define LAS0_DAC2_CYCLE 0x016C /* D/A2 cycle mode */

Definition at line 101 of file rtd520.h.

#define LAS0_DAC2_FIFO_CLEAR 0x0174 /* D/A2 FIFO clear */

Definition at line 103 of file rtd520.h.

#define LAS0_DAC2_RESET 0x0170 /* D/A2 FIFO reset */

Definition at line 102 of file rtd520.h.

#define LAS0_DAC2_SRC 0x0168 /* D/A2 update source */

Definition at line 100 of file rtd520.h.

#define LAS0_DAC2_UCNT 0x0050 /* D/A2 Update counter value (10 bit) D/A2 Update counter load (10bit) */

Definition at line 57 of file rtd520.h.

#define LAS0_DAC_CLK 0x005C /* DAC clock value (16bit) DAC clock load (16bit) */

Definition at line 60 of file rtd520.h.

#define LAS0_DCNT 0x0054 /* Delay counter value (16 bit) Delay counter load (16bit) */

Definition at line 58 of file rtd520.h.

#define LAS0_DIN_FIFO_CLEAR 0x0128 /* Digital Input FIFO Clear */

Definition at line 84 of file rtd520.h.

#define LAS0_DIN_START 0x0124 /* High Speed Digital Input Sampling Signal select */

Definition at line 83 of file rtd520.h.

#define LAS0_DIO0 0x0070 /* Digital I/O Port 0 Read Port Digital I/O Port 0 Write Port */

Definition at line 65 of file rtd520.h.

#define LAS0_DIO0_CTRL 0x0078 /* Clear digital IRQ status flag/read Clear digital chip/program Port 0 */

Definition at line 67 of file rtd520.h.

#define LAS0_DIO1 0x0074 /* Digital I/O Port 1 Read Port Digital I/O Port 1 Write Port */

Definition at line 66 of file rtd520.h.

#define LAS0_DIO_STATUS 0x007C /* Read Digital I/O Status word Program digital control register & */

Definition at line 68 of file rtd520.h.

#define LAS0_DMA0_RESET 0x01CC /* DMA0 Request state machine reset */

Definition at line 122 of file rtd520.h.

#define LAS0_DMA0_SRC 0x0104 /* DMA 0 Sources select */

Definition at line 75 of file rtd520.h.

#define LAS0_DMA1_RESET 0x01D0 /* DMA1 Request state machine reset */

Definition at line 123 of file rtd520.h.

#define LAS0_DMA1_SRC 0x0108 /* DMA 1 Sources select */

Definition at line 76 of file rtd520.h.

#define LAS0_EINT_POLARITY 0x01A8 /* External Interrupt polarity select */

Definition at line 113 of file rtd520.h.

#define LAS0_ETRG_POLARITY 0x01A4 /* External Trigger polarity select */

Definition at line 112 of file rtd520.h.

#define LAS0_IT 0x0030 /* Read Interrupt Status Write Interrupt Enable Mask Register */

Definition at line 44 of file rtd520.h.

#define LAS0_OVERRUN 0x0038 /* Read pending interrupts Clear Overrun Register */

Definition at line 46 of file rtd520.h.

#define LAS0_PACER 0x0028 /* Software Pacer Start Software Pacer Stop */

Definition at line 42 of file rtd520.h.

#define LAS0_PACER_REPEAT 0x0120 /* Pacer Start Trigger Mode select */

Definition at line 82 of file rtd520.h.

#define LAS0_PACER_SELECT 0x0180 /* Pacer Clock select */

Definition at line 105 of file rtd520.h.

#define LAS0_PACER_START 0x0114 /* Pacer Clock Start Trigger select */

Definition at line 79 of file rtd520.h.

#define LAS0_PACER_STOP 0x0118 /* Pacer Clock Stop Trigger select */

Definition at line 80 of file rtd520.h.

#define LAS0_PCLK 0x0040 /* Pacer Clock value (24bit) Pacer Clock load (24bit) */

Definition at line 53 of file rtd520.h.

#define LAS0_SBUS0_ENABLE 0x0188 /* SyncBus 0 enable */

Definition at line 107 of file rtd520.h.

#define LAS0_SBUS0_SRC 0x0184 /* SyncBus 0 Source select */

Definition at line 106 of file rtd520.h.

#define LAS0_SBUS1_ENABLE 0x0190 /* SyncBus 1 enable */

Definition at line 109 of file rtd520.h.

#define LAS0_SBUS1_SRC 0x018C /* SyncBus 1 Source select */

Definition at line 108 of file rtd520.h.

#define LAS0_SBUS2_ENABLE 0x019C /* SyncBus 2 enable */

Definition at line 111 of file rtd520.h.

#define LAS0_SBUS2_SRC 0x0198 /* SyncBus 2 Source select */

Definition at line 110 of file rtd520.h.

#define LAS0_SPARE_00 0x0000 /* - - */

Definition at line 32 of file rtd520.h.

#define LAS0_SPARE_04 0x0004 /* - - */

Definition at line 33 of file rtd520.h.

#define LAS0_SPARE_0C 0x000C /* - - */

Definition at line 35 of file rtd520.h.

#define LAS0_SPARE_1C 0x001C /* - - */

Definition at line 39 of file rtd520.h.

#define LAS0_SPARE_20 0x0020 /* - - */

Definition at line 40 of file rtd520.h.

#define LAS0_SPARE_3C 0x003C /* - - */

Definition at line 47 of file rtd520.h.

#define LAS0_TIMER 0x002C /* Read Timer Counters Status HDIN Software Trigger */

Definition at line 43 of file rtd520.h.

#define LAS0_UOUT0_SELECT 0x01C4 /* User Output 0 source select */

Definition at line 120 of file rtd520.h.

#define LAS0_UOUT1_SELECT 0x01C8 /* User Output 1 source select */

Definition at line 121 of file rtd520.h.

#define LAS0_USER_IO 0x0008 /* Read User Inputs Write User Outputs */

Definition at line 34 of file rtd520.h.

#define LAS0_UTC0 0x0060 /* 8254 TC Counter 0 User TC 0 value Load count in TC Counter 0 */

Definition at line 61 of file rtd520.h.

#define LAS0_UTC0_CLOCK 0x01AC /* UTC0 Clock select */

Definition at line 114 of file rtd520.h.

#define LAS0_UTC0_GATE 0x01B0 /* UTC0 Gate select */

Definition at line 115 of file rtd520.h.

#define LAS0_UTC1 0x0064 /* 8254 TC Counter 1 User TC 1 value Load count in TC Counter 1 */

Definition at line 62 of file rtd520.h.

#define LAS0_UTC1_CLOCK 0x01B4 /* UTC1 Clock select */

Definition at line 116 of file rtd520.h.

#define LAS0_UTC1_GATE 0x01B8 /* UTC1 Gate select */

Definition at line 117 of file rtd520.h.

#define LAS0_UTC2 0x0068 /* 8254 TC Counter 2 User TC 2 value Load count in TC Counter 2 */

Definition at line 63 of file rtd520.h.

#define LAS0_UTC2_CLOCK 0x01BC /* UTC2 Clock select */

Definition at line 118 of file rtd520.h.

#define LAS0_UTC2_GATE 0x01C0 /* UTC2 Gate select */

Definition at line 119 of file rtd520.h.

#define LAS0_UTC_CTRL 0x006C /* 8254 TC Control Word Program counter mode for TC */

Definition at line 64 of file rtd520.h.

#define LAS1_ADC_FIFO 0x0000 /* Read A/D FIFO (16bit) - */

Definition at line 129 of file rtd520.h.

#define LAS1_DAC1_FIFO 0x0008 /* - Write D/A1 FIFO (16bit) */

Definition at line 131 of file rtd520.h.

#define LAS1_DAC2_FIFO 0x000C /* - Write D/A2 FIFO (16bit) */

Definition at line 132 of file rtd520.h.

#define LAS1_HDIO_FIFO 0x0004 /* Read High Speed Digital Input FIFO (16bit) - */

Definition at line 130 of file rtd520.h.

#define LCFG_DMAARB 0x00AC /* DMA Arbitration Register */

Definition at line 151 of file rtd520.h.

#define LCFG_DMACSR0 0x00A8 /* DMA Channel 0 Command/Status Register */

Definition at line 149 of file rtd520.h.

#define LCFG_DMACSR1 0x00A9 /* DMA Channel 0 Command/Status Register */

Definition at line 150 of file rtd520.h.

#define LCFG_DMADPR0 0x0090 /* DMA Channel 0 Descriptor Pointer Register */

Definition at line 143 of file rtd520.h.

#define LCFG_DMADPR1 0x00A4 /* DMA Channel 1 Descriptor Pointer Register */

Definition at line 148 of file rtd520.h.

#define LCFG_DMALADR0 0x0088 /* DMA Channel 0 Local Address Reg */

Definition at line 141 of file rtd520.h.

#define LCFG_DMALADR1 0x009C /* DMA Channel 1 Local Address Register */

Definition at line 146 of file rtd520.h.

#define LCFG_DMAMODE0 0x0080 /* DMA Channel 0 Mode Register */

Definition at line 139 of file rtd520.h.

#define LCFG_DMAMODE1 0x0094 /* DMA Channel 1 Mode Register */

Definition at line 144 of file rtd520.h.

#define LCFG_DMAPADR0 0x0084 /* DMA Channel 0 PCI Address Register */

Definition at line 140 of file rtd520.h.

#define LCFG_DMAPADR1 0x0098 /* DMA Channel 1 PCI Address Register */

Definition at line 145 of file rtd520.h.

#define LCFG_DMASIZ0 0x008C /* DMA Channel 0 Transfer Size (Bytes) Register */

Definition at line 142 of file rtd520.h.

#define LCFG_DMASIZ1 0x00A0 /* DMA Channel 1 Transfer Size (Bytes) Register */

Definition at line 147 of file rtd520.h.

#define LCFG_DMATHR 0x00B0 /* DMA Threshold Register */

Definition at line 152 of file rtd520.h.

#define LCFG_ITCSR 0x0068 /* INTCSR, Interrupt Control/Status Register */

Definition at line 138 of file rtd520.h.

#define M8254_EVENT_COUNTER 0 /* Event Counter */

Definition at line 278 of file rtd520.h.

#define M8254_HW_ONE_SHOT 1 /* Hardware-Retriggerable One-Shot */

Definition at line 279 of file rtd520.h.

#define M8254_HW_STROBE 5 /* Hardware Triggered Strobe (Retriggerable) */

Definition at line 283 of file rtd520.h.

#define M8254_RATE_GENERATOR 2 /* Rate Generator */

Definition at line 280 of file rtd520.h.

#define M8254_SQUARE_WAVE 3 /* Square Wave Mode */

Definition at line 281 of file rtd520.h.

#define M8254_SW_STROBE 4 /* Software Triggered Strobe */

Definition at line 282 of file rtd520.h.

#define NRSE_AGND 0 /* AGND referenced SE input */

Definition at line 407 of file rtd520.h.

#define NRSE_AINS 1 /* AIN SENSE referenced SE input */

Definition at line 408 of file rtd520.h.

#define PCLK_EXTERNAL 0 /* External Pacer Clock */

Definition at line 200 of file rtd520.h.

#define PCLK_INTERNAL 1 /* Internal Pacer Clock */

Definition at line 199 of file rtd520.h.

#define PCLK_START_D_DIGITAL_IT 0xA /* Delayed digital interrupt */

Definition at line 236 of file rtd520.h.

#define PCLK_START_D_ETRIG 0x9 /* Delayed external trigger */

Definition at line 235 of file rtd520.h.

#define PCLK_START_D_SBUS0 0xC /* Delayed SyncBus 0 */

Definition at line 238 of file rtd520.h.

#define PCLK_START_D_SBUS1 0xD /* Delayed SyncBus 1 */

Definition at line 239 of file rtd520.h.

#define PCLK_START_D_SBUS2 0xE /* Delayed SyncBus 2 */

Definition at line 240 of file rtd520.h.

#define PCLK_START_D_SOFTWARE 0x8 /* Delayed Software Pacer Start */

Definition at line 234 of file rtd520.h.

#define PCLK_START_D_UTC2 0xB /* Delayed User TC 2 out */

Definition at line 237 of file rtd520.h.

#define PCLK_START_DIGITAL_IT 0x2 /* Digital interrupt */

Definition at line 229 of file rtd520.h.

#define PCLK_START_ETRIG 0x1 /* External trigger */

Definition at line 228 of file rtd520.h.

#define PCLK_START_ETRIG_GATED 0xF /* External Trigger Gated controlled mode */

Definition at line 241 of file rtd520.h.

#define PCLK_START_SBUS0 0x4 /* SyncBus 0 */

Definition at line 231 of file rtd520.h.

#define PCLK_START_SBUS1 0x5 /* SyncBus 1 */

Definition at line 232 of file rtd520.h.

#define PCLK_START_SBUS2 0x6 /* SyncBus 2 */

Definition at line 233 of file rtd520.h.

#define PCLK_START_SOFTWARE 0x0 /* Software Pacer Start (StartPacer) */

Definition at line 227 of file rtd520.h.

#define PCLK_START_UTC2 0x3 /* User TC 2 out */

Definition at line 230 of file rtd520.h.

#define PCLK_STOP_A_DIGITAL_IT 0xA /* About Digital Interrupt */

Definition at line 254 of file rtd520.h.

#define PCLK_STOP_A_ETRIG 0x9 /* About External Trigger */

Definition at line 253 of file rtd520.h.

#define PCLK_STOP_A_SBUS0 0xD /* About SyncBus 0 */

Definition at line 256 of file rtd520.h.

#define PCLK_STOP_A_SBUS1 0xE /* About SyncBus 1 */

Definition at line 257 of file rtd520.h.

#define PCLK_STOP_A_SBUS2 0xF /* About SyncBus 2 */

Definition at line 258 of file rtd520.h.

#define PCLK_STOP_A_SOFTWARE 0x8 /* About Software Pacer Stop */

Definition at line 252 of file rtd520.h.

#define PCLK_STOP_A_UTC2 0xC /* About User TC2 out */

Definition at line 255 of file rtd520.h.

#define PCLK_STOP_ACNT 0x3 /* About Counter */

Definition at line 247 of file rtd520.h.

#define PCLK_STOP_DIGITAL_IT 0x2 /* Digital Interrupt */

Definition at line 246 of file rtd520.h.

#define PCLK_STOP_ETRIG 0x1 /* External Trigger */

Definition at line 245 of file rtd520.h.

#define PCLK_STOP_SBUS0 0x5 /* SyncBus 0 */

Definition at line 249 of file rtd520.h.

#define PCLK_STOP_SBUS1 0x6 /* SyncBus 1 */

Definition at line 250 of file rtd520.h.

#define PCLK_STOP_SBUS2 0x7 /* SyncBus 2 */

Definition at line 251 of file rtd520.h.

#define PCLK_STOP_SOFTWARE 0x0 /* Software Pacer Stop (StopPacer) */

Definition at line 244 of file rtd520.h.

#define PCLK_STOP_UTC2 0x4 /* User TC2 out */

Definition at line 248 of file rtd520.h.

#define POL_NEGATIVE 0x1 /* negative edge */

Definition at line 190 of file rtd520.h.

#define POL_POSITIVE 0x0 /* positive edge */

Definition at line 189 of file rtd520.h.

#define TS_ACNT_GATE 0x0008

Definition at line 180 of file rtd520.h.

#define TS_BCLK_GATE 0x0002

Definition at line 175 of file rtd520.h.

#define TS_DCNT_GATE 0x0004

Definition at line 177 of file rtd520.h.

#define TS_PCLK_GATE 0x0001

Definition at line 173 of file rtd520.h.

#define TS_PCLK_RUN 0x0010

Definition at line 182 of file rtd520.h.

#define UOUT_ADC 0x0 /* A/D Conversion Signal */

Definition at line 193 of file rtd520.h.

#define UOUT_DAC1 0x1 /* D/A1 Update */

Definition at line 194 of file rtd520.h.

#define UOUT_DAC2 0x2 /* D/A2 Update */

Definition at line 195 of file rtd520.h.

#define UOUT_SOFTWARE 0x3 /* Software Programmable */

Definition at line 196 of file rtd520.h.

Macros

Macro Definition Documentation