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Data Structures
struct	_nsp32_sgtable

struct	_nsp32_sglun

struct	_nsp32_autoparam

struct	_nsp32_lunt

struct	_nsp32_sync_table

struct	_nsp32_target

struct	_nsp32_hw_data

Macros
#define	PCI_VENDOR_ID_IODATA 0x10fc

#define	PCI_VENDOR_ID_WORKBIT 0x1145

#define	PCI_DEVICE_ID_NINJASCSI_32BI_CBSC_II 0x0005

#define	PCI_DEVICE_ID_NINJASCSI_32BI_KME 0xf007

#define	PCI_DEVICE_ID_NINJASCSI_32BI_WBT 0x8007

#define	PCI_DEVICE_ID_WORKBIT_STANDARD 0xf010

#define	PCI_DEVICE_ID_WORKBIT_DUALEDGE 0xf011

#define	PCI_DEVICE_ID_NINJASCSI_32BI_LOGITEC 0xf012

#define	PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC 0xf013

#define	PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO 0xf015

#define	PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO_II 0x8009

#define	EXTENDED_SDTR_LEN 0x03

#define	TRUE 1

#define	FALSE 0

#define	ASSERT 1

#define	NEGATE 0

#define	IRQ_CONTROL 0x00 /* BASE+00, W, W */

#define	IRQ_STATUS 0x00 /* BASE+00, W, R */

#define	IRQSTATUS_LATCHED_MSG BIT(0)

#define	IRQSTATUS_LATCHED_IO BIT(1)

#define	IRQSTATUS_LATCHED_CD BIT(2)

#define	IRQSTATUS_LATCHED_BUS_FREE BIT(3)

#define	IRQSTATUS_RESELECT_OCCUER BIT(4)

#define	IRQSTATUS_PHASE_CHANGE_IRQ BIT(5)

#define	IRQSTATUS_SCSIRESET_IRQ BIT(6)

#define	IRQSTATUS_TIMER_IRQ BIT(7)

#define	IRQSTATUS_FIFO_SHLD_IRQ BIT(8)

#define	IRQSTATUS_PCI_IRQ BIT(9)

#define	IRQSTATUS_BMCNTERR_IRQ BIT(10)

#define	IRQSTATUS_AUTOSCSI_IRQ BIT(11)

#define	PCI_IRQ_MASK BIT(12)

#define	TIMER_IRQ_MASK BIT(13)

#define	FIFO_IRQ_MASK BIT(14)

#define	SCSI_IRQ_MASK BIT(15)

#define	IRQ_CONTROL_ALL_IRQ_MASK

#define	IRQSTATUS_ANY_IRQ

#define	TRANSFER_CONTROL 0x02 /* BASE+02, W, W */

#define	TRANSFER_STATUS 0x02 /* BASE+02, W, R */

#define	CB_MMIO_MODE BIT(0)

#define	CB_IO_MODE BIT(1)

#define	BM_TEST BIT(2)

#define	BM_TEST_DIR BIT(3)

#define	DUAL_EDGE_ENABLE BIT(4)

#define	NO_TRANSFER_TO_HOST BIT(5)

#define	TRANSFER_GO BIT(7)

#define	BLIEND_MODE BIT(8)

#define	BM_START BIT(9)

#define	ADVANCED_BM_WRITE BIT(10)

#define	BM_SINGLE_MODE BIT(11)

#define	FIFO_TRUE_FULL BIT(12)

#define	FIFO_TRUE_EMPTY BIT(13)

#define	ALL_COUNTER_CLR BIT(14)

#define	FIFOTEST BIT(15)

#define	INDEX_REG 0x04 /* BASE+04, Byte(R/W), Word(R) */

#define	TIMER_SET 0x06 /* BASE+06, W, R/W */

#define	TIMER_CNT_MASK (0xff)

#define	TIMER_STOP BIT(8)

#define	DATA_REG_LOW 0x08 /* BASE+08, LowW, R/W */

#define	DATA_REG_HI 0x0a /* BASE+0a, Hi-W, R/W */

#define	FIFO_REST_CNT 0x0c /* BASE+0c, W, R/W */

#define	FIFO_REST_MASK 0x1ff

#define	FIFO_EMPTY_SHLD_FLAG BIT(14)

#define	FIFO_FULL_SHLD_FLAG BIT(15)

#define	SREQ_SMPL_RATE 0x0f /* BASE+0f, B, R/W */

#define	SREQSMPLRATE_RATE0 BIT(0)

#define	SREQSMPLRATE_RATE1 BIT(1)

#define	SAMPLING_ENABLE BIT(2)

#define	SMPL_40M (0) /* 40MHz: 0-100ns/period */

#define	SMPL_20M (SREQSMPLRATE_RATE0) /* 20MHz: 100-200ns/period */

#define	SMPL_10M (SREQSMPLRATE_RATE1) /* 10Mhz: 200- ns/period */

#define	SCSI_BUS_CONTROL 0x10 /* BASE+10, B, R/W */

#define	BUSCTL_SEL BIT(0)

#define	BUSCTL_RST BIT(1)

#define	BUSCTL_DATAOUT_ENB BIT(2)

#define	BUSCTL_ATN BIT(3)

#define	BUSCTL_ACK BIT(4)

#define	BUSCTL_BSY BIT(5)

#define	AUTODIRECTION BIT(6)

#define	ACKENB BIT(7)

#define	CLR_COUNTER 0x12 /* BASE+12, B, W */

#define	ACK_COUNTER_CLR BIT(0)

#define	SREQ_COUNTER_CLR BIT(1)

#define	FIFO_HOST_POINTER_CLR BIT(2)

#define	FIFO_REST_COUNT_CLR BIT(3)

#define	BM_COUNTER_CLR BIT(4)

#define	SAVED_ACK_CLR BIT(5)

#define	CLRCOUNTER_ALLMASK

#define	SCSI_BUS_MONITOR 0x12 /* BASE+12, B, R */

#define	BUSMON_MSG BIT(0)

#define	BUSMON_IO BIT(1)

#define	BUSMON_CD BIT(2)

#define	BUSMON_BSY BIT(3)

#define	BUSMON_ACK BIT(4)

#define	BUSMON_REQ BIT(5)

#define	BUSMON_SEL BIT(6)

#define	BUSMON_ATN BIT(7)

#define	COMMAND_DATA 0x14 /* BASE+14, B, R/W */

#define	PARITY_CONTROL 0x16 /* BASE+16, B, W */

#define	PARITY_CHECK_ENABLE BIT(0)

#define	PARITY_ERROR_CLEAR BIT(1)

#define	PARITY_STATUS 0x16 /* BASE+16, B, R */

#define	PARITY_ERROR_NORMAL BIT(1)

#define	PARITY_ERROR_LSB BIT(1)

#define	PARITY_ERROR_MSB BIT(2)

#define	RESELECT_ID 0x18 /* BASE+18, B, R */

#define	COMMAND_CONTROL 0x18 /* BASE+18, W, W */

#define	CLEAR_CDB_FIFO_POINTER BIT(0)

#define	AUTO_COMMAND_PHASE BIT(1)

#define	AUTOSCSI_START BIT(2)

#define	AUTOSCSI_RESTART BIT(3)

#define	AUTO_PARAMETER BIT(4)

#define	AUTO_ATN BIT(5)

#define	AUTO_MSGIN_00_OR_04 BIT(6)

#define	AUTO_MSGIN_02 BIT(7)

#define	AUTO_MSGIN_03 BIT(8)

#define	SET_ARBIT 0x1a /* BASE+1a, B, W */

#define	ARBIT_GO BIT(0)

#define	ARBIT_CLEAR BIT(1)

#define	ARBIT_STATUS 0x1a /* BASE+1a, B, R */

#define	ARBIT_WIN BIT(1)

#define	ARBIT_FAIL BIT(2)

#define	AUTO_PARAMETER_VALID BIT(3)

#define	SGT_VALID BIT(4)

#define	SYNC_REG 0x1c /* BASE+1c, B, R/W */

#define	ACK_WIDTH 0x1d /* BASE+1d, B, R/W */

#define	SCSI_DATA_WITH_ACK 0x20 /* BASE+20, B, R/W */

#define	SCSI_OUT_LATCH_TARGET_ID 0x22 /* BASE+22, B, W */

#define	SCSI_DATA_IN 0x22 /* BASE+22, B, R */

#define	SCAM_CONTROL 0x24 /* BASE+24, B, W */

#define	SCAM_STATUS 0x24 /* BASE+24, B, R */

#define	SCAM_MSG BIT(0)

#define	SCAM_IO BIT(1)

#define	SCAM_CD BIT(2)

#define	SCAM_BSY BIT(3)

#define	SCAM_SEL BIT(4)

#define	SCAM_XFEROK BIT(5)

#define	SCAM_DATA 0x26 /* BASE+26, B, R/W */

#define	SD0 BIT(0)

#define	SD1 BIT(1)

#define	SD2 BIT(2)

#define	SD3 BIT(3)

#define	SD4 BIT(4)

#define	SD5 BIT(5)

#define	SD6 BIT(6)

#define	SD7 BIT(7)

#define	SACK_CNT 0x28 /* BASE+28, DW, R/W */

#define	SREQ_CNT 0x2c /* BASE+2c, DW, R/W */

#define	FIFO_DATA_LOW 0x30 /* BASE+30, B/W/DW, R/W */

#define	FIFO_DATA_HIGH 0x32 /* BASE+32, B/W, R/W */

#define	BM_START_ADR 0x34 /* BASE+34, DW, R/W */

#define	BM_CNT 0x38 /* BASE+38, DW, R/W */

#define	BM_COUNT_MASK 0x0001ffffUL

#define	SGTEND BIT(31) /* Last SGT marker */

#define	SGT_ADR 0x3c /* BASE+3c, DW, R/W */

#define	WAIT_REG 0x40 /* Bi only */

#define	SCSI_EXECUTE_PHASE 0x40 /* BASE+40, W, R */

#define	COMMAND_PHASE BIT(0)

#define	DATA_IN_PHASE BIT(1)

#define	DATA_OUT_PHASE BIT(2)

#define	MSGOUT_PHASE BIT(3)

#define	STATUS_PHASE BIT(4)

#define	ILLEGAL_PHASE BIT(5)

#define	BUS_FREE_OCCUER BIT(6)

#define	MSG_IN_OCCUER BIT(7)

#define	MSG_OUT_OCCUER BIT(8)

#define	SELECTION_TIMEOUT BIT(9)

#define	MSGIN_00_VALID BIT(10)

#define	MSGIN_02_VALID BIT(11)

#define	MSGIN_03_VALID BIT(12)

#define	MSGIN_04_VALID BIT(13)

#define	AUTOSCSI_BUSY BIT(15)

#define	SCSI_CSB_IN 0x42 /* BASE+42, B, R */

#define	SCSI_MSG_OUT 0x44 /* BASE+44, DW, R/W */

#define	MSGOUT_COUNT_MASK (BIT(0)\|BIT(1))

#define	MV_VALID BIT(7)

#define	SEL_TIME_OUT 0x48 /* BASE+48, W, R/W */

#define	SAVED_SACK_CNT 0x4c /* BASE+4c, DW, R */

#define	HTOSDATADELAY 0x50 /* BASE+50, B, R/W */

#define	STOHDATADELAY 0x54 /* BASE+54, B, R/W */

#define	ACKSUMCHECKRD 0x58 /* BASE+58, W, R */

#define	REQSUMCHECKRD 0x5c /* BASE+5c, W, R */

#define	CLOCK_DIV 0x00 /* BASE+08, IDX+00, B, R/W */

#define	CLOCK_2 BIT(0) /* MCLK/2 */

#define	CLOCK_4 BIT(1) /* MCLK/4 */

#define	PCICLK BIT(7) /* PCICLK (33MHz) */

#define	TERM_PWR_CONTROL 0x01 /* BASE+08, IDX+01, B, R/W */

#define	BPWR BIT(0)

#define	SENSE BIT(1) /* Read Only */

#define	EXT_PORT_DDR 0x02 /* BASE+08, IDX+02, B, R/W */

#define	EXT_PORT 0x03 /* BASE+08, IDX+03, B, R/W */

#define	LED_ON (0)

#define	LED_OFF BIT(0)

#define	IRQ_SELECT 0x04 /* BASE+08, IDX+04, W, R/W */

#define	IRQSELECT_RESELECT_IRQ BIT(0)

#define	IRQSELECT_PHASE_CHANGE_IRQ BIT(1)

#define	IRQSELECT_SCSIRESET_IRQ BIT(2)

#define	IRQSELECT_TIMER_IRQ BIT(3)

#define	IRQSELECT_FIFO_SHLD_IRQ BIT(4)

#define	IRQSELECT_TARGET_ABORT_IRQ BIT(5)

#define	IRQSELECT_MASTER_ABORT_IRQ BIT(6)

#define	IRQSELECT_SERR_IRQ BIT(7)

#define	IRQSELECT_PERR_IRQ BIT(8)

#define	IRQSELECT_BMCNTERR_IRQ BIT(9)

#define	IRQSELECT_AUTO_SCSI_SEQ_IRQ BIT(10)

#define	OLD_SCSI_PHASE 0x05 /* BASE+08, IDX+05, B, R */

#define	OLD_MSG BIT(0)

#define	OLD_IO BIT(1)

#define	OLD_CD BIT(2)

#define	OLD_BUSY BIT(3)

#define	FIFO_FULL_SHLD_COUNT 0x06 /* BASE+08, IDX+06, B, R/W */

#define	FIFO_EMPTY_SHLD_COUNT 0x07 /* BASE+08, IDX+07, B, R/W */

#define	EXP_ROM_CONTROL 0x08 /* BASE+08, IDX+08, B, R/W / / external ROM control */

#define	ROM_WRITE_ENB BIT(0)

#define	IO_ACCESS_ENB BIT(1)

#define	ROM_ADR_CLEAR BIT(2)

#define	EXP_ROM_ADR 0x09 /* BASE+08, IDX+09, W, R/W */

#define	EXP_ROM_DATA 0x0a /* BASE+08, IDX+0a, B, R/W */

#define	CHIP_MODE 0x0b /* BASE+08, IDX+0b, B, R / / NinjaSCSI-32Bi only */

#define	OEM0 BIT(1) /* OEM select / / 00=I-O DATA, 01=KME, 10=Workbit, 11=Ext ROM */

#define	OEM1 BIT(2) /* OEM select */

#define	OPTB BIT(3) /* KME mode select */

#define	OPTC BIT(4) /* KME mode select */

#define	OPTD BIT(5) /* KME mode select */

#define	OPTE BIT(6) /* KME mode select */

#define	OPTF BIT(7) /* Power management */

#define	MISC_WR 0x0c /* BASE+08, IDX+0c, W, R/W */

#define	MISC_RD 0x0c

#define	SCSI_DIRECTION_DETECTOR_SELECT BIT(0)

#define	SCSI2_HOST_DIRECTION_VALID BIT(1) /* Read only */

#define	HOST2_SCSI_DIRECTION_VALID BIT(2) /* Read only */

#define	DELAYED_BMSTART BIT(3)

#define	MASTER_TERMINATION_SELECT BIT(4)

#define	BMREQ_NEGATE_TIMING_SEL BIT(5)

#define	AUTOSEL_TIMING_SEL BIT(6)

#define	MISC_MABORT_MASK BIT(7)

#define	BMSTOP_CHANGE2_NONDATA_PHASE BIT(8)

#define	BM_CYCLE 0x0d /* BASE+08, IDX+0d, B, R/W */

#define	BM_CYCLE0 BIT(0)

#define	BM_CYCLE1 BIT(1)

#define	BM_FRAME_ASSERT_TIMING BIT(2)

#define	BM_IRDY_ASSERT_TIMING BIT(3)

#define	BM_SINGLE_BUS_MASTER BIT(4)

#define	MEMRD_CMD0 BIT(5)

#define	SGT_AUTO_PARA_MEMED_CMD BIT(6)

#define	MEMRD_CMD1 BIT(7)

#define	SREQ_EDGH 0x0e /* BASE+08, IDX+0e, B, W */

#define	SREQ_EDGH_SELECT BIT(0)

#define	UP_CNT 0x0f /* BASE+08, IDX+0f, B, W */

#define	REQCNT_UP BIT(0)

#define	ACKCNT_UP BIT(1)

#define	BMADR_UP BIT(4)

#define	BMCNT_UP BIT(5)

#define	SGT_CNT_UP BIT(7)

#define	CFG_CMD_STR 0x10 /* BASE+08, IDX+10, W, R */

#define	CFG_LATE_CACHE 0x11 /* BASE+08, IDX+11, W, R/W */

#define	CFG_BASE_ADR_1 0x12 /* BASE+08, IDX+12, W, R */

#define	CFG_BASE_ADR_2 0x13 /* BASE+08, IDX+13, W, R */

#define	CFG_INLINE 0x14 /* BASE+08, IDX+14, W, R */

#define	SERIAL_ROM_CTL 0x15 /* BASE+08, IDX+15, B, R */

#define	SCL BIT(0)

#define	ENA BIT(1)

#define	SDA BIT(2)

#define	FIFO_HST_POINTER 0x16 /* BASE+08, IDX+16, B, R/W */

#define	SREQ_DELAY 0x17 /* BASE+08, IDX+17, B, R/W */

#define	SACK_DELAY 0x18 /* BASE+08, IDX+18, B, R/W */

#define	SREQ_NOISE_CANCEL 0x19 /* BASE+08, IDX+19, B, R/W */

#define	SDP_NOISE_CANCEL 0x1a /* BASE+08, IDX+1a, B, R/W */

#define	DELAY_TEST 0x1b /* BASE+08, IDX+1b, B, R/W */

#define	SD0_NOISE_CANCEL 0x20 /* BASE+08, IDX+20, B, R/W */

#define	SD1_NOISE_CANCEL 0x21 /* BASE+08, IDX+21, B, R/W */

#define	SD2_NOISE_CANCEL 0x22 /* BASE+08, IDX+22, B, R/W */

#define	SD3_NOISE_CANCEL 0x23 /* BASE+08, IDX+23, B, R/W */

#define	SD4_NOISE_CANCEL 0x24 /* BASE+08, IDX+24, B, R/W */

#define	SD5_NOISE_CANCEL 0x25 /* BASE+08, IDX+25, B, R/W */

#define	SD6_NOISE_CANCEL 0x26 /* BASE+08, IDX+26, B, R/W */

#define	SD7_NOISE_CANCEL 0x27 /* BASE+08, IDX+27, B, R/W */

#define	BUSMON_BUS_FREE 0

#define	BUSMON_COMMAND ( BUSMON_BSY \| BUSMON_CD \| BUSMON_REQ )

#define	BUSMON_MESSAGE_IN ( BUSMON_BSY \| BUSMON_MSG \| BUSMON_IO \| BUSMON_CD \| BUSMON_REQ )

#define	BUSMON_MESSAGE_OUT ( BUSMON_BSY \| BUSMON_MSG \| BUSMON_CD \| BUSMON_REQ )

#define	BUSMON_DATA_IN ( BUSMON_BSY \| BUSMON_IO \| BUSMON_REQ )

#define	BUSMON_DATA_OUT ( BUSMON_BSY \| BUSMON_REQ )

#define	BUSMON_STATUS ( BUSMON_BSY \| BUSMON_IO \| BUSMON_CD \| BUSMON_REQ )

#define	BUSMON_RESELECT ( BUSMON_IO \| BUSMON_SEL)

#define	BUSMON_PHASE_MASK ( BUSMON_MSG \| BUSMON_IO \| BUSMON_CD \| BUSMON_SEL)

#define	BUSPHASE_COMMAND ( BUSMON_COMMAND & BUSMON_PHASE_MASK )

#define	BUSPHASE_MESSAGE_IN ( BUSMON_MESSAGE_IN & BUSMON_PHASE_MASK )

#define	BUSPHASE_MESSAGE_OUT ( BUSMON_MESSAGE_OUT & BUSMON_PHASE_MASK )

#define	BUSPHASE_DATA_IN ( BUSMON_DATA_IN & BUSMON_PHASE_MASK )

#define	BUSPHASE_DATA_OUT ( BUSMON_DATA_OUT & BUSMON_PHASE_MASK )

#define	BUSPHASE_STATUS ( BUSMON_STATUS & BUSMON_PHASE_MASK )

#define	BUSPHASE_SELECT ( BUSMON_SEL \| BUSMON_IO )

#define	NSP32_SG_SIZE SG_ALL

#define	NSP32_SG_TABLE_SIZE (sizeof(nsp32_sgtable) * NSP32_SG_SIZE * MAX_TARGET * MAX_LUN)

#define	MSGOUTBUF_MAX 20

#define	MSGINBUF_MAX 20

#define	NSP32_TRANSFER_BUSMASTER BIT(0)

#define	NSP32_TRANSFER_MMIO BIT(1) /* Not supported yet */

#define	NSP32_TRANSFER_PIO BIT(2) /* Not supported yet */

#define	DISCPRIV_OK BIT(0) /* DISCPRIV Enable mode */

#define	MSGIN03 BIT(1) /* Auto Msg In 03 Flag */

#define	NSP32_HOST_SCSIID 7 /* SCSI initiator is every time defined as 7 */

#define	MAX_TARGET 8

#define	MAX_LUN 8 /* XXX: In SPI3, max number of LUN is 64. */

#define	SDTR_INITIATOR BIT(0) /* sending SDTR from initiator */

#define	SDTR_TARGET BIT(1) /* sending SDTR from target */

#define	SDTR_DONE BIT(2) /* exchanging SDTR has been processed */

#define	FAST5M 0x32

#define	FAST10M 0x19

#define	ULTRA20M 0x0c

#define	ASYNC_OFFSET 0 /* asynchronous transfer */

#define	SYNC_OFFSET 0xf /* synchronous transfer max offset */

#define	TO_SYNCREG(period, offset) (((period) & 0x0f) << 4 \| ((offset) & 0x0f))

#define	NSP32_MMIO_OFFSET 0x0800

#define	RESET_HOLD_TIME

#define	SEL_TIMEOUT_TIME

#define	ARBIT_TIMEOUT_TIME 100 /* 100us */

#define	REQSACK_TIMEOUT_TIME

Typedefs
typedef u32	u32_le

typedef u16	u16_le

typedef struct _nsp32_lunt	nsp32_lunt

typedef struct _nsp32_sync_table	nsp32_sync_table

typedef struct _nsp32_target	nsp32_target

typedef struct _nsp32_hw_data	nsp32_hw_data

Enumerations
enum	{ MODEL_IODATA = 0, MODEL_KME = 1, MODEL_WORKBIT = 2, MODEL_LOGITEC = 3, MODEL_PCI_WORKBIT = 4, MODEL_PCI_LOGITEC = 5, MODEL_PCI_MELCO = 6 }

Functions
struct _nsp32_sgtable	__attribute__ ((packed)) nsp32_sgtable

Variables
u32_le	addr

u32_le	len

nsp32_sgtable	sgt [NSP32_SG_SIZE+1]

u8	cdb [4 *0x10]

u32_le	msgout

u8	syncreg

u8	ackwidth

u8	target_id

u8	sample_reg

u16_le	command_control

u16_le	transfer_control

u32_le	sgt_pointer

u32_le	dummy [2]

Macro Definition Documentation

#define ACK_COUNTER_CLR BIT(0)

Definition at line 172 of file nsp32.h.

#define ACK_WIDTH 0x1d /* BASE+1d, B, R/W */

Definition at line 232 of file nsp32.h.

#define ACKCNT_UP BIT(1)

Definition at line 389 of file nsp32.h.

#define ACKENB BIT(7)

Definition at line 169 of file nsp32.h.

#define ACKSUMCHECKRD 0x58 /* BASE+58, W, R */

Definition at line 299 of file nsp32.h.

#define ADVANCED_BM_WRITE BIT(10)

Definition at line 132 of file nsp32.h.

#define ALL_COUNTER_CLR BIT(14)

Definition at line 136 of file nsp32.h.

#define ARBIT_CLEAR BIT(1)

Definition at line 221 of file nsp32.h.

#define ARBIT_FAIL BIT(2)

Definition at line 226 of file nsp32.h.

#define ARBIT_GO BIT(0)

Definition at line 220 of file nsp32.h.

#define ARBIT_STATUS 0x1a /* BASE+1a, B, R */

Definition at line 223 of file nsp32.h.

#define ARBIT_TIMEOUT_TIME 100 /* 100us */

Definition at line 610 of file nsp32.h.

#define ARBIT_WIN BIT(1)

Definition at line 225 of file nsp32.h.

#define ASSERT 1

Definition at line 79 of file nsp32.h.

#define ASYNC_OFFSET 0 /* asynchronous transfer */

Definition at line 538 of file nsp32.h.

#define AUTO_ATN BIT(5)

Definition at line 214 of file nsp32.h.

#define AUTO_COMMAND_PHASE BIT(1)

Definition at line 210 of file nsp32.h.

#define AUTO_MSGIN_00_OR_04 BIT(6)

Definition at line 215 of file nsp32.h.

#define AUTO_MSGIN_02 BIT(7)

Definition at line 216 of file nsp32.h.

#define AUTO_MSGIN_03 BIT(8)

Definition at line 217 of file nsp32.h.

#define AUTO_PARAMETER BIT(4)

Definition at line 213 of file nsp32.h.

#define AUTO_PARAMETER_VALID BIT(3)

Definition at line 227 of file nsp32.h.

#define AUTODIRECTION BIT(6)

Definition at line 168 of file nsp32.h.

#define AUTOSCSI_BUSY BIT(15)

Definition at line 286 of file nsp32.h.

#define AUTOSCSI_RESTART BIT(3)

Definition at line 212 of file nsp32.h.

#define AUTOSCSI_START BIT(2)

Definition at line 211 of file nsp32.h.

#define AUTOSEL_TIMING_SEL BIT(6)

Definition at line 369 of file nsp32.h.

#define BLIEND_MODE BIT(8)

Definition at line 130 of file nsp32.h.

#define BM_CNT 0x38 /* BASE+38, DW, R/W */

Definition at line 264 of file nsp32.h.

#define BM_COUNT_MASK 0x0001ffffUL

Definition at line 265 of file nsp32.h.

#define BM_COUNTER_CLR BIT(4)

Definition at line 176 of file nsp32.h.

#define BM_CYCLE 0x0d /* BASE+08, IDX+0d, B, R/W */

Definition at line 373 of file nsp32.h.

#define BM_CYCLE0 BIT(0)

Definition at line 374 of file nsp32.h.

#define BM_CYCLE1 BIT(1)

Definition at line 375 of file nsp32.h.

#define BM_FRAME_ASSERT_TIMING BIT(2)

Definition at line 376 of file nsp32.h.

#define BM_IRDY_ASSERT_TIMING BIT(3)

Definition at line 377 of file nsp32.h.

#define BM_SINGLE_BUS_MASTER BIT(4)

Definition at line 378 of file nsp32.h.

#define BM_SINGLE_MODE BIT(11)

Definition at line 133 of file nsp32.h.

#define BM_START BIT(9)

Definition at line 131 of file nsp32.h.

#define BM_START_ADR 0x34 /* BASE+34, DW, R/W */

Definition at line 262 of file nsp32.h.

#define BM_TEST BIT(2)

Definition at line 125 of file nsp32.h.

#define BM_TEST_DIR BIT(3)

Definition at line 126 of file nsp32.h.

#define BMADR_UP BIT(4)

Definition at line 390 of file nsp32.h.

#define BMCNT_UP BIT(5)

Definition at line 391 of file nsp32.h.

#define BMREQ_NEGATE_TIMING_SEL BIT(5)

Definition at line 368 of file nsp32.h.

#define BMSTOP_CHANGE2_NONDATA_PHASE BIT(8)

Definition at line 371 of file nsp32.h.

#define BPWR BIT(0)

Definition at line 313 of file nsp32.h.

#define BUS_FREE_OCCUER BIT(6)

Definition at line 278 of file nsp32.h.

#define BUSCTL_ACK BIT(4)

Definition at line 166 of file nsp32.h.

#define BUSCTL_ATN BIT(3)

Definition at line 165 of file nsp32.h.

#define BUSCTL_BSY BIT(5)

Definition at line 167 of file nsp32.h.

#define BUSCTL_DATAOUT_ENB BIT(2)

Definition at line 164 of file nsp32.h.

#define BUSCTL_RST BIT(1)

Definition at line 163 of file nsp32.h.

#define BUSCTL_SEL BIT(0)

Definition at line 162 of file nsp32.h.

#define BUSMON_ACK BIT(4)

Definition at line 190 of file nsp32.h.

#define BUSMON_ATN BIT(7)

Definition at line 193 of file nsp32.h.

#define BUSMON_BSY BIT(3)

Definition at line 189 of file nsp32.h.

#define BUSMON_BUS_FREE 0

Definition at line 424 of file nsp32.h.

#define BUSMON_CD BIT(2)

Definition at line 188 of file nsp32.h.

#define BUSMON_COMMAND ( BUSMON_BSY | BUSMON_CD | BUSMON_REQ )

Definition at line 425 of file nsp32.h.

#define BUSMON_DATA_IN ( BUSMON_BSY | BUSMON_IO | BUSMON_REQ )

Definition at line 428 of file nsp32.h.

#define BUSMON_DATA_OUT ( BUSMON_BSY | BUSMON_REQ )

Definition at line 429 of file nsp32.h.

#define BUSMON_IO BIT(1)

Definition at line 187 of file nsp32.h.

#define BUSMON_MESSAGE_IN ( BUSMON_BSY | BUSMON_MSG | BUSMON_IO | BUSMON_CD | BUSMON_REQ )

Definition at line 426 of file nsp32.h.

#define BUSMON_MESSAGE_OUT ( BUSMON_BSY | BUSMON_MSG | BUSMON_CD | BUSMON_REQ )

Definition at line 427 of file nsp32.h.

#define BUSMON_MSG BIT(0)

Definition at line 186 of file nsp32.h.

#define BUSMON_PHASE_MASK ( BUSMON_MSG | BUSMON_IO | BUSMON_CD | BUSMON_SEL)

Definition at line 432 of file nsp32.h.

#define BUSMON_REQ BIT(5)

Definition at line 191 of file nsp32.h.

#define BUSMON_RESELECT ( BUSMON_IO | BUSMON_SEL)

Definition at line 431 of file nsp32.h.

#define BUSMON_SEL BIT(6)

Definition at line 192 of file nsp32.h.

#define BUSMON_STATUS ( BUSMON_BSY | BUSMON_IO | BUSMON_CD | BUSMON_REQ )

Definition at line 430 of file nsp32.h.

#define BUSPHASE_COMMAND ( BUSMON_COMMAND & BUSMON_PHASE_MASK )

Definition at line 434 of file nsp32.h.

#define BUSPHASE_DATA_IN ( BUSMON_DATA_IN & BUSMON_PHASE_MASK )

Definition at line 437 of file nsp32.h.

#define BUSPHASE_DATA_OUT ( BUSMON_DATA_OUT & BUSMON_PHASE_MASK )

Definition at line 438 of file nsp32.h.

#define BUSPHASE_MESSAGE_IN ( BUSMON_MESSAGE_IN & BUSMON_PHASE_MASK )

Definition at line 435 of file nsp32.h.

#define BUSPHASE_MESSAGE_OUT ( BUSMON_MESSAGE_OUT & BUSMON_PHASE_MASK )

Definition at line 436 of file nsp32.h.

#define BUSPHASE_SELECT ( BUSMON_SEL | BUSMON_IO )

Definition at line 440 of file nsp32.h.

#define BUSPHASE_STATUS ( BUSMON_STATUS & BUSMON_PHASE_MASK )

Definition at line 439 of file nsp32.h.

#define CB_IO_MODE BIT(1)

Definition at line 124 of file nsp32.h.

#define CB_MMIO_MODE BIT(0)

Definition at line 123 of file nsp32.h.

#define CFG_BASE_ADR_1 0x12 /* BASE+08, IDX+12, W, R */

Definition at line 396 of file nsp32.h.

#define CFG_BASE_ADR_2 0x13 /* BASE+08, IDX+13, W, R */

Definition at line 397 of file nsp32.h.

#define CFG_CMD_STR 0x10 /* BASE+08, IDX+10, W, R */

Definition at line 394 of file nsp32.h.

#define CFG_INLINE 0x14 /* BASE+08, IDX+14, W, R */

Definition at line 398 of file nsp32.h.

#define CFG_LATE_CACHE 0x11 /* BASE+08, IDX+11, W, R/W */

Definition at line 395 of file nsp32.h.

#define CHIP_MODE 0x0b /* BASE+08, IDX+0b, B, R */ /* NinjaSCSI-32Bi only */

Definition at line 352 of file nsp32.h.

#define CLEAR_CDB_FIFO_POINTER BIT(0)

Definition at line 209 of file nsp32.h.

#define CLOCK_2 BIT(0) /* MCLK/2 */

Definition at line 308 of file nsp32.h.

#define CLOCK_4 BIT(1) /* MCLK/4 */

Definition at line 309 of file nsp32.h.

#define CLOCK_DIV 0x00 /* BASE+08, IDX+00, B, R/W */

Definition at line 307 of file nsp32.h.

#define CLR_COUNTER 0x12 /* BASE+12, B, W */

Definition at line 171 of file nsp32.h.

#define CLRCOUNTER_ALLMASK

Value:

(ACK_COUNTER_CLR       | \
                                SREQ_COUNTER_CLR      | \
                                FIFO_HOST_POINTER_CLR | \
                                FIFO_REST_COUNT_CLR   | \
                                BM_COUNTER_CLR        | \
                                SAVED_ACK_CLR         )

Definition at line 178 of file nsp32.h.

#define COMMAND_CONTROL 0x18 /* BASE+18, W, W */

Definition at line 208 of file nsp32.h.

#define COMMAND_DATA 0x14 /* BASE+14, B, R/W */

Definition at line 195 of file nsp32.h.

#define COMMAND_PHASE BIT(0)

Definition at line 272 of file nsp32.h.

#define DATA_IN_PHASE BIT(1)

Definition at line 273 of file nsp32.h.

#define DATA_OUT_PHASE BIT(2)

Definition at line 274 of file nsp32.h.

#define DATA_REG_HI 0x0a /* BASE+0a, Hi-W, R/W */

Definition at line 146 of file nsp32.h.

#define DATA_REG_LOW 0x08 /* BASE+08, LowW, R/W */

Definition at line 145 of file nsp32.h.

#define DELAY_TEST 0x1b /* BASE+08, IDX+1b, B, R/W */

Definition at line 410 of file nsp32.h.

#define DELAYED_BMSTART BIT(3)

Definition at line 366 of file nsp32.h.

#define DISCPRIV_OK BIT(0) /* DISCPRIV Enable mode */

Definition at line 493 of file nsp32.h.

#define DUAL_EDGE_ENABLE BIT(4)

Definition at line 127 of file nsp32.h.

#define ENA BIT(1)

Definition at line 402 of file nsp32.h.

#define EXP_ROM_ADR 0x09 /* BASE+08, IDX+09, W, R/W */

Definition at line 348 of file nsp32.h.

#define EXP_ROM_CONTROL 0x08 /* BASE+08, IDX+08, B, R/W */ /* external ROM control */

Definition at line 343 of file nsp32.h.

#define EXP_ROM_DATA 0x0a /* BASE+08, IDX+0a, B, R/W */

Definition at line 350 of file nsp32.h.

#define EXT_PORT 0x03 /* BASE+08, IDX+03, B, R/W */

Definition at line 317 of file nsp32.h.

#define EXT_PORT_DDR 0x02 /* BASE+08, IDX+02, B, R/W */

Definition at line 316 of file nsp32.h.

#define EXTENDED_SDTR_LEN 0x03

Definition at line 64 of file nsp32.h.

#define FALSE 0

Definition at line 77 of file nsp32.h.

#define FAST10M 0x19

Definition at line 534 of file nsp32.h.

#define FAST5M 0x32

Definition at line 533 of file nsp32.h.

#define FIFO_DATA_HIGH 0x32 /* BASE+32, B/W, R/W */

Definition at line 261 of file nsp32.h.

#define FIFO_DATA_LOW 0x30 /* BASE+30, B/W/DW, R/W */

Definition at line 260 of file nsp32.h.

#define FIFO_EMPTY_SHLD_COUNT 0x07 /* BASE+08, IDX+07, B, R/W */

Definition at line 341 of file nsp32.h.

#define FIFO_EMPTY_SHLD_FLAG BIT(14)

Definition at line 150 of file nsp32.h.

#define FIFO_FULL_SHLD_COUNT 0x06 /* BASE+08, IDX+06, B, R/W */

Definition at line 340 of file nsp32.h.

#define FIFO_FULL_SHLD_FLAG BIT(15)

Definition at line 151 of file nsp32.h.

#define FIFO_HOST_POINTER_CLR BIT(2)

Definition at line 174 of file nsp32.h.

#define FIFO_HST_POINTER 0x16 /* BASE+08, IDX+16, B, R/W */

Definition at line 405 of file nsp32.h.

#define FIFO_IRQ_MASK BIT(14)

Definition at line 106 of file nsp32.h.

#define FIFO_REST_CNT 0x0c /* BASE+0c, W, R/W */

Definition at line 148 of file nsp32.h.

#define FIFO_REST_COUNT_CLR BIT(3)

Definition at line 175 of file nsp32.h.

#define FIFO_REST_MASK 0x1ff

Definition at line 149 of file nsp32.h.

#define FIFO_TRUE_EMPTY BIT(13)

Definition at line 135 of file nsp32.h.

#define FIFO_TRUE_FULL BIT(12)

Definition at line 134 of file nsp32.h.

#define FIFOTEST BIT(15)

Definition at line 137 of file nsp32.h.

#define HOST2_SCSI_DIRECTION_VALID BIT(2) /* Read only */

Definition at line 365 of file nsp32.h.

#define HTOSDATADELAY 0x50 /* BASE+50, B, R/W */

Definition at line 297 of file nsp32.h.

#define ILLEGAL_PHASE BIT(5)

Definition at line 277 of file nsp32.h.

#define INDEX_REG 0x04 /* BASE+04, Byte(R/W), Word(R) */

Definition at line 139 of file nsp32.h.

#define IO_ACCESS_ENB BIT(1)

Definition at line 345 of file nsp32.h.

#define IRQ_CONTROL 0x00 /* BASE+00, W, W */

Definition at line 90 of file nsp32.h.

#define IRQ_CONTROL_ALL_IRQ_MASK

Value:

(PCI_IRQ_MASK   | \
                                     TIMER_IRQ_MASK | \
                                     FIFO_IRQ_MASK  | \
                                     SCSI_IRQ_MASK  )

Definition at line 108 of file nsp32.h.

#define IRQ_SELECT 0x04 /* BASE+08, IDX+04, W, R/W */

Definition at line 321 of file nsp32.h.

#define IRQ_STATUS 0x00 /* BASE+00, W, R */

Definition at line 91 of file nsp32.h.

#define IRQSELECT_AUTO_SCSI_SEQ_IRQ BIT(10)

Definition at line 332 of file nsp32.h.

#define IRQSELECT_BMCNTERR_IRQ BIT(9)

Definition at line 331 of file nsp32.h.

#define IRQSELECT_FIFO_SHLD_IRQ BIT(4)

Definition at line 326 of file nsp32.h.

#define IRQSELECT_MASTER_ABORT_IRQ BIT(6)

Definition at line 328 of file nsp32.h.

#define IRQSELECT_PERR_IRQ BIT(8)

Definition at line 330 of file nsp32.h.

#define IRQSELECT_PHASE_CHANGE_IRQ BIT(1)

Definition at line 323 of file nsp32.h.

#define IRQSELECT_RESELECT_IRQ BIT(0)

Definition at line 322 of file nsp32.h.

#define IRQSELECT_SCSIRESET_IRQ BIT(2)

Definition at line 324 of file nsp32.h.

#define IRQSELECT_SERR_IRQ BIT(7)

Definition at line 329 of file nsp32.h.

#define IRQSELECT_TARGET_ABORT_IRQ BIT(5)

Definition at line 327 of file nsp32.h.

#define IRQSELECT_TIMER_IRQ BIT(3)

Definition at line 325 of file nsp32.h.

#define IRQSTATUS_ANY_IRQ

Value:

(IRQSTATUS_RESELECT_OCCUER  | \
                     IRQSTATUS_PHASE_CHANGE_IRQ | \
                     IRQSTATUS_SCSIRESET_IRQ    | \
                     IRQSTATUS_TIMER_IRQ    | \
                     IRQSTATUS_FIFO_SHLD_IRQ    | \
                     IRQSTATUS_PCI_IRQ      | \
                     IRQSTATUS_BMCNTERR_IRQ | \
                     IRQSTATUS_AUTOSCSI_IRQ )

Definition at line 112 of file nsp32.h.

#define IRQSTATUS_AUTOSCSI_IRQ BIT(11)

Definition at line 103 of file nsp32.h.

#define IRQSTATUS_BMCNTERR_IRQ BIT(10)

Definition at line 102 of file nsp32.h.

#define IRQSTATUS_FIFO_SHLD_IRQ BIT(8)

Definition at line 100 of file nsp32.h.

#define IRQSTATUS_LATCHED_BUS_FREE BIT(3)

Definition at line 95 of file nsp32.h.

#define IRQSTATUS_LATCHED_CD BIT(2)

Definition at line 94 of file nsp32.h.

#define IRQSTATUS_LATCHED_IO BIT(1)

Definition at line 93 of file nsp32.h.

#define IRQSTATUS_LATCHED_MSG BIT(0)

Definition at line 92 of file nsp32.h.

#define IRQSTATUS_PCI_IRQ BIT(9)

Definition at line 101 of file nsp32.h.

#define IRQSTATUS_PHASE_CHANGE_IRQ BIT(5)

Definition at line 97 of file nsp32.h.

#define IRQSTATUS_RESELECT_OCCUER BIT(4)

Definition at line 96 of file nsp32.h.

#define IRQSTATUS_SCSIRESET_IRQ BIT(6)

Definition at line 98 of file nsp32.h.

#define IRQSTATUS_TIMER_IRQ BIT(7)

Definition at line 99 of file nsp32.h.

#define LED_OFF BIT(0)

Definition at line 319 of file nsp32.h.

#define LED_ON (0)

Definition at line 318 of file nsp32.h.

#define MASTER_TERMINATION_SELECT BIT(4)

Definition at line 367 of file nsp32.h.

#define MAX_LUN 8 /* XXX: In SPI3, max number of LUN is 64. */

Definition at line 512 of file nsp32.h.

#define MAX_TARGET 8

Definition at line 511 of file nsp32.h.

#define MEMRD_CMD0 BIT(5)

Definition at line 379 of file nsp32.h.

#define MEMRD_CMD1 BIT(7)

Definition at line 381 of file nsp32.h.

#define MISC_MABORT_MASK BIT(7)

Definition at line 370 of file nsp32.h.

#define MISC_RD 0x0c

Definition at line 362 of file nsp32.h.

#define MISC_WR 0x0c /* BASE+08, IDX+0c, W, R/W */

Definition at line 361 of file nsp32.h.

#define MSG_IN_OCCUER BIT(7)

Definition at line 279 of file nsp32.h.

#define MSG_OUT_OCCUER BIT(8)

Definition at line 280 of file nsp32.h.

#define MSGIN03 BIT(1) /* Auto Msg In 03 Flag */

Definition at line 494 of file nsp32.h.

#define MSGIN_00_VALID BIT(10)

Definition at line 282 of file nsp32.h.

#define MSGIN_02_VALID BIT(11)

Definition at line 283 of file nsp32.h.

#define MSGIN_03_VALID BIT(12)

Definition at line 284 of file nsp32.h.

#define MSGIN_04_VALID BIT(13)

Definition at line 285 of file nsp32.h.

#define MSGINBUF_MAX 20

Definition at line 479 of file nsp32.h.

#define MSGOUT_COUNT_MASK (BIT(0)|BIT(1))

Definition at line 291 of file nsp32.h.

#define MSGOUT_PHASE BIT(3)

Definition at line 275 of file nsp32.h.

#define MSGOUTBUF_MAX 20

Definition at line 478 of file nsp32.h.

#define MV_VALID BIT(7)

Definition at line 292 of file nsp32.h.

#define NEGATE 0

Definition at line 80 of file nsp32.h.

#define NO_TRANSFER_TO_HOST BIT(5)

Definition at line 128 of file nsp32.h.

#define NSP32_HOST_SCSIID 7 /* SCSI initiator is every time defined as 7 */

Definition at line 510 of file nsp32.h.

#define NSP32_MMIO_OFFSET 0x0800

Definition at line 562 of file nsp32.h.

#define NSP32_SG_SIZE SG_ALL

Definition at line 446 of file nsp32.h.

#define NSP32_SG_TABLE_SIZE (sizeof(nsp32_sgtable) * NSP32_SG_SIZE * MAX_TARGET * MAX_LUN)

Definition at line 457 of file nsp32.h.

#define NSP32_TRANSFER_BUSMASTER BIT(0)

Definition at line 482 of file nsp32.h.

#define NSP32_TRANSFER_MMIO BIT(1) /* Not supported yet */

Definition at line 483 of file nsp32.h.

#define NSP32_TRANSFER_PIO BIT(2) /* Not supported yet */

Definition at line 484 of file nsp32.h.

#define OEM0 BIT(1) /* OEM select */ /* 00=I-O DATA, 01=KME, 10=Workbit, 11=Ext ROM */

Definition at line 353 of file nsp32.h.

#define OEM1 BIT(2) /* OEM select */

Definition at line 354 of file nsp32.h.

#define OLD_BUSY BIT(3)

Definition at line 338 of file nsp32.h.

#define OLD_CD BIT(2)

Definition at line 337 of file nsp32.h.

#define OLD_IO BIT(1)

Definition at line 336 of file nsp32.h.

#define OLD_MSG BIT(0)

Definition at line 335 of file nsp32.h.

#define OLD_SCSI_PHASE 0x05 /* BASE+08, IDX+05, B, R */

Definition at line 334 of file nsp32.h.

#define OPTB BIT(3) /* KME mode select */

Definition at line 355 of file nsp32.h.

#define OPTC BIT(4) /* KME mode select */

Definition at line 356 of file nsp32.h.

#define OPTD BIT(5) /* KME mode select */

Definition at line 357 of file nsp32.h.

#define OPTE BIT(6) /* KME mode select */

Definition at line 358 of file nsp32.h.

#define OPTF BIT(7) /* Power management */

Definition at line 359 of file nsp32.h.

#define PARITY_CHECK_ENABLE BIT(0)

Definition at line 198 of file nsp32.h.

#define PARITY_CONTROL 0x16 /* BASE+16, B, W */

Definition at line 197 of file nsp32.h.

#define PARITY_ERROR_CLEAR BIT(1)

Definition at line 199 of file nsp32.h.

#define PARITY_ERROR_LSB BIT(1)

Definition at line 203 of file nsp32.h.

#define PARITY_ERROR_MSB BIT(2)

Definition at line 204 of file nsp32.h.

#define PARITY_ERROR_NORMAL BIT(1)

Definition at line 202 of file nsp32.h.

#define PARITY_STATUS 0x16 /* BASE+16, B, R */

Definition at line 200 of file nsp32.h.

#define PCI_DEVICE_ID_NINJASCSI_32BI_CBSC_II 0x0005

Definition at line 27 of file nsp32.h.

#define PCI_DEVICE_ID_NINJASCSI_32BI_KME 0xf007

Definition at line 28 of file nsp32.h.

#define PCI_DEVICE_ID_NINJASCSI_32BI_LOGITEC 0xf012

Definition at line 32 of file nsp32.h.

#define PCI_DEVICE_ID_NINJASCSI_32BI_WBT 0x8007

Definition at line 29 of file nsp32.h.

#define PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC 0xf013

Definition at line 33 of file nsp32.h.

#define PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO 0xf015

Definition at line 34 of file nsp32.h.

#define PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO_II 0x8009

Definition at line 35 of file nsp32.h.

#define PCI_DEVICE_ID_WORKBIT_DUALEDGE 0xf011

Definition at line 31 of file nsp32.h.

#define PCI_DEVICE_ID_WORKBIT_STANDARD 0xf010

Definition at line 30 of file nsp32.h.

#define PCI_IRQ_MASK BIT(12)

Definition at line 104 of file nsp32.h.

#define PCI_VENDOR_ID_IODATA 0x10fc

Definition at line 24 of file nsp32.h.

#define PCI_VENDOR_ID_WORKBIT 0x1145

Definition at line 25 of file nsp32.h.

#define PCICLK BIT(7) /* PCICLK (33MHz) */

Definition at line 310 of file nsp32.h.

#define REQCNT_UP BIT(0)

Definition at line 388 of file nsp32.h.

#define REQSACK_TIMEOUT_TIME

Value:

10000 /* max wait time for REQ/SACK assertion

or negation, 10000us == 10ms */

Definition at line 611 of file nsp32.h.

#define REQSUMCHECKRD 0x5c /* BASE+5c, W, R */

Definition at line 300 of file nsp32.h.

#define RESELECT_ID 0x18 /* BASE+18, B, R */

Definition at line 206 of file nsp32.h.

#define RESET_HOLD_TIME

Value:

10000 /* reset time in us (SCSI-2 says the

minimum is 25us) */

Definition at line 608 of file nsp32.h.

#define ROM_ADR_CLEAR BIT(2)

Definition at line 346 of file nsp32.h.

#define ROM_WRITE_ENB BIT(0)

Definition at line 344 of file nsp32.h.

#define SACK_CNT 0x28 /* BASE+28, DW, R/W */

Definition at line 257 of file nsp32.h.

#define SACK_DELAY 0x18 /* BASE+08, IDX+18, B, R/W */

Definition at line 407 of file nsp32.h.

#define SAMPLING_ENABLE BIT(2)

Definition at line 156 of file nsp32.h.

#define SAVED_ACK_CLR BIT(5)

Definition at line 177 of file nsp32.h.

#define SAVED_SACK_CNT 0x4c /* BASE+4c, DW, R */

Definition at line 295 of file nsp32.h.

#define SCAM_BSY BIT(3)

Definition at line 243 of file nsp32.h.

#define SCAM_CD BIT(2)

Definition at line 242 of file nsp32.h.

#define SCAM_CONTROL 0x24 /* BASE+24, B, W */

Definition at line 238 of file nsp32.h.

#define SCAM_DATA 0x26 /* BASE+26, B, R/W */

Definition at line 247 of file nsp32.h.

#define SCAM_IO BIT(1)

Definition at line 241 of file nsp32.h.

#define SCAM_MSG BIT(0)

Definition at line 240 of file nsp32.h.

#define SCAM_SEL BIT(4)

Definition at line 244 of file nsp32.h.

#define SCAM_STATUS 0x24 /* BASE+24, B, R */

Definition at line 239 of file nsp32.h.

#define SCAM_XFEROK BIT(5)

Definition at line 245 of file nsp32.h.

#define SCL BIT(0)

Definition at line 401 of file nsp32.h.

#define SCSI2_HOST_DIRECTION_VALID BIT(1) /* Read only */

Definition at line 364 of file nsp32.h.

#define SCSI_BUS_CONTROL 0x10 /* BASE+10, B, R/W */

Definition at line 161 of file nsp32.h.

#define SCSI_BUS_MONITOR 0x12 /* BASE+12, B, R */

Definition at line 185 of file nsp32.h.

#define SCSI_CSB_IN 0x42 /* BASE+42, B, R */

Definition at line 288 of file nsp32.h.

#define SCSI_DATA_IN 0x22 /* BASE+22, B, R */

Definition at line 236 of file nsp32.h.

#define SCSI_DATA_WITH_ACK 0x20 /* BASE+20, B, R/W */

Definition at line 234 of file nsp32.h.

#define SCSI_DIRECTION_DETECTOR_SELECT BIT(0)

Definition at line 363 of file nsp32.h.

#define SCSI_EXECUTE_PHASE 0x40 /* BASE+40, W, R */

Definition at line 271 of file nsp32.h.

#define SCSI_IRQ_MASK BIT(15)

Definition at line 107 of file nsp32.h.

#define SCSI_MSG_OUT 0x44 /* BASE+44, DW, R/W */

Definition at line 290 of file nsp32.h.

#define SCSI_OUT_LATCH_TARGET_ID 0x22 /* BASE+22, B, W */

Definition at line 235 of file nsp32.h.

#define SD0 BIT(0)

Definition at line 248 of file nsp32.h.

#define SD0_NOISE_CANCEL 0x20 /* BASE+08, IDX+20, B, R/W */

Definition at line 411 of file nsp32.h.

#define SD1 BIT(1)

Definition at line 249 of file nsp32.h.

#define SD1_NOISE_CANCEL 0x21 /* BASE+08, IDX+21, B, R/W */

Definition at line 412 of file nsp32.h.

#define SD2 BIT(2)

Definition at line 250 of file nsp32.h.

#define SD2_NOISE_CANCEL 0x22 /* BASE+08, IDX+22, B, R/W */

Definition at line 413 of file nsp32.h.

#define SD3 BIT(3)

Definition at line 251 of file nsp32.h.

#define SD3_NOISE_CANCEL 0x23 /* BASE+08, IDX+23, B, R/W */

Definition at line 414 of file nsp32.h.

#define SD4 BIT(4)

Definition at line 252 of file nsp32.h.

#define SD4_NOISE_CANCEL 0x24 /* BASE+08, IDX+24, B, R/W */

Definition at line 415 of file nsp32.h.

#define SD5 BIT(5)

Definition at line 253 of file nsp32.h.

#define SD5_NOISE_CANCEL 0x25 /* BASE+08, IDX+25, B, R/W */

Definition at line 416 of file nsp32.h.

#define SD6 BIT(6)

Definition at line 254 of file nsp32.h.

#define SD6_NOISE_CANCEL 0x26 /* BASE+08, IDX+26, B, R/W */

Definition at line 417 of file nsp32.h.

#define SD7 BIT(7)

Definition at line 255 of file nsp32.h.

#define SD7_NOISE_CANCEL 0x27 /* BASE+08, IDX+27, B, R/W */

Definition at line 418 of file nsp32.h.

#define SDA BIT(2)

Definition at line 403 of file nsp32.h.

#define SDP_NOISE_CANCEL 0x1a /* BASE+08, IDX+1a, B, R/W */

Definition at line 409 of file nsp32.h.

#define SDTR_DONE BIT(2) /* exchanging SDTR has been processed */

Definition at line 530 of file nsp32.h.

#define SDTR_INITIATOR BIT(0) /* sending SDTR from initiator */

Definition at line 528 of file nsp32.h.

#define SDTR_TARGET BIT(1) /* sending SDTR from target */

Definition at line 529 of file nsp32.h.

#define SEL_TIME_OUT 0x48 /* BASE+48, W, R/W */

Definition at line 294 of file nsp32.h.

#define SEL_TIMEOUT_TIME

Value:

10000 /* 250ms defined in SCSI specification

(25.6us/1unit) */

Definition at line 609 of file nsp32.h.

#define SELECTION_TIMEOUT BIT(9)

Definition at line 281 of file nsp32.h.

#define SENSE BIT(1) /* Read Only */

Definition at line 314 of file nsp32.h.

#define SERIAL_ROM_CTL 0x15 /* BASE+08, IDX+15, B, R */

Definition at line 400 of file nsp32.h.

#define SET_ARBIT 0x1a /* BASE+1a, B, W */

Definition at line 219 of file nsp32.h.

#define SGT_ADR 0x3c /* BASE+3c, DW, R/W */

Definition at line 268 of file nsp32.h.

#define SGT_AUTO_PARA_MEMED_CMD BIT(6)

Definition at line 380 of file nsp32.h.

#define SGT_CNT_UP BIT(7)

Definition at line 392 of file nsp32.h.

#define SGT_VALID BIT(4)

Definition at line 228 of file nsp32.h.

#define SGTEND BIT(31) /* Last SGT marker */

Definition at line 266 of file nsp32.h.

#define SMPL_10M (SREQSMPLRATE_RATE1) /* 10Mhz: 200- ns/period */

Definition at line 159 of file nsp32.h.

#define SMPL_20M (SREQSMPLRATE_RATE0) /* 20MHz: 100-200ns/period */

Definition at line 158 of file nsp32.h.

#define SMPL_40M (0) /* 40MHz: 0-100ns/period */

Definition at line 157 of file nsp32.h.

#define SREQ_CNT 0x2c /* BASE+2c, DW, R/W */

Definition at line 258 of file nsp32.h.

#define SREQ_COUNTER_CLR BIT(1)

Definition at line 173 of file nsp32.h.

#define SREQ_DELAY 0x17 /* BASE+08, IDX+17, B, R/W */

Definition at line 406 of file nsp32.h.

#define SREQ_EDGH 0x0e /* BASE+08, IDX+0e, B, W */

Definition at line 384 of file nsp32.h.

#define SREQ_EDGH_SELECT BIT(0)

Definition at line 385 of file nsp32.h.

#define SREQ_NOISE_CANCEL 0x19 /* BASE+08, IDX+19, B, R/W */

Definition at line 408 of file nsp32.h.

#define SREQ_SMPL_RATE 0x0f /* BASE+0f, B, R/W */

Definition at line 153 of file nsp32.h.

#define SREQSMPLRATE_RATE0 BIT(0)

Definition at line 154 of file nsp32.h.

#define SREQSMPLRATE_RATE1 BIT(1)

Definition at line 155 of file nsp32.h.

#define STATUS_PHASE BIT(4)

Definition at line 276 of file nsp32.h.

#define STOHDATADELAY 0x54 /* BASE+54, B, R/W */

Definition at line 298 of file nsp32.h.

#define SYNC_OFFSET 0xf /* synchronous transfer max offset */

Definition at line 539 of file nsp32.h.

#define SYNC_REG 0x1c /* BASE+1c, B, R/W */

Definition at line 230 of file nsp32.h.

#define TERM_PWR_CONTROL 0x01 /* BASE+08, IDX+01, B, R/W */

Definition at line 312 of file nsp32.h.

#define TIMER_CNT_MASK (0xff)

Definition at line 142 of file nsp32.h.

#define TIMER_IRQ_MASK BIT(13)

Definition at line 105 of file nsp32.h.

#define TIMER_SET 0x06 /* BASE+06, W, R/W */

Definition at line 141 of file nsp32.h.

#define TIMER_STOP BIT(8)

Definition at line 143 of file nsp32.h.

#define TO_SYNCREG	(	period,
		offset
	)	(((period) & 0x0f) << 4 \| ((offset) & 0x0f))

Definition at line 544 of file nsp32.h.

#define TRANSFER_CONTROL 0x02 /* BASE+02, W, W */

Definition at line 121 of file nsp32.h.

#define TRANSFER_GO BIT(7)

Definition at line 129 of file nsp32.h.

#define TRANSFER_STATUS 0x02 /* BASE+02, W, R */

Definition at line 122 of file nsp32.h.

#define TRUE 1

Definition at line 74 of file nsp32.h.

#define ULTRA20M 0x0c

Definition at line 535 of file nsp32.h.

#define UP_CNT 0x0f /* BASE+08, IDX+0f, B, W */

Definition at line 387 of file nsp32.h.

#define WAIT_REG 0x40 /* Bi only */

Definition at line 269 of file nsp32.h.

Typedef Documentation

typedef struct _nsp32_hw_data nsp32_hw_data

typedef struct _nsp32_lunt nsp32_lunt

typedef struct _nsp32_sync_table nsp32_sync_table

typedef struct _nsp32_target nsp32_target

typedef u16 u16_le

Definition at line 68 of file nsp32.h.

typedef u32 u32_le

Definition at line 67 of file nsp32.h.

Enumeration Type Documentation

anonymous enum

Enumerator:

MODEL_IODATA
MODEL_KME
MODEL_WORKBIT
MODEL_LOGITEC
MODEL_PCI_WORKBIT
MODEL_PCI_LOGITEC
MODEL_PCI_MELCO

Definition at line 40 of file nsp32.h.

Function Documentation

struct _nsp32_sgtable __attribute__ ( (packed) )

read

mcontroller : adapter info structure for old mimd_t apps

: base address : irq number : number of logical drives : pci bus : pci device : pci function : pci id : vendor id : slot number : unique id

Definition at line 171 of file esd_usb2.c.

Variable Documentation

u8 ackwidth

Definition at line 476 of file nsp32.h.

u32_le addr

Definition at line 454 of file nsp32.h.

u8 cdb[4 *0x10]

Definition at line 473 of file nsp32.h.

u16_le command_control

Definition at line 479 of file nsp32.h.

u32_le dummy[2]

Definition at line 482 of file nsp32.h.

u32_le len

Definition at line 455 of file nsp32.h.

u32_le msgout

Definition at line 474 of file nsp32.h.

u8 sample_reg

Definition at line 478 of file nsp32.h.

nsp32_sgtable sgt[NSP32_SG_SIZE+1]

Definition at line 457 of file nsp32.h.

u32_le sgt_pointer

Definition at line 481 of file nsp32.h.

u8 syncreg

Definition at line 475 of file nsp32.h.

u8 target_id

Definition at line 477 of file nsp32.h.

u16_le transfer_control

Definition at line 480 of file nsp32.h.

Data Structures

Macros

Typedefs

Enumerations

Functions

Variables

Macro Definition Documentation

Typedef Documentation

Enumeration Type Documentation

Function Documentation

Variable Documentation