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ms.c
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1 /* Driver for Realtek PCI-Express card reader
2  *
3  * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of the GNU General Public License as published by the
7  * Free Software Foundation; either version 2, or (at your option) any
8  * later version.
9  *
10  * This program is distributed in the hope that it will be useful, but
11  * WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13  * General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, see <http://www.gnu.org/licenses/>.
17  *
18  * Author:
19  * wwang ([email protected])
20  * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21  */
22 
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
26 #include <linux/vmalloc.h>
27 
28 #include "rtsx.h"
29 #include "rtsx_transport.h"
30 #include "rtsx_scsi.h"
31 #include "rtsx_card.h"
32 #include "ms.h"
33 
34 static inline void ms_set_err_code(struct rtsx_chip *chip, u8 err_code)
35 {
36  struct ms_info *ms_card = &(chip->ms_card);
37 
38  ms_card->err_code = err_code;
39 }
40 
41 static inline int ms_check_err_code(struct rtsx_chip *chip, u8 err_code)
42 {
43  struct ms_info *ms_card = &(chip->ms_card);
44 
45  return (ms_card->err_code == err_code);
46 }
47 
48 static int ms_parse_err_code(struct rtsx_chip *chip)
49 {
50  TRACE_RET(chip, STATUS_FAIL);
51 }
52 
53 static int ms_transfer_tpc(struct rtsx_chip *chip, u8 trans_mode, u8 tpc, u8 cnt, u8 cfg)
54 {
55  struct ms_info *ms_card = &(chip->ms_card);
56  int retval;
57  u8 *ptr;
58 
59  RTSX_DEBUGP("ms_transfer_tpc: tpc = 0x%x\n", tpc);
60 
61  rtsx_init_cmd(chip);
62 
63  rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
64  rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
65  rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
66  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
67 
68  rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, MS_TRANSFER_START | trans_mode);
69  rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END);
70 
71  rtsx_add_cmd(chip, READ_REG_CMD, MS_TRANS_CFG, 0, 0);
72 
73  retval = rtsx_send_cmd(chip, MS_CARD, 5000);
74  if (retval < 0) {
75  rtsx_clear_ms_error(chip);
76  ms_set_err_code(chip, MS_TO_ERROR);
77  TRACE_RET(chip, ms_parse_err_code(chip));
78  }
79 
80  ptr = rtsx_get_cmd_data(chip) + 1;
81 
82  if (!(tpc & 0x08)) { /* Read Packet */
83  if (*ptr & MS_CRC16_ERR) {
84  ms_set_err_code(chip, MS_CRC16_ERROR);
85  TRACE_RET(chip, ms_parse_err_code(chip));
86  }
87  } else { /* Write Packet */
88  if (CHK_MSPRO(ms_card) && !(*ptr & 0x80)) {
89  if (*ptr & (MS_INT_ERR | MS_INT_CMDNK)) {
90  ms_set_err_code(chip, MS_CMD_NK);
91  TRACE_RET(chip, ms_parse_err_code(chip));
92  }
93  }
94  }
95 
96  if (*ptr & MS_RDY_TIMEOUT) {
97  rtsx_clear_ms_error(chip);
98  ms_set_err_code(chip, MS_TO_ERROR);
99  TRACE_RET(chip, ms_parse_err_code(chip));
100  }
101 
102  return STATUS_SUCCESS;
103 }
104 
105 static int ms_transfer_data(struct rtsx_chip *chip, u8 trans_mode, u8 tpc, u16 sec_cnt,
106  u8 cfg, int mode_2k, int use_sg, void *buf, int buf_len)
107 {
108  int retval;
109  u8 val, err_code = 0;
110  enum dma_data_direction dir;
111 
112  if (!buf || !buf_len)
113  TRACE_RET(chip, STATUS_FAIL);
114 
115  if (trans_mode == MS_TM_AUTO_READ) {
116  dir = DMA_FROM_DEVICE;
117  err_code = MS_FLASH_READ_ERROR;
118  } else if (trans_mode == MS_TM_AUTO_WRITE) {
119  dir = DMA_TO_DEVICE;
120  err_code = MS_FLASH_WRITE_ERROR;
121  } else {
122  TRACE_RET(chip, STATUS_FAIL);
123  }
124 
125  rtsx_init_cmd(chip);
126 
127  rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
128  rtsx_add_cmd(chip, WRITE_REG_CMD,
129  MS_SECTOR_CNT_H, 0xFF, (u8)(sec_cnt >> 8));
130  rtsx_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_L, 0xFF, (u8)sec_cnt);
131  rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
132 
133  if (mode_2k) {
134  rtsx_add_cmd(chip, WRITE_REG_CMD,
135  MS_CFG, MS_2K_SECTOR_MODE, MS_2K_SECTOR_MODE);
136  } else {
137  rtsx_add_cmd(chip, WRITE_REG_CMD, MS_CFG, MS_2K_SECTOR_MODE, 0);
138  }
139 
140  trans_dma_enable(dir, chip, sec_cnt * 512, DMA_512);
141 
142  rtsx_add_cmd(chip, WRITE_REG_CMD,
143  MS_TRANSFER, 0xFF, MS_TRANSFER_START | trans_mode);
144  rtsx_add_cmd(chip, CHECK_REG_CMD,
145  MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END);
146 
147  rtsx_send_cmd_no_wait(chip);
148 
149  retval = rtsx_transfer_data(chip, MS_CARD, buf, buf_len,
150  use_sg, dir, chip->mspro_timeout);
151  if (retval < 0) {
152  ms_set_err_code(chip, err_code);
153  if (retval == -ETIMEDOUT)
154  retval = STATUS_TIMEDOUT;
155  else
156  retval = STATUS_FAIL;
157 
158  TRACE_RET(chip, retval);
159  }
160 
161  RTSX_READ_REG(chip, MS_TRANS_CFG, &val);
162  if (val & (MS_INT_CMDNK | MS_INT_ERR | MS_CRC16_ERR | MS_RDY_TIMEOUT))
163  TRACE_RET(chip, STATUS_FAIL);
164 
165  return STATUS_SUCCESS;
166 }
167 
168 static int ms_write_bytes(struct rtsx_chip *chip,
169  u8 tpc, u8 cnt, u8 cfg, u8 *data, int data_len)
170 {
171  struct ms_info *ms_card = &(chip->ms_card);
172  int retval, i;
173 
174  if (!data || (data_len < cnt))
175  TRACE_RET(chip, STATUS_ERROR);
176 
177  rtsx_init_cmd(chip);
178 
179  for (i = 0; i < cnt; i++) {
180  rtsx_add_cmd(chip, WRITE_REG_CMD,
181  PPBUF_BASE2 + i, 0xFF, data[i]);
182  }
183  if (cnt % 2)
184  rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i, 0xFF, 0xFF);
185 
186  rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
187  rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
188  rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
189  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
190 
191  rtsx_add_cmd(chip, WRITE_REG_CMD,
192  MS_TRANSFER, 0xFF, MS_TRANSFER_START | MS_TM_WRITE_BYTES);
193  rtsx_add_cmd(chip, CHECK_REG_CMD,
194  MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END);
195 
196  retval = rtsx_send_cmd(chip, MS_CARD, 5000);
197  if (retval < 0) {
198  u8 val = 0;
199 
200  rtsx_read_register(chip, MS_TRANS_CFG, &val);
201  RTSX_DEBUGP("MS_TRANS_CFG: 0x%02x\n", val);
202 
203  rtsx_clear_ms_error(chip);
204 
205  if (!(tpc & 0x08)) {
206  if (val & MS_CRC16_ERR) {
207  ms_set_err_code(chip, MS_CRC16_ERROR);
208  TRACE_RET(chip, ms_parse_err_code(chip));
209  }
210  } else {
211  if (CHK_MSPRO(ms_card) && !(val & 0x80)) {
212  if (val & (MS_INT_ERR | MS_INT_CMDNK)) {
213  ms_set_err_code(chip, MS_CMD_NK);
214  TRACE_RET(chip, ms_parse_err_code(chip));
215  }
216  }
217  }
218 
219  if (val & MS_RDY_TIMEOUT) {
220  ms_set_err_code(chip, MS_TO_ERROR);
221  TRACE_RET(chip, ms_parse_err_code(chip));
222  }
223 
224  ms_set_err_code(chip, MS_TO_ERROR);
225  TRACE_RET(chip, ms_parse_err_code(chip));
226  }
227 
228  return STATUS_SUCCESS;
229 }
230 
231 static int ms_read_bytes(struct rtsx_chip *chip, u8 tpc, u8 cnt, u8 cfg, u8 *data, int data_len)
232 {
233  struct ms_info *ms_card = &(chip->ms_card);
234  int retval, i;
235  u8 *ptr;
236 
237  if (!data)
238  TRACE_RET(chip, STATUS_ERROR);
239 
240  rtsx_init_cmd(chip);
241 
242  rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
243  rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
244  rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
245  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
246 
247  rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, MS_TRANSFER_START | MS_TM_READ_BYTES);
248  rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END);
249 
250  for (i = 0; i < data_len - 1; i++)
251  rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + i, 0, 0);
252 
253  if (data_len % 2)
254  rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len, 0, 0);
255  else
256  rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len - 1, 0, 0);
257 
258  retval = rtsx_send_cmd(chip, MS_CARD, 5000);
259  if (retval < 0) {
260  u8 val = 0;
261 
262  rtsx_read_register(chip, MS_TRANS_CFG, &val);
263  rtsx_clear_ms_error(chip);
264 
265  if (!(tpc & 0x08)) {
266  if (val & MS_CRC16_ERR) {
267  ms_set_err_code(chip, MS_CRC16_ERROR);
268  TRACE_RET(chip, ms_parse_err_code(chip));
269  }
270  } else {
271  if (CHK_MSPRO(ms_card) && !(val & 0x80)) {
272  if (val & (MS_INT_ERR | MS_INT_CMDNK)) {
273  ms_set_err_code(chip, MS_CMD_NK);
274  TRACE_RET(chip, ms_parse_err_code(chip));
275  }
276  }
277  }
278 
279  if (val & MS_RDY_TIMEOUT) {
280  ms_set_err_code(chip, MS_TO_ERROR);
281  TRACE_RET(chip, ms_parse_err_code(chip));
282  }
283 
284  ms_set_err_code(chip, MS_TO_ERROR);
285  TRACE_RET(chip, ms_parse_err_code(chip));
286  }
287 
288  ptr = rtsx_get_cmd_data(chip) + 1;
289 
290  for (i = 0; i < data_len; i++)
291  data[i] = ptr[i];
292 
293  if ((tpc == PRO_READ_SHORT_DATA) && (data_len == 8)) {
294  RTSX_DEBUGP("Read format progress:\n");
295  RTSX_DUMP(ptr, cnt);
296  }
297 
298  return STATUS_SUCCESS;
299 }
300 
301 static int ms_set_rw_reg_addr(struct rtsx_chip *chip,
302  u8 read_start, u8 read_cnt, u8 write_start, u8 write_cnt)
303 {
304  int retval, i;
305  u8 data[4];
306 
307  data[0] = read_start;
308  data[1] = read_cnt;
309  data[2] = write_start;
310  data[3] = write_cnt;
311 
312  for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
313  retval = ms_write_bytes(chip, SET_RW_REG_ADRS, 4,
314  NO_WAIT_INT, data, 4);
315  if (retval == STATUS_SUCCESS)
316  return STATUS_SUCCESS;
317  rtsx_clear_ms_error(chip);
318  }
319 
320  TRACE_RET(chip, STATUS_FAIL);
321 }
322 
323 static int ms_send_cmd(struct rtsx_chip *chip, u8 cmd, u8 cfg)
324 {
325  u8 data[2];
326 
327  data[0] = cmd;
328  data[1] = 0;
329 
330  return ms_write_bytes(chip, PRO_SET_CMD, 1, cfg, data, 1);
331 }
332 
333 static int ms_set_init_para(struct rtsx_chip *chip)
334 {
335  struct ms_info *ms_card = &(chip->ms_card);
336  int retval;
337 
338  if (CHK_HG8BIT(ms_card)) {
339  if (chip->asic_code)
340  ms_card->ms_clock = chip->asic_ms_hg_clk;
341  else
342  ms_card->ms_clock = chip->fpga_ms_hg_clk;
343 
344  } else if (CHK_MSPRO(ms_card) || CHK_MS4BIT(ms_card)) {
345  if (chip->asic_code)
346  ms_card->ms_clock = chip->asic_ms_4bit_clk;
347  else
348  ms_card->ms_clock = chip->fpga_ms_4bit_clk;
349 
350  } else {
351  if (chip->asic_code)
352  ms_card->ms_clock = chip->asic_ms_1bit_clk;
353  else
354  ms_card->ms_clock = chip->fpga_ms_1bit_clk;
355  }
356 
357  retval = switch_clock(chip, ms_card->ms_clock);
358  if (retval != STATUS_SUCCESS)
359  TRACE_RET(chip, STATUS_FAIL);
360 
361  retval = select_card(chip, MS_CARD);
362  if (retval != STATUS_SUCCESS)
363  TRACE_RET(chip, STATUS_FAIL);
364 
365  return STATUS_SUCCESS;
366 }
367 
368 static int ms_switch_clock(struct rtsx_chip *chip)
369 {
370  struct ms_info *ms_card = &(chip->ms_card);
371  int retval;
372 
373  retval = select_card(chip, MS_CARD);
374  if (retval != STATUS_SUCCESS)
375  TRACE_RET(chip, STATUS_FAIL);
376 
377  retval = switch_clock(chip, ms_card->ms_clock);
378  if (retval != STATUS_SUCCESS)
379  TRACE_RET(chip, STATUS_FAIL);
380 
381  return STATUS_SUCCESS;
382 }
383 
384 static int ms_pull_ctl_disable(struct rtsx_chip *chip)
385 {
386  if (CHECK_PID(chip, 0x5209)) {
387  RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x55);
388  RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF, 0x55);
389  RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF, 0x15);
390  } else if (CHECK_PID(chip, 0x5208)) {
391  RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF,
392  MS_D1_PD | MS_D2_PD | MS_CLK_PD | MS_D6_PD);
393  RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF,
394  MS_D3_PD | MS_D0_PD | MS_BS_PD | XD_D4_PD);
395  RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF,
396  MS_D7_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
397  RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF,
398  XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD);
399  RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF,
400  MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
401  RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF,
402  MS_D5_PD | MS_D4_PD);
403  } else if (CHECK_PID(chip, 0x5288)) {
404  if (CHECK_BARO_PKG(chip, QFN)) {
405  RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55);
406  RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55);
407  RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0x4B);
408  RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x69);
409  }
410  }
411 
412  return STATUS_SUCCESS;
413 }
414 
415 static int ms_pull_ctl_enable(struct rtsx_chip *chip)
416 {
417  int retval;
418 
419  rtsx_init_cmd(chip);
420 
421  if (CHECK_PID(chip, 0x5209)) {
422  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
423  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
424  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x15);
425  } else if (CHECK_PID(chip, 0x5208)) {
426  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
427  MS_D1_PD | MS_D2_PD | MS_CLK_NP | MS_D6_PD);
428  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
429  MS_D3_PD | MS_D0_PD | MS_BS_NP | XD_D4_PD);
430  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
431  MS_D7_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
432  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
433  XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD);
434  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
435  MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
436  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF,
437  MS_D5_PD | MS_D4_PD);
438  } else if (CHECK_PID(chip, 0x5288)) {
439  if (CHECK_BARO_PKG(chip, QFN)) {
440  rtsx_add_cmd(chip, WRITE_REG_CMD,
441  CARD_PULL_CTL1, 0xFF, 0x55);
442  rtsx_add_cmd(chip, WRITE_REG_CMD,
443  CARD_PULL_CTL2, 0xFF, 0x45);
444  rtsx_add_cmd(chip, WRITE_REG_CMD,
445  CARD_PULL_CTL3, 0xFF, 0x4B);
446  rtsx_add_cmd(chip, WRITE_REG_CMD,
447  CARD_PULL_CTL4, 0xFF, 0x29);
448  }
449  }
450 
451  retval = rtsx_send_cmd(chip, MS_CARD, 100);
452  if (retval < 0)
453  TRACE_RET(chip, STATUS_FAIL);
454 
455  return STATUS_SUCCESS;
456 }
457 
458 static int ms_prepare_reset(struct rtsx_chip *chip)
459 {
460  struct ms_info *ms_card = &(chip->ms_card);
461  int retval;
462  u8 oc_mask = 0;
463 
464  ms_card->ms_type = 0;
465  ms_card->check_ms_flow = 0;
466  ms_card->switch_8bit_fail = 0;
467  ms_card->delay_write.delay_write_flag = 0;
468 
469  ms_card->pro_under_formatting = 0;
470 
471  retval = ms_power_off_card3v3(chip);
472  if (retval != STATUS_SUCCESS)
473  TRACE_RET(chip, STATUS_FAIL);
474 
475  if (!chip->ft2_fast_mode)
476  wait_timeout(250);
477 
478  retval = enable_card_clock(chip, MS_CARD);
479  if (retval != STATUS_SUCCESS)
480  TRACE_RET(chip, STATUS_FAIL);
481 
482  if (chip->asic_code) {
483  retval = ms_pull_ctl_enable(chip);
484  if (retval != STATUS_SUCCESS)
485  TRACE_RET(chip, STATUS_FAIL);
486  } else {
487  RTSX_WRITE_REG(chip, FPGA_PULL_CTL, FPGA_MS_PULL_CTL_BIT | 0x20, 0);
488  }
489 
490  if (!chip->ft2_fast_mode) {
491  retval = card_power_on(chip, MS_CARD);
492  if (retval != STATUS_SUCCESS)
493  TRACE_RET(chip, STATUS_FAIL);
494 
495  wait_timeout(150);
496 
497 #ifdef SUPPORT_OCP
498  if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
499  oc_mask = MS_OC_NOW | MS_OC_EVER;
500  else
501  oc_mask = SD_OC_NOW | SD_OC_EVER;
502 
503  if (chip->ocp_stat & oc_mask) {
504  RTSX_DEBUGP("Over current, OCPSTAT is 0x%x\n",
505  chip->ocp_stat);
506  TRACE_RET(chip, STATUS_FAIL);
507  }
508 #endif
509  }
510 
511  RTSX_WRITE_REG(chip, CARD_OE, MS_OUTPUT_EN, MS_OUTPUT_EN);
512 
513  if (chip->asic_code) {
514  RTSX_WRITE_REG(chip, MS_CFG, 0xFF,
515  SAMPLE_TIME_RISING | PUSH_TIME_DEFAULT |
516  NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1);
517  } else {
518  RTSX_WRITE_REG(chip, MS_CFG, 0xFF,
519  SAMPLE_TIME_FALLING | PUSH_TIME_DEFAULT |
520  NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1);
521  }
522  RTSX_WRITE_REG(chip, MS_TRANS_CFG, 0xFF, NO_WAIT_INT | NO_AUTO_READ_INT_REG);
523  RTSX_WRITE_REG(chip, CARD_STOP, MS_STOP | MS_CLR_ERR, MS_STOP | MS_CLR_ERR);
524 
525  retval = ms_set_init_para(chip);
526  if (retval != STATUS_SUCCESS)
527  TRACE_RET(chip, STATUS_FAIL);
528 
529  return STATUS_SUCCESS;
530 }
531 
532 static int ms_identify_media_type(struct rtsx_chip *chip, int switch_8bit_bus)
533 {
534  struct ms_info *ms_card = &(chip->ms_card);
535  int retval, i;
536  u8 val;
537 
538  retval = ms_set_rw_reg_addr(chip, Pro_StatusReg, 6, SystemParm, 1);
539  if (retval != STATUS_SUCCESS)
540  TRACE_RET(chip, STATUS_FAIL);
541 
542  for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
543  retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, READ_REG, 6, NO_WAIT_INT);
544  if (retval == STATUS_SUCCESS)
545  break;
546  }
547  if (i == MS_MAX_RETRY_COUNT)
548  TRACE_RET(chip, STATUS_FAIL);
549 
550  RTSX_READ_REG(chip, PPBUF_BASE2 + 2, &val);
551  RTSX_DEBUGP("Type register: 0x%x\n", val);
552  if (val != 0x01) {
553  if (val != 0x02)
554  ms_card->check_ms_flow = 1;
555 
556  TRACE_RET(chip, STATUS_FAIL);
557  }
558 
559  RTSX_READ_REG(chip, PPBUF_BASE2 + 4, &val);
560  RTSX_DEBUGP("Category register: 0x%x\n", val);
561  if (val != 0) {
562  ms_card->check_ms_flow = 1;
563  TRACE_RET(chip, STATUS_FAIL);
564  }
565 
566  RTSX_READ_REG(chip, PPBUF_BASE2 + 5, &val);
567  RTSX_DEBUGP("Class register: 0x%x\n", val);
568  if (val == 0) {
569  RTSX_READ_REG(chip, PPBUF_BASE2, &val);
570  if (val & WRT_PRTCT)
571  chip->card_wp |= MS_CARD;
572  else
573  chip->card_wp &= ~MS_CARD;
574 
575  } else if ((val == 0x01) || (val == 0x02) || (val == 0x03)) {
576  chip->card_wp |= MS_CARD;
577  } else {
578  ms_card->check_ms_flow = 1;
579  TRACE_RET(chip, STATUS_FAIL);
580  }
581 
582  ms_card->ms_type |= TYPE_MSPRO;
583 
584  RTSX_READ_REG(chip, PPBUF_BASE2 + 3, &val);
585  RTSX_DEBUGP("IF Mode register: 0x%x\n", val);
586  if (val == 0) {
587  ms_card->ms_type &= 0x0F;
588  } else if (val == 7) {
589  if (switch_8bit_bus)
590  ms_card->ms_type |= MS_HG;
591  else
592  ms_card->ms_type &= 0x0F;
593 
594  } else {
595  TRACE_RET(chip, STATUS_FAIL);
596  }
597 
598  return STATUS_SUCCESS;
599 }
600 
601 static int ms_confirm_cpu_startup(struct rtsx_chip *chip)
602 {
603  int retval, i, k;
604  u8 val;
605 
606  /* Confirm CPU StartUp */
607  k = 0;
608  do {
609  if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
610  ms_set_err_code(chip, MS_NO_CARD);
611  TRACE_RET(chip, STATUS_FAIL);
612  }
613 
614  for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
615  retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
616  if (retval == STATUS_SUCCESS)
617  break;
618  }
619  if (i == MS_MAX_RETRY_COUNT)
620  TRACE_RET(chip, STATUS_FAIL);
621 
622  if (k > 100)
623  TRACE_RET(chip, STATUS_FAIL);
624 
625  k++;
626  wait_timeout(100);
627  } while (!(val & INT_REG_CED));
628 
629  for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
630  retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
631  if (retval == STATUS_SUCCESS)
632  break;
633  }
634  if (i == MS_MAX_RETRY_COUNT)
635  TRACE_RET(chip, STATUS_FAIL);
636 
637  if (val & INT_REG_ERR) {
638  if (val & INT_REG_CMDNK)
639  chip->card_wp |= (MS_CARD);
640  else
641  TRACE_RET(chip, STATUS_FAIL);
642  }
643  /* -- end confirm CPU startup */
644 
645  return STATUS_SUCCESS;
646 }
647 
648 static int ms_switch_parallel_bus(struct rtsx_chip *chip)
649 {
650  int retval, i;
651  u8 data[2];
652 
653  data[0] = PARALLEL_4BIT_IF;
654  data[1] = 0;
655  for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
656  retval = ms_write_bytes(chip, WRITE_REG, 1, NO_WAIT_INT, data, 2);
657  if (retval == STATUS_SUCCESS)
658  break;
659  }
660  if (retval != STATUS_SUCCESS)
661  TRACE_RET(chip, STATUS_FAIL);
662 
663  return STATUS_SUCCESS;
664 }
665 
666 static int ms_switch_8bit_bus(struct rtsx_chip *chip)
667 {
668  struct ms_info *ms_card = &(chip->ms_card);
669  int retval, i;
670  u8 data[2];
671 
672  data[0] = PARALLEL_8BIT_IF;
673  data[1] = 0;
674  for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
675  retval = ms_write_bytes(chip, WRITE_REG, 1, NO_WAIT_INT, data, 2);
676  if (retval == STATUS_SUCCESS)
677  break;
678  }
679  if (retval != STATUS_SUCCESS)
680  TRACE_RET(chip, STATUS_FAIL);
681 
682  RTSX_WRITE_REG(chip, MS_CFG, 0x98, MS_BUS_WIDTH_8 | SAMPLE_TIME_FALLING);
683  ms_card->ms_type |= MS_8BIT;
684  retval = ms_set_init_para(chip);
685  if (retval != STATUS_SUCCESS)
686  TRACE_RET(chip, STATUS_FAIL);
687 
688  for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
689  retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT, 1, NO_WAIT_INT);
690  if (retval != STATUS_SUCCESS)
691  TRACE_RET(chip, STATUS_FAIL);
692  }
693 
694  return STATUS_SUCCESS;
695 }
696 
697 static int ms_pro_reset_flow(struct rtsx_chip *chip, int switch_8bit_bus)
698 {
699  struct ms_info *ms_card = &(chip->ms_card);
700  int retval, i;
701 
702  for (i = 0; i < 3; i++) {
703  retval = ms_prepare_reset(chip);
704  if (retval != STATUS_SUCCESS)
705  TRACE_RET(chip, STATUS_FAIL);
706 
707  retval = ms_identify_media_type(chip, switch_8bit_bus);
708  if (retval != STATUS_SUCCESS)
709  TRACE_RET(chip, STATUS_FAIL);
710 
711  retval = ms_confirm_cpu_startup(chip);
712  if (retval != STATUS_SUCCESS)
713  TRACE_RET(chip, STATUS_FAIL);
714 
715  retval = ms_switch_parallel_bus(chip);
716  if (retval != STATUS_SUCCESS) {
717  if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
718  ms_set_err_code(chip, MS_NO_CARD);
719  TRACE_RET(chip, STATUS_FAIL);
720  }
721  continue;
722  } else {
723  break;
724  }
725  }
726 
727  if (retval != STATUS_SUCCESS)
728  TRACE_RET(chip, STATUS_FAIL);
729 
730  /* Switch MS-PRO into Parallel mode */
731  RTSX_WRITE_REG(chip, MS_CFG, 0x18, MS_BUS_WIDTH_4);
732  RTSX_WRITE_REG(chip, MS_CFG, PUSH_TIME_ODD, PUSH_TIME_ODD);
733 
734  retval = ms_set_init_para(chip);
735  if (retval != STATUS_SUCCESS)
736  TRACE_RET(chip, STATUS_FAIL);
737 
738  /* If MSPro HG Card, We shall try to switch to 8-bit bus */
739  if (CHK_MSHG(ms_card) && chip->support_ms_8bit && switch_8bit_bus) {
740  retval = ms_switch_8bit_bus(chip);
741  if (retval != STATUS_SUCCESS) {
742  ms_card->switch_8bit_fail = 1;
743  TRACE_RET(chip, STATUS_FAIL);
744  }
745  }
746 
747  return STATUS_SUCCESS;
748 }
749 
750 #ifdef XC_POWERCLASS
751 static int msxc_change_power(struct rtsx_chip *chip, u8 mode)
752 {
753  int retval;
754  u8 buf[6];
755 
756  ms_cleanup_work(chip);
757 
758  retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6);
759  if (retval != STATUS_SUCCESS)
760  TRACE_RET(chip, STATUS_FAIL);
761 
762  buf[0] = 0;
763  buf[1] = mode;
764  buf[2] = 0;
765  buf[3] = 0;
766  buf[4] = 0;
767  buf[5] = 0;
768 
769  retval = ms_write_bytes(chip, PRO_WRITE_REG , 6, NO_WAIT_INT, buf, 6);
770  if (retval != STATUS_SUCCESS)
771  TRACE_RET(chip, STATUS_FAIL);
772 
773  retval = ms_send_cmd(chip, XC_CHG_POWER, WAIT_INT);
774  if (retval != STATUS_SUCCESS)
775  TRACE_RET(chip, STATUS_FAIL);
776 
777  RTSX_READ_REG(chip, MS_TRANS_CFG, buf);
778  if (buf[0] & (MS_INT_CMDNK | MS_INT_ERR))
779  TRACE_RET(chip, STATUS_FAIL);
780 
781  return STATUS_SUCCESS;
782 }
783 #endif
784 
785 static int ms_read_attribute_info(struct rtsx_chip *chip)
786 {
787  struct ms_info *ms_card = &(chip->ms_card);
788  int retval, i;
789  u8 val, *buf, class_code, device_type, sub_class, data[16];
790  u16 total_blk = 0, blk_size = 0;
791 #ifdef SUPPORT_MSXC
792  u32 xc_total_blk = 0, xc_blk_size = 0;
793 #endif
794  u32 sys_info_addr = 0, sys_info_size;
795 #ifdef SUPPORT_PCGL_1P18
796  u32 model_name_addr = 0, model_name_size;
797  int found_sys_info = 0, found_model_name = 0;
798 #endif
799 
800  retval = ms_set_rw_reg_addr(chip, Pro_IntReg, 2, Pro_SystemParm, 7);
801  if (retval != STATUS_SUCCESS)
802  TRACE_RET(chip, STATUS_FAIL);
803 
804  if (CHK_MS8BIT(ms_card))
805  data[0] = PARALLEL_8BIT_IF;
806  else
807  data[0] = PARALLEL_4BIT_IF;
808 
809  data[1] = 0;
810 
811  data[2] = 0x40;
812  data[3] = 0;
813  data[4] = 0;
814  data[5] = 0;
815  data[6] = 0;
816  data[7] = 0;
817 
818  for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
819  retval = ms_write_bytes(chip, PRO_WRITE_REG, 7, NO_WAIT_INT, data, 8);
820  if (retval == STATUS_SUCCESS)
821  break;
822  }
823  if (retval != STATUS_SUCCESS)
824  TRACE_RET(chip, STATUS_FAIL);
825 
826  buf = kmalloc(64 * 512, GFP_KERNEL);
827  if (buf == NULL)
828  TRACE_RET(chip, STATUS_ERROR);
829 
830  for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
831  retval = ms_send_cmd(chip, PRO_READ_ATRB, WAIT_INT);
832  if (retval != STATUS_SUCCESS)
833  continue;
834 
835  retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
836  if (retval != STATUS_SUCCESS) {
837  kfree(buf);
838  TRACE_RET(chip, STATUS_FAIL);
839  }
840  if (!(val & MS_INT_BREQ)) {
841  kfree(buf);
842  TRACE_RET(chip, STATUS_FAIL);
843  }
844  retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA,
845  0x40, WAIT_INT, 0, 0, buf, 64 * 512);
846  if (retval == STATUS_SUCCESS)
847  break;
848  else
849  rtsx_clear_ms_error(chip);
850  }
851  if (retval != STATUS_SUCCESS) {
852  kfree(buf);
853  TRACE_RET(chip, STATUS_FAIL);
854  }
855 
856  i = 0;
857  do {
858  retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
859  if (retval != STATUS_SUCCESS) {
860  kfree(buf);
861  TRACE_RET(chip, STATUS_FAIL);
862  }
863 
864  if ((val & MS_INT_CED) || !(val & MS_INT_BREQ))
865  break;
866 
867  retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ, PRO_READ_LONG_DATA, 0, WAIT_INT);
868  if (retval != STATUS_SUCCESS) {
869  kfree(buf);
870  TRACE_RET(chip, STATUS_FAIL);
871  }
872 
873  i++;
874  } while (i < 1024);
875 
876  if (retval != STATUS_SUCCESS) {
877  kfree(buf);
878  TRACE_RET(chip, STATUS_FAIL);
879  }
880 
881  if ((buf[0] != 0xa5) && (buf[1] != 0xc3)) {
882  /* Signature code is wrong */
883  kfree(buf);
884  TRACE_RET(chip, STATUS_FAIL);
885  }
886 
887  if ((buf[4] < 1) || (buf[4] > 12)) {
888  kfree(buf);
889  TRACE_RET(chip, STATUS_FAIL);
890  }
891 
892  for (i = 0; i < buf[4]; i++) {
893  int cur_addr_off = 16 + i * 12;
894 
895 #ifdef SUPPORT_MSXC
896  if ((buf[cur_addr_off + 8] == 0x10) || (buf[cur_addr_off + 8] == 0x13))
897 #else
898  if (buf[cur_addr_off + 8] == 0x10)
899 #endif
900  {
901  sys_info_addr = ((u32)buf[cur_addr_off + 0] << 24) |
902  ((u32)buf[cur_addr_off + 1] << 16) |
903  ((u32)buf[cur_addr_off + 2] << 8) | buf[cur_addr_off + 3];
904  sys_info_size = ((u32)buf[cur_addr_off + 4] << 24) |
905  ((u32)buf[cur_addr_off + 5] << 16) |
906  ((u32)buf[cur_addr_off + 6] << 8) | buf[cur_addr_off + 7];
907  RTSX_DEBUGP("sys_info_addr = 0x%x, sys_info_size = 0x%x\n",
908  sys_info_addr, sys_info_size);
909  if (sys_info_size != 96) {
910  kfree(buf);
911  TRACE_RET(chip, STATUS_FAIL);
912  }
913  if (sys_info_addr < 0x1A0) {
914  kfree(buf);
915  TRACE_RET(chip, STATUS_FAIL);
916  }
917  if ((sys_info_size + sys_info_addr) > 0x8000) {
918  kfree(buf);
919  TRACE_RET(chip, STATUS_FAIL);
920  }
921 
922 #ifdef SUPPORT_MSXC
923  if (buf[cur_addr_off + 8] == 0x13)
924  ms_card->ms_type |= MS_XC;
925 #endif
926 #ifdef SUPPORT_PCGL_1P18
927  found_sys_info = 1;
928 #else
929  break;
930 #endif
931  }
932 #ifdef SUPPORT_PCGL_1P18
933  if (buf[cur_addr_off + 8] == 0x15) {
934  model_name_addr = ((u32)buf[cur_addr_off + 0] << 24) |
935  ((u32)buf[cur_addr_off + 1] << 16) |
936  ((u32)buf[cur_addr_off + 2] << 8) | buf[cur_addr_off + 3];
937  model_name_size = ((u32)buf[cur_addr_off + 4] << 24) |
938  ((u32)buf[cur_addr_off + 5] << 16) |
939  ((u32)buf[cur_addr_off + 6] << 8) | buf[cur_addr_off + 7];
940  RTSX_DEBUGP("model_name_addr = 0x%x, model_name_size = 0x%x\n",
941  model_name_addr, model_name_size);
942  if (model_name_size != 48) {
943  kfree(buf);
944  TRACE_RET(chip, STATUS_FAIL);
945  }
946  if (model_name_addr < 0x1A0) {
947  kfree(buf);
948  TRACE_RET(chip, STATUS_FAIL);
949  }
950  if ((model_name_size + model_name_addr) > 0x8000) {
951  kfree(buf);
952  TRACE_RET(chip, STATUS_FAIL);
953  }
954 
955  found_model_name = 1;
956  }
957 
958  if (found_sys_info && found_model_name)
959  break;
960 #endif
961  }
962 
963  if (i == buf[4]) {
964  kfree(buf);
965  TRACE_RET(chip, STATUS_FAIL);
966  }
967 
968  class_code = buf[sys_info_addr + 0];
969  device_type = buf[sys_info_addr + 56];
970  sub_class = buf[sys_info_addr + 46];
971 #ifdef SUPPORT_MSXC
972  if (CHK_MSXC(ms_card)) {
973  xc_total_blk = ((u32)buf[sys_info_addr + 6] << 24) |
974  ((u32)buf[sys_info_addr + 7] << 16) |
975  ((u32)buf[sys_info_addr + 8] << 8) |
976  buf[sys_info_addr + 9];
977  xc_blk_size = ((u32)buf[sys_info_addr + 32] << 24) |
978  ((u32)buf[sys_info_addr + 33] << 16) |
979  ((u32)buf[sys_info_addr + 34] << 8) |
980  buf[sys_info_addr + 35];
981  RTSX_DEBUGP("xc_total_blk = 0x%x, xc_blk_size = 0x%x\n", xc_total_blk, xc_blk_size);
982  } else {
983  total_blk = ((u16)buf[sys_info_addr + 6] << 8) | buf[sys_info_addr + 7];
984  blk_size = ((u16)buf[sys_info_addr + 2] << 8) | buf[sys_info_addr + 3];
985  RTSX_DEBUGP("total_blk = 0x%x, blk_size = 0x%x\n", total_blk, blk_size);
986  }
987 #else
988  total_blk = ((u16)buf[sys_info_addr + 6] << 8) | buf[sys_info_addr + 7];
989  blk_size = ((u16)buf[sys_info_addr + 2] << 8) | buf[sys_info_addr + 3];
990  RTSX_DEBUGP("total_blk = 0x%x, blk_size = 0x%x\n", total_blk, blk_size);
991 #endif
992 
993  RTSX_DEBUGP("class_code = 0x%x, device_type = 0x%x, sub_class = 0x%x\n",
994  class_code, device_type, sub_class);
995 
996  memcpy(ms_card->raw_sys_info, buf + sys_info_addr, 96);
997 #ifdef SUPPORT_PCGL_1P18
998  memcpy(ms_card->raw_model_name, buf + model_name_addr, 48);
999 #endif
1000 
1001  kfree(buf);
1002 
1003 #ifdef SUPPORT_MSXC
1004  if (CHK_MSXC(ms_card)) {
1005  if (class_code != 0x03)
1006  TRACE_RET(chip, STATUS_FAIL);
1007  } else {
1008  if (class_code != 0x02)
1009  TRACE_RET(chip, STATUS_FAIL);
1010  }
1011 #else
1012  if (class_code != 0x02)
1013  TRACE_RET(chip, STATUS_FAIL);
1014 #endif
1015 
1016  if (device_type != 0x00) {
1017  if ((device_type == 0x01) || (device_type == 0x02) ||
1018  (device_type == 0x03)) {
1019  chip->card_wp |= MS_CARD;
1020  } else {
1021  TRACE_RET(chip, STATUS_FAIL);
1022  }
1023  }
1024 
1025  if (sub_class & 0xC0)
1026  TRACE_RET(chip, STATUS_FAIL);
1027 
1028  RTSX_DEBUGP("class_code: 0x%x, device_type: 0x%x, sub_class: 0x%x\n",
1029  class_code, device_type, sub_class);
1030 
1031 #ifdef SUPPORT_MSXC
1032  if (CHK_MSXC(ms_card)) {
1033  chip->capacity[chip->card2lun[MS_CARD]] =
1034  ms_card->capacity = xc_total_blk * xc_blk_size;
1035  } else {
1036  chip->capacity[chip->card2lun[MS_CARD]] =
1037  ms_card->capacity = total_blk * blk_size;
1038  }
1039 #else
1040  chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity = total_blk * blk_size;
1041 #endif
1042 
1043  return STATUS_SUCCESS;
1044 }
1045 
1046 #ifdef SUPPORT_MAGIC_GATE
1047 static int mg_set_tpc_para_sub(struct rtsx_chip *chip, int type, u8 mg_entry_num);
1048 #endif
1049 
1050 static int reset_ms_pro(struct rtsx_chip *chip)
1051 {
1052  struct ms_info *ms_card = &(chip->ms_card);
1053  int retval;
1054 #ifdef XC_POWERCLASS
1055  u8 change_power_class;
1056 
1057  if (chip->ms_power_class_en & 0x02)
1058  change_power_class = 2;
1059  else if (chip->ms_power_class_en & 0x01)
1060  change_power_class = 1;
1061  else
1062  change_power_class = 0;
1063 #endif
1064 
1065 #ifdef XC_POWERCLASS
1066 Retry:
1067 #endif
1068  retval = ms_pro_reset_flow(chip, 1);
1069  if (retval != STATUS_SUCCESS) {
1070  if (ms_card->switch_8bit_fail) {
1071  retval = ms_pro_reset_flow(chip, 0);
1072  if (retval != STATUS_SUCCESS)
1073  TRACE_RET(chip, STATUS_FAIL);
1074  } else {
1075  TRACE_RET(chip, STATUS_FAIL);
1076  }
1077  }
1078 
1079  retval = ms_read_attribute_info(chip);
1080  if (retval != STATUS_SUCCESS)
1081  TRACE_RET(chip, STATUS_FAIL);
1082 
1083 #ifdef XC_POWERCLASS
1084  if (CHK_HG8BIT(ms_card))
1085  change_power_class = 0;
1086 
1087  if (change_power_class && CHK_MSXC(ms_card)) {
1088  u8 power_class_en = chip->ms_power_class_en;
1089 
1090  RTSX_DEBUGP("power_class_en = 0x%x\n", power_class_en);
1091  RTSX_DEBUGP("change_power_class = %d\n", change_power_class);
1092 
1093  if (change_power_class)
1094  power_class_en &= (1 << (change_power_class - 1));
1095  else
1096  power_class_en = 0;
1097 
1098  if (power_class_en) {
1099  u8 power_class_mode = (ms_card->raw_sys_info[46] & 0x18) >> 3;
1100  RTSX_DEBUGP("power_class_mode = 0x%x", power_class_mode);
1101  if (change_power_class > power_class_mode)
1102  change_power_class = power_class_mode;
1103  if (change_power_class) {
1104  retval = msxc_change_power(chip, change_power_class);
1105  if (retval != STATUS_SUCCESS) {
1106  change_power_class--;
1107  goto Retry;
1108  }
1109  }
1110  }
1111  }
1112 #endif
1113 
1114 #ifdef SUPPORT_MAGIC_GATE
1115  retval = mg_set_tpc_para_sub(chip, 0, 0);
1116  if (retval != STATUS_SUCCESS)
1117  TRACE_RET(chip, STATUS_FAIL);
1118 #endif
1119 
1120  if (CHK_HG8BIT(ms_card))
1121  chip->card_bus_width[chip->card2lun[MS_CARD]] = 8;
1122  else
1123  chip->card_bus_width[chip->card2lun[MS_CARD]] = 4;
1124 
1125  return STATUS_SUCCESS;
1126 }
1127 
1128 static int ms_read_status_reg(struct rtsx_chip *chip)
1129 {
1130  int retval;
1131  u8 val[2];
1132 
1133  retval = ms_set_rw_reg_addr(chip, StatusReg0, 2, 0, 0);
1134  if (retval != STATUS_SUCCESS)
1135  TRACE_RET(chip, STATUS_FAIL);
1136 
1137  retval = ms_read_bytes(chip, READ_REG, 2, NO_WAIT_INT, val, 2);
1138  if (retval != STATUS_SUCCESS)
1139  TRACE_RET(chip, STATUS_FAIL);
1140 
1141  if (val[1] & (STS_UCDT | STS_UCEX | STS_UCFG)) {
1142  ms_set_err_code(chip, MS_FLASH_READ_ERROR);
1143  TRACE_RET(chip, STATUS_FAIL);
1144  }
1145 
1146  return STATUS_SUCCESS;
1147 }
1148 
1149 
1150 static int ms_read_extra_data(struct rtsx_chip *chip,
1151  u16 block_addr, u8 page_num, u8 *buf, int buf_len)
1152 {
1153  struct ms_info *ms_card = &(chip->ms_card);
1154  int retval, i;
1155  u8 val, data[10];
1156 
1157  retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6);
1158  if (retval != STATUS_SUCCESS)
1159  TRACE_RET(chip, STATUS_FAIL);
1160 
1161  if (CHK_MS4BIT(ms_card)) {
1162  /* Parallel interface */
1163  data[0] = 0x88;
1164  } else {
1165  /* Serial interface */
1166  data[0] = 0x80;
1167  }
1168  data[1] = 0;
1169  data[2] = (u8)(block_addr >> 8);
1170  data[3] = (u8)block_addr;
1171  data[4] = 0x40;
1172  data[5] = page_num;
1173 
1174  for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
1175  retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6);
1176  if (retval == STATUS_SUCCESS)
1177  break;
1178  }
1179  if (i == MS_MAX_RETRY_COUNT)
1180  TRACE_RET(chip, STATUS_FAIL);
1181 
1182  ms_set_err_code(chip, MS_NO_ERROR);
1183 
1184  for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
1185  retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
1186  if (retval == STATUS_SUCCESS)
1187  break;
1188  }
1189  if (i == MS_MAX_RETRY_COUNT)
1190  TRACE_RET(chip, STATUS_FAIL);
1191 
1192  ms_set_err_code(chip, MS_NO_ERROR);
1193  retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1194  if (retval != STATUS_SUCCESS)
1195  TRACE_RET(chip, STATUS_FAIL);
1196 
1197  if (val & INT_REG_CMDNK) {
1198  ms_set_err_code(chip, MS_CMD_NK);
1199  TRACE_RET(chip, STATUS_FAIL);
1200  }
1201  if (val & INT_REG_CED) {
1202  if (val & INT_REG_ERR) {
1203  retval = ms_read_status_reg(chip);
1204  if (retval != STATUS_SUCCESS)
1205  TRACE_RET(chip, STATUS_FAIL);
1206 
1207  retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6);
1208  if (retval != STATUS_SUCCESS)
1209  TRACE_RET(chip, STATUS_FAIL);
1210  }
1211  }
1212 
1213  retval = ms_read_bytes(chip, READ_REG, MS_EXTRA_SIZE, NO_WAIT_INT, data, MS_EXTRA_SIZE);
1214  if (retval != STATUS_SUCCESS)
1215  TRACE_RET(chip, STATUS_FAIL);
1216 
1217  if (buf && buf_len) {
1218  if (buf_len > MS_EXTRA_SIZE)
1219  buf_len = MS_EXTRA_SIZE;
1220  memcpy(buf, data, buf_len);
1221  }
1222 
1223  return STATUS_SUCCESS;
1224 }
1225 
1226 static int ms_write_extra_data(struct rtsx_chip *chip,
1227  u16 block_addr, u8 page_num, u8 *buf, int buf_len)
1228 {
1229  struct ms_info *ms_card = &(chip->ms_card);
1230  int retval, i;
1231  u8 val, data[16];
1232 
1233  if (!buf || (buf_len < MS_EXTRA_SIZE))
1234  TRACE_RET(chip, STATUS_FAIL);
1235 
1236  retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6 + MS_EXTRA_SIZE);
1237  if (retval != STATUS_SUCCESS)
1238  TRACE_RET(chip, STATUS_FAIL);
1239 
1240  if (CHK_MS4BIT(ms_card))
1241  data[0] = 0x88;
1242  else
1243  data[0] = 0x80;
1244 
1245  data[1] = 0;
1246  data[2] = (u8)(block_addr >> 8);
1247  data[3] = (u8)block_addr;
1248  data[4] = 0x40;
1249  data[5] = page_num;
1250 
1251  for (i = 6; i < MS_EXTRA_SIZE + 6; i++)
1252  data[i] = buf[i - 6];
1253 
1254  retval = ms_write_bytes(chip, WRITE_REG , (6+MS_EXTRA_SIZE), NO_WAIT_INT, data, 16);
1255  if (retval != STATUS_SUCCESS)
1256  TRACE_RET(chip, STATUS_FAIL);
1257 
1258  retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
1259  if (retval != STATUS_SUCCESS)
1260  TRACE_RET(chip, STATUS_FAIL);
1261 
1262  ms_set_err_code(chip, MS_NO_ERROR);
1263  retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1264  if (retval != STATUS_SUCCESS)
1265  TRACE_RET(chip, STATUS_FAIL);
1266 
1267  if (val & INT_REG_CMDNK) {
1268  ms_set_err_code(chip, MS_CMD_NK);
1269  TRACE_RET(chip, STATUS_FAIL);
1270  }
1271  if (val & INT_REG_CED) {
1272  if (val & INT_REG_ERR) {
1273  ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1274  TRACE_RET(chip, STATUS_FAIL);
1275  }
1276  }
1277 
1278  return STATUS_SUCCESS;
1279 }
1280 
1281 
1282 static int ms_read_page(struct rtsx_chip *chip, u16 block_addr, u8 page_num)
1283 {
1284  struct ms_info *ms_card = &(chip->ms_card);
1285  int retval;
1286  u8 val, data[6];
1287 
1288  retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6);
1289  if (retval != STATUS_SUCCESS)
1290  TRACE_RET(chip, STATUS_FAIL);
1291 
1292  if (CHK_MS4BIT(ms_card))
1293  data[0] = 0x88;
1294  else
1295  data[0] = 0x80;
1296 
1297  data[1] = 0;
1298  data[2] = (u8)(block_addr >> 8);
1299  data[3] = (u8)block_addr;
1300  data[4] = 0x20;
1301  data[5] = page_num;
1302 
1303  retval = ms_write_bytes(chip, WRITE_REG , 6, NO_WAIT_INT, data, 6);
1304  if (retval != STATUS_SUCCESS)
1305  TRACE_RET(chip, STATUS_FAIL);
1306 
1307  retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
1308  if (retval != STATUS_SUCCESS)
1309  TRACE_RET(chip, STATUS_FAIL);
1310 
1311  ms_set_err_code(chip, MS_NO_ERROR);
1312  retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1313  if (retval != STATUS_SUCCESS)
1314  TRACE_RET(chip, STATUS_FAIL);
1315 
1316  if (val & INT_REG_CMDNK) {
1317  ms_set_err_code(chip, MS_CMD_NK);
1318  TRACE_RET(chip, STATUS_FAIL);
1319  }
1320 
1321  if (val & INT_REG_CED) {
1322  if (val & INT_REG_ERR) {
1323  if (!(val & INT_REG_BREQ)) {
1324  ms_set_err_code(chip, MS_FLASH_READ_ERROR);
1325  TRACE_RET(chip, STATUS_FAIL);
1326  }
1327  retval = ms_read_status_reg(chip);
1328  if (retval != STATUS_SUCCESS)
1329  ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1330 
1331  } else {
1332  if (!(val & INT_REG_BREQ)) {
1333  ms_set_err_code(chip, MS_BREQ_ERROR);
1334  TRACE_RET(chip, STATUS_FAIL);
1335  }
1336  }
1337  }
1338 
1339  retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ, READ_PAGE_DATA, 0, NO_WAIT_INT);
1340  if (retval != STATUS_SUCCESS)
1341  TRACE_RET(chip, STATUS_FAIL);
1342 
1343  if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR))
1344  TRACE_RET(chip, STATUS_FAIL);
1345 
1346  return STATUS_SUCCESS;
1347 }
1348 
1349 
1350 static int ms_set_bad_block(struct rtsx_chip *chip, u16 phy_blk)
1351 {
1352  struct ms_info *ms_card = &(chip->ms_card);
1353  int retval;
1354  u8 val, data[8], extra[MS_EXTRA_SIZE];
1355 
1356  retval = ms_read_extra_data(chip, phy_blk, 0, extra, MS_EXTRA_SIZE);
1357  if (retval != STATUS_SUCCESS)
1358  TRACE_RET(chip, STATUS_FAIL);
1359 
1360  retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 7);
1361  if (retval != STATUS_SUCCESS)
1362  TRACE_RET(chip, STATUS_FAIL);
1363 
1364  ms_set_err_code(chip, MS_NO_ERROR);
1365 
1366  if (CHK_MS4BIT(ms_card))
1367  data[0] = 0x88;
1368  else
1369  data[0] = 0x80;
1370 
1371  data[1] = 0;
1372  data[2] = (u8)(phy_blk >> 8);
1373  data[3] = (u8)phy_blk;
1374  data[4] = 0x80;
1375  data[5] = 0;
1376  data[6] = extra[0] & 0x7F;
1377  data[7] = 0xFF;
1378 
1379  retval = ms_write_bytes(chip, WRITE_REG , 7, NO_WAIT_INT, data, 7);
1380  if (retval != STATUS_SUCCESS)
1381  TRACE_RET(chip, STATUS_FAIL);
1382 
1383  retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
1384  if (retval != STATUS_SUCCESS)
1385  TRACE_RET(chip, STATUS_FAIL);
1386 
1387  ms_set_err_code(chip, MS_NO_ERROR);
1388  retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1389  if (retval != STATUS_SUCCESS)
1390  TRACE_RET(chip, STATUS_FAIL);
1391 
1392  if (val & INT_REG_CMDNK) {
1393  ms_set_err_code(chip, MS_CMD_NK);
1394  TRACE_RET(chip, STATUS_FAIL);
1395  }
1396 
1397  if (val & INT_REG_CED) {
1398  if (val & INT_REG_ERR) {
1399  ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1400  TRACE_RET(chip, STATUS_FAIL);
1401  }
1402  }
1403 
1404  return STATUS_SUCCESS;
1405 }
1406 
1407 
1408 static int ms_erase_block(struct rtsx_chip *chip, u16 phy_blk)
1409 {
1410  struct ms_info *ms_card = &(chip->ms_card);
1411  int retval, i = 0;
1412  u8 val, data[6];
1413 
1414  retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6);
1415  if (retval != STATUS_SUCCESS)
1416  TRACE_RET(chip, STATUS_FAIL);
1417 
1418  ms_set_err_code(chip, MS_NO_ERROR);
1419 
1420  if (CHK_MS4BIT(ms_card))
1421  data[0] = 0x88;
1422  else
1423  data[0] = 0x80;
1424 
1425  data[1] = 0;
1426  data[2] = (u8)(phy_blk >> 8);
1427  data[3] = (u8)phy_blk;
1428  data[4] = 0;
1429  data[5] = 0;
1430 
1431  retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6);
1432  if (retval != STATUS_SUCCESS)
1433  TRACE_RET(chip, STATUS_FAIL);
1434 
1435 ERASE_RTY:
1436  retval = ms_send_cmd(chip, BLOCK_ERASE, WAIT_INT);
1437  if (retval != STATUS_SUCCESS)
1438  TRACE_RET(chip, STATUS_FAIL);
1439 
1440  ms_set_err_code(chip, MS_NO_ERROR);
1441  retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1442  if (retval != STATUS_SUCCESS)
1443  TRACE_RET(chip, STATUS_FAIL);
1444 
1445  if (val & INT_REG_CMDNK) {
1446  if (i < 3) {
1447  i++;
1448  goto ERASE_RTY;
1449  }
1450 
1451  ms_set_err_code(chip, MS_CMD_NK);
1452  ms_set_bad_block(chip, phy_blk);
1453  TRACE_RET(chip, STATUS_FAIL);
1454  }
1455 
1456  if (val & INT_REG_CED) {
1457  if (val & INT_REG_ERR) {
1458  ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1459  TRACE_RET(chip, STATUS_FAIL);
1460  }
1461  }
1462 
1463  return STATUS_SUCCESS;
1464 }
1465 
1466 
1467 static void ms_set_page_status(u16 log_blk, u8 type, u8 *extra, int extra_len)
1468 {
1469  if (!extra || (extra_len < MS_EXTRA_SIZE))
1470  return;
1471 
1472  memset(extra, 0xFF, MS_EXTRA_SIZE);
1473 
1474  if (type == setPS_NG) {
1475  /* set page status as 1:NG,and block status keep 1:OK */
1476  extra[0] = 0xB8;
1477  } else {
1478  /* set page status as 0:Data Error,and block status keep 1:OK */
1479  extra[0] = 0x98;
1480  }
1481 
1482  extra[2] = (u8)(log_blk >> 8);
1483  extra[3] = (u8)log_blk;
1484 }
1485 
1486 static int ms_init_page(struct rtsx_chip *chip, u16 phy_blk, u16 log_blk, u8 start_page, u8 end_page)
1487 {
1488  int retval;
1489  u8 extra[MS_EXTRA_SIZE], i;
1490 
1491  memset(extra, 0xff, MS_EXTRA_SIZE);
1492 
1493  extra[0] = 0xf8; /* Block, page OK, data erased */
1494  extra[1] = 0xff;
1495  extra[2] = (u8)(log_blk >> 8);
1496  extra[3] = (u8)log_blk;
1497 
1498  for (i = start_page; i < end_page; i++) {
1499  if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
1500  ms_set_err_code(chip, MS_NO_CARD);
1501  TRACE_RET(chip, STATUS_FAIL);
1502  }
1503 
1504  retval = ms_write_extra_data(chip, phy_blk, i, extra, MS_EXTRA_SIZE);
1505  if (retval != STATUS_SUCCESS)
1506  TRACE_RET(chip, STATUS_FAIL);
1507  }
1508 
1509  return STATUS_SUCCESS;
1510 }
1511 
1512 static int ms_copy_page(struct rtsx_chip *chip, u16 old_blk, u16 new_blk,
1513  u16 log_blk, u8 start_page, u8 end_page)
1514 {
1515  struct ms_info *ms_card = &(chip->ms_card);
1516  int retval, rty_cnt, uncorrect_flag = 0;
1517  u8 extra[MS_EXTRA_SIZE], val, i, j, data[16];
1518 
1519  RTSX_DEBUGP("Copy page from 0x%x to 0x%x, logical block is 0x%x\n",
1520  old_blk, new_blk, log_blk);
1521  RTSX_DEBUGP("start_page = %d, end_page = %d\n", start_page, end_page);
1522 
1523  retval = ms_read_extra_data(chip, new_blk, 0, extra, MS_EXTRA_SIZE);
1524  if (retval != STATUS_SUCCESS)
1525  TRACE_RET(chip, STATUS_FAIL);
1526 
1527  retval = ms_read_status_reg(chip);
1528  if (retval != STATUS_SUCCESS)
1529  TRACE_RET(chip, STATUS_FAIL);
1530 
1531  RTSX_READ_REG(chip, PPBUF_BASE2, &val);
1532 
1533  if (val & BUF_FULL) {
1534  retval = ms_send_cmd(chip, CLEAR_BUF, WAIT_INT);
1535  if (retval != STATUS_SUCCESS)
1536  TRACE_RET(chip, STATUS_FAIL);
1537 
1538  retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1539  if (retval != STATUS_SUCCESS)
1540  TRACE_RET(chip, STATUS_FAIL);
1541 
1542  if (!(val & INT_REG_CED)) {
1543  ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1544  TRACE_RET(chip, STATUS_FAIL);
1545  }
1546  }
1547 
1548  for (i = start_page; i < end_page; i++) {
1549  if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
1550  ms_set_err_code(chip, MS_NO_CARD);
1551  TRACE_RET(chip, STATUS_FAIL);
1552  }
1553 
1554  ms_read_extra_data(chip, old_blk, i, extra, MS_EXTRA_SIZE);
1555 
1556  retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6);
1557  if (retval != STATUS_SUCCESS)
1558  TRACE_RET(chip, STATUS_FAIL);
1559 
1560  ms_set_err_code(chip, MS_NO_ERROR);
1561 
1562  if (CHK_MS4BIT(ms_card))
1563  data[0] = 0x88;
1564  else
1565  data[0] = 0x80;
1566 
1567  data[1] = 0;
1568  data[2] = (u8)(old_blk >> 8);
1569  data[3] = (u8)old_blk;
1570  data[4] = 0x20;
1571  data[5] = i;
1572 
1573  retval = ms_write_bytes(chip, WRITE_REG , 6, NO_WAIT_INT, data, 6);
1574  if (retval != STATUS_SUCCESS)
1575  TRACE_RET(chip, STATUS_FAIL);
1576 
1577  retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
1578  if (retval != STATUS_SUCCESS)
1579  TRACE_RET(chip, STATUS_FAIL);
1580 
1581  ms_set_err_code(chip, MS_NO_ERROR);
1582  retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1583  if (retval != STATUS_SUCCESS)
1584  TRACE_RET(chip, STATUS_FAIL);
1585 
1586  if (val & INT_REG_CMDNK) {
1587  ms_set_err_code(chip, MS_CMD_NK);
1588  TRACE_RET(chip, STATUS_FAIL);
1589  }
1590 
1591  if (val & INT_REG_CED) {
1592  if (val & INT_REG_ERR) {
1593  retval = ms_read_status_reg(chip);
1594  if (retval != STATUS_SUCCESS) {
1595  uncorrect_flag = 1;
1596  RTSX_DEBUGP("Uncorrectable error\n");
1597  } else {
1598  uncorrect_flag = 0;
1599  }
1600 
1601  retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ, READ_PAGE_DATA, 0, NO_WAIT_INT);
1602  if (retval != STATUS_SUCCESS)
1603  TRACE_RET(chip, STATUS_FAIL);
1604 
1605  if (uncorrect_flag) {
1606  ms_set_page_status(log_blk, setPS_NG, extra, MS_EXTRA_SIZE);
1607  if (i == 0)
1608  extra[0] &= 0xEF;
1609 
1610  ms_write_extra_data(chip, old_blk, i, extra, MS_EXTRA_SIZE);
1611  RTSX_DEBUGP("page %d : extra[0] = 0x%x\n", i, extra[0]);
1612  MS_SET_BAD_BLOCK_FLG(ms_card);
1613 
1614  ms_set_page_status(log_blk, setPS_Error, extra, MS_EXTRA_SIZE);
1615  ms_write_extra_data(chip, new_blk, i, extra, MS_EXTRA_SIZE);
1616  continue;
1617  }
1618 
1619  for (rty_cnt = 0; rty_cnt < MS_MAX_RETRY_COUNT; rty_cnt++) {
1620  retval = ms_transfer_tpc(chip, MS_TM_NORMAL_WRITE,
1621  WRITE_PAGE_DATA, 0, NO_WAIT_INT);
1622  if (retval == STATUS_SUCCESS)
1623  break;
1624  }
1625  if (rty_cnt == MS_MAX_RETRY_COUNT)
1626  TRACE_RET(chip, STATUS_FAIL);
1627  }
1628 
1629  if (!(val & INT_REG_BREQ)) {
1630  ms_set_err_code(chip, MS_BREQ_ERROR);
1631  TRACE_RET(chip, STATUS_FAIL);
1632  }
1633  }
1634 
1635  retval = ms_set_rw_reg_addr(chip, OverwriteFlag,
1636  MS_EXTRA_SIZE, SystemParm, (6+MS_EXTRA_SIZE));
1637 
1638  ms_set_err_code(chip, MS_NO_ERROR);
1639 
1640  if (CHK_MS4BIT(ms_card))
1641  data[0] = 0x88;
1642  else
1643  data[0] = 0x80;
1644 
1645  data[1] = 0;
1646  data[2] = (u8)(new_blk >> 8);
1647  data[3] = (u8)new_blk;
1648  data[4] = 0x20;
1649  data[5] = i;
1650 
1651  if ((extra[0] & 0x60) != 0x60)
1652  data[6] = extra[0];
1653  else
1654  data[6] = 0xF8;
1655 
1656  data[6 + 1] = 0xFF;
1657  data[6 + 2] = (u8)(log_blk >> 8);
1658  data[6 + 3] = (u8)log_blk;
1659 
1660  for (j = 4; j <= MS_EXTRA_SIZE; j++)
1661  data[6 + j] = 0xFF;
1662 
1663  retval = ms_write_bytes(chip, WRITE_REG, (6 + MS_EXTRA_SIZE), NO_WAIT_INT, data, 16);
1664  if (retval != STATUS_SUCCESS)
1665  TRACE_RET(chip, STATUS_FAIL);
1666 
1667  retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
1668  if (retval != STATUS_SUCCESS)
1669  TRACE_RET(chip, STATUS_FAIL);
1670 
1671  ms_set_err_code(chip, MS_NO_ERROR);
1672  retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1673  if (retval != STATUS_SUCCESS)
1674  TRACE_RET(chip, STATUS_FAIL);
1675 
1676  if (val & INT_REG_CMDNK) {
1677  ms_set_err_code(chip, MS_CMD_NK);
1678  TRACE_RET(chip, STATUS_FAIL);
1679  }
1680 
1681  if (val & INT_REG_CED) {
1682  if (val & INT_REG_ERR) {
1683  ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1684  TRACE_RET(chip, STATUS_FAIL);
1685  }
1686  }
1687 
1688  if (i == 0) {
1689  retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 7);
1690  if (retval != STATUS_SUCCESS)
1691  TRACE_RET(chip, STATUS_FAIL);
1692 
1693  ms_set_err_code(chip, MS_NO_ERROR);
1694 
1695  if (CHK_MS4BIT(ms_card))
1696  data[0] = 0x88;
1697  else
1698  data[0] = 0x80;
1699 
1700  data[1] = 0;
1701  data[2] = (u8)(old_blk >> 8);
1702  data[3] = (u8)old_blk;
1703  data[4] = 0x80;
1704  data[5] = 0;
1705  data[6] = 0xEF;
1706  data[7] = 0xFF;
1707 
1708  retval = ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT, data, 8);
1709  if (retval != STATUS_SUCCESS)
1710  TRACE_RET(chip, STATUS_FAIL);
1711 
1712  retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
1713  if (retval != STATUS_SUCCESS)
1714  TRACE_RET(chip, STATUS_FAIL);
1715 
1716  ms_set_err_code(chip, MS_NO_ERROR);
1717  retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1718  if (retval != STATUS_SUCCESS)
1719  TRACE_RET(chip, STATUS_FAIL);
1720 
1721  if (val & INT_REG_CMDNK) {
1722  ms_set_err_code(chip, MS_CMD_NK);
1723  TRACE_RET(chip, STATUS_FAIL);
1724  }
1725 
1726  if (val & INT_REG_CED) {
1727  if (val & INT_REG_ERR) {
1728  ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1729  TRACE_RET(chip, STATUS_FAIL);
1730  }
1731  }
1732  }
1733  }
1734 
1735  return STATUS_SUCCESS;
1736 }
1737 
1738 
1739 static int reset_ms(struct rtsx_chip *chip)
1740 {
1741  struct ms_info *ms_card = &(chip->ms_card);
1742  int retval;
1743  u16 i, reg_addr, block_size;
1744  u8 val, extra[MS_EXTRA_SIZE], j, *ptr;
1745 #ifndef SUPPORT_MAGIC_GATE
1746  u16 eblock_cnt;
1747 #endif
1748 
1749  retval = ms_prepare_reset(chip);
1750  if (retval != STATUS_SUCCESS)
1751  TRACE_RET(chip, STATUS_FAIL);
1752 
1753  ms_card->ms_type |= TYPE_MS;
1754 
1755  retval = ms_send_cmd(chip, MS_RESET, NO_WAIT_INT);
1756  if (retval != STATUS_SUCCESS)
1757  TRACE_RET(chip, STATUS_FAIL);
1758 
1759  retval = ms_read_status_reg(chip);
1760  if (retval != STATUS_SUCCESS)
1761  TRACE_RET(chip, STATUS_FAIL);
1762 
1763  RTSX_READ_REG(chip, PPBUF_BASE2, &val);
1764  if (val & WRT_PRTCT)
1765  chip->card_wp |= MS_CARD;
1766  else
1767  chip->card_wp &= ~MS_CARD;
1768 
1769  i = 0;
1770 
1771 RE_SEARCH:
1772  /* Search Boot Block */
1773  while (i < (MAX_DEFECTIVE_BLOCK + 2)) {
1774  if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
1775  ms_set_err_code(chip, MS_NO_CARD);
1776  TRACE_RET(chip, STATUS_FAIL);
1777  }
1778 
1779  retval = ms_read_extra_data(chip, i, 0, extra, MS_EXTRA_SIZE);
1780  if (retval != STATUS_SUCCESS) {
1781  i++;
1782  continue;
1783  }
1784 
1785  if (extra[0] & BLOCK_OK) {
1786  if (!(extra[1] & NOT_BOOT_BLOCK)) {
1787  ms_card->boot_block = i;
1788  break;
1789  }
1790  }
1791  i++;
1792  }
1793 
1794  if (i == (MAX_DEFECTIVE_BLOCK + 2)) {
1795  RTSX_DEBUGP("No boot block found!");
1796  TRACE_RET(chip, STATUS_FAIL);
1797  }
1798 
1799  for (j = 0; j < 3; j++) {
1800  retval = ms_read_page(chip, ms_card->boot_block, j);
1801  if (retval != STATUS_SUCCESS) {
1802  if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR)) {
1803  i = ms_card->boot_block + 1;
1804  ms_set_err_code(chip, MS_NO_ERROR);
1805  goto RE_SEARCH;
1806  }
1807  }
1808  }
1809 
1810  retval = ms_read_page(chip, ms_card->boot_block, 0);
1811  if (retval != STATUS_SUCCESS)
1812  TRACE_RET(chip, STATUS_FAIL);
1813 
1814  /* Read MS system information as sys_info */
1815  rtsx_init_cmd(chip);
1816 
1817  for (i = 0; i < 96; i++)
1818  rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 0x1A0 + i, 0, 0);
1819 
1820  retval = rtsx_send_cmd(chip, MS_CARD, 100);
1821  if (retval < 0)
1822  TRACE_RET(chip, STATUS_FAIL);
1823 
1824  ptr = rtsx_get_cmd_data(chip);
1825  memcpy(ms_card->raw_sys_info, ptr, 96);
1826 
1827  /* Read useful block contents */
1828  rtsx_init_cmd(chip);
1829 
1830  rtsx_add_cmd(chip, READ_REG_CMD, HEADER_ID0, 0, 0);
1831  rtsx_add_cmd(chip, READ_REG_CMD, HEADER_ID1, 0, 0);
1832 
1833  for (reg_addr = DISABLED_BLOCK0; reg_addr <= DISABLED_BLOCK3; reg_addr++)
1834  rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
1835 
1836  for (reg_addr = BLOCK_SIZE_0; reg_addr <= PAGE_SIZE_1; reg_addr++)
1837  rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
1838 
1839  rtsx_add_cmd(chip, READ_REG_CMD, MS_Device_Type, 0, 0);
1840  rtsx_add_cmd(chip, READ_REG_CMD, MS_4bit_Support, 0, 0);
1841 
1842  retval = rtsx_send_cmd(chip, MS_CARD, 100);
1843  if (retval < 0)
1844  TRACE_RET(chip, STATUS_FAIL);
1845 
1846  ptr = rtsx_get_cmd_data(chip);
1847 
1848  RTSX_DEBUGP("Boot block data:\n");
1849  RTSX_DUMP(ptr, 16);
1850 
1851  /* Block ID error
1852  * HEADER_ID0, HEADER_ID1
1853  */
1854  if (ptr[0] != 0x00 || ptr[1] != 0x01) {
1855  i = ms_card->boot_block + 1;
1856  goto RE_SEARCH;
1857  }
1858 
1859  /* Page size error
1860  * PAGE_SIZE_0, PAGE_SIZE_1
1861  */
1862  if (ptr[12] != 0x02 || ptr[13] != 0x00) {
1863  i = ms_card->boot_block + 1;
1864  goto RE_SEARCH;
1865  }
1866 
1867  if ((ptr[14] == 1) || (ptr[14] == 3))
1868  chip->card_wp |= MS_CARD;
1869 
1870  /* BLOCK_SIZE_0, BLOCK_SIZE_1 */
1871  block_size = ((u16)ptr[6] << 8) | ptr[7];
1872  if (block_size == 0x0010) {
1873  /* Block size 16KB */
1874  ms_card->block_shift = 5;
1875  ms_card->page_off = 0x1F;
1876  } else if (block_size == 0x0008) {
1877  /* Block size 8KB */
1878  ms_card->block_shift = 4;
1879  ms_card->page_off = 0x0F;
1880  }
1881 
1882  /* BLOCK_COUNT_0, BLOCK_COUNT_1 */
1883  ms_card->total_block = ((u16)ptr[8] << 8) | ptr[9];
1884 
1885 #ifdef SUPPORT_MAGIC_GATE
1886  j = ptr[10];
1887 
1888  if (ms_card->block_shift == 4) { /* 4MB or 8MB */
1889  if (j < 2) { /* Effective block for 4MB: 0x1F0 */
1890  ms_card->capacity = 0x1EE0;
1891  } else { /* Effective block for 8MB: 0x3E0 */
1892  ms_card->capacity = 0x3DE0;
1893  }
1894  } else { /* 16MB, 32MB, 64MB or 128MB */
1895  if (j < 5) { /* Effective block for 16MB: 0x3E0 */
1896  ms_card->capacity = 0x7BC0;
1897  } else if (j < 0xA) { /* Effective block for 32MB: 0x7C0 */
1898  ms_card->capacity = 0xF7C0;
1899  } else if (j < 0x11) { /* Effective block for 64MB: 0xF80 */
1900  ms_card->capacity = 0x1EF80;
1901  } else { /* Effective block for 128MB: 0x1F00 */
1902  ms_card->capacity = 0x3DF00;
1903  }
1904  }
1905 #else
1906  /* EBLOCK_COUNT_0, EBLOCK_COUNT_1 */
1907  eblock_cnt = ((u16)ptr[10] << 8) | ptr[11];
1908 
1909  ms_card->capacity = ((u32)eblock_cnt - 2) << ms_card->block_shift;
1910 #endif
1911 
1912  chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity;
1913 
1914  /* Switch I/F Mode */
1915  if (ptr[15]) {
1916  retval = ms_set_rw_reg_addr(chip, 0, 0, SystemParm, 1);
1917  if (retval != STATUS_SUCCESS)
1918  TRACE_RET(chip, STATUS_FAIL);
1919 
1920  RTSX_WRITE_REG(chip, PPBUF_BASE2, 0xFF, 0x88);
1921  RTSX_WRITE_REG(chip, PPBUF_BASE2 + 1, 0xFF, 0);
1922 
1923  retval = ms_transfer_tpc(chip, MS_TM_WRITE_BYTES, WRITE_REG , 1, NO_WAIT_INT);
1924  if (retval != STATUS_SUCCESS)
1925  TRACE_RET(chip, STATUS_FAIL);
1926 
1927  RTSX_WRITE_REG(chip, MS_CFG, 0x58 | MS_NO_CHECK_INT,
1928  MS_BUS_WIDTH_4 | PUSH_TIME_ODD | MS_NO_CHECK_INT);
1929 
1930  ms_card->ms_type |= MS_4BIT;
1931  }
1932 
1933  if (CHK_MS4BIT(ms_card))
1934  chip->card_bus_width[chip->card2lun[MS_CARD]] = 4;
1935  else
1936  chip->card_bus_width[chip->card2lun[MS_CARD]] = 1;
1937 
1938  return STATUS_SUCCESS;
1939 }
1940 
1941 static int ms_init_l2p_tbl(struct rtsx_chip *chip)
1942 {
1943  struct ms_info *ms_card = &(chip->ms_card);
1944  int size, i, seg_no, retval;
1945  u16 defect_block, reg_addr;
1946  u8 val1, val2;
1947 
1948  ms_card->segment_cnt = ms_card->total_block >> 9;
1949  RTSX_DEBUGP("ms_card->segment_cnt = %d\n", ms_card->segment_cnt);
1950 
1951  size = ms_card->segment_cnt * sizeof(struct zone_entry);
1952  ms_card->segment = vzalloc(size);
1953  if (ms_card->segment == NULL)
1954  TRACE_RET(chip, STATUS_FAIL);
1955 
1956  retval = ms_read_page(chip, ms_card->boot_block, 1);
1957  if (retval != STATUS_SUCCESS)
1958  TRACE_GOTO(chip, INIT_FAIL);
1959 
1960  reg_addr = PPBUF_BASE2;
1961  for (i = 0; i < (((ms_card->total_block >> 9) * 10) + 1); i++) {
1962  retval = rtsx_read_register(chip, reg_addr++, &val1);
1963  if (retval != STATUS_SUCCESS)
1964  TRACE_GOTO(chip, INIT_FAIL);
1965 
1966  retval = rtsx_read_register(chip, reg_addr++, &val2);
1967  if (retval != STATUS_SUCCESS)
1968  TRACE_GOTO(chip, INIT_FAIL);
1969 
1970  defect_block = ((u16)val1 << 8) | val2;
1971  if (defect_block == 0xFFFF)
1972  break;
1973 
1974  seg_no = defect_block / 512;
1975  ms_card->segment[seg_no].defect_list[ms_card->segment[seg_no].disable_count++] = defect_block;
1976  }
1977 
1978  for (i = 0; i < ms_card->segment_cnt; i++) {
1979  ms_card->segment[i].build_flag = 0;
1980  ms_card->segment[i].l2p_table = NULL;
1981  ms_card->segment[i].free_table = NULL;
1982  ms_card->segment[i].get_index = 0;
1983  ms_card->segment[i].set_index = 0;
1984  ms_card->segment[i].unused_blk_cnt = 0;
1985 
1986  RTSX_DEBUGP("defective block count of segment %d is %d\n",
1987  i, ms_card->segment[i].disable_count);
1988  }
1989 
1990  return STATUS_SUCCESS;
1991 
1992 INIT_FAIL:
1993  if (ms_card->segment) {
1994  vfree(ms_card->segment);
1995  ms_card->segment = NULL;
1996  }
1997 
1998  return STATUS_FAIL;
1999 }
2000 
2001 static u16 ms_get_l2p_tbl(struct rtsx_chip *chip, int seg_no, u16 log_off)
2002 {
2003  struct ms_info *ms_card = &(chip->ms_card);
2004  struct zone_entry *segment;
2005 
2006  if (ms_card->segment == NULL)
2007  return 0xFFFF;
2008 
2009  segment = &(ms_card->segment[seg_no]);
2010 
2011  if (segment->l2p_table)
2012  return segment->l2p_table[log_off];
2013 
2014  return 0xFFFF;
2015 }
2016 
2017 static void ms_set_l2p_tbl(struct rtsx_chip *chip, int seg_no, u16 log_off, u16 phy_blk)
2018 {
2019  struct ms_info *ms_card = &(chip->ms_card);
2020  struct zone_entry *segment;
2021 
2022  if (ms_card->segment == NULL)
2023  return;
2024 
2025  segment = &(ms_card->segment[seg_no]);
2026  if (segment->l2p_table)
2027  segment->l2p_table[log_off] = phy_blk;
2028 }
2029 
2030 static void ms_set_unused_block(struct rtsx_chip *chip, u16 phy_blk)
2031 {
2032  struct ms_info *ms_card = &(chip->ms_card);
2033  struct zone_entry *segment;
2034  int seg_no;
2035 
2036  seg_no = (int)phy_blk >> 9;
2037  segment = &(ms_card->segment[seg_no]);
2038 
2039  segment->free_table[segment->set_index++] = phy_blk;
2040  if (segment->set_index >= MS_FREE_TABLE_CNT)
2041  segment->set_index = 0;
2042 
2043  segment->unused_blk_cnt++;
2044 }
2045 
2046 static u16 ms_get_unused_block(struct rtsx_chip *chip, int seg_no)
2047 {
2048  struct ms_info *ms_card = &(chip->ms_card);
2049  struct zone_entry *segment;
2050  u16 phy_blk;
2051 
2052  segment = &(ms_card->segment[seg_no]);
2053 
2054  if (segment->unused_blk_cnt <= 0)
2055  return 0xFFFF;
2056 
2057  phy_blk = segment->free_table[segment->get_index];
2058  segment->free_table[segment->get_index++] = 0xFFFF;
2059  if (segment->get_index >= MS_FREE_TABLE_CNT)
2060  segment->get_index = 0;
2061 
2062  segment->unused_blk_cnt--;
2063 
2064  return phy_blk;
2065 }
2066 
2067 static const unsigned short ms_start_idx[] = {0, 494, 990, 1486, 1982, 2478, 2974, 3470,
2068  3966, 4462, 4958, 5454, 5950, 6446, 6942, 7438, 7934};
2069 
2070 static int ms_arbitrate_l2p(struct rtsx_chip *chip, u16 phy_blk, u16 log_off, u8 us1, u8 us2)
2071 {
2072  struct ms_info *ms_card = &(chip->ms_card);
2073  struct zone_entry *segment;
2074  int seg_no;
2075  u16 tmp_blk;
2076 
2077  seg_no = (int)phy_blk >> 9;
2078  segment = &(ms_card->segment[seg_no]);
2079  tmp_blk = segment->l2p_table[log_off];
2080 
2081  if (us1 != us2) {
2082  if (us1 == 0) {
2083  if (!(chip->card_wp & MS_CARD))
2084  ms_erase_block(chip, tmp_blk);
2085 
2086  ms_set_unused_block(chip, tmp_blk);
2087  segment->l2p_table[log_off] = phy_blk;
2088  } else {
2089  if (!(chip->card_wp & MS_CARD))
2090  ms_erase_block(chip, phy_blk);
2091 
2092  ms_set_unused_block(chip, phy_blk);
2093  }
2094  } else {
2095  if (phy_blk < tmp_blk) {
2096  if (!(chip->card_wp & MS_CARD))
2097  ms_erase_block(chip, phy_blk);
2098 
2099  ms_set_unused_block(chip, phy_blk);
2100  } else {
2101  if (!(chip->card_wp & MS_CARD))
2102  ms_erase_block(chip, tmp_blk);
2103 
2104  ms_set_unused_block(chip, tmp_blk);
2105  segment->l2p_table[log_off] = phy_blk;
2106  }
2107  }
2108 
2109  return STATUS_SUCCESS;
2110 }
2111 
2112 static int ms_build_l2p_tbl(struct rtsx_chip *chip, int seg_no)
2113 {
2114  struct ms_info *ms_card = &(chip->ms_card);
2115  struct zone_entry *segment;
2116  int retval, table_size, disable_cnt, defect_flag, i;
2117  u16 start, end, phy_blk, log_blk, tmp_blk;
2118  u8 extra[MS_EXTRA_SIZE], us1, us2;
2119 
2120  RTSX_DEBUGP("ms_build_l2p_tbl: %d\n", seg_no);
2121 
2122  if (ms_card->segment == NULL) {
2123  retval = ms_init_l2p_tbl(chip);
2124  if (retval != STATUS_SUCCESS)
2125  TRACE_RET(chip, retval);
2126  }
2127 
2128  if (ms_card->segment[seg_no].build_flag) {
2129  RTSX_DEBUGP("l2p table of segment %d has been built\n", seg_no);
2130  return STATUS_SUCCESS;
2131  }
2132 
2133  if (seg_no == 0)
2134  table_size = 494;
2135  else
2136  table_size = 496;
2137 
2138  segment = &(ms_card->segment[seg_no]);
2139 
2140  if (segment->l2p_table == NULL) {
2141  segment->l2p_table = (u16 *)vmalloc(table_size * 2);
2142  if (segment->l2p_table == NULL)
2143  TRACE_GOTO(chip, BUILD_FAIL);
2144  }
2145  memset((u8 *)(segment->l2p_table), 0xff, table_size * 2);
2146 
2147  if (segment->free_table == NULL) {
2148  segment->free_table = (u16 *)vmalloc(MS_FREE_TABLE_CNT * 2);
2149  if (segment->free_table == NULL)
2150  TRACE_GOTO(chip, BUILD_FAIL);
2151  }
2152  memset((u8 *)(segment->free_table), 0xff, MS_FREE_TABLE_CNT * 2);
2153 
2154  start = (u16)seg_no << 9;
2155  end = (u16)(seg_no + 1) << 9;
2156 
2157  disable_cnt = segment->disable_count;
2158 
2159  segment->get_index = segment->set_index = 0;
2160  segment->unused_blk_cnt = 0;
2161 
2162  for (phy_blk = start; phy_blk < end; phy_blk++) {
2163  if (disable_cnt) {
2164  defect_flag = 0;
2165  for (i = 0; i < segment->disable_count; i++) {
2166  if (phy_blk == segment->defect_list[i]) {
2167  defect_flag = 1;
2168  break;
2169  }
2170  }
2171  if (defect_flag) {
2172  disable_cnt--;
2173  continue;
2174  }
2175  }
2176 
2177  retval = ms_read_extra_data(chip, phy_blk, 0, extra, MS_EXTRA_SIZE);
2178  if (retval != STATUS_SUCCESS) {
2179  RTSX_DEBUGP("read extra data fail\n");
2180  ms_set_bad_block(chip, phy_blk);
2181  continue;
2182  }
2183 
2184  if (seg_no == ms_card->segment_cnt - 1) {
2185  if (!(extra[1] & NOT_TRANSLATION_TABLE)) {
2186  if (!(chip->card_wp & MS_CARD)) {
2187  retval = ms_erase_block(chip, phy_blk);
2188  if (retval != STATUS_SUCCESS)
2189  continue;
2190  extra[2] = 0xff;
2191  extra[3] = 0xff;
2192  }
2193  }
2194  }
2195 
2196  if (!(extra[0] & BLOCK_OK))
2197  continue;
2198  if (!(extra[1] & NOT_BOOT_BLOCK))
2199  continue;
2200  if ((extra[0] & PAGE_OK) != PAGE_OK)
2201  continue;
2202 
2203  log_blk = ((u16)extra[2] << 8) | extra[3];
2204 
2205  if (log_blk == 0xFFFF) {
2206  if (!(chip->card_wp & MS_CARD)) {
2207  retval = ms_erase_block(chip, phy_blk);
2208  if (retval != STATUS_SUCCESS)
2209  continue;
2210  }
2211  ms_set_unused_block(chip, phy_blk);
2212  continue;
2213  }
2214 
2215  if ((log_blk < ms_start_idx[seg_no]) ||
2216  (log_blk >= ms_start_idx[seg_no+1])) {
2217  if (!(chip->card_wp & MS_CARD)) {
2218  retval = ms_erase_block(chip, phy_blk);
2219  if (retval != STATUS_SUCCESS)
2220  continue;
2221  }
2222  ms_set_unused_block(chip, phy_blk);
2223  continue;
2224  }
2225 
2226  if (segment->l2p_table[log_blk - ms_start_idx[seg_no]] == 0xFFFF) {
2227  segment->l2p_table[log_blk - ms_start_idx[seg_no]] = phy_blk;
2228  continue;
2229  }
2230 
2231  us1 = extra[0] & 0x10;
2232  tmp_blk = segment->l2p_table[log_blk - ms_start_idx[seg_no]];
2233  retval = ms_read_extra_data(chip, tmp_blk, 0, extra, MS_EXTRA_SIZE);
2234  if (retval != STATUS_SUCCESS)
2235  continue;
2236  us2 = extra[0] & 0x10;
2237 
2238  (void)ms_arbitrate_l2p(chip, phy_blk, log_blk-ms_start_idx[seg_no], us1, us2);
2239  continue;
2240  }
2241 
2242  segment->build_flag = 1;
2243 
2244  RTSX_DEBUGP("unused block count: %d\n", segment->unused_blk_cnt);
2245 
2246  /* Logical Address Confirmation Process */
2247  if (seg_no == ms_card->segment_cnt - 1) {
2248  if (segment->unused_blk_cnt < 2)
2249  chip->card_wp |= MS_CARD;
2250  } else {
2251  if (segment->unused_blk_cnt < 1)
2252  chip->card_wp |= MS_CARD;
2253  }
2254 
2255  if (chip->card_wp & MS_CARD)
2256  return STATUS_SUCCESS;
2257 
2258  for (log_blk = ms_start_idx[seg_no]; log_blk < ms_start_idx[seg_no + 1]; log_blk++) {
2259  if (segment->l2p_table[log_blk-ms_start_idx[seg_no]] == 0xFFFF) {
2260  phy_blk = ms_get_unused_block(chip, seg_no);
2261  if (phy_blk == 0xFFFF) {
2262  chip->card_wp |= MS_CARD;
2263  return STATUS_SUCCESS;
2264  }
2265  retval = ms_init_page(chip, phy_blk, log_blk, 0, 1);
2266  if (retval != STATUS_SUCCESS)
2267  TRACE_GOTO(chip, BUILD_FAIL);
2268 
2269  segment->l2p_table[log_blk-ms_start_idx[seg_no]] = phy_blk;
2270  if (seg_no == ms_card->segment_cnt - 1) {
2271  if (segment->unused_blk_cnt < 2) {
2272  chip->card_wp |= MS_CARD;
2273  return STATUS_SUCCESS;
2274  }
2275  } else {
2276  if (segment->unused_blk_cnt < 1) {
2277  chip->card_wp |= MS_CARD;
2278  return STATUS_SUCCESS;
2279  }
2280  }
2281  }
2282  }
2283 
2284  /* Make boot block be the first normal block */
2285  if (seg_no == 0) {
2286  for (log_blk = 0; log_blk < 494; log_blk++) {
2287  tmp_blk = segment->l2p_table[log_blk];
2288  if (tmp_blk < ms_card->boot_block) {
2289  RTSX_DEBUGP("Boot block is not the first normal block.\n");
2290 
2291  if (chip->card_wp & MS_CARD)
2292  break;
2293 
2294  phy_blk = ms_get_unused_block(chip, 0);
2295  retval = ms_copy_page(chip, tmp_blk, phy_blk,
2296  log_blk, 0, ms_card->page_off + 1);
2297  if (retval != STATUS_SUCCESS)
2298  TRACE_RET(chip, STATUS_FAIL);
2299 
2300  segment->l2p_table[log_blk] = phy_blk;
2301 
2302  retval = ms_set_bad_block(chip, tmp_blk);
2303  if (retval != STATUS_SUCCESS)
2304  TRACE_RET(chip, STATUS_FAIL);
2305  }
2306  }
2307  }
2308 
2309  return STATUS_SUCCESS;
2310 
2311 BUILD_FAIL:
2312  segment->build_flag = 0;
2313  if (segment->l2p_table) {
2314  vfree(segment->l2p_table);
2315  segment->l2p_table = NULL;
2316  }
2317  if (segment->free_table) {
2318  vfree(segment->free_table);
2319  segment->free_table = NULL;
2320  }
2321 
2322  return STATUS_FAIL;
2323 }
2324 
2325 
2326 int reset_ms_card(struct rtsx_chip *chip)
2327 {
2328  struct ms_info *ms_card = &(chip->ms_card);
2329  int retval;
2330 
2331  memset(ms_card, 0, sizeof(struct ms_info));
2332 
2333  retval = enable_card_clock(chip, MS_CARD);
2334  if (retval != STATUS_SUCCESS)
2335  TRACE_RET(chip, STATUS_FAIL);
2336 
2337  retval = select_card(chip, MS_CARD);
2338  if (retval != STATUS_SUCCESS)
2339  TRACE_RET(chip, STATUS_FAIL);
2340 
2341  ms_card->ms_type = 0;
2342 
2343  retval = reset_ms_pro(chip);
2344  if (retval != STATUS_SUCCESS) {
2345  if (ms_card->check_ms_flow) {
2346  retval = reset_ms(chip);
2347  if (retval != STATUS_SUCCESS)
2348  TRACE_RET(chip, STATUS_FAIL);
2349  } else {
2350  TRACE_RET(chip, STATUS_FAIL);
2351  }
2352  }
2353 
2354  retval = ms_set_init_para(chip);
2355  if (retval != STATUS_SUCCESS)
2356  TRACE_RET(chip, STATUS_FAIL);
2357 
2358  if (!CHK_MSPRO(ms_card)) {
2359  /* Build table for the last segment,
2360  * to check if L2P table block exists, erasing it
2361  */
2362  retval = ms_build_l2p_tbl(chip, ms_card->total_block / 512 - 1);
2363  if (retval != STATUS_SUCCESS)
2364  TRACE_RET(chip, STATUS_FAIL);
2365  }
2366 
2367  RTSX_DEBUGP("ms_card->ms_type = 0x%x\n", ms_card->ms_type);
2368 
2369  return STATUS_SUCCESS;
2370 }
2371 
2372 static int mspro_set_rw_cmd(struct rtsx_chip *chip, u32 start_sec, u16 sec_cnt, u8 cmd)
2373 {
2374  int retval, i;
2375  u8 data[8];
2376 
2377  data[0] = cmd;
2378  data[1] = (u8)(sec_cnt >> 8);
2379  data[2] = (u8)sec_cnt;
2380  data[3] = (u8)(start_sec >> 24);
2381  data[4] = (u8)(start_sec >> 16);
2382  data[5] = (u8)(start_sec >> 8);
2383  data[6] = (u8)start_sec;
2384  data[7] = 0;
2385 
2386  for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
2387  retval = ms_write_bytes(chip, PRO_EX_SET_CMD, 7, WAIT_INT, data, 8);
2388  if (retval == STATUS_SUCCESS)
2389  break;
2390  }
2391  if (i == MS_MAX_RETRY_COUNT)
2392  TRACE_RET(chip, STATUS_FAIL);
2393 
2394  return STATUS_SUCCESS;
2395 }
2396 
2397 
2398 void mspro_stop_seq_mode(struct rtsx_chip *chip)
2399 {
2400  struct ms_info *ms_card = &(chip->ms_card);
2401  int retval;
2402 
2403  RTSX_DEBUGP("--%s--\n", __func__);
2404 
2405  if (ms_card->seq_mode) {
2406  retval = ms_switch_clock(chip);
2407  if (retval != STATUS_SUCCESS)
2408  return;
2409 
2410  ms_card->seq_mode = 0;
2411  ms_card->total_sec_cnt = 0;
2412  ms_send_cmd(chip, PRO_STOP, WAIT_INT);
2413 
2414  rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
2415  }
2416 }
2417 
2418 static inline int ms_auto_tune_clock(struct rtsx_chip *chip)
2419 {
2420  struct ms_info *ms_card = &(chip->ms_card);
2421  int retval;
2422 
2423  RTSX_DEBUGP("--%s--\n", __func__);
2424 
2425  if (chip->asic_code) {
2426  if (ms_card->ms_clock > 30)
2427  ms_card->ms_clock -= 20;
2428  } else {
2429  if (ms_card->ms_clock == CLK_80)
2430  ms_card->ms_clock = CLK_60;
2431  else if (ms_card->ms_clock == CLK_60)
2432  ms_card->ms_clock = CLK_40;
2433  }
2434 
2435  retval = ms_switch_clock(chip);
2436  if (retval != STATUS_SUCCESS)
2437  TRACE_RET(chip, STATUS_FAIL);
2438 
2439  return STATUS_SUCCESS;
2440 }
2441 
2442 static int mspro_rw_multi_sector(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector, u16 sector_cnt)
2443 {
2444  struct ms_info *ms_card = &(chip->ms_card);
2445  int retval, mode_2k = 0;
2446  u16 count;
2447  u8 val, trans_mode, rw_tpc, rw_cmd;
2448 
2449  ms_set_err_code(chip, MS_NO_ERROR);
2450 
2451  ms_card->cleanup_counter = 0;
2452 
2453  if (CHK_MSHG(ms_card)) {
2454  if ((start_sector % 4) || (sector_cnt % 4)) {
2455  if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2456  rw_tpc = PRO_READ_LONG_DATA;
2457  rw_cmd = PRO_READ_DATA;
2458  } else {
2459  rw_tpc = PRO_WRITE_LONG_DATA;
2460  rw_cmd = PRO_WRITE_DATA;
2461  }
2462  } else {
2463  if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2464  rw_tpc = PRO_READ_QUAD_DATA;
2465  rw_cmd = PRO_READ_2K_DATA;
2466  } else {
2467  rw_tpc = PRO_WRITE_QUAD_DATA;
2468  rw_cmd = PRO_WRITE_2K_DATA;
2469  }
2470  mode_2k = 1;
2471  }
2472  } else {
2473  if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2474  rw_tpc = PRO_READ_LONG_DATA;
2475  rw_cmd = PRO_READ_DATA;
2476  } else {
2477  rw_tpc = PRO_WRITE_LONG_DATA;
2478  rw_cmd = PRO_WRITE_DATA;
2479  }
2480  }
2481 
2482  retval = ms_switch_clock(chip);
2483  if (retval != STATUS_SUCCESS)
2484  TRACE_RET(chip, STATUS_FAIL);
2485 
2486  if (srb->sc_data_direction == DMA_FROM_DEVICE)
2487  trans_mode = MS_TM_AUTO_READ;
2488  else
2489  trans_mode = MS_TM_AUTO_WRITE;
2490 
2491  RTSX_READ_REG(chip, MS_TRANS_CFG, &val);
2492 
2493  if (ms_card->seq_mode) {
2494  if ((ms_card->pre_dir != srb->sc_data_direction)
2495  || ((ms_card->pre_sec_addr + ms_card->pre_sec_cnt) != start_sector)
2496  || (mode_2k && (ms_card->seq_mode & MODE_512_SEQ))
2497  || (!mode_2k && (ms_card->seq_mode & MODE_2K_SEQ))
2498  || !(val & MS_INT_BREQ)
2499  || ((ms_card->total_sec_cnt + sector_cnt) > 0xFE00)) {
2500  ms_card->seq_mode = 0;
2501  ms_card->total_sec_cnt = 0;
2502  if (val & MS_INT_BREQ) {
2503  retval = ms_send_cmd(chip, PRO_STOP, WAIT_INT);
2504  if (retval != STATUS_SUCCESS)
2505  TRACE_RET(chip, STATUS_FAIL);
2506 
2507  rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
2508  }
2509  }
2510  }
2511 
2512  if (!ms_card->seq_mode) {
2513  ms_card->total_sec_cnt = 0;
2514  if (sector_cnt >= SEQ_START_CRITERIA) {
2515  if ((ms_card->capacity - start_sector) > 0xFE00)
2516  count = 0xFE00;
2517  else
2518  count = (u16)(ms_card->capacity - start_sector);
2519 
2520  if (count > sector_cnt) {
2521  if (mode_2k)
2522  ms_card->seq_mode |= MODE_2K_SEQ;
2523  else
2524  ms_card->seq_mode |= MODE_512_SEQ;
2525  }
2526  } else {
2527  count = sector_cnt;
2528  }
2529  retval = mspro_set_rw_cmd(chip, start_sector, count, rw_cmd);
2530  if (retval != STATUS_SUCCESS) {
2531  ms_card->seq_mode = 0;
2532  TRACE_RET(chip, STATUS_FAIL);
2533  }
2534  }
2535 
2536  retval = ms_transfer_data(chip, trans_mode, rw_tpc, sector_cnt, WAIT_INT, mode_2k,
2537  scsi_sg_count(srb), scsi_sglist(srb), scsi_bufflen(srb));
2538  if (retval != STATUS_SUCCESS) {
2539  ms_card->seq_mode = 0;
2540  rtsx_read_register(chip, MS_TRANS_CFG, &val);
2541  rtsx_clear_ms_error(chip);
2542 
2543  if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
2544  chip->rw_need_retry = 0;
2545  RTSX_DEBUGP("No card exist, exit mspro_rw_multi_sector\n");
2546  TRACE_RET(chip, STATUS_FAIL);
2547  }
2548 
2549  if (val & MS_INT_BREQ)
2550  ms_send_cmd(chip, PRO_STOP, WAIT_INT);
2551 
2552  if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) {
2553  RTSX_DEBUGP("MSPro CRC error, tune clock!\n");
2554  chip->rw_need_retry = 1;
2555  ms_auto_tune_clock(chip);
2556  }
2557 
2558  TRACE_RET(chip, retval);
2559  }
2560 
2561  if (ms_card->seq_mode) {
2562  ms_card->pre_sec_addr = start_sector;
2563  ms_card->pre_sec_cnt = sector_cnt;
2564  ms_card->pre_dir = srb->sc_data_direction;
2565  ms_card->total_sec_cnt += sector_cnt;
2566  }
2567 
2568  return STATUS_SUCCESS;
2569 }
2570 
2571 static int mspro_read_format_progress(struct rtsx_chip *chip, const int short_data_len)
2572 {
2573  struct ms_info *ms_card = &(chip->ms_card);
2574  int retval, i;
2575  u32 total_progress, cur_progress;
2576  u8 cnt, tmp;
2577  u8 data[8];
2578 
2579  RTSX_DEBUGP("mspro_read_format_progress, short_data_len = %d\n", short_data_len);
2580 
2581  retval = ms_switch_clock(chip);
2582  if (retval != STATUS_SUCCESS) {
2583  ms_card->format_status = FORMAT_FAIL;
2584  TRACE_RET(chip, STATUS_FAIL);
2585  }
2586 
2587  retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp);
2588  if (retval != STATUS_SUCCESS) {
2589  ms_card->format_status = FORMAT_FAIL;
2590  TRACE_RET(chip, STATUS_FAIL);
2591  }
2592 
2593  if (!(tmp & MS_INT_BREQ)) {
2594  if ((tmp & (MS_INT_CED | MS_INT_BREQ | MS_INT_CMDNK | MS_INT_ERR)) == MS_INT_CED) {
2595  ms_card->format_status = FORMAT_SUCCESS;
2596  return STATUS_SUCCESS;
2597  }
2598  ms_card->format_status = FORMAT_FAIL;
2599  TRACE_RET(chip, STATUS_FAIL);
2600  }
2601 
2602  if (short_data_len >= 256)
2603  cnt = 0;
2604  else
2605  cnt = (u8)short_data_len;
2606 
2607  retval = rtsx_write_register(chip, MS_CFG, MS_NO_CHECK_INT, MS_NO_CHECK_INT);
2608  if (retval != STATUS_SUCCESS) {
2609  ms_card->format_status = FORMAT_FAIL;
2610  TRACE_RET(chip, STATUS_FAIL);
2611  }
2612 
2613  retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, cnt, WAIT_INT, data, 8);
2614  if (retval != STATUS_SUCCESS) {
2615  ms_card->format_status = FORMAT_FAIL;
2616  TRACE_RET(chip, STATUS_FAIL);
2617  }
2618 
2619  total_progress = (data[0] << 24) | (data[1] << 16) | (data[2] << 8) | data[3];
2620  cur_progress = (data[4] << 24) | (data[5] << 16) | (data[6] << 8) | data[7];
2621 
2622  RTSX_DEBUGP("total_progress = %d, cur_progress = %d\n",
2623  total_progress, cur_progress);
2624 
2625  if (total_progress == 0) {
2626  ms_card->progress = 0;
2627  } else {
2628  u64 ulltmp = (u64)cur_progress * (u64)65535;
2629  do_div(ulltmp, total_progress);
2630  ms_card->progress = (u16)ulltmp;
2631  }
2632  RTSX_DEBUGP("progress = %d\n", ms_card->progress);
2633 
2634  for (i = 0; i < 5000; i++) {
2635  retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp);
2636  if (retval != STATUS_SUCCESS) {
2637  ms_card->format_status = FORMAT_FAIL;
2638  TRACE_RET(chip, STATUS_FAIL);
2639  }
2640  if (tmp & (MS_INT_CED | MS_INT_CMDNK | MS_INT_BREQ | MS_INT_ERR))
2641  break;
2642 
2643  wait_timeout(1);
2644  }
2645 
2646  retval = rtsx_write_register(chip, MS_CFG, MS_NO_CHECK_INT, 0);
2647  if (retval != STATUS_SUCCESS) {
2648  ms_card->format_status = FORMAT_FAIL;
2649  TRACE_RET(chip, STATUS_FAIL);
2650  }
2651 
2652  if (i == 5000) {
2653  ms_card->format_status = FORMAT_FAIL;
2654  TRACE_RET(chip, STATUS_FAIL);
2655  }
2656 
2657  if (tmp & (MS_INT_CMDNK | MS_INT_ERR)) {
2658  ms_card->format_status = FORMAT_FAIL;
2659  TRACE_RET(chip, STATUS_FAIL);
2660  }
2661 
2662  if (tmp & MS_INT_CED) {
2663  ms_card->format_status = FORMAT_SUCCESS;
2664  ms_card->pro_under_formatting = 0;
2665  } else if (tmp & MS_INT_BREQ) {
2666  ms_card->format_status = FORMAT_IN_PROGRESS;
2667  } else {
2668  ms_card->format_status = FORMAT_FAIL;
2669  ms_card->pro_under_formatting = 0;
2670  TRACE_RET(chip, STATUS_FAIL);
2671  }
2672 
2673  return STATUS_SUCCESS;
2674 }
2675 
2676 void mspro_polling_format_status(struct rtsx_chip *chip)
2677 {
2678  struct ms_info *ms_card = &(chip->ms_card);
2679  int i;
2680 
2681  if (ms_card->pro_under_formatting && (rtsx_get_stat(chip) != RTSX_STAT_SS)) {
2682  rtsx_set_stat(chip, RTSX_STAT_RUN);
2683 
2684  for (i = 0; i < 65535; i++) {
2685  mspro_read_format_progress(chip, MS_SHORT_DATA_LEN);
2686  if (ms_card->format_status != FORMAT_IN_PROGRESS)
2687  break;
2688  }
2689  }
2690 
2691  return;
2692 }
2693 
2694 int mspro_format(struct scsi_cmnd *srb, struct rtsx_chip *chip, int short_data_len, int quick_format)
2695 {
2696  struct ms_info *ms_card = &(chip->ms_card);
2697  int retval, i;
2698  u8 buf[8], tmp;
2699  u16 para;
2700 
2701  RTSX_DEBUGP("--%s--\n", __func__);
2702 
2703  retval = ms_switch_clock(chip);
2704  if (retval != STATUS_SUCCESS)
2705  TRACE_RET(chip, STATUS_FAIL);
2706 
2707  retval = ms_set_rw_reg_addr(chip, 0x00, 0x00, Pro_TPCParm, 0x01);
2708  if (retval != STATUS_SUCCESS)
2709  TRACE_RET(chip, STATUS_FAIL);
2710 
2711  memset(buf, 0, 2);
2712  switch (short_data_len) {
2713  case 32:
2714  buf[0] = 0;
2715  break;
2716  case 64:
2717  buf[0] = 1;
2718  break;
2719  case 128:
2720  buf[0] = 2;
2721  break;
2722  case 256:
2723  default:
2724  buf[0] = 3;
2725  break;
2726  }
2727 
2728  for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
2729  retval = ms_write_bytes(chip, PRO_WRITE_REG, 1, NO_WAIT_INT, buf, 2);
2730  if (retval == STATUS_SUCCESS)
2731  break;
2732  }
2733  if (i == MS_MAX_RETRY_COUNT)
2734  TRACE_RET(chip, STATUS_FAIL);
2735 
2736  if (quick_format)
2737  para = 0x0000;
2738  else
2739  para = 0x0001;
2740 
2741  retval = mspro_set_rw_cmd(chip, 0, para, PRO_FORMAT);
2742  if (retval != STATUS_SUCCESS)
2743  TRACE_RET(chip, STATUS_FAIL);
2744 
2745  RTSX_READ_REG(chip, MS_TRANS_CFG, &tmp);
2746 
2747  if (tmp & (MS_INT_CMDNK | MS_INT_ERR))
2748  TRACE_RET(chip, STATUS_FAIL);
2749 
2750  if ((tmp & (MS_INT_BREQ | MS_INT_CED)) == MS_INT_BREQ) {
2751  ms_card->pro_under_formatting = 1;
2752  ms_card->progress = 0;
2753  ms_card->format_status = FORMAT_IN_PROGRESS;
2754  return STATUS_SUCCESS;
2755  }
2756 
2757  if (tmp & MS_INT_CED) {
2758  ms_card->pro_under_formatting = 0;
2759  ms_card->progress = 0;
2760  ms_card->format_status = FORMAT_SUCCESS;
2761  set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_NO_SENSE);
2762  return STATUS_SUCCESS;
2763  }
2764 
2765  TRACE_RET(chip, STATUS_FAIL);
2766 }
2767 
2768 
2769 static int ms_read_multiple_pages(struct rtsx_chip *chip, u16 phy_blk, u16 log_blk,
2770  u8 start_page, u8 end_page, u8 *buf, unsigned int *index, unsigned int *offset)
2771 {
2772  struct ms_info *ms_card = &(chip->ms_card);
2773  int retval, i;
2774  u8 extra[MS_EXTRA_SIZE], page_addr, val, trans_cfg, data[6];
2775  u8 *ptr;
2776 
2777  retval = ms_read_extra_data(chip, phy_blk, start_page, extra, MS_EXTRA_SIZE);
2778  if (retval == STATUS_SUCCESS) {
2779  if ((extra[1] & 0x30) != 0x30) {
2780  ms_set_err_code(chip, MS_FLASH_READ_ERROR);
2781  TRACE_RET(chip, STATUS_FAIL);
2782  }
2783  }
2784 
2785  retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6);
2786  if (retval != STATUS_SUCCESS)
2787  TRACE_RET(chip, STATUS_FAIL);
2788 
2789  if (CHK_MS4BIT(ms_card))
2790  data[0] = 0x88;
2791  else
2792  data[0] = 0x80;
2793 
2794  data[1] = 0;
2795  data[2] = (u8)(phy_blk >> 8);
2796  data[3] = (u8)phy_blk;
2797  data[4] = 0;
2798  data[5] = start_page;
2799 
2800  for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
2801  retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6);
2802  if (retval == STATUS_SUCCESS)
2803  break;
2804  }
2805  if (i == MS_MAX_RETRY_COUNT)
2806  TRACE_RET(chip, STATUS_FAIL);
2807 
2808  ms_set_err_code(chip, MS_NO_ERROR);
2809 
2810  retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
2811  if (retval != STATUS_SUCCESS)
2812  TRACE_RET(chip, STATUS_FAIL);
2813 
2814  ptr = buf;
2815 
2816  for (page_addr = start_page; page_addr < end_page; page_addr++) {
2817  ms_set_err_code(chip, MS_NO_ERROR);
2818 
2819  if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
2820  ms_set_err_code(chip, MS_NO_CARD);
2821  TRACE_RET(chip, STATUS_FAIL);
2822  }
2823 
2824  retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
2825  if (retval != STATUS_SUCCESS)
2826  TRACE_RET(chip, STATUS_FAIL);
2827 
2828  if (val & INT_REG_CMDNK) {
2829  ms_set_err_code(chip, MS_CMD_NK);
2830  TRACE_RET(chip, STATUS_FAIL);
2831  }
2832  if (val & INT_REG_ERR) {
2833  if (val & INT_REG_BREQ) {
2834  retval = ms_read_status_reg(chip);
2835  if (retval != STATUS_SUCCESS) {
2836  if (!(chip->card_wp & MS_CARD)) {
2837  reset_ms(chip);
2838  ms_set_page_status(log_blk, setPS_NG, extra, MS_EXTRA_SIZE);
2839  ms_write_extra_data(chip, phy_blk,
2840  page_addr, extra, MS_EXTRA_SIZE);
2841  }
2842  ms_set_err_code(chip, MS_FLASH_READ_ERROR);
2843  TRACE_RET(chip, STATUS_FAIL);
2844  }
2845  } else {
2846  ms_set_err_code(chip, MS_FLASH_READ_ERROR);
2847  TRACE_RET(chip, STATUS_FAIL);
2848  }
2849  } else {
2850  if (!(val & INT_REG_BREQ)) {
2851  ms_set_err_code(chip, MS_BREQ_ERROR);
2852  TRACE_RET(chip, STATUS_FAIL);
2853  }
2854  }
2855 
2856  if (page_addr == (end_page - 1)) {
2857  if (!(val & INT_REG_CED)) {
2858  retval = ms_send_cmd(chip, BLOCK_END, WAIT_INT);
2859  if (retval != STATUS_SUCCESS)
2860  TRACE_RET(chip, STATUS_FAIL);
2861  }
2862 
2863  retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
2864  if (retval != STATUS_SUCCESS)
2865  TRACE_RET(chip, STATUS_FAIL);
2866 
2867  if (!(val & INT_REG_CED)) {
2868  ms_set_err_code(chip, MS_FLASH_READ_ERROR);
2869  TRACE_RET(chip, STATUS_FAIL);
2870  }
2871 
2872  trans_cfg = NO_WAIT_INT;
2873  } else {
2874  trans_cfg = WAIT_INT;
2875  }
2876 
2877  rtsx_init_cmd(chip);
2878 
2879  rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, READ_PAGE_DATA);
2880  rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, trans_cfg);
2881  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
2882 
2883  trans_dma_enable(DMA_FROM_DEVICE, chip, 512, DMA_512);
2884 
2885  rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
2886  MS_TRANSFER_START | MS_TM_NORMAL_READ);
2887  rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END);
2888 
2889  rtsx_send_cmd_no_wait(chip);
2890 
2891  retval = rtsx_transfer_data_partial(chip, MS_CARD, ptr, 512, scsi_sg_count(chip->srb),
2892  index, offset, DMA_FROM_DEVICE, chip->ms_timeout);
2893  if (retval < 0) {
2894  if (retval == -ETIMEDOUT) {
2895  ms_set_err_code(chip, MS_TO_ERROR);
2896  rtsx_clear_ms_error(chip);
2897  TRACE_RET(chip, STATUS_TIMEDOUT);
2898  }
2899 
2900  retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
2901  if (retval != STATUS_SUCCESS) {
2902  ms_set_err_code(chip, MS_TO_ERROR);
2903  rtsx_clear_ms_error(chip);
2904  TRACE_RET(chip, STATUS_TIMEDOUT);
2905  }
2906  if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) {
2907  ms_set_err_code(chip, MS_CRC16_ERROR);
2908  rtsx_clear_ms_error(chip);
2909  TRACE_RET(chip, STATUS_FAIL);
2910  }
2911  }
2912 
2913  if (scsi_sg_count(chip->srb) == 0)
2914  ptr += 512;
2915  }
2916 
2917  return STATUS_SUCCESS;
2918 }
2919 
2920 static int ms_write_multiple_pages(struct rtsx_chip *chip, u16 old_blk, u16 new_blk,
2921  u16 log_blk, u8 start_page, u8 end_page, u8 *buf,
2922  unsigned int *index, unsigned int *offset)
2923 {
2924  struct ms_info *ms_card = &(chip->ms_card);
2925  int retval, i;
2926  u8 page_addr, val, data[16];
2927  u8 *ptr;
2928 
2929  if (!start_page) {
2930  retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 7);
2931  if (retval != STATUS_SUCCESS)
2932  TRACE_RET(chip, STATUS_FAIL);
2933 
2934  if (CHK_MS4BIT(ms_card))
2935  data[0] = 0x88;
2936  else
2937  data[0] = 0x80;
2938 
2939  data[1] = 0;
2940  data[2] = (u8)(old_blk >> 8);
2941  data[3] = (u8)old_blk;
2942  data[4] = 0x80;
2943  data[5] = 0;
2944  data[6] = 0xEF;
2945  data[7] = 0xFF;
2946 
2947  retval = ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT, data, 8);
2948  if (retval != STATUS_SUCCESS)
2949  TRACE_RET(chip, STATUS_FAIL);
2950 
2951  retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
2952  if (retval != STATUS_SUCCESS)
2953  TRACE_RET(chip, STATUS_FAIL);
2954 
2955  ms_set_err_code(chip, MS_NO_ERROR);
2956  retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT, 1, NO_WAIT_INT);
2957  if (retval != STATUS_SUCCESS)
2958  TRACE_RET(chip, STATUS_FAIL);
2959  }
2960 
2961  retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, (6 + MS_EXTRA_SIZE));
2962  if (retval != STATUS_SUCCESS)
2963  TRACE_RET(chip, STATUS_FAIL);
2964 
2965  ms_set_err_code(chip, MS_NO_ERROR);
2966 
2967  if (CHK_MS4BIT(ms_card))
2968  data[0] = 0x88;
2969  else
2970  data[0] = 0x80;
2971 
2972  data[1] = 0;
2973  data[2] = (u8)(new_blk >> 8);
2974  data[3] = (u8)new_blk;
2975  if ((end_page - start_page) == 1)
2976  data[4] = 0x20;
2977  else
2978  data[4] = 0;
2979 
2980  data[5] = start_page;
2981  data[6] = 0xF8;
2982  data[7] = 0xFF;
2983  data[8] = (u8)(log_blk >> 8);
2984  data[9] = (u8)log_blk;
2985 
2986  for (i = 0x0A; i < 0x10; i++)
2987  data[i] = 0xFF;
2988 
2989  for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
2990  retval = ms_write_bytes(chip, WRITE_REG, 6 + MS_EXTRA_SIZE, NO_WAIT_INT, data, 16);
2991  if (retval == STATUS_SUCCESS)
2992  break;
2993  }
2994  if (i == MS_MAX_RETRY_COUNT)
2995  TRACE_RET(chip, STATUS_FAIL);
2996 
2997  for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
2998  retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
2999  if (retval == STATUS_SUCCESS)
3000  break;
3001  }
3002  if (i == MS_MAX_RETRY_COUNT)
3003  TRACE_RET(chip, STATUS_FAIL);
3004 
3005  retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
3006  if (retval != STATUS_SUCCESS)
3007  TRACE_RET(chip, STATUS_FAIL);
3008 
3009  ptr = buf;
3010  for (page_addr = start_page; page_addr < end_page; page_addr++) {
3011  ms_set_err_code(chip, MS_NO_ERROR);
3012 
3013  if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3014  ms_set_err_code(chip, MS_NO_CARD);
3015  TRACE_RET(chip, STATUS_FAIL);
3016  }
3017 
3018  if (val & INT_REG_CMDNK) {
3019  ms_set_err_code(chip, MS_CMD_NK);
3020  TRACE_RET(chip, STATUS_FAIL);
3021  }
3022  if (val & INT_REG_ERR) {
3023  ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
3024  TRACE_RET(chip, STATUS_FAIL);
3025  }
3026  if (!(val & INT_REG_BREQ)) {
3027  ms_set_err_code(chip, MS_BREQ_ERROR);
3028  TRACE_RET(chip, STATUS_FAIL);
3029  }
3030 
3031  udelay(30);
3032 
3033  rtsx_init_cmd(chip);
3034 
3035  rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, WRITE_PAGE_DATA);
3036  rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, WAIT_INT);
3037  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
3038 
3039  trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512);
3040 
3041  rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
3042  MS_TRANSFER_START | MS_TM_NORMAL_WRITE);
3043  rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END);
3044 
3045  rtsx_send_cmd_no_wait(chip);
3046 
3047  retval = rtsx_transfer_data_partial(chip, MS_CARD, ptr, 512, scsi_sg_count(chip->srb),
3048  index, offset, DMA_TO_DEVICE, chip->ms_timeout);
3049  if (retval < 0) {
3050  ms_set_err_code(chip, MS_TO_ERROR);
3051  rtsx_clear_ms_error(chip);
3052 
3053  if (retval == -ETIMEDOUT)
3054  TRACE_RET(chip, STATUS_TIMEDOUT);
3055  else
3056  TRACE_RET(chip, STATUS_FAIL);
3057  }
3058 
3059  retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
3060  if (retval != STATUS_SUCCESS)
3061  TRACE_RET(chip, STATUS_FAIL);
3062 
3063  if ((end_page - start_page) == 1) {
3064  if (!(val & INT_REG_CED)) {
3065  ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
3066  TRACE_RET(chip, STATUS_FAIL);
3067  }
3068  } else {
3069  if (page_addr == (end_page - 1)) {
3070  if (!(val & INT_REG_CED)) {
3071  retval = ms_send_cmd(chip, BLOCK_END, WAIT_INT);
3072  if (retval != STATUS_SUCCESS)
3073  TRACE_RET(chip, STATUS_FAIL);
3074  }
3075 
3076  retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
3077  if (retval != STATUS_SUCCESS)
3078  TRACE_RET(chip, STATUS_FAIL);
3079  }
3080 
3081  if ((page_addr == (end_page - 1)) || (page_addr == ms_card->page_off)) {
3082  if (!(val & INT_REG_CED)) {
3083  ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
3084  TRACE_RET(chip, STATUS_FAIL);
3085  }
3086  }
3087  }
3088 
3089  if (scsi_sg_count(chip->srb) == 0)
3090  ptr += 512;
3091  }
3092 
3093  return STATUS_SUCCESS;
3094 }
3095 
3096 
3097 static int ms_finish_write(struct rtsx_chip *chip, u16 old_blk, u16 new_blk,
3098  u16 log_blk, u8 page_off)
3099 {
3100  struct ms_info *ms_card = &(chip->ms_card);
3101  int retval, seg_no;
3102 
3103  retval = ms_copy_page(chip, old_blk, new_blk, log_blk,
3104  page_off, ms_card->page_off + 1);
3105  if (retval != STATUS_SUCCESS)
3106  TRACE_RET(chip, STATUS_FAIL);
3107 
3108  seg_no = old_blk >> 9;
3109 
3110  if (MS_TST_BAD_BLOCK_FLG(ms_card)) {
3111  MS_CLR_BAD_BLOCK_FLG(ms_card);
3112  ms_set_bad_block(chip, old_blk);
3113  } else {
3114  retval = ms_erase_block(chip, old_blk);
3115  if (retval == STATUS_SUCCESS)
3116  ms_set_unused_block(chip, old_blk);
3117  }
3118 
3119  ms_set_l2p_tbl(chip, seg_no, log_blk - ms_start_idx[seg_no], new_blk);
3120 
3121  return STATUS_SUCCESS;
3122 }
3123 
3124 static int ms_prepare_write(struct rtsx_chip *chip, u16 old_blk, u16 new_blk,
3125  u16 log_blk, u8 start_page)
3126 {
3127  int retval;
3128 
3129  if (start_page) {
3130  retval = ms_copy_page(chip, old_blk, new_blk, log_blk, 0, start_page);
3131  if (retval != STATUS_SUCCESS)
3132  TRACE_RET(chip, STATUS_FAIL);
3133  }
3134 
3135  return STATUS_SUCCESS;
3136 }
3137 
3138 #ifdef MS_DELAY_WRITE
3139 int ms_delay_write(struct rtsx_chip *chip)
3140 {
3141  struct ms_info *ms_card = &(chip->ms_card);
3142  struct ms_delay_write_tag *delay_write = &(ms_card->delay_write);
3143  int retval;
3144 
3145  if (delay_write->delay_write_flag) {
3146  retval = ms_set_init_para(chip);
3147  if (retval != STATUS_SUCCESS)
3148  TRACE_RET(chip, STATUS_FAIL);
3149 
3150  delay_write->delay_write_flag = 0;
3151  retval = ms_finish_write(chip,
3152  delay_write->old_phyblock, delay_write->new_phyblock,
3153  delay_write->logblock, delay_write->pageoff);
3154  if (retval != STATUS_SUCCESS)
3155  TRACE_RET(chip, STATUS_FAIL);
3156  }
3157 
3158  return STATUS_SUCCESS;
3159 }
3160 #endif
3161 
3162 static inline void ms_rw_fail(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3163 {
3164  if (srb->sc_data_direction == DMA_FROM_DEVICE)
3165  set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3166  else
3167  set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR);
3168 }
3169 
3170 static int ms_rw_multi_sector(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector, u16 sector_cnt)
3171 {
3172  struct ms_info *ms_card = &(chip->ms_card);
3173  unsigned int lun = SCSI_LUN(srb);
3174  int retval, seg_no;
3175  unsigned int index = 0, offset = 0;
3176  u16 old_blk = 0, new_blk = 0, log_blk, total_sec_cnt = sector_cnt;
3177  u8 start_page, end_page = 0, page_cnt;
3178  u8 *ptr;
3179 #ifdef MS_DELAY_WRITE
3180  struct ms_delay_write_tag *delay_write = &(ms_card->delay_write);
3181 #endif
3182 
3183  ms_set_err_code(chip, MS_NO_ERROR);
3184 
3185  ms_card->cleanup_counter = 0;
3186 
3187  ptr = (u8 *)scsi_sglist(srb);
3188 
3189  retval = ms_switch_clock(chip);
3190  if (retval != STATUS_SUCCESS) {
3191  ms_rw_fail(srb, chip);
3192  TRACE_RET(chip, STATUS_FAIL);
3193  }
3194 
3195  log_blk = (u16)(start_sector >> ms_card->block_shift);
3196  start_page = (u8)(start_sector & ms_card->page_off);
3197 
3198  for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1; seg_no++) {
3199  if (log_blk < ms_start_idx[seg_no+1])
3200  break;
3201  }
3202 
3203  if (ms_card->segment[seg_no].build_flag == 0) {
3204  retval = ms_build_l2p_tbl(chip, seg_no);
3205  if (retval != STATUS_SUCCESS) {
3206  chip->card_fail |= MS_CARD;
3207  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
3208  TRACE_RET(chip, STATUS_FAIL);
3209  }
3210  }
3211 
3212  if (srb->sc_data_direction == DMA_TO_DEVICE) {
3213 #ifdef MS_DELAY_WRITE
3214  if (delay_write->delay_write_flag &&
3215  (delay_write->logblock == log_blk) &&
3216  (start_page > delay_write->pageoff)) {
3217  delay_write->delay_write_flag = 0;
3218  retval = ms_copy_page(chip,
3219  delay_write->old_phyblock,
3220  delay_write->new_phyblock, log_blk,
3221  delay_write->pageoff, start_page);
3222  if (retval != STATUS_SUCCESS) {
3223  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
3224  TRACE_RET(chip, STATUS_FAIL);
3225  }
3226  old_blk = delay_write->old_phyblock;
3227  new_blk = delay_write->new_phyblock;
3228  } else if (delay_write->delay_write_flag &&
3229  (delay_write->logblock == log_blk) &&
3230  (start_page == delay_write->pageoff)) {
3231  delay_write->delay_write_flag = 0;
3232  old_blk = delay_write->old_phyblock;
3233  new_blk = delay_write->new_phyblock;
3234  } else {
3235  retval = ms_delay_write(chip);
3236  if (retval != STATUS_SUCCESS) {
3237  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
3238  TRACE_RET(chip, STATUS_FAIL);
3239  }
3240 #endif
3241  old_blk = ms_get_l2p_tbl(chip, seg_no, log_blk - ms_start_idx[seg_no]);
3242  new_blk = ms_get_unused_block(chip, seg_no);
3243  if ((old_blk == 0xFFFF) || (new_blk == 0xFFFF)) {
3244  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
3245  TRACE_RET(chip, STATUS_FAIL);
3246  }
3247 
3248  retval = ms_prepare_write(chip, old_blk, new_blk, log_blk, start_page);
3249  if (retval != STATUS_SUCCESS) {
3250  if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3251  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
3252  TRACE_RET(chip, STATUS_FAIL);
3253  }
3254  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
3255  TRACE_RET(chip, STATUS_FAIL);
3256  }
3257 #ifdef MS_DELAY_WRITE
3258  }
3259 #endif
3260  } else {
3261 #ifdef MS_DELAY_WRITE
3262  retval = ms_delay_write(chip);
3263  if (retval != STATUS_SUCCESS) {
3264  if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3265  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
3266  TRACE_RET(chip, STATUS_FAIL);
3267  }
3268  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3269  TRACE_RET(chip, STATUS_FAIL);
3270  }
3271 #endif
3272  old_blk = ms_get_l2p_tbl(chip, seg_no, log_blk - ms_start_idx[seg_no]);
3273  if (old_blk == 0xFFFF) {
3274  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3275  TRACE_RET(chip, STATUS_FAIL);
3276  }
3277  }
3278 
3279  RTSX_DEBUGP("seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n", seg_no, old_blk, new_blk);
3280 
3281  while (total_sec_cnt) {
3282  if ((start_page + total_sec_cnt) > (ms_card->page_off + 1))
3283  end_page = ms_card->page_off + 1;
3284  else
3285  end_page = start_page + (u8)total_sec_cnt;
3286 
3287  page_cnt = end_page - start_page;
3288 
3289  RTSX_DEBUGP("start_page = %d, end_page = %d, page_cnt = %d\n",
3290  start_page, end_page, page_cnt);
3291 
3292  if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3293  retval = ms_read_multiple_pages(chip,
3294  old_blk, log_blk, start_page, end_page,
3295  ptr, &index, &offset);
3296  } else {
3297  retval = ms_write_multiple_pages(chip, old_blk,
3298  new_blk, log_blk, start_page, end_page,
3299  ptr, &index, &offset);
3300  }
3301 
3302  if (retval != STATUS_SUCCESS) {
3303  toggle_gpio(chip, 1);
3304  if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3305  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
3306  TRACE_RET(chip, STATUS_FAIL);
3307  }
3308  ms_rw_fail(srb, chip);
3309  TRACE_RET(chip, STATUS_FAIL);
3310  }
3311 
3312  if (srb->sc_data_direction == DMA_TO_DEVICE) {
3313  if (end_page == (ms_card->page_off + 1)) {
3314  retval = ms_erase_block(chip, old_blk);
3315  if (retval == STATUS_SUCCESS)
3316  ms_set_unused_block(chip, old_blk);
3317 
3318  ms_set_l2p_tbl(chip, seg_no, log_blk - ms_start_idx[seg_no], new_blk);
3319  }
3320  }
3321 
3322  total_sec_cnt -= page_cnt;
3323  if (scsi_sg_count(srb) == 0)
3324  ptr += page_cnt * 512;
3325 
3326  if (total_sec_cnt == 0)
3327  break;
3328 
3329  log_blk++;
3330 
3331  for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1;
3332  seg_no++) {
3333  if (log_blk < ms_start_idx[seg_no+1])
3334  break;
3335  }
3336 
3337  if (ms_card->segment[seg_no].build_flag == 0) {
3338  retval = ms_build_l2p_tbl(chip, seg_no);
3339  if (retval != STATUS_SUCCESS) {
3340  chip->card_fail |= MS_CARD;
3341  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
3342  TRACE_RET(chip, STATUS_FAIL);
3343  }
3344  }
3345 
3346  old_blk = ms_get_l2p_tbl(chip, seg_no, log_blk - ms_start_idx[seg_no]);
3347  if (old_blk == 0xFFFF) {
3348  ms_rw_fail(srb, chip);
3349  TRACE_RET(chip, STATUS_FAIL);
3350  }
3351 
3352  if (srb->sc_data_direction == DMA_TO_DEVICE) {
3353  new_blk = ms_get_unused_block(chip, seg_no);
3354  if (new_blk == 0xFFFF) {
3355  ms_rw_fail(srb, chip);
3356  TRACE_RET(chip, STATUS_FAIL);
3357  }
3358  }
3359 
3360  RTSX_DEBUGP("seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n", seg_no, old_blk, new_blk);
3361 
3362  start_page = 0;
3363  }
3364 
3365  if (srb->sc_data_direction == DMA_TO_DEVICE) {
3366  if (end_page < (ms_card->page_off + 1)) {
3367 #ifdef MS_DELAY_WRITE
3368  delay_write->delay_write_flag = 1;
3369  delay_write->old_phyblock = old_blk;
3370  delay_write->new_phyblock = new_blk;
3371  delay_write->logblock = log_blk;
3372  delay_write->pageoff = end_page;
3373 #else
3374  retval = ms_finish_write(chip, old_blk, new_blk, log_blk, end_page);
3375  if (retval != STATUS_SUCCESS) {
3376  if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3377  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
3378  TRACE_RET(chip, STATUS_FAIL);
3379  }
3380 
3381  ms_rw_fail(srb, chip);
3382  TRACE_RET(chip, STATUS_FAIL);
3383  }
3384 #endif
3385  }
3386  }
3387 
3388  scsi_set_resid(srb, 0);
3389 
3390  return STATUS_SUCCESS;
3391 }
3392 
3393 int ms_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector, u16 sector_cnt)
3394 {
3395  struct ms_info *ms_card = &(chip->ms_card);
3396  int retval;
3397 
3398  if (CHK_MSPRO(ms_card))
3399  retval = mspro_rw_multi_sector(srb, chip, start_sector, sector_cnt);
3400  else
3401  retval = ms_rw_multi_sector(srb, chip, start_sector, sector_cnt);
3402 
3403  return retval;
3404 }
3405 
3406 
3407 void ms_free_l2p_tbl(struct rtsx_chip *chip)
3408 {
3409  struct ms_info *ms_card = &(chip->ms_card);
3410  int i = 0;
3411 
3412  if (ms_card->segment != NULL) {
3413  for (i = 0; i < ms_card->segment_cnt; i++) {
3414  if (ms_card->segment[i].l2p_table != NULL) {
3415  vfree(ms_card->segment[i].l2p_table);
3416  ms_card->segment[i].l2p_table = NULL;
3417  }
3418  if (ms_card->segment[i].free_table != NULL) {
3419  vfree(ms_card->segment[i].free_table);
3420  ms_card->segment[i].free_table = NULL;
3421  }
3422  }
3423  vfree(ms_card->segment);
3424  ms_card->segment = NULL;
3425  }
3426 }
3427 
3428 #ifdef SUPPORT_MAGIC_GATE
3429 
3430 #ifdef READ_BYTES_WAIT_INT
3431 static int ms_poll_int(struct rtsx_chip *chip)
3432 {
3433  int retval;
3434  u8 val;
3435 
3436  rtsx_init_cmd(chip);
3437 
3438  rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANS_CFG, MS_INT_CED, MS_INT_CED);
3439 
3440  retval = rtsx_send_cmd(chip, MS_CARD, 5000);
3441  if (retval != STATUS_SUCCESS)
3442  TRACE_RET(chip, STATUS_FAIL);
3443 
3444  val = *rtsx_get_cmd_data(chip);
3445  if (val & MS_INT_ERR)
3446  TRACE_RET(chip, STATUS_FAIL);
3447 
3448  return STATUS_SUCCESS;
3449 }
3450 #endif
3451 
3452 #ifdef MS_SAMPLE_INT_ERR
3453 static int check_ms_err(struct rtsx_chip *chip)
3454 {
3455  int retval;
3456  u8 val;
3457 
3458  retval = rtsx_read_register(chip, MS_TRANSFER, &val);
3459  if (retval != STATUS_SUCCESS)
3460  return 1;
3461  if (val & MS_TRANSFER_ERR)
3462  return 1;
3463 
3464  retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
3465  if (retval != STATUS_SUCCESS)
3466  return 1;
3467 
3468  if (val & (MS_INT_ERR | MS_INT_CMDNK))
3469  return 1;
3470 
3471  return 0;
3472 }
3473 #else
3474 static int check_ms_err(struct rtsx_chip *chip)
3475 {
3476  int retval;
3477  u8 val;
3478 
3479  retval = rtsx_read_register(chip, MS_TRANSFER, &val);
3480  if (retval != STATUS_SUCCESS)
3481  return 1;
3482  if (val & MS_TRANSFER_ERR)
3483  return 1;
3484 
3485  return 0;
3486 }
3487 #endif
3488 
3489 static int mg_send_ex_cmd(struct rtsx_chip *chip, u8 cmd, u8 entry_num)
3490 {
3491  int retval, i;
3492  u8 data[8];
3493 
3494  data[0] = cmd;
3495  data[1] = 0;
3496  data[2] = 0;
3497  data[3] = 0;
3498  data[4] = 0;
3499  data[5] = 0;
3500  data[6] = entry_num;
3501  data[7] = 0;
3502 
3503  for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3504  retval = ms_write_bytes(chip, PRO_EX_SET_CMD, 7, WAIT_INT, data, 8);
3505  if (retval == STATUS_SUCCESS)
3506  break;
3507  }
3508  if (i == MS_MAX_RETRY_COUNT)
3509  TRACE_RET(chip, STATUS_FAIL);
3510 
3511  if (check_ms_err(chip)) {
3512  rtsx_clear_ms_error(chip);
3513  TRACE_RET(chip, STATUS_FAIL);
3514  }
3515 
3516  return STATUS_SUCCESS;
3517 }
3518 
3519 static int mg_set_tpc_para_sub(struct rtsx_chip *chip, int type, u8 mg_entry_num)
3520 {
3521  int retval;
3522  u8 buf[6];
3523 
3524  RTSX_DEBUGP("--%s--\n", __func__);
3525 
3526  if (type == 0)
3527  retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_TPCParm, 1);
3528  else
3529  retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6);
3530 
3531  if (retval != STATUS_SUCCESS)
3532  TRACE_RET(chip, STATUS_FAIL);
3533 
3534  buf[0] = 0;
3535  buf[1] = 0;
3536  if (type == 1) {
3537  buf[2] = 0;
3538  buf[3] = 0;
3539  buf[4] = 0;
3540  buf[5] = mg_entry_num;
3541  }
3542  retval = ms_write_bytes(chip, PRO_WRITE_REG, (type == 0) ? 1 : 6, NO_WAIT_INT, buf, 6);
3543  if (retval != STATUS_SUCCESS)
3544  TRACE_RET(chip, STATUS_FAIL);
3545 
3546  return STATUS_SUCCESS;
3547 }
3548 
3549 int mg_set_leaf_id(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3550 {
3551  int retval;
3552  int i;
3553  unsigned int lun = SCSI_LUN(srb);
3554  u8 buf1[32], buf2[12];
3555 
3556  RTSX_DEBUGP("--%s--\n", __func__);
3557 
3558  if (scsi_bufflen(srb) < 12) {
3559  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3560  TRACE_RET(chip, STATUS_FAIL);
3561  }
3562 
3563  ms_cleanup_work(chip);
3564 
3565  retval = ms_switch_clock(chip);
3566  if (retval != STATUS_SUCCESS)
3567  TRACE_RET(chip, STATUS_FAIL);
3568 
3569  retval = mg_send_ex_cmd(chip, MG_SET_LID, 0);
3570  if (retval != STATUS_SUCCESS) {
3571  set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
3572  TRACE_RET(chip, STATUS_FAIL);
3573  }
3574 
3575  memset(buf1, 0, 32);
3576  rtsx_stor_get_xfer_buf(buf2, min(12, (int)scsi_bufflen(srb)), srb);
3577  for (i = 0; i < 8; i++)
3578  buf1[8+i] = buf2[4+i];
3579 
3580  retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 32, WAIT_INT, buf1, 32);
3581  if (retval != STATUS_SUCCESS) {
3582  set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
3583  TRACE_RET(chip, STATUS_FAIL);
3584  }
3585  if (check_ms_err(chip)) {
3586  set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
3587  rtsx_clear_ms_error(chip);
3588  TRACE_RET(chip, STATUS_FAIL);
3589  }
3590 
3591  return STATUS_SUCCESS;
3592 }
3593 
3594 int mg_get_local_EKB(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3595 {
3596  int retval = STATUS_FAIL;
3597  int bufflen;
3598  unsigned int lun = SCSI_LUN(srb);
3599  u8 *buf = NULL;
3600 
3601  RTSX_DEBUGP("--%s--\n", __func__);
3602 
3603  ms_cleanup_work(chip);
3604 
3605  retval = ms_switch_clock(chip);
3606  if (retval != STATUS_SUCCESS)
3607  TRACE_RET(chip, STATUS_FAIL);
3608 
3609  buf = kmalloc(1540, GFP_KERNEL);
3610  if (!buf)
3611  TRACE_RET(chip, STATUS_ERROR);
3612 
3613  buf[0] = 0x04;
3614  buf[1] = 0x1A;
3615  buf[2] = 0x00;
3616  buf[3] = 0x00;
3617 
3618  retval = mg_send_ex_cmd(chip, MG_GET_LEKB, 0);
3619  if (retval != STATUS_SUCCESS) {
3620  set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3621  TRACE_GOTO(chip, GetEKBFinish);
3622  }
3623 
3624  retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA,
3625  3, WAIT_INT, 0, 0, buf + 4, 1536);
3626  if (retval != STATUS_SUCCESS) {
3627  set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3628  rtsx_clear_ms_error(chip);
3629  TRACE_GOTO(chip, GetEKBFinish);
3630  }
3631  if (check_ms_err(chip)) {
3632  set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3633  rtsx_clear_ms_error(chip);
3634  TRACE_RET(chip, STATUS_FAIL);
3635  }
3636 
3637  bufflen = min(1052, (int)scsi_bufflen(srb));
3638  rtsx_stor_set_xfer_buf(buf, bufflen, srb);
3639 
3640 GetEKBFinish:
3641  kfree(buf);
3642  return retval;
3643 }
3644 
3645 int mg_chg(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3646 {
3647  struct ms_info *ms_card = &(chip->ms_card);
3648  int retval;
3649  int bufflen;
3650  int i;
3651  unsigned int lun = SCSI_LUN(srb);
3652  u8 buf[32];
3653 
3654  RTSX_DEBUGP("--%s--\n", __func__);
3655 
3656  ms_cleanup_work(chip);
3657 
3658  retval = ms_switch_clock(chip);
3659  if (retval != STATUS_SUCCESS)
3660  TRACE_RET(chip, STATUS_FAIL);
3661 
3662  retval = mg_send_ex_cmd(chip, MG_GET_ID, 0);
3663  if (retval != STATUS_SUCCESS) {
3664  set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
3665  TRACE_RET(chip, STATUS_FAIL);
3666  }
3667 
3668  retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, 32, WAIT_INT, buf, 32);
3669  if (retval != STATUS_SUCCESS) {
3670  set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
3671  TRACE_RET(chip, STATUS_FAIL);
3672  }
3673  if (check_ms_err(chip)) {
3674  set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
3675  rtsx_clear_ms_error(chip);
3676  TRACE_RET(chip, STATUS_FAIL);
3677  }
3678 
3679  memcpy(ms_card->magic_gate_id, buf, 16);
3680 
3681 #ifdef READ_BYTES_WAIT_INT
3682  retval = ms_poll_int(chip);
3683  if (retval != STATUS_SUCCESS) {
3684  set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
3685  TRACE_RET(chip, STATUS_FAIL);
3686  }
3687 #endif
3688 
3689  retval = mg_send_ex_cmd(chip, MG_SET_RD, 0);
3690  if (retval != STATUS_SUCCESS) {
3691  set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
3692  TRACE_RET(chip, STATUS_FAIL);
3693  }
3694 
3695  bufflen = min(12, (int)scsi_bufflen(srb));
3696  rtsx_stor_get_xfer_buf(buf, bufflen, srb);
3697 
3698  for (i = 0; i < 8; i++)
3699  buf[i] = buf[4+i];
3700 
3701  for (i = 0; i < 24; i++)
3702  buf[8+i] = 0;
3703 
3704  retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA,
3705  32, WAIT_INT, buf, 32);
3706  if (retval != STATUS_SUCCESS) {
3707  set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
3708  TRACE_RET(chip, STATUS_FAIL);
3709  }
3710  if (check_ms_err(chip)) {
3711  set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
3712  rtsx_clear_ms_error(chip);
3713  TRACE_RET(chip, STATUS_FAIL);
3714  }
3715 
3716  ms_card->mg_auth = 0;
3717 
3718  return STATUS_SUCCESS;
3719 }
3720 
3721 int mg_get_rsp_chg(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3722 {
3723  struct ms_info *ms_card = &(chip->ms_card);
3724  int retval;
3725  int bufflen;
3726  unsigned int lun = SCSI_LUN(srb);
3727  u8 buf1[32], buf2[36];
3728 
3729  RTSX_DEBUGP("--%s--\n", __func__);
3730 
3731  ms_cleanup_work(chip);
3732 
3733  retval = ms_switch_clock(chip);
3734  if (retval != STATUS_SUCCESS)
3735  TRACE_RET(chip, STATUS_FAIL);
3736 
3737  retval = mg_send_ex_cmd(chip, MG_MAKE_RMS, 0);
3738  if (retval != STATUS_SUCCESS) {
3739  set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3740  TRACE_RET(chip, STATUS_FAIL);
3741  }
3742 
3743  retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, 32, WAIT_INT, buf1, 32);
3744  if (retval != STATUS_SUCCESS) {
3745  set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3746  TRACE_RET(chip, STATUS_FAIL);
3747  }
3748  if (check_ms_err(chip)) {
3749  set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3750  rtsx_clear_ms_error(chip);
3751  TRACE_RET(chip, STATUS_FAIL);
3752  }
3753 
3754  buf2[0] = 0x00;
3755  buf2[1] = 0x22;
3756  buf2[2] = 0x00;
3757  buf2[3] = 0x00;
3758 
3759  memcpy(buf2 + 4, ms_card->magic_gate_id, 16);
3760  memcpy(buf2 + 20, buf1, 16);
3761 
3762  bufflen = min(36, (int)scsi_bufflen(srb));
3763  rtsx_stor_set_xfer_buf(buf2, bufflen, srb);
3764 
3765 #ifdef READ_BYTES_WAIT_INT
3766  retval = ms_poll_int(chip);
3767  if (retval != STATUS_SUCCESS) {
3768  set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3769  TRACE_RET(chip, STATUS_FAIL);
3770  }
3771 #endif
3772 
3773  return STATUS_SUCCESS;
3774 }
3775 
3776 int mg_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3777 {
3778  struct ms_info *ms_card = &(chip->ms_card);
3779  int retval;
3780  int i;
3781  int bufflen;
3782  unsigned int lun = SCSI_LUN(srb);
3783  u8 buf[32];
3784 
3785  RTSX_DEBUGP("--%s--\n", __func__);
3786 
3787  ms_cleanup_work(chip);
3788 
3789  retval = ms_switch_clock(chip);
3790  if (retval != STATUS_SUCCESS)
3791  TRACE_RET(chip, STATUS_FAIL);
3792 
3793  retval = mg_send_ex_cmd(chip, MG_MAKE_KSE, 0);
3794  if (retval != STATUS_SUCCESS) {
3795  set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3796  TRACE_RET(chip, STATUS_FAIL);
3797  }
3798 
3799  bufflen = min(12, (int)scsi_bufflen(srb));
3800  rtsx_stor_get_xfer_buf(buf, bufflen, srb);
3801 
3802  for (i = 0; i < 8; i++)
3803  buf[i] = buf[4+i];
3804 
3805  for (i = 0; i < 24; i++)
3806  buf[8+i] = 0;
3807 
3808  retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 32, WAIT_INT, buf, 32);
3809  if (retval != STATUS_SUCCESS) {
3810  set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3811  TRACE_RET(chip, STATUS_FAIL);
3812  }
3813  if (check_ms_err(chip)) {
3814  set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3815  rtsx_clear_ms_error(chip);
3816  TRACE_RET(chip, STATUS_FAIL);
3817  }
3818 
3819  ms_card->mg_auth = 1;
3820 
3821  return STATUS_SUCCESS;
3822 }
3823 
3824 int mg_get_ICV(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3825 {
3826  struct ms_info *ms_card = &(chip->ms_card);
3827  int retval;
3828  int bufflen;
3829  unsigned int lun = SCSI_LUN(srb);
3830  u8 *buf = NULL;
3831 
3832  RTSX_DEBUGP("--%s--\n", __func__);
3833 
3834  ms_cleanup_work(chip);
3835 
3836  retval = ms_switch_clock(chip);
3837  if (retval != STATUS_SUCCESS)
3838  TRACE_RET(chip, STATUS_FAIL);
3839 
3840  buf = kmalloc(1028, GFP_KERNEL);
3841  if (!buf)
3842  TRACE_RET(chip, STATUS_ERROR);
3843 
3844  buf[0] = 0x04;
3845  buf[1] = 0x02;
3846  buf[2] = 0x00;
3847  buf[3] = 0x00;
3848 
3849  retval = mg_send_ex_cmd(chip, MG_GET_IBD, ms_card->mg_entry_num);
3850  if (retval != STATUS_SUCCESS) {
3851  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3852  TRACE_GOTO(chip, GetICVFinish);
3853  }
3854 
3855  retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA,
3856  2, WAIT_INT, 0, 0, buf + 4, 1024);
3857  if (retval != STATUS_SUCCESS) {
3858  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3859  rtsx_clear_ms_error(chip);
3860  TRACE_GOTO(chip, GetICVFinish);
3861  }
3862  if (check_ms_err(chip)) {
3863  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3864  rtsx_clear_ms_error(chip);
3865  TRACE_RET(chip, STATUS_FAIL);
3866  }
3867 
3868  bufflen = min(1028, (int)scsi_bufflen(srb));
3869  rtsx_stor_set_xfer_buf(buf, bufflen, srb);
3870 
3871 GetICVFinish:
3872  kfree(buf);
3873  return retval;
3874 }
3875 
3876 int mg_set_ICV(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3877 {
3878  struct ms_info *ms_card = &(chip->ms_card);
3879  int retval;
3880  int bufflen;
3881 #ifdef MG_SET_ICV_SLOW
3882  int i;
3883 #endif
3884  unsigned int lun = SCSI_LUN(srb);
3885  u8 *buf = NULL;
3886 
3887  RTSX_DEBUGP("--%s--\n", __func__);
3888 
3889  ms_cleanup_work(chip);
3890 
3891  retval = ms_switch_clock(chip);
3892  if (retval != STATUS_SUCCESS)
3893  TRACE_RET(chip, STATUS_FAIL);
3894 
3895  buf = kmalloc(1028, GFP_KERNEL);
3896  if (!buf)
3897  TRACE_RET(chip, STATUS_ERROR);
3898 
3899  bufflen = min(1028, (int)scsi_bufflen(srb));
3900  rtsx_stor_get_xfer_buf(buf, bufflen, srb);
3901 
3902  retval = mg_send_ex_cmd(chip, MG_SET_IBD, ms_card->mg_entry_num);
3903  if (retval != STATUS_SUCCESS) {
3904  if (ms_card->mg_auth == 0) {
3905  if ((buf[5] & 0xC0) != 0)
3906  set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
3907  else
3908  set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR);
3909  } else {
3910  set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR);
3911  }
3912  TRACE_GOTO(chip, SetICVFinish);
3913  }
3914 
3915 #ifdef MG_SET_ICV_SLOW
3916  for (i = 0; i < 2; i++) {
3917  udelay(50);
3918 
3919  rtsx_init_cmd(chip);
3920 
3921  rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, PRO_WRITE_LONG_DATA);
3922  rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, WAIT_INT);
3923  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
3924 
3925  trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512);
3926 
3927  rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
3928  MS_TRANSFER_START | MS_TM_NORMAL_WRITE);
3929  rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END);
3930 
3931  rtsx_send_cmd_no_wait(chip);
3932 
3933  retval = rtsx_transfer_data(chip, MS_CARD, buf + 4 + i*512, 512, 0, DMA_TO_DEVICE, 3000);
3934  if ((retval < 0) || check_ms_err(chip)) {
3935  rtsx_clear_ms_error(chip);
3936  if (ms_card->mg_auth == 0) {
3937  if ((buf[5] & 0xC0) != 0)
3938  set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
3939  else
3940  set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR);
3941  } else {
3942  set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR);
3943  }
3944  retval = STATUS_FAIL;
3945  TRACE_GOTO(chip, SetICVFinish);
3946  }
3947  }
3948 #else
3949  retval = ms_transfer_data(chip, MS_TM_AUTO_WRITE, PRO_WRITE_LONG_DATA,
3950  2, WAIT_INT, 0, 0, buf + 4, 1024);
3951  if ((retval != STATUS_SUCCESS) || check_ms_err(chip)) {
3952  rtsx_clear_ms_error(chip);
3953  if (ms_card->mg_auth == 0) {
3954  if ((buf[5] & 0xC0) != 0)
3955  set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
3956  else
3957  set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR);
3958  } else {
3959  set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR);
3960  }
3961  TRACE_GOTO(chip, SetICVFinish);
3962  }
3963 #endif
3964 
3965 SetICVFinish:
3966  kfree(buf);
3967  return retval;
3968 }
3969 
3970 #endif /* SUPPORT_MAGIC_GATE */
3971 
3972 void ms_cleanup_work(struct rtsx_chip *chip)
3973 {
3974  struct ms_info *ms_card = &(chip->ms_card);
3975 
3976  if (CHK_MSPRO(ms_card)) {
3977  if (ms_card->seq_mode) {
3978  RTSX_DEBUGP("MS Pro: stop transmission\n");
3979  mspro_stop_seq_mode(chip);
3980  ms_card->cleanup_counter = 0;
3981  }
3982  if (CHK_MSHG(ms_card)) {
3983  rtsx_write_register(chip, MS_CFG,
3984  MS_2K_SECTOR_MODE, 0x00);
3985  }
3986  }
3987 #ifdef MS_DELAY_WRITE
3988  else if ((!CHK_MSPRO(ms_card)) && ms_card->delay_write.delay_write_flag) {
3989  RTSX_DEBUGP("MS: delay write\n");
3990  ms_delay_write(chip);
3991  ms_card->cleanup_counter = 0;
3992  }
3993 #endif
3994 }
3995 
3996 int ms_power_off_card3v3(struct rtsx_chip *chip)
3997 {
3998  int retval;
3999 
4000  retval = disable_card_clock(chip, MS_CARD);
4001  if (retval != STATUS_SUCCESS)
4002  TRACE_RET(chip, STATUS_FAIL);
4003 
4004  if (chip->asic_code) {
4005  retval = ms_pull_ctl_disable(chip);
4006  if (retval != STATUS_SUCCESS)
4007  TRACE_RET(chip, STATUS_FAIL);
4008  } else {
4009  RTSX_WRITE_REG(chip, FPGA_PULL_CTL,
4010  FPGA_MS_PULL_CTL_BIT | 0x20, FPGA_MS_PULL_CTL_BIT);
4011  }
4012  RTSX_WRITE_REG(chip, CARD_OE, MS_OUTPUT_EN, 0);
4013  if (!chip->ft2_fast_mode) {
4014  retval = card_power_off(chip, MS_CARD);
4015  if (retval != STATUS_SUCCESS)
4016  TRACE_RET(chip, STATUS_FAIL);
4017  }
4018 
4019  return STATUS_SUCCESS;
4020 }
4021 
4022 int release_ms_card(struct rtsx_chip *chip)
4023 {
4024  struct ms_info *ms_card = &(chip->ms_card);
4025  int retval;
4026 
4027  RTSX_DEBUGP("release_ms_card\n");
4028 
4029 #ifdef MS_DELAY_WRITE
4030  ms_card->delay_write.delay_write_flag = 0;
4031 #endif
4032  ms_card->pro_under_formatting = 0;
4033 
4034  chip->card_ready &= ~MS_CARD;
4035  chip->card_fail &= ~MS_CARD;
4036  chip->card_wp &= ~MS_CARD;
4037 
4038  ms_free_l2p_tbl(chip);
4039 
4040  memset(ms_card->raw_sys_info, 0, 96);
4041 #ifdef SUPPORT_PCGL_1P18
4042  memset(ms_card->raw_model_name, 0, 48);
4043 #endif
4044 
4045  retval = ms_power_off_card3v3(chip);
4046  if (retval != STATUS_SUCCESS)
4047  TRACE_RET(chip, STATUS_FAIL);
4048 
4049  return STATUS_SUCCESS;
4050 }
4051 
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