|
| #define | pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| |
| #define | FST_MAX_PORTS 4 |
| |
| #define | FST_MAX_CARDS 32 |
| |
| #define | FST_TX_QUEUE_LEN |
| |
| #define | FST_TXQ_DEPTH |
| |
| #define | FST_HIGH_WATER_MARK |
| |
| #define | FST_LOW_WATER_MARK |
| |
| #define | FST_MAX_MTU 8000 /* Huge but possible */ |
| |
| #define | FST_DEF_MTU 1500 /* Common sane value */ |
| |
| #define | FST_TX_TIMEOUT (2*HZ) |
| |
| #define | ARPHRD_MYTYPE ARPHRD_HDLC /* Cisco-HDLC (keepalives etc) */ |
| |
| #define | SMC_VERSION 24 |
| |
| #define | FST_MEMSIZE 0x100000 /* Size of card memory (1Mb) */ |
| |
| #define | SMC_BASE |
| |
| #define | BFM_BASE |
| |
| #define | LEN_TX_BUFFER 8192 /* Size of packet buffers */ |
| |
| #define | LEN_RX_BUFFER 8192 |
| |
| #define | LEN_SMALL_TX_BUFFER 256 /* Size of obsolete buffs used for DOS diags */ |
| |
| #define | LEN_SMALL_RX_BUFFER 256 |
| |
| #define | NUM_TX_BUFFER 2 /* Must be power of 2. Fixed by firmware */ |
| |
| #define | NUM_RX_BUFFER 8 |
| |
| #define | INT_RETRY_TIME 2 |
| |
| #define | cnv_bcnt(len) (-(len)) |
| |
| #define | DMA_OWN 0x80 /* SmartDMA owns the descriptor */ |
| |
| #define | TX_STP 0x02 /* Tx: start of packet */ |
| |
| #define | TX_ENP 0x01 /* Tx: end of packet */ |
| |
| #define | RX_ERR 0x40 /* Rx: error (OR of next 4 bits) */ |
| |
| #define | RX_FRAM 0x20 /* Rx: framing error */ |
| |
| #define | RX_OFLO 0x10 /* Rx: overflow error */ |
| |
| #define | RX_CRC 0x08 /* Rx: CRC error */ |
| |
| #define | RX_HBUF 0x04 /* Rx: buffer error */ |
| |
| #define | RX_STP 0x02 /* Rx: start of packet */ |
| |
| #define | RX_ENP 0x01 /* Rx: end of packet */ |
| |
| #define | MAX_CIRBUFF 32 |
| |
| #define | CTLA_CHG 0x18 /* Control signal changed */ |
| |
| #define | CTLB_CHG 0x19 |
| |
| #define | CTLC_CHG 0x1A |
| |
| #define | CTLD_CHG 0x1B |
| |
| #define | INIT_CPLT 0x20 /* Initialisation complete */ |
| |
| #define | INIT_FAIL 0x21 /* Initialisation failed */ |
| |
| #define | ABTA_SENT 0x24 /* Abort sent */ |
| |
| #define | ABTB_SENT 0x25 |
| |
| #define | ABTC_SENT 0x26 |
| |
| #define | ABTD_SENT 0x27 |
| |
| #define | TXA_UNDF 0x28 /* Transmission underflow */ |
| |
| #define | TXB_UNDF 0x29 |
| |
| #define | TXC_UNDF 0x2A |
| |
| #define | TXD_UNDF 0x2B |
| |
| #define | F56_INT 0x2C |
| |
| #define | M32_INT 0x2D |
| |
| #define | TE1_ALMA 0x30 |
| |
| #define | END_SIG 0x12345678 |
| |
| #define | NOP 0 /* No operation */ |
| |
| #define | ACK 1 /* Positive acknowledgement to PC driver */ |
| |
| #define | NAK 2 /* Negative acknowledgement to PC driver */ |
| |
| #define | STARTPORT 3 /* Start an HDLC port */ |
| |
| #define | STOPPORT 4 /* Stop an HDLC port */ |
| |
| #define | ABORTTX 5 /* Abort the transmitter for a port */ |
| |
| #define | SETV24O 6 /* Set V24 outputs */ |
| |
| #define | CNTRL_9052 0x50 /* Control Register */ |
| |
| #define | CNTRL_9054 0x6c /* Control Register */ |
| |
| #define | INTCSR_9052 0x4c /* Interrupt control/status register */ |
| |
| #define | INTCSR_9054 0x68 /* Interrupt control/status register */ |
| |
| #define | DMAMODE0 0x80 |
| |
| #define | DMAPADR0 0x84 |
| |
| #define | DMALADR0 0x88 |
| |
| #define | DMASIZ0 0x8c |
| |
| #define | DMADPR0 0x90 |
| |
| #define | DMAMODE1 0x94 |
| |
| #define | DMAPADR1 0x98 |
| |
| #define | DMALADR1 0x9c |
| |
| #define | DMASIZ1 0xa0 |
| |
| #define | DMADPR1 0xa4 |
| |
| #define | DMACSR0 0xa8 |
| |
| #define | DMACSR1 0xa9 |
| |
| #define | DMAARB 0xac |
| |
| #define | DMATHR 0xb0 |
| |
| #define | DMADAC0 0xb4 |
| |
| #define | DMADAC1 0xb8 |
| |
| #define | DMAMARBR 0xac |
| |
| #define | FST_MIN_DMA_LEN 64 |
| |
| #define | FST_RX_DMA_INT 0x01 |
| |
| #define | FST_TX_DMA_INT 0x02 |
| |
| #define | FST_CARD_INT 0x04 |
| |
| #define | BUF_OFFSET(X) (BFM_BASE + offsetof(struct buf_window, X)) |
| |
| #define | dev_to_port(D) (dev_to_hdlc(D)->priv) |
| |
| #define | port_to_dev(P) ((P)->dev) |
| |
| #define | WIN_OFFSET(X) ((long)&(((struct fst_shared *)SMC_BASE)->X)) |
| |
| #define | FST_RDB(C, E) readb ((C)->mem + WIN_OFFSET(E)) |
| |
| #define | FST_RDW(C, E) readw ((C)->mem + WIN_OFFSET(E)) |
| |
| #define | FST_RDL(C, E) readl ((C)->mem + WIN_OFFSET(E)) |
| |
| #define | FST_WRB(C, E, B) writeb ((B), (C)->mem + WIN_OFFSET(E)) |
| |
| #define | FST_WRW(C, E, W) writew ((W), (C)->mem + WIN_OFFSET(E)) |
| |
| #define | FST_WRL(C, E, L) writel ((L), (C)->mem + WIN_OFFSET(E)) |
| |
| #define | dbg(F, fmt, args...) |
| |
1.8.2