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Data Structures | Macros
s2io-regs.h File Reference

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Data Structures

struct  XENA_dev_config
 

Macros

#define TBD   0
 
#define GEN_INTR_TXPIC   s2BIT(0)
 
#define GEN_INTR_TXDMA   s2BIT(1)
 
#define GEN_INTR_TXMAC   s2BIT(2)
 
#define GEN_INTR_TXXGXS   s2BIT(3)
 
#define GEN_INTR_TXTRAFFIC   s2BIT(8)
 
#define GEN_INTR_RXPIC   s2BIT(32)
 
#define GEN_INTR_RXDMA   s2BIT(33)
 
#define GEN_INTR_RXMAC   s2BIT(34)
 
#define GEN_INTR_MC   s2BIT(35)
 
#define GEN_INTR_RXXGXS   s2BIT(36)
 
#define GEN_INTR_RXTRAFFIC   s2BIT(40)
 
#define GEN_ERROR_INTR
 
#define SW_RESET_XENA   vBIT(0xA5,0,8)
 
#define SW_RESET_FLASH   vBIT(0xA5,8,8)
 
#define SW_RESET_EOI   vBIT(0xA5,16,8)
 
#define SW_RESET_ALL
 
#define SW_RESET_RAW_VAL   0xA5000000
 
#define ADAPTER_STATUS_TDMA_READY   s2BIT(0)
 
#define ADAPTER_STATUS_RDMA_READY   s2BIT(1)
 
#define ADAPTER_STATUS_PFC_READY   s2BIT(2)
 
#define ADAPTER_STATUS_TMAC_BUF_EMPTY   s2BIT(3)
 
#define ADAPTER_STATUS_PIC_QUIESCENT   s2BIT(5)
 
#define ADAPTER_STATUS_RMAC_REMOTE_FAULT   s2BIT(6)
 
#define ADAPTER_STATUS_RMAC_LOCAL_FAULT   s2BIT(7)
 
#define ADAPTER_STATUS_RMAC_PCC_IDLE   vBIT(0xFF,8,8)
 
#define ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE   vBIT(0x0F,8,8)
 
#define ADAPTER_STATUS_RC_PRC_QUIESCENT   vBIT(0xFF,16,8)
 
#define ADAPTER_STATUS_MC_DRAM_READY   s2BIT(24)
 
#define ADAPTER_STATUS_MC_QUEUES_READY   s2BIT(25)
 
#define ADAPTER_STATUS_RIC_RUNNING   s2BIT(26)
 
#define ADAPTER_STATUS_M_PLL_LOCK   s2BIT(30)
 
#define ADAPTER_STATUS_P_PLL_LOCK   s2BIT(31)
 
#define ADAPTER_CNTL_EN   s2BIT(7)
 
#define ADAPTER_EOI_TX_ON   s2BIT(15)
 
#define ADAPTER_LED_ON   s2BIT(23)
 
#define ADAPTER_UDPI(val)   vBIT(val,36,4)
 
#define ADAPTER_WAIT_INT   s2BIT(48)
 
#define ADAPTER_ECC_EN   s2BIT(55)
 
#define SERR_SOURCE_PIC   s2BIT(0)
 
#define SERR_SOURCE_TXDMA   s2BIT(1)
 
#define SERR_SOURCE_RXDMA   s2BIT(2)
 
#define SERR_SOURCE_MAC   s2BIT(3)
 
#define SERR_SOURCE_MC   s2BIT(4)
 
#define SERR_SOURCE_XGXS   s2BIT(5)
 
#define SERR_SOURCE_ANY
 
#define GET_PCI_MODE(val)   ((val & vBIT(0xF, 0, 4)) >> 60)
 
#define PCI_MODE_PCI_33   0
 
#define PCI_MODE_PCI_66   0x1
 
#define PCI_MODE_PCIX_M1_66   0x2
 
#define PCI_MODE_PCIX_M1_100   0x3
 
#define PCI_MODE_PCIX_M1_133   0x4
 
#define PCI_MODE_PCIX_M2_66   0x5
 
#define PCI_MODE_PCIX_M2_100   0x6
 
#define PCI_MODE_PCIX_M2_133   0x7
 
#define PCI_MODE_UNSUPPORTED   s2BIT(0)
 
#define PCI_MODE_32_BITS   s2BIT(8)
 
#define PCI_MODE_UNKNOWN_MODE   s2BIT(9)
 
#define PIC_INT_TX   s2BIT(0)
 
#define PIC_INT_FLSH   s2BIT(1)
 
#define PIC_INT_MDIO   s2BIT(2)
 
#define PIC_INT_IIC   s2BIT(3)
 
#define PIC_INT_GPIO   s2BIT(4)
 
#define PIC_INT_RX   s2BIT(32)
 
#define PCIX_INT_REG_ECC_SG_ERR   s2BIT(0)
 
#define PCIX_INT_REG_ECC_DB_ERR   s2BIT(1)
 
#define PCIX_INT_REG_FLASHR_R_FSM_ERR   s2BIT(8)
 
#define PCIX_INT_REG_FLASHR_W_FSM_ERR   s2BIT(9)
 
#define PCIX_INT_REG_INI_TX_FSM_SERR   s2BIT(10)
 
#define PCIX_INT_REG_INI_TXO_FSM_ERR   s2BIT(11)
 
#define PCIX_INT_REG_TRT_FSM_SERR   s2BIT(13)
 
#define PCIX_INT_REG_SRT_FSM_SERR   s2BIT(14)
 
#define PCIX_INT_REG_PIFR_FSM_SERR   s2BIT(15)
 
#define PCIX_INT_REG_WRC_TX_SEND_FSM_SERR   s2BIT(21)
 
#define PCIX_INT_REG_RRC_TX_REQ_FSM_SERR   s2BIT(23)
 
#define PCIX_INT_REG_INI_RX_FSM_SERR   s2BIT(48)
 
#define PCIX_INT_REG_RA_RX_FSM_SERR   s2BIT(50)
 
#define PIC_FLSH_INT_REG_CYCLE_FSM_ERR   s2BIT(63)
 
#define PIC_FLSH_INT_REG_ERR   s2BIT(62)
 
#define MDIO_INT_REG_MDIO_BUS_ERR   s2BIT(0)
 
#define MDIO_INT_REG_DTX_BUS_ERR   s2BIT(8)
 
#define MDIO_INT_REG_LASI   s2BIT(39)
 
#define IIC_INT_REG_BUS_FSM_ERR   s2BIT(4)
 
#define IIC_INT_REG_BIT_FSM_ERR   s2BIT(5)
 
#define IIC_INT_REG_CYCLE_FSM_ERR   s2BIT(6)
 
#define IIC_INT_REG_REQ_FSM_ERR   s2BIT(7)
 
#define IIC_INT_REG_ACK_ERR   s2BIT(8)
 
#define GPIO_INT_REG_DP_ERR_INT   s2BIT(0)
 
#define GPIO_INT_REG_LINK_DOWN   s2BIT(1)
 
#define GPIO_INT_REG_LINK_UP   s2BIT(2)
 
#define GPIO_INT_MASK_LINK_DOWN   s2BIT(1)
 
#define GPIO_INT_MASK_LINK_UP   s2BIT(2)
 
#define TX_TRAFFIC_INT_n(n)   s2BIT(n)
 
#define RX_TRAFFIC_INT_n(n)   s2BIT(n)
 
#define PIC_CNTL_RX_ALARM_MAP_1   s2BIT(0)
 
#define PIC_CNTL_SHARED_SPLITS(n)   vBIT(n,11,5)
 
#define SWAPPER_CTRL_PIF_R_FE   s2BIT(0)
 
#define SWAPPER_CTRL_PIF_R_SE   s2BIT(1)
 
#define SWAPPER_CTRL_PIF_W_FE   s2BIT(8)
 
#define SWAPPER_CTRL_PIF_W_SE   s2BIT(9)
 
#define SWAPPER_CTRL_TXP_FE   s2BIT(16)
 
#define SWAPPER_CTRL_TXP_SE   s2BIT(17)
 
#define SWAPPER_CTRL_TXD_R_FE   s2BIT(18)
 
#define SWAPPER_CTRL_TXD_R_SE   s2BIT(19)
 
#define SWAPPER_CTRL_TXD_W_FE   s2BIT(20)
 
#define SWAPPER_CTRL_TXD_W_SE   s2BIT(21)
 
#define SWAPPER_CTRL_TXF_R_FE   s2BIT(22)
 
#define SWAPPER_CTRL_TXF_R_SE   s2BIT(23)
 
#define SWAPPER_CTRL_RXD_R_FE   s2BIT(32)
 
#define SWAPPER_CTRL_RXD_R_SE   s2BIT(33)
 
#define SWAPPER_CTRL_RXD_W_FE   s2BIT(34)
 
#define SWAPPER_CTRL_RXD_W_SE   s2BIT(35)
 
#define SWAPPER_CTRL_RXF_W_FE   s2BIT(36)
 
#define SWAPPER_CTRL_RXF_W_SE   s2BIT(37)
 
#define SWAPPER_CTRL_XMSI_FE   s2BIT(40)
 
#define SWAPPER_CTRL_XMSI_SE   s2BIT(41)
 
#define SWAPPER_CTRL_STATS_FE   s2BIT(48)
 
#define SWAPPER_CTRL_STATS_SE   s2BIT(49)
 
#define IF_RD_SWAPPER_FB   0x0123456789ABCDEF
 
#define SCHED_INT_CTRL_TIMER_EN   s2BIT(0)
 
#define SCHED_INT_CTRL_ONE_SHOT   s2BIT(1)
 
#define SCHED_INT_CTRL_INT2MSI(val)   vBIT(val,10,6)
 
#define SCHED_INT_PERIOD   TBD
 
#define TXREQTO_VAL(val)   vBIT(val,0,32)
 
#define TXREQTO_EN   s2BIT(63)
 
#define STATREQTO_VAL(n)   TBD
 
#define STATREQTO_EN   s2BIT(63)
 
#define RX_MAT_SET(ring, msi)   vBIT(msi, (8 * ring), 8)
 
#define TX_MAT_SET(fifo, msi)   vBIT(msi, (8 * fifo), 8)
 
#define STAT_BC(n)   vBIT(n,4,12)
 
#define STAT_CFG_STAT_EN   s2BIT(0)
 
#define STAT_CFG_ONE_SHOT_EN   s2BIT(1)
 
#define STAT_CFG_STAT_NS_EN   s2BIT(8)
 
#define STAT_CFG_STAT_RO   s2BIT(9)
 
#define STAT_TRSF_PER(n)   TBD
 
#define PER_SEC   0x208d5
 
#define SET_UPDT_PERIOD(n)   vBIT((PER_SEC*n),32,32)
 
#define SET_UPDT_CLICKS(val)   vBIT(val, 32, 32)
 
#define MDIO_MMD_INDX_ADDR(val)   vBIT(val, 0, 16)
 
#define MDIO_MMD_DEV_ADDR(val)   vBIT(val, 19, 5)
 
#define MDIO_MMS_PRT_ADDR(val)   vBIT(val, 27, 5)
 
#define MDIO_CTRL_START_TRANS(val)   vBIT(val, 56, 4)
 
#define MDIO_OP(val)   vBIT(val, 60, 2)
 
#define MDIO_OP_ADDR_TRANS   0x0
 
#define MDIO_OP_WRITE_TRANS   0x1
 
#define MDIO_OP_READ_POST_INC_TRANS   0x2
 
#define MDIO_OP_READ_TRANS   0x3
 
#define MDIO_MDIO_DATA(val)   vBIT(val, 32, 16)
 
#define I2C_CONTROL_DEV_ID(id)   vBIT(id,1,3)
 
#define I2C_CONTROL_ADDR(addr)   vBIT(addr,5,11)
 
#define I2C_CONTROL_BYTE_CNT(cnt)   vBIT(cnt,22,2)
 
#define I2C_CONTROL_READ   s2BIT(24)
 
#define I2C_CONTROL_NACK   s2BIT(25)
 
#define I2C_CONTROL_CNTL_START   vBIT(0xE,28,4)
 
#define I2C_CONTROL_CNTL_END(val)   (val & vBIT(0x1,28,4))
 
#define I2C_CONTROL_GET_DATA(val)   (u32)(val & 0xFFFFFFFF)
 
#define I2C_CONTROL_SET_DATA(val)   vBIT(val,32,32)
 
#define GPIO_CTRL_GPIO_0   s2BIT(8)
 
#define FAULT_BEHAVIOUR   s2BIT(0)
 
#define EXT_REQ_EN   s2BIT(1)
 
#define MISC_LINK_STABILITY_PRD(val)   vBIT(val,29,3)
 
#define WREQ_SPLIT_MASK_SET_MASK(val)   vBIT(val, 52, 12)
 
#define TXDMA_PFC_INT   s2BIT(0)
 
#define TXDMA_TDA_INT   s2BIT(1)
 
#define TXDMA_PCC_INT   s2BIT(2)
 
#define TXDMA_TTI_INT   s2BIT(3)
 
#define TXDMA_LSO_INT   s2BIT(4)
 
#define TXDMA_TPA_INT   s2BIT(5)
 
#define TXDMA_SM_INT   s2BIT(6)
 
#define PFC_ECC_SG_ERR   s2BIT(7)
 
#define PFC_ECC_DB_ERR   s2BIT(15)
 
#define PFC_SM_ERR_ALARM   s2BIT(23)
 
#define PFC_MISC_0_ERR   s2BIT(31)
 
#define PFC_MISC_1_ERR   s2BIT(32)
 
#define PFC_PCIX_ERR   s2BIT(39)
 
#define TDA_Fn_ECC_SG_ERR   vBIT(0xff,0,8)
 
#define TDA_Fn_ECC_DB_ERR   vBIT(0xff,8,8)
 
#define TDA_SM0_ERR_ALARM   s2BIT(22)
 
#define TDA_SM1_ERR_ALARM   s2BIT(23)
 
#define TDA_PCIX_ERR   s2BIT(39)
 
#define PCC_FB_ECC_SG_ERR   vBIT(0xFF,0,8)
 
#define PCC_TXB_ECC_SG_ERR   vBIT(0xFF,8,8)
 
#define PCC_FB_ECC_DB_ERR   vBIT(0xFF,16, 8)
 
#define PCC_TXB_ECC_DB_ERR   vBIT(0xff,24,8)
 
#define PCC_SM_ERR_ALARM   vBIT(0xff,32,8)
 
#define PCC_WR_ERR_ALARM   vBIT(0xff,40,8)
 
#define PCC_N_SERR   vBIT(0xff,48,8)
 
#define PCC_6_COF_OV_ERR   s2BIT(56)
 
#define PCC_7_COF_OV_ERR   s2BIT(57)
 
#define PCC_6_LSO_OV_ERR   s2BIT(58)
 
#define PCC_7_LSO_OV_ERR   s2BIT(59)
 
#define PCC_ENABLE_FOUR   vBIT(0x0F,0,8)
 
#define TTI_ECC_SG_ERR   s2BIT(7)
 
#define TTI_ECC_DB_ERR   s2BIT(15)
 
#define TTI_SM_ERR_ALARM   s2BIT(23)
 
#define LSO6_SEND_OFLOW   s2BIT(12)
 
#define LSO7_SEND_OFLOW   s2BIT(13)
 
#define LSO6_ABORT   s2BIT(14)
 
#define LSO7_ABORT   s2BIT(15)
 
#define LSO6_SM_ERR_ALARM   s2BIT(22)
 
#define LSO7_SM_ERR_ALARM   s2BIT(23)
 
#define TPA_TX_FRM_DROP   s2BIT(7)
 
#define TPA_SM_ERR_ALARM   s2BIT(23)
 
#define SM_SM_ERR_ALARM   s2BIT(15)
 
#define X_MAX_FIFOS   8
 
#define X_FIFO_MAX_LEN   0x1FFF /*8191 */
 
#define TX_FIFO_PARTITION_EN   s2BIT(0)
 
#define TX_FIFO_PARTITION_0_PRI(val)   vBIT(val,5,3)
 
#define TX_FIFO_PARTITION_0_LEN(val)   vBIT(val,19,13)
 
#define TX_FIFO_PARTITION_1_PRI(val)   vBIT(val,37,3)
 
#define TX_FIFO_PARTITION_1_LEN(val)   vBIT(val,51,13 )
 
#define TX_FIFO_PARTITION_2_PRI(val)   vBIT(val,5,3)
 
#define TX_FIFO_PARTITION_2_LEN(val)   vBIT(val,19,13)
 
#define TX_FIFO_PARTITION_3_PRI(val)   vBIT(val,37,3)
 
#define TX_FIFO_PARTITION_3_LEN(val)   vBIT(val,51,13)
 
#define TX_FIFO_PARTITION_4_PRI(val)   vBIT(val,5,3)
 
#define TX_FIFO_PARTITION_4_LEN(val)   vBIT(val,19,13)
 
#define TX_FIFO_PARTITION_5_PRI(val)   vBIT(val,37,3)
 
#define TX_FIFO_PARTITION_5_LEN(val)   vBIT(val,51,13)
 
#define TX_FIFO_PARTITION_6_PRI(val)   vBIT(val,5,3)
 
#define TX_FIFO_PARTITION_6_LEN(val)   vBIT(val,19,13)
 
#define TX_FIFO_PARTITION_7_PRI(val)   vBIT(val,37,3)
 
#define TX_FIFO_PARTITION_7_LEN(val)   vBIT(val,51,13)
 
#define TX_FIFO_PARTITION_PRI_0   0 /* highest */
 
#define TX_FIFO_PARTITION_PRI_1   1
 
#define TX_FIFO_PARTITION_PRI_2   2
 
#define TX_FIFO_PARTITION_PRI_3   3
 
#define TX_FIFO_PARTITION_PRI_4   4
 
#define TX_FIFO_PARTITION_PRI_5   5
 
#define TX_FIFO_PARTITION_PRI_6   6
 
#define TX_FIFO_PARTITION_PRI_7   7 /* lowest */
 
#define TTI_CMD_MEM_WE   s2BIT(7)
 
#define TTI_CMD_MEM_STROBE_NEW_CMD   s2BIT(15)
 
#define TTI_CMD_MEM_STROBE_BEING_EXECUTED   s2BIT(15)
 
#define TTI_CMD_MEM_OFFSET(n)   vBIT(n,26,6)
 
#define TTI_DATA1_MEM_TX_TIMER_VAL(n)   vBIT(n,6,26)
 
#define TTI_DATA1_MEM_TX_TIMER_AC_CI(n)   vBIT(n,38,2)
 
#define TTI_DATA1_MEM_TX_TIMER_AC_EN   s2BIT(38)
 
#define TTI_DATA1_MEM_TX_TIMER_CI_EN   s2BIT(39)
 
#define TTI_DATA1_MEM_TX_URNG_A(n)   vBIT(n,41,7)
 
#define TTI_DATA1_MEM_TX_URNG_B(n)   vBIT(n,49,7)
 
#define TTI_DATA1_MEM_TX_URNG_C(n)   vBIT(n,57,7)
 
#define TTI_DATA2_MEM_TX_UFC_A(n)   vBIT(n,0,16)
 
#define TTI_DATA2_MEM_TX_UFC_B(n)   vBIT(n,16,16)
 
#define TTI_DATA2_MEM_TX_UFC_C(n)   vBIT(n,32,16)
 
#define TTI_DATA2_MEM_TX_UFC_D(n)   vBIT(n,48,16)
 
#define TX_PA_CFG_IGNORE_FRM_ERR   s2BIT(1)
 
#define TX_PA_CFG_IGNORE_SNAP_OUI   s2BIT(2)
 
#define TX_PA_CFG_IGNORE_LLC_CTRL   s2BIT(3)
 
#define TX_PA_CFG_IGNORE_L2_ERR   s2BIT(6)
 
#define RX_PA_CFG_STRIP_VLAN_TAG   s2BIT(15)
 
#define RXDMA_INT_RC_INT_M   s2BIT(0)
 
#define RXDMA_INT_RPA_INT_M   s2BIT(1)
 
#define RXDMA_INT_RDA_INT_M   s2BIT(2)
 
#define RXDMA_INT_RTI_INT_M   s2BIT(3)
 
#define RDA_RXDn_ECC_SG_ERR   vBIT(0xFF,0,8)
 
#define RDA_RXDn_ECC_DB_ERR   vBIT(0xFF,8,8)
 
#define RDA_FRM_ECC_SG_ERR   s2BIT(23)
 
#define RDA_FRM_ECC_DB_N_AERR   s2BIT(31)
 
#define RDA_SM1_ERR_ALARM   s2BIT(38)
 
#define RDA_SM0_ERR_ALARM   s2BIT(39)
 
#define RDA_MISC_ERR   s2BIT(47)
 
#define RDA_PCIX_ERR   s2BIT(55)
 
#define RDA_RXD_ECC_DB_SERR   s2BIT(63)
 
#define RC_PRCn_ECC_SG_ERR   vBIT(0xFF,0,8)
 
#define RC_PRCn_ECC_DB_ERR   vBIT(0xFF,8,8)
 
#define RC_FTC_ECC_SG_ERR   s2BIT(23)
 
#define RC_FTC_ECC_DB_ERR   s2BIT(31)
 
#define RC_PRCn_SM_ERR_ALARM   vBIT(0xFF,32,8)
 
#define RC_FTC_SM_ERR_ALARM   s2BIT(47)
 
#define RC_RDA_FAIL_WR_Rn   vBIT(0xFF,48,8)
 
#define PRC_PCI_AB_RD_Rn   vBIT(0xFF,0,8)
 
#define PRC_PCI_DP_RD_Rn   vBIT(0xFF,8,8)
 
#define PRC_PCI_AB_WR_Rn   vBIT(0xFF,16,8)
 
#define PRC_PCI_DP_WR_Rn   vBIT(0xFF,24,8)
 
#define PRC_PCI_AB_F_WR_Rn   vBIT(0xFF,32,8)
 
#define PRC_PCI_DP_F_WR_Rn   vBIT(0xFF,40,8)
 
#define RPA_ECC_SG_ERR   s2BIT(7)
 
#define RPA_ECC_DB_ERR   s2BIT(15)
 
#define RPA_FLUSH_REQUEST   s2BIT(22)
 
#define RPA_SM_ERR_ALARM   s2BIT(23)
 
#define RPA_CREDIT_ERR   s2BIT(31)
 
#define RTI_ECC_SG_ERR   s2BIT(7)
 
#define RTI_ECC_DB_ERR   s2BIT(15)
 
#define RTI_SM_ERR_ALARM   s2BIT(23)
 
#define RX_QUEUE_0_PRIORITY(val)   vBIT(val,5,3)
 
#define RX_QUEUE_1_PRIORITY(val)   vBIT(val,13,3)
 
#define RX_QUEUE_2_PRIORITY(val)   vBIT(val,21,3)
 
#define RX_QUEUE_3_PRIORITY(val)   vBIT(val,29,3)
 
#define RX_QUEUE_4_PRIORITY(val)   vBIT(val,37,3)
 
#define RX_QUEUE_5_PRIORITY(val)   vBIT(val,45,3)
 
#define RX_QUEUE_6_PRIORITY(val)   vBIT(val,53,3)
 
#define RX_QUEUE_7_PRIORITY(val)   vBIT(val,61,3)
 
#define RX_QUEUE_PRI_0   0 /* highest */
 
#define RX_QUEUE_PRI_1   1
 
#define RX_QUEUE_PRI_2   2
 
#define RX_QUEUE_PRI_3   3
 
#define RX_QUEUE_PRI_4   4
 
#define RX_QUEUE_PRI_5   5
 
#define RX_QUEUE_PRI_6   6
 
#define RX_QUEUE_PRI_7   7 /* lowest */
 
#define RX_MAX_RINGS   8
 
#define PRC_CTRL_RC_ENABLED   s2BIT(7)
 
#define PRC_CTRL_RING_MODE   (s2BIT(14)|s2BIT(15))
 
#define PRC_CTRL_RING_MODE_1   vBIT(0,14,2)
 
#define PRC_CTRL_RING_MODE_3   vBIT(1,14,2)
 
#define PRC_CTRL_RING_MODE_5   vBIT(2,14,2)
 
#define PRC_CTRL_RING_MODE_x   vBIT(3,14,2)
 
#define PRC_CTRL_NO_SNOOP   (s2BIT(22)|s2BIT(23))
 
#define PRC_CTRL_NO_SNOOP_DESC   s2BIT(22)
 
#define PRC_CTRL_NO_SNOOP_BUFF   s2BIT(23)
 
#define PRC_CTRL_BIMODAL_INTERRUPT   s2BIT(37)
 
#define PRC_CTRL_GROUP_READS   s2BIT(38)
 
#define PRC_CTRL_RXD_BACKOFF_INTERVAL(val)   vBIT(val,40,24)
 
#define PRC_ALARM_ACTION_RR_R0_STOP   s2BIT(3)
 
#define PRC_ALARM_ACTION_RW_R0_STOP   s2BIT(7)
 
#define PRC_ALARM_ACTION_RR_R1_STOP   s2BIT(11)
 
#define PRC_ALARM_ACTION_RW_R1_STOP   s2BIT(15)
 
#define PRC_ALARM_ACTION_RR_R2_STOP   s2BIT(19)
 
#define PRC_ALARM_ACTION_RW_R2_STOP   s2BIT(23)
 
#define PRC_ALARM_ACTION_RR_R3_STOP   s2BIT(27)
 
#define PRC_ALARM_ACTION_RW_R3_STOP   s2BIT(31)
 
#define PRC_ALARM_ACTION_RR_R4_STOP   s2BIT(35)
 
#define PRC_ALARM_ACTION_RW_R4_STOP   s2BIT(39)
 
#define PRC_ALARM_ACTION_RR_R5_STOP   s2BIT(43)
 
#define PRC_ALARM_ACTION_RW_R5_STOP   s2BIT(47)
 
#define PRC_ALARM_ACTION_RR_R6_STOP   s2BIT(51)
 
#define PRC_ALARM_ACTION_RW_R6_STOP   s2BIT(55)
 
#define PRC_ALARM_ACTION_RR_R7_STOP   s2BIT(59)
 
#define PRC_ALARM_ACTION_RW_R7_STOP   s2BIT(63)
 
#define RTI_CMD_MEM_WE   s2BIT(7)
 
#define RTI_CMD_MEM_STROBE   s2BIT(15)
 
#define RTI_CMD_MEM_STROBE_NEW_CMD   s2BIT(15)
 
#define RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED   s2BIT(15)
 
#define RTI_CMD_MEM_OFFSET(n)   vBIT(n,29,3)
 
#define RTI_DATA1_MEM_RX_TIMER_VAL(n)   vBIT(n,3,29)
 
#define RTI_DATA1_MEM_RX_TIMER_AC_EN   s2BIT(38)
 
#define RTI_DATA1_MEM_RX_TIMER_CI_EN   s2BIT(39)
 
#define RTI_DATA1_MEM_RX_URNG_A(n)   vBIT(n,41,7)
 
#define RTI_DATA1_MEM_RX_URNG_B(n)   vBIT(n,49,7)
 
#define RTI_DATA1_MEM_RX_URNG_C(n)   vBIT(n,57,7)
 
#define RTI_DATA2_MEM_RX_UFC_A(n)   vBIT(n,0,16)
 
#define RTI_DATA2_MEM_RX_UFC_B(n)   vBIT(n,16,16)
 
#define RTI_DATA2_MEM_RX_UFC_C(n)   vBIT(n,32,16)
 
#define RTI_DATA2_MEM_RX_UFC_D(n)   vBIT(n,48,16)
 
#define RX_PA_CFG_IGNORE_FRM_ERR   s2BIT(1)
 
#define RX_PA_CFG_IGNORE_SNAP_OUI   s2BIT(2)
 
#define RX_PA_CFG_IGNORE_LLC_CTRL   s2BIT(3)
 
#define RX_PA_CFG_IGNORE_L2_ERR   s2BIT(6)
 
#define MAC_INT_STATUS_TMAC_INT   s2BIT(0)
 
#define MAC_INT_STATUS_RMAC_INT   s2BIT(1)
 
#define TMAC_ECC_SG_ERR   s2BIT(7)
 
#define TMAC_ECC_DB_ERR   s2BIT(15)
 
#define TMAC_TX_BUF_OVRN   s2BIT(23)
 
#define TMAC_TX_CRI_ERR   s2BIT(31)
 
#define TMAC_TX_SM_ERR   s2BIT(39)
 
#define TMAC_DESC_ECC_SG_ERR   s2BIT(47)
 
#define TMAC_DESC_ECC_DB_ERR   s2BIT(55)
 
#define RMAC_RX_BUFF_OVRN   s2BIT(0)
 
#define RMAC_FRM_RCVD_INT   s2BIT(1)
 
#define RMAC_UNUSED_INT   s2BIT(2)
 
#define RMAC_RTS_PNUM_ECC_SG_ERR   s2BIT(5)
 
#define RMAC_RTS_DS_ECC_SG_ERR   s2BIT(6)
 
#define RMAC_RD_BUF_ECC_SG_ERR   s2BIT(7)
 
#define RMAC_RTH_MAP_ECC_SG_ERR   s2BIT(8)
 
#define RMAC_RTH_SPDM_ECC_SG_ERR   s2BIT(9)
 
#define RMAC_RTS_VID_ECC_SG_ERR   s2BIT(10)
 
#define RMAC_DA_SHADOW_ECC_SG_ERR   s2BIT(11)
 
#define RMAC_RTS_PNUM_ECC_DB_ERR   s2BIT(13)
 
#define RMAC_RTS_DS_ECC_DB_ERR   s2BIT(14)
 
#define RMAC_RD_BUF_ECC_DB_ERR   s2BIT(15)
 
#define RMAC_RTH_MAP_ECC_DB_ERR   s2BIT(16)
 
#define RMAC_RTH_SPDM_ECC_DB_ERR   s2BIT(17)
 
#define RMAC_RTS_VID_ECC_DB_ERR   s2BIT(18)
 
#define RMAC_DA_SHADOW_ECC_DB_ERR   s2BIT(19)
 
#define RMAC_LINK_STATE_CHANGE_INT   s2BIT(31)
 
#define RMAC_RX_SM_ERR   s2BIT(39)
 
#define RMAC_SINGLE_ECC_ERR
 
#define RMAC_DOUBLE_ECC_ERR
 
#define MAC_CFG_TMAC_ENABLE   s2BIT(0)
 
#define MAC_CFG_RMAC_ENABLE   s2BIT(1)
 
#define MAC_CFG_LAN_NOT_WAN   s2BIT(2)
 
#define MAC_CFG_TMAC_LOOPBACK   s2BIT(3)
 
#define MAC_CFG_TMAC_APPEND_PAD   s2BIT(4)
 
#define MAC_CFG_RMAC_STRIP_FCS   s2BIT(5)
 
#define MAC_CFG_RMAC_STRIP_PAD   s2BIT(6)
 
#define MAC_CFG_RMAC_PROM_ENABLE   s2BIT(7)
 
#define MAC_RMAC_DISCARD_PFRM   s2BIT(8)
 
#define MAC_RMAC_BCAST_ENABLE   s2BIT(9)
 
#define MAC_RMAC_ALL_ADDR_ENABLE   s2BIT(10)
 
#define MAC_RMAC_INVLD_IPG_THR(val)   vBIT(val,16,8)
 
#define TMAC_AVG_IPG(val)   vBIT(val,0,8)
 
#define RMAC_MAX_PYLD_LEN(val)   vBIT(val,2,14)
 
#define RMAC_MAX_PYLD_LEN_DEF   vBIT(1500,2,14)
 
#define RMAC_MAX_PYLD_LEN_JUMBO_DEF   vBIT(9600,2,14)
 
#define RMAC_ERR_FCS   s2BIT(0)
 
#define RMAC_ERR_FCS_ACCEPT   s2BIT(1)
 
#define RMAC_ERR_TOO_LONG   s2BIT(1)
 
#define RMAC_ERR_TOO_LONG_ACCEPT   s2BIT(1)
 
#define RMAC_ERR_RUNT   s2BIT(2)
 
#define RMAC_ERR_RUNT_ACCEPT   s2BIT(2)
 
#define RMAC_ERR_LEN_MISMATCH   s2BIT(3)
 
#define RMAC_ERR_LEN_MISMATCH_ACCEPT   s2BIT(3)
 
#define RMAC_CFG_KEY(val)   vBIT(val,0,16)
 
#define S2IO_MAC_ADDR_START_OFFSET   0
 
#define S2IO_XENA_MAX_MC_ADDRESSES   64 /* multicast addresses */
 
#define S2IO_HERC_MAX_MC_ADDRESSES   256
 
#define S2IO_XENA_MAX_MAC_ADDRESSES   16
 
#define S2IO_HERC_MAX_MAC_ADDRESSES   64
 
#define S2IO_XENA_MC_ADDR_START_OFFSET   16
 
#define S2IO_HERC_MC_ADDR_START_OFFSET   64
 
#define RMAC_ADDR_CMD_MEM_WE   s2BIT(7)
 
#define RMAC_ADDR_CMD_MEM_RD   0
 
#define RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD   s2BIT(15)
 
#define RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING   s2BIT(15)
 
#define RMAC_ADDR_CMD_MEM_OFFSET(n)   vBIT(n,26,6)
 
#define RMAC_ADDR_DATA0_MEM_ADDR(n)   vBIT(n,0,48)
 
#define RMAC_ADDR_DATA0_MEM_USER   s2BIT(48)
 
#define RMAC_ADDR_DATA1_MEM_MASK(n)   vBIT(n,0,48)
 
#define RMAC_PAUSE_GEN   s2BIT(0)
 
#define RMAC_PAUSE_GEN_ENABLE   s2BIT(0)
 
#define RMAC_PAUSE_RX   s2BIT(1)
 
#define RMAC_PAUSE_RX_ENABLE   s2BIT(1)
 
#define RMAC_PAUSE_HG_PTIME_DEF   vBIT(0xFFFF,16,16)
 
#define RMAC_PAUSE_HG_PTIME(val)   vBIT(val,16,16)
 
#define MAC_TX_LINK_UTIL   vBIT(0xFE,1,7)
 
#define MAC_TX_LINK_UTIL_DISABLE   vBIT(0xF, 8,4)
 
#define MAC_TX_LINK_UTIL_VAL(n)   vBIT(n,8,4)
 
#define MAC_RX_LINK_UTIL   vBIT(0xFE,33,7)
 
#define MAC_RX_LINK_UTIL_DISABLE   vBIT(0xF,40,4)
 
#define MAC_RX_LINK_UTIL_VAL(n)   vBIT(n,40,4)
 
#define MAC_LINK_UTIL_DISABLE
 
#define MAC_RTS_FRM_LEN_SET(len)   vBIT(len,2,14)
 
#define MAX_DIX_MAP   4
 
#define RTS_DIX_MAP_ETYPE(val)   vBIT(val,0,16)
 
#define RTS_DIX_MAP_SCW(val)   s2BIT(val,21)
 
#define RTS_CTRL_IGNORE_SNAP_OUI   s2BIT(2)
 
#define RTS_CTRL_IGNORE_LLC_CTRL   s2BIT(3)
 
#define RTS_PN_CAM_CTRL_WE   s2BIT(7)
 
#define RTS_PN_CAM_CTRL_STROBE_NEW_CMD   s2BIT(15)
 
#define RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED   s2BIT(15)
 
#define RTS_PN_CAM_CTRL_OFFSET(n)   vBIT(n,24,8)
 
#define RTS_PN_CAM_DATA_TCP_SELECT   s2BIT(7)
 
#define RTS_PN_CAM_DATA_PORT(val)   vBIT(val,8,16)
 
#define RTS_PN_CAM_DATA_SCW(val)   vBIT(val,24,8)
 
#define RTS_DS_MEM_CTRL_WE   s2BIT(7)
 
#define RTS_DS_MEM_CTRL_STROBE_NEW_CMD   s2BIT(15)
 
#define RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED   s2BIT(15)
 
#define RTS_DS_MEM_CTRL_OFFSET(n)   vBIT(n,26,6)
 
#define RTS_DS_MEM_DATA(n)   vBIT(n,0,8)
 
#define MAC_DBG_ACTIVITY_VALUE   0x411040400000000ULL
 
#define MC_INT_STATUS_MC_INT   s2BIT(0)
 
#define MC_INT_MASK_MC_INT   s2BIT(0)
 
#define MC_ERR_REG_ECC_DB_ERR_L   s2BIT(14)
 
#define MC_ERR_REG_ECC_DB_ERR_U   s2BIT(15)
 
#define MC_ERR_REG_MIRI_ECC_DB_ERR_0   s2BIT(18)
 
#define MC_ERR_REG_MIRI_ECC_DB_ERR_1   s2BIT(20)
 
#define MC_ERR_REG_MIRI_CRI_ERR_0   s2BIT(22)
 
#define MC_ERR_REG_MIRI_CRI_ERR_1   s2BIT(23)
 
#define MC_ERR_REG_SM_ERR   s2BIT(31)
 
#define MC_ERR_REG_ECC_ALL_SNG
 
#define MC_ERR_REG_ECC_ALL_DBL
 
#define PLL_LOCK_N   s2BIT(39)
 
#define RX_QUEUE_CFG_Q0_SZ(n)   vBIT(n,0,8)
 
#define RX_QUEUE_CFG_Q1_SZ(n)   vBIT(n,8,8)
 
#define RX_QUEUE_CFG_Q2_SZ(n)   vBIT(n,16,8)
 
#define RX_QUEUE_CFG_Q3_SZ(n)   vBIT(n,24,8)
 
#define RX_QUEUE_CFG_Q4_SZ(n)   vBIT(n,32,8)
 
#define RX_QUEUE_CFG_Q5_SZ(n)   vBIT(n,40,8)
 
#define RX_QUEUE_CFG_Q6_SZ(n)   vBIT(n,48,8)
 
#define RX_QUEUE_CFG_Q7_SZ(n)   vBIT(n,56,8)
 
#define MC_RLDRAM_QUEUE_SIZE_ENABLE   s2BIT(39)
 
#define MC_RLDRAM_MRS_ENABLE   s2BIT(47)
 
#define MC_RLDRAM_TEST_MODE   s2BIT(47)
 
#define MC_RLDRAM_TEST_WRITE   s2BIT(7)
 
#define MC_RLDRAM_TEST_GO   s2BIT(15)
 
#define MC_RLDRAM_TEST_DONE   s2BIT(23)
 
#define MC_RLDRAM_TEST_PASS   s2BIT(31)
 
#define MC_RLDRAM_ENABLE_ODT   s2BIT(7)
 
#define MC_RLDRAM_SET_REF_PERIOD(val)   vBIT(val, 0, 16)
 
#define XGXS_INT_STATUS_TXGXS   s2BIT(0)
 
#define XGXS_INT_STATUS_RXGXS   s2BIT(1)
 
#define XGXS_INT_MASK_TXGXS   s2BIT(0)
 
#define XGXS_INT_MASK_RXGXS   s2BIT(1)
 
#define TXGXS_ECC_SG_ERR   s2BIT(7)
 
#define TXGXS_ECC_DB_ERR   s2BIT(15)
 
#define TXGXS_ESTORE_UFLOW   s2BIT(31)
 
#define TXGXS_TX_SM_ERR   s2BIT(39)
 
#define RXGXS_ESTORE_OFLOW   s2BIT(7)
 
#define RXGXS_RX_SM_ERR   s2BIT(39)
 
#define SPI_CONTROL_KEY(key)   vBIT(key,0,4)
 
#define SPI_CONTROL_BYTECNT(cnt)   vBIT(cnt,29,3)
 
#define SPI_CONTROL_CMD(cmd)   vBIT(cmd,32,8)
 
#define SPI_CONTROL_ADDR(addr)   vBIT(addr,40,24)
 
#define SPI_CONTROL_SEL1   s2BIT(4)
 
#define SPI_CONTROL_REQ   s2BIT(7)
 
#define SPI_CONTROL_NACK   s2BIT(5)
 
#define SPI_CONTROL_DONE   s2BIT(6)
 
#define SPI_DATA_WRITE(data, len)   vBIT(data,0,len)
 
#define XENA_REG_SPACE   sizeof(struct XENA_dev_config)
 
#define XENA_EEPROM_SPACE   (0x01 << 11)
 

Macro Definition Documentation

#define ADAPTER_CNTL_EN   s2BIT(7)

Definition at line 74 of file s2io-regs.h.

#define ADAPTER_ECC_EN   s2BIT(55)

Definition at line 79 of file s2io-regs.h.

#define ADAPTER_EOI_TX_ON   s2BIT(15)

Definition at line 75 of file s2io-regs.h.

#define ADAPTER_LED_ON   s2BIT(23)

Definition at line 76 of file s2io-regs.h.

#define ADAPTER_STATUS_M_PLL_LOCK   s2BIT(30)

Definition at line 70 of file s2io-regs.h.

#define ADAPTER_STATUS_MC_DRAM_READY   s2BIT(24)

Definition at line 67 of file s2io-regs.h.

#define ADAPTER_STATUS_MC_QUEUES_READY   s2BIT(25)

Definition at line 68 of file s2io-regs.h.

#define ADAPTER_STATUS_P_PLL_LOCK   s2BIT(31)

Definition at line 71 of file s2io-regs.h.

#define ADAPTER_STATUS_PFC_READY   s2BIT(2)

Definition at line 59 of file s2io-regs.h.

#define ADAPTER_STATUS_PIC_QUIESCENT   s2BIT(5)

Definition at line 61 of file s2io-regs.h.

#define ADAPTER_STATUS_RC_PRC_QUIESCENT   vBIT(0xFF,16,8)

Definition at line 66 of file s2io-regs.h.

#define ADAPTER_STATUS_RDMA_READY   s2BIT(1)

Definition at line 58 of file s2io-regs.h.

#define ADAPTER_STATUS_RIC_RUNNING   s2BIT(26)

Definition at line 69 of file s2io-regs.h.

#define ADAPTER_STATUS_RMAC_LOCAL_FAULT   s2BIT(7)

Definition at line 63 of file s2io-regs.h.

#define ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE   vBIT(0x0F,8,8)

Definition at line 65 of file s2io-regs.h.

#define ADAPTER_STATUS_RMAC_PCC_IDLE   vBIT(0xFF,8,8)

Definition at line 64 of file s2io-regs.h.

#define ADAPTER_STATUS_RMAC_REMOTE_FAULT   s2BIT(6)

Definition at line 62 of file s2io-regs.h.

#define ADAPTER_STATUS_TDMA_READY   s2BIT(0)

Definition at line 57 of file s2io-regs.h.

#define ADAPTER_STATUS_TMAC_BUF_EMPTY   s2BIT(3)

Definition at line 60 of file s2io-regs.h.

#define ADAPTER_UDPI (   val)    vBIT(val,36,4)

Definition at line 77 of file s2io-regs.h.

#define ADAPTER_WAIT_INT   s2BIT(48)

Definition at line 78 of file s2io-regs.h.

#define EXT_REQ_EN   s2BIT(1)

Definition at line 300 of file s2io-regs.h.

#define FAULT_BEHAVIOUR   s2BIT(0)

Definition at line 299 of file s2io-regs.h.

#define GEN_ERROR_INTR
Value:
GEN_INTR_TXPIC | GEN_INTR_RXPIC | \
GEN_INTR_TXDMA | GEN_INTR_RXDMA | \
GEN_INTR_TXMAC | GEN_INTR_RXMAC | \
GEN_INTR_TXXGXS| GEN_INTR_RXXGXS| \
GEN_INTR_MC

Definition at line 34 of file s2io-regs.h.

#define GEN_INTR_MC   s2BIT(35)

Definition at line 31 of file s2io-regs.h.

#define GEN_INTR_RXDMA   s2BIT(33)

Definition at line 29 of file s2io-regs.h.

#define GEN_INTR_RXMAC   s2BIT(34)

Definition at line 30 of file s2io-regs.h.

#define GEN_INTR_RXPIC   s2BIT(32)

Definition at line 28 of file s2io-regs.h.

#define GEN_INTR_RXTRAFFIC   s2BIT(40)

Definition at line 33 of file s2io-regs.h.

#define GEN_INTR_RXXGXS   s2BIT(36)

Definition at line 32 of file s2io-regs.h.

#define GEN_INTR_TXDMA   s2BIT(1)

Definition at line 24 of file s2io-regs.h.

#define GEN_INTR_TXMAC   s2BIT(2)

Definition at line 25 of file s2io-regs.h.

#define GEN_INTR_TXPIC   s2BIT(0)

Definition at line 23 of file s2io-regs.h.

#define GEN_INTR_TXTRAFFIC   s2BIT(8)

Definition at line 27 of file s2io-regs.h.

#define GEN_INTR_TXXGXS   s2BIT(3)

Definition at line 26 of file s2io-regs.h.

#define GET_PCI_MODE (   val)    ((val & vBIT(0xF, 0, 4)) >> 60)

Definition at line 96 of file s2io-regs.h.

#define GPIO_CTRL_GPIO_0   s2BIT(8)

Definition at line 297 of file s2io-regs.h.

#define GPIO_INT_MASK_LINK_DOWN   s2BIT(1)

Definition at line 175 of file s2io-regs.h.

#define GPIO_INT_MASK_LINK_UP   s2BIT(2)

Definition at line 176 of file s2io-regs.h.

#define GPIO_INT_REG_DP_ERR_INT   s2BIT(0)

Definition at line 171 of file s2io-regs.h.

#define GPIO_INT_REG_LINK_DOWN   s2BIT(1)

Definition at line 172 of file s2io-regs.h.

#define GPIO_INT_REG_LINK_UP   s2BIT(2)

Definition at line 173 of file s2io-regs.h.

#define I2C_CONTROL_ADDR (   addr)    vBIT(addr,5,11)

Definition at line 287 of file s2io-regs.h.

#define I2C_CONTROL_BYTE_CNT (   cnt)    vBIT(cnt,22,2)

Definition at line 288 of file s2io-regs.h.

#define I2C_CONTROL_CNTL_END (   val)    (val & vBIT(0x1,28,4))

Definition at line 292 of file s2io-regs.h.

#define I2C_CONTROL_CNTL_START   vBIT(0xE,28,4)

Definition at line 291 of file s2io-regs.h.

#define I2C_CONTROL_DEV_ID (   id)    vBIT(id,1,3)

Definition at line 286 of file s2io-regs.h.

#define I2C_CONTROL_GET_DATA (   val)    (u32)(val & 0xFFFFFFFF)

Definition at line 293 of file s2io-regs.h.

#define I2C_CONTROL_NACK   s2BIT(25)

Definition at line 290 of file s2io-regs.h.

#define I2C_CONTROL_READ   s2BIT(24)

Definition at line 289 of file s2io-regs.h.

#define I2C_CONTROL_SET_DATA (   val)    vBIT(val,32,32)

Definition at line 294 of file s2io-regs.h.

#define IF_RD_SWAPPER_FB   0x0123456789ABCDEF

Definition at line 219 of file s2io-regs.h.

#define IIC_INT_REG_ACK_ERR   s2BIT(8)

Definition at line 165 of file s2io-regs.h.

#define IIC_INT_REG_BIT_FSM_ERR   s2BIT(5)

Definition at line 162 of file s2io-regs.h.

#define IIC_INT_REG_BUS_FSM_ERR   s2BIT(4)

Definition at line 161 of file s2io-regs.h.

#define IIC_INT_REG_CYCLE_FSM_ERR   s2BIT(6)

Definition at line 163 of file s2io-regs.h.

#define IIC_INT_REG_REQ_FSM_ERR   s2BIT(7)

Definition at line 164 of file s2io-regs.h.

#define LSO6_ABORT   s2BIT(14)

Definition at line 368 of file s2io-regs.h.

#define LSO6_SEND_OFLOW   s2BIT(12)

Definition at line 366 of file s2io-regs.h.

#define LSO6_SM_ERR_ALARM   s2BIT(22)

Definition at line 370 of file s2io-regs.h.

#define LSO7_ABORT   s2BIT(15)

Definition at line 369 of file s2io-regs.h.

#define LSO7_SEND_OFLOW   s2BIT(13)

Definition at line 367 of file s2io-regs.h.

#define LSO7_SM_ERR_ALARM   s2BIT(23)

Definition at line 371 of file s2io-regs.h.

#define MAC_CFG_LAN_NOT_WAN   s2BIT(2)

Definition at line 689 of file s2io-regs.h.

#define MAC_CFG_RMAC_ENABLE   s2BIT(1)

Definition at line 688 of file s2io-regs.h.

#define MAC_CFG_RMAC_PROM_ENABLE   s2BIT(7)

Definition at line 694 of file s2io-regs.h.

#define MAC_CFG_RMAC_STRIP_FCS   s2BIT(5)

Definition at line 692 of file s2io-regs.h.

#define MAC_CFG_RMAC_STRIP_PAD   s2BIT(6)

Definition at line 693 of file s2io-regs.h.

#define MAC_CFG_TMAC_APPEND_PAD   s2BIT(4)

Definition at line 691 of file s2io-regs.h.

#define MAC_CFG_TMAC_ENABLE   s2BIT(0)

Definition at line 687 of file s2io-regs.h.

#define MAC_CFG_TMAC_LOOPBACK   s2BIT(3)

Definition at line 690 of file s2io-regs.h.

#define MAC_DBG_ACTIVITY_VALUE   0x411040400000000ULL

Definition at line 822 of file s2io-regs.h.

#define MAC_INT_STATUS_RMAC_INT   s2BIT(1)

Definition at line 641 of file s2io-regs.h.

#define MAC_INT_STATUS_TMAC_INT   s2BIT(0)

Definition at line 640 of file s2io-regs.h.

#define MAC_LINK_UTIL_DISABLE
Value:
MAC_TX_LINK_UTIL_DISABLE | \
MAC_RX_LINK_UTIL_DISABLE

Definition at line 778 of file s2io-regs.h.

#define MAC_RMAC_ALL_ADDR_ENABLE   s2BIT(10)

Definition at line 697 of file s2io-regs.h.

#define MAC_RMAC_BCAST_ENABLE   s2BIT(9)

Definition at line 696 of file s2io-regs.h.

#define MAC_RMAC_DISCARD_PFRM   s2BIT(8)

Definition at line 695 of file s2io-regs.h.

#define MAC_RMAC_INVLD_IPG_THR (   val)    vBIT(val,16,8)

Definition at line 698 of file s2io-regs.h.

#define MAC_RTS_FRM_LEN_SET (   len)    vBIT(len,2,14)

Definition at line 784 of file s2io-regs.h.

#define MAC_RX_LINK_UTIL   vBIT(0xFE,33,7)

Definition at line 774 of file s2io-regs.h.

#define MAC_RX_LINK_UTIL_DISABLE   vBIT(0xF,40,4)

Definition at line 775 of file s2io-regs.h.

#define MAC_RX_LINK_UTIL_VAL (   n)    vBIT(n,40,4)

Definition at line 776 of file s2io-regs.h.

#define MAC_TX_LINK_UTIL   vBIT(0xFE,1,7)

Definition at line 771 of file s2io-regs.h.

#define MAC_TX_LINK_UTIL_DISABLE   vBIT(0xF, 8,4)

Definition at line 772 of file s2io-regs.h.

#define MAC_TX_LINK_UTIL_VAL (   n)    vBIT(n,8,4)

Definition at line 773 of file s2io-regs.h.

#define MAX_DIX_MAP   4

Definition at line 789 of file s2io-regs.h.

#define MC_ERR_REG_ECC_ALL_DBL
Value:
(s2BIT(10) | s2BIT(11) | s2BIT(12) |\
s2BIT(13) | s2BIT(18) | s2BIT(20))

Definition at line 842 of file s2io-regs.h.

#define MC_ERR_REG_ECC_ALL_SNG
Value:
(s2BIT(2) | s2BIT(3) | s2BIT(4) | s2BIT(5) |\
s2BIT(17) | s2BIT(19))

Definition at line 840 of file s2io-regs.h.

#define MC_ERR_REG_ECC_DB_ERR_L   s2BIT(14)

Definition at line 833 of file s2io-regs.h.

#define MC_ERR_REG_ECC_DB_ERR_U   s2BIT(15)

Definition at line 834 of file s2io-regs.h.

#define MC_ERR_REG_MIRI_CRI_ERR_0   s2BIT(22)

Definition at line 837 of file s2io-regs.h.

#define MC_ERR_REG_MIRI_CRI_ERR_1   s2BIT(23)

Definition at line 838 of file s2io-regs.h.

#define MC_ERR_REG_MIRI_ECC_DB_ERR_0   s2BIT(18)

Definition at line 835 of file s2io-regs.h.

#define MC_ERR_REG_MIRI_ECC_DB_ERR_1   s2BIT(20)

Definition at line 836 of file s2io-regs.h.

#define MC_ERR_REG_SM_ERR   s2BIT(31)

Definition at line 839 of file s2io-regs.h.

#define MC_INT_MASK_MC_INT   s2BIT(0)

Definition at line 830 of file s2io-regs.h.

#define MC_INT_STATUS_MC_INT   s2BIT(0)

Definition at line 828 of file s2io-regs.h.

#define MC_RLDRAM_ENABLE_ODT   s2BIT(7)

Definition at line 893 of file s2io-regs.h.

#define MC_RLDRAM_MRS_ENABLE   s2BIT(47)

Definition at line 863 of file s2io-regs.h.

#define MC_RLDRAM_QUEUE_SIZE_ENABLE   s2BIT(39)

Definition at line 862 of file s2io-regs.h.

#define MC_RLDRAM_SET_REF_PERIOD (   val)    vBIT(val, 0, 16)

Definition at line 897 of file s2io-regs.h.

#define MC_RLDRAM_TEST_DONE   s2BIT(23)

Definition at line 879 of file s2io-regs.h.

#define MC_RLDRAM_TEST_GO   s2BIT(15)

Definition at line 878 of file s2io-regs.h.

#define MC_RLDRAM_TEST_MODE   s2BIT(47)

Definition at line 876 of file s2io-regs.h.

#define MC_RLDRAM_TEST_PASS   s2BIT(31)

Definition at line 880 of file s2io-regs.h.

#define MC_RLDRAM_TEST_WRITE   s2BIT(7)

Definition at line 877 of file s2io-regs.h.

#define MDIO_CTRL_START_TRANS (   val)    vBIT(val, 56, 4)

Definition at line 275 of file s2io-regs.h.

#define MDIO_INT_REG_DTX_BUS_ERR   s2BIT(8)

Definition at line 155 of file s2io-regs.h.

#define MDIO_INT_REG_LASI   s2BIT(39)

Definition at line 156 of file s2io-regs.h.

#define MDIO_INT_REG_MDIO_BUS_ERR   s2BIT(0)

Definition at line 154 of file s2io-regs.h.

#define MDIO_MDIO_DATA (   val)    vBIT(val, 32, 16)

Definition at line 281 of file s2io-regs.h.

#define MDIO_MMD_DEV_ADDR (   val)    vBIT(val, 19, 5)

Definition at line 273 of file s2io-regs.h.

#define MDIO_MMD_INDX_ADDR (   val)    vBIT(val, 0, 16)

Definition at line 272 of file s2io-regs.h.

#define MDIO_MMS_PRT_ADDR (   val)    vBIT(val, 27, 5)

Definition at line 274 of file s2io-regs.h.

#define MDIO_OP (   val)    vBIT(val, 60, 2)

Definition at line 276 of file s2io-regs.h.

#define MDIO_OP_ADDR_TRANS   0x0

Definition at line 277 of file s2io-regs.h.

#define MDIO_OP_READ_POST_INC_TRANS   0x2

Definition at line 279 of file s2io-regs.h.

#define MDIO_OP_READ_TRANS   0x3

Definition at line 280 of file s2io-regs.h.

#define MDIO_OP_WRITE_TRANS   0x1

Definition at line 278 of file s2io-regs.h.

#define MISC_LINK_STABILITY_PRD (   val)    vBIT(val,29,3)

Definition at line 301 of file s2io-regs.h.

#define PCC_6_COF_OV_ERR   s2BIT(56)

Definition at line 350 of file s2io-regs.h.

#define PCC_6_LSO_OV_ERR   s2BIT(58)

Definition at line 352 of file s2io-regs.h.

#define PCC_7_COF_OV_ERR   s2BIT(57)

Definition at line 351 of file s2io-regs.h.

#define PCC_7_LSO_OV_ERR   s2BIT(59)

Definition at line 353 of file s2io-regs.h.

#define PCC_ENABLE_FOUR   vBIT(0x0F,0,8)

Definition at line 354 of file s2io-regs.h.

#define PCC_FB_ECC_DB_ERR   vBIT(0xFF,16, 8)

Definition at line 345 of file s2io-regs.h.

#define PCC_FB_ECC_SG_ERR   vBIT(0xFF,0,8)

Definition at line 343 of file s2io-regs.h.

#define PCC_N_SERR   vBIT(0xff,48,8)

Definition at line 349 of file s2io-regs.h.

#define PCC_SM_ERR_ALARM   vBIT(0xff,32,8)

Definition at line 347 of file s2io-regs.h.

#define PCC_TXB_ECC_DB_ERR   vBIT(0xff,24,8)

Definition at line 346 of file s2io-regs.h.

#define PCC_TXB_ECC_SG_ERR   vBIT(0xFF,8,8)

Definition at line 344 of file s2io-regs.h.

#define PCC_WR_ERR_ALARM   vBIT(0xff,40,8)

Definition at line 348 of file s2io-regs.h.

#define PCI_MODE_32_BITS   s2BIT(8)

Definition at line 106 of file s2io-regs.h.

#define PCI_MODE_PCI_33   0

Definition at line 97 of file s2io-regs.h.

#define PCI_MODE_PCI_66   0x1

Definition at line 98 of file s2io-regs.h.

#define PCI_MODE_PCIX_M1_100   0x3

Definition at line 100 of file s2io-regs.h.

#define PCI_MODE_PCIX_M1_133   0x4

Definition at line 101 of file s2io-regs.h.

#define PCI_MODE_PCIX_M1_66   0x2

Definition at line 99 of file s2io-regs.h.

#define PCI_MODE_PCIX_M2_100   0x6

Definition at line 103 of file s2io-regs.h.

#define PCI_MODE_PCIX_M2_133   0x7

Definition at line 104 of file s2io-regs.h.

#define PCI_MODE_PCIX_M2_66   0x5

Definition at line 102 of file s2io-regs.h.

#define PCI_MODE_UNKNOWN_MODE   s2BIT(9)

Definition at line 107 of file s2io-regs.h.

#define PCI_MODE_UNSUPPORTED   s2BIT(0)

Definition at line 105 of file s2io-regs.h.

#define PCIX_INT_REG_ECC_DB_ERR   s2BIT(1)

Definition at line 124 of file s2io-regs.h.

#define PCIX_INT_REG_ECC_SG_ERR   s2BIT(0)

Definition at line 123 of file s2io-regs.h.

#define PCIX_INT_REG_FLASHR_R_FSM_ERR   s2BIT(8)

Definition at line 125 of file s2io-regs.h.

#define PCIX_INT_REG_FLASHR_W_FSM_ERR   s2BIT(9)

Definition at line 126 of file s2io-regs.h.

#define PCIX_INT_REG_INI_RX_FSM_SERR   s2BIT(48)

Definition at line 134 of file s2io-regs.h.

#define PCIX_INT_REG_INI_TX_FSM_SERR   s2BIT(10)

Definition at line 127 of file s2io-regs.h.

#define PCIX_INT_REG_INI_TXO_FSM_ERR   s2BIT(11)

Definition at line 128 of file s2io-regs.h.

#define PCIX_INT_REG_PIFR_FSM_SERR   s2BIT(15)

Definition at line 131 of file s2io-regs.h.

#define PCIX_INT_REG_RA_RX_FSM_SERR   s2BIT(50)

Definition at line 135 of file s2io-regs.h.

#define PCIX_INT_REG_RRC_TX_REQ_FSM_SERR   s2BIT(23)

Definition at line 133 of file s2io-regs.h.

#define PCIX_INT_REG_SRT_FSM_SERR   s2BIT(14)

Definition at line 130 of file s2io-regs.h.

#define PCIX_INT_REG_TRT_FSM_SERR   s2BIT(13)

Definition at line 129 of file s2io-regs.h.

#define PCIX_INT_REG_WRC_TX_SEND_FSM_SERR   s2BIT(21)

Definition at line 132 of file s2io-regs.h.

#define PER_SEC   0x208d5

Definition at line 264 of file s2io-regs.h.

#define PFC_ECC_DB_ERR   s2BIT(15)

Definition at line 325 of file s2io-regs.h.

#define PFC_ECC_SG_ERR   s2BIT(7)

Definition at line 324 of file s2io-regs.h.

#define PFC_MISC_0_ERR   s2BIT(31)

Definition at line 327 of file s2io-regs.h.

#define PFC_MISC_1_ERR   s2BIT(32)

Definition at line 328 of file s2io-regs.h.

#define PFC_PCIX_ERR   s2BIT(39)

Definition at line 329 of file s2io-regs.h.

#define PFC_SM_ERR_ALARM   s2BIT(23)

Definition at line 326 of file s2io-regs.h.

#define PIC_CNTL_RX_ALARM_MAP_1   s2BIT(0)

Definition at line 191 of file s2io-regs.h.

#define PIC_CNTL_SHARED_SPLITS (   n)    vBIT(n,11,5)

Definition at line 192 of file s2io-regs.h.

#define PIC_FLSH_INT_REG_CYCLE_FSM_ERR   s2BIT(63)

Definition at line 148 of file s2io-regs.h.

#define PIC_FLSH_INT_REG_ERR   s2BIT(62)

Definition at line 149 of file s2io-regs.h.

#define PIC_INT_FLSH   s2BIT(1)

Definition at line 115 of file s2io-regs.h.

#define PIC_INT_GPIO   s2BIT(4)

Definition at line 118 of file s2io-regs.h.

#define PIC_INT_IIC   s2BIT(3)

Definition at line 117 of file s2io-regs.h.

#define PIC_INT_MDIO   s2BIT(2)

Definition at line 116 of file s2io-regs.h.

#define PIC_INT_RX   s2BIT(32)

Definition at line 119 of file s2io-regs.h.

#define PIC_INT_TX   s2BIT(0)

Definition at line 114 of file s2io-regs.h.

#define PLL_LOCK_N   s2BIT(39)

Definition at line 844 of file s2io-regs.h.

#define PRC_ALARM_ACTION_RR_R0_STOP   s2BIT(3)

Definition at line 581 of file s2io-regs.h.

#define PRC_ALARM_ACTION_RR_R1_STOP   s2BIT(11)

Definition at line 583 of file s2io-regs.h.

#define PRC_ALARM_ACTION_RR_R2_STOP   s2BIT(19)

Definition at line 585 of file s2io-regs.h.

#define PRC_ALARM_ACTION_RR_R3_STOP   s2BIT(27)

Definition at line 587 of file s2io-regs.h.

#define PRC_ALARM_ACTION_RR_R4_STOP   s2BIT(35)

Definition at line 589 of file s2io-regs.h.

#define PRC_ALARM_ACTION_RR_R5_STOP   s2BIT(43)

Definition at line 591 of file s2io-regs.h.

#define PRC_ALARM_ACTION_RR_R6_STOP   s2BIT(51)

Definition at line 593 of file s2io-regs.h.

#define PRC_ALARM_ACTION_RR_R7_STOP   s2BIT(59)

Definition at line 595 of file s2io-regs.h.

#define PRC_ALARM_ACTION_RW_R0_STOP   s2BIT(7)

Definition at line 582 of file s2io-regs.h.

#define PRC_ALARM_ACTION_RW_R1_STOP   s2BIT(15)

Definition at line 584 of file s2io-regs.h.

#define PRC_ALARM_ACTION_RW_R2_STOP   s2BIT(23)

Definition at line 586 of file s2io-regs.h.

#define PRC_ALARM_ACTION_RW_R3_STOP   s2BIT(31)

Definition at line 588 of file s2io-regs.h.

#define PRC_ALARM_ACTION_RW_R4_STOP   s2BIT(39)

Definition at line 590 of file s2io-regs.h.

#define PRC_ALARM_ACTION_RW_R5_STOP   s2BIT(47)

Definition at line 592 of file s2io-regs.h.

#define PRC_ALARM_ACTION_RW_R6_STOP   s2BIT(55)

Definition at line 594 of file s2io-regs.h.

#define PRC_ALARM_ACTION_RW_R7_STOP   s2BIT(63)

Definition at line 596 of file s2io-regs.h.

#define PRC_CTRL_BIMODAL_INTERRUPT   s2BIT(37)

Definition at line 576 of file s2io-regs.h.

#define PRC_CTRL_GROUP_READS   s2BIT(38)

Definition at line 577 of file s2io-regs.h.

#define PRC_CTRL_NO_SNOOP   (s2BIT(22)|s2BIT(23))

Definition at line 573 of file s2io-regs.h.

#define PRC_CTRL_NO_SNOOP_BUFF   s2BIT(23)

Definition at line 575 of file s2io-regs.h.

#define PRC_CTRL_NO_SNOOP_DESC   s2BIT(22)

Definition at line 574 of file s2io-regs.h.

#define PRC_CTRL_RC_ENABLED   s2BIT(7)

Definition at line 567 of file s2io-regs.h.

#define PRC_CTRL_RING_MODE   (s2BIT(14)|s2BIT(15))

Definition at line 568 of file s2io-regs.h.

#define PRC_CTRL_RING_MODE_1   vBIT(0,14,2)

Definition at line 569 of file s2io-regs.h.

#define PRC_CTRL_RING_MODE_3   vBIT(1,14,2)

Definition at line 570 of file s2io-regs.h.

#define PRC_CTRL_RING_MODE_5   vBIT(2,14,2)

Definition at line 571 of file s2io-regs.h.

#define PRC_CTRL_RING_MODE_x   vBIT(3,14,2)

Definition at line 572 of file s2io-regs.h.

#define PRC_CTRL_RXD_BACKOFF_INTERVAL (   val)    vBIT(val,40,24)

Definition at line 578 of file s2io-regs.h.

#define PRC_PCI_AB_F_WR_Rn   vBIT(0xFF,32,8)

Definition at line 510 of file s2io-regs.h.

#define PRC_PCI_AB_RD_Rn   vBIT(0xFF,0,8)

Definition at line 506 of file s2io-regs.h.

#define PRC_PCI_AB_WR_Rn   vBIT(0xFF,16,8)

Definition at line 508 of file s2io-regs.h.

#define PRC_PCI_DP_F_WR_Rn   vBIT(0xFF,40,8)

Definition at line 511 of file s2io-regs.h.

#define PRC_PCI_DP_RD_Rn   vBIT(0xFF,8,8)

Definition at line 507 of file s2io-regs.h.

#define PRC_PCI_DP_WR_Rn   vBIT(0xFF,24,8)

Definition at line 509 of file s2io-regs.h.

#define RC_FTC_ECC_DB_ERR   s2BIT(31)

Definition at line 498 of file s2io-regs.h.

#define RC_FTC_ECC_SG_ERR   s2BIT(23)

Definition at line 497 of file s2io-regs.h.

#define RC_FTC_SM_ERR_ALARM   s2BIT(47)

Definition at line 500 of file s2io-regs.h.

#define RC_PRCn_ECC_DB_ERR   vBIT(0xFF,8,8)

Definition at line 496 of file s2io-regs.h.

#define RC_PRCn_ECC_SG_ERR   vBIT(0xFF,0,8)

Definition at line 495 of file s2io-regs.h.

#define RC_PRCn_SM_ERR_ALARM   vBIT(0xFF,32,8)

Definition at line 499 of file s2io-regs.h.

#define RC_RDA_FAIL_WR_Rn   vBIT(0xFF,48,8)

Definition at line 501 of file s2io-regs.h.

#define RDA_FRM_ECC_DB_N_AERR   s2BIT(31)

Definition at line 485 of file s2io-regs.h.

#define RDA_FRM_ECC_SG_ERR   s2BIT(23)

Definition at line 484 of file s2io-regs.h.

#define RDA_MISC_ERR   s2BIT(47)

Definition at line 488 of file s2io-regs.h.

#define RDA_PCIX_ERR   s2BIT(55)

Definition at line 489 of file s2io-regs.h.

#define RDA_RXD_ECC_DB_SERR   s2BIT(63)

Definition at line 490 of file s2io-regs.h.

#define RDA_RXDn_ECC_DB_ERR   vBIT(0xFF,8,8)

Definition at line 483 of file s2io-regs.h.

#define RDA_RXDn_ECC_SG_ERR   vBIT(0xFF,0,8)

Definition at line 482 of file s2io-regs.h.

#define RDA_SM0_ERR_ALARM   s2BIT(39)

Definition at line 487 of file s2io-regs.h.

#define RDA_SM1_ERR_ALARM   s2BIT(38)

Definition at line 486 of file s2io-regs.h.

#define RMAC_ADDR_CMD_MEM_OFFSET (   n)    vBIT(n,26,6)

Definition at line 737 of file s2io-regs.h.

#define RMAC_ADDR_CMD_MEM_RD   0

Definition at line 734 of file s2io-regs.h.

#define RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING   s2BIT(15)

Definition at line 736 of file s2io-regs.h.

#define RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD   s2BIT(15)

Definition at line 735 of file s2io-regs.h.

#define RMAC_ADDR_CMD_MEM_WE   s2BIT(7)

Definition at line 733 of file s2io-regs.h.

#define RMAC_ADDR_DATA0_MEM_ADDR (   n)    vBIT(n,0,48)

Definition at line 740 of file s2io-regs.h.

#define RMAC_ADDR_DATA0_MEM_USER   s2BIT(48)

Definition at line 741 of file s2io-regs.h.

#define RMAC_ADDR_DATA1_MEM_MASK (   n)    vBIT(n,0,48)

Definition at line 744 of file s2io-regs.h.

#define RMAC_CFG_KEY (   val)    vBIT(val,0,16)

Definition at line 719 of file s2io-regs.h.

#define RMAC_DA_SHADOW_ECC_DB_ERR   s2BIT(19)

Definition at line 672 of file s2io-regs.h.

#define RMAC_DA_SHADOW_ECC_SG_ERR   s2BIT(11)

Definition at line 665 of file s2io-regs.h.

#define RMAC_DOUBLE_ECC_ERR
Value:
(s2BIT(13) | s2BIT(14) | s2BIT(15) |\
s2BIT(16) | s2BIT(17) | s2BIT(18)|\
s2BIT(19))

Definition at line 678 of file s2io-regs.h.

#define RMAC_ERR_FCS   s2BIT(0)

Definition at line 709 of file s2io-regs.h.

#define RMAC_ERR_FCS_ACCEPT   s2BIT(1)

Definition at line 710 of file s2io-regs.h.

#define RMAC_ERR_LEN_MISMATCH   s2BIT(3)

Definition at line 715 of file s2io-regs.h.

#define RMAC_ERR_LEN_MISMATCH_ACCEPT   s2BIT(3)

Definition at line 716 of file s2io-regs.h.

#define RMAC_ERR_RUNT   s2BIT(2)

Definition at line 713 of file s2io-regs.h.

#define RMAC_ERR_RUNT_ACCEPT   s2BIT(2)

Definition at line 714 of file s2io-regs.h.

#define RMAC_ERR_TOO_LONG   s2BIT(1)

Definition at line 711 of file s2io-regs.h.

#define RMAC_ERR_TOO_LONG_ACCEPT   s2BIT(1)

Definition at line 712 of file s2io-regs.h.

#define RMAC_FRM_RCVD_INT   s2BIT(1)

Definition at line 657 of file s2io-regs.h.

#define RMAC_LINK_STATE_CHANGE_INT   s2BIT(31)

Definition at line 673 of file s2io-regs.h.

#define RMAC_MAX_PYLD_LEN (   val)    vBIT(val,2,14)

Definition at line 704 of file s2io-regs.h.

#define RMAC_MAX_PYLD_LEN_DEF   vBIT(1500,2,14)

Definition at line 705 of file s2io-regs.h.

#define RMAC_MAX_PYLD_LEN_JUMBO_DEF   vBIT(9600,2,14)

Definition at line 706 of file s2io-regs.h.

#define RMAC_PAUSE_GEN   s2BIT(0)

Definition at line 758 of file s2io-regs.h.

#define RMAC_PAUSE_GEN_ENABLE   s2BIT(0)

Definition at line 759 of file s2io-regs.h.

#define RMAC_PAUSE_HG_PTIME (   val)    vBIT(val,16,16)

Definition at line 763 of file s2io-regs.h.

#define RMAC_PAUSE_HG_PTIME_DEF   vBIT(0xFFFF,16,16)

Definition at line 762 of file s2io-regs.h.

#define RMAC_PAUSE_RX   s2BIT(1)

Definition at line 760 of file s2io-regs.h.

#define RMAC_PAUSE_RX_ENABLE   s2BIT(1)

Definition at line 761 of file s2io-regs.h.

#define RMAC_RD_BUF_ECC_DB_ERR   s2BIT(15)

Definition at line 668 of file s2io-regs.h.

#define RMAC_RD_BUF_ECC_SG_ERR   s2BIT(7)

Definition at line 661 of file s2io-regs.h.

#define RMAC_RTH_MAP_ECC_DB_ERR   s2BIT(16)

Definition at line 669 of file s2io-regs.h.

#define RMAC_RTH_MAP_ECC_SG_ERR   s2BIT(8)

Definition at line 662 of file s2io-regs.h.

#define RMAC_RTH_SPDM_ECC_DB_ERR   s2BIT(17)

Definition at line 670 of file s2io-regs.h.

#define RMAC_RTH_SPDM_ECC_SG_ERR   s2BIT(9)

Definition at line 663 of file s2io-regs.h.

#define RMAC_RTS_DS_ECC_DB_ERR   s2BIT(14)

Definition at line 667 of file s2io-regs.h.

#define RMAC_RTS_DS_ECC_SG_ERR   s2BIT(6)

Definition at line 660 of file s2io-regs.h.

#define RMAC_RTS_PNUM_ECC_DB_ERR   s2BIT(13)

Definition at line 666 of file s2io-regs.h.

#define RMAC_RTS_PNUM_ECC_SG_ERR   s2BIT(5)

Definition at line 659 of file s2io-regs.h.

#define RMAC_RTS_VID_ECC_DB_ERR   s2BIT(18)

Definition at line 671 of file s2io-regs.h.

#define RMAC_RTS_VID_ECC_SG_ERR   s2BIT(10)

Definition at line 664 of file s2io-regs.h.

#define RMAC_RX_BUFF_OVRN   s2BIT(0)

Definition at line 656 of file s2io-regs.h.

#define RMAC_RX_SM_ERR   s2BIT(39)

Definition at line 674 of file s2io-regs.h.

#define RMAC_SINGLE_ECC_ERR
Value:
(s2BIT(5) | s2BIT(6) | s2BIT(7) |\
s2BIT(8) | s2BIT(9) | s2BIT(10)|\
s2BIT(11))

Definition at line 675 of file s2io-regs.h.

#define RMAC_UNUSED_INT   s2BIT(2)

Definition at line 658 of file s2io-regs.h.

#define RPA_CREDIT_ERR   s2BIT(31)

Definition at line 520 of file s2io-regs.h.

#define RPA_ECC_DB_ERR   s2BIT(15)

Definition at line 517 of file s2io-regs.h.

#define RPA_ECC_SG_ERR   s2BIT(7)

Definition at line 516 of file s2io-regs.h.

#define RPA_FLUSH_REQUEST   s2BIT(22)

Definition at line 518 of file s2io-regs.h.

#define RPA_SM_ERR_ALARM   s2BIT(23)

Definition at line 519 of file s2io-regs.h.

#define RTI_CMD_MEM_OFFSET (   n)    vBIT(n,29,3)

Definition at line 604 of file s2io-regs.h.

#define RTI_CMD_MEM_STROBE   s2BIT(15)

Definition at line 601 of file s2io-regs.h.

#define RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED   s2BIT(15)

Definition at line 603 of file s2io-regs.h.

#define RTI_CMD_MEM_STROBE_NEW_CMD   s2BIT(15)

Definition at line 602 of file s2io-regs.h.

#define RTI_CMD_MEM_WE   s2BIT(7)

Definition at line 600 of file s2io-regs.h.

#define RTI_DATA1_MEM_RX_TIMER_AC_EN   s2BIT(38)

Definition at line 608 of file s2io-regs.h.

#define RTI_DATA1_MEM_RX_TIMER_CI_EN   s2BIT(39)

Definition at line 609 of file s2io-regs.h.

#define RTI_DATA1_MEM_RX_TIMER_VAL (   n)    vBIT(n,3,29)

Definition at line 607 of file s2io-regs.h.

#define RTI_DATA1_MEM_RX_URNG_A (   n)    vBIT(n,41,7)

Definition at line 610 of file s2io-regs.h.

#define RTI_DATA1_MEM_RX_URNG_B (   n)    vBIT(n,49,7)

Definition at line 611 of file s2io-regs.h.

#define RTI_DATA1_MEM_RX_URNG_C (   n)    vBIT(n,57,7)

Definition at line 612 of file s2io-regs.h.

#define RTI_DATA2_MEM_RX_UFC_A (   n)    vBIT(n,0,16)

Definition at line 615 of file s2io-regs.h.

#define RTI_DATA2_MEM_RX_UFC_B (   n)    vBIT(n,16,16)

Definition at line 616 of file s2io-regs.h.

#define RTI_DATA2_MEM_RX_UFC_C (   n)    vBIT(n,32,16)

Definition at line 617 of file s2io-regs.h.

#define RTI_DATA2_MEM_RX_UFC_D (   n)    vBIT(n,48,16)

Definition at line 618 of file s2io-regs.h.

#define RTI_ECC_DB_ERR   s2BIT(15)

Definition at line 526 of file s2io-regs.h.

#define RTI_ECC_SG_ERR   s2BIT(7)

Definition at line 525 of file s2io-regs.h.

#define RTI_SM_ERR_ALARM   s2BIT(23)

Definition at line 527 of file s2io-regs.h.

#define RTS_CTRL_IGNORE_LLC_CTRL   s2BIT(3)

Definition at line 799 of file s2io-regs.h.

#define RTS_CTRL_IGNORE_SNAP_OUI   s2BIT(2)

Definition at line 798 of file s2io-regs.h.

#define RTS_DIX_MAP_ETYPE (   val)    vBIT(val,0,16)

Definition at line 791 of file s2io-regs.h.

#define RTS_DIX_MAP_SCW (   val)    s2BIT(val,21)

Definition at line 792 of file s2io-regs.h.

#define RTS_DS_MEM_CTRL_OFFSET (   n)    vBIT(n,26,6)

Definition at line 815 of file s2io-regs.h.

#define RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED   s2BIT(15)

Definition at line 814 of file s2io-regs.h.

#define RTS_DS_MEM_CTRL_STROBE_NEW_CMD   s2BIT(15)

Definition at line 813 of file s2io-regs.h.

#define RTS_DS_MEM_CTRL_WE   s2BIT(7)

Definition at line 812 of file s2io-regs.h.

#define RTS_DS_MEM_DATA (   n)    vBIT(n,0,8)

Definition at line 817 of file s2io-regs.h.

#define RTS_PN_CAM_CTRL_OFFSET (   n)    vBIT(n,24,8)

Definition at line 805 of file s2io-regs.h.

#define RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED   s2BIT(15)

Definition at line 804 of file s2io-regs.h.

#define RTS_PN_CAM_CTRL_STROBE_NEW_CMD   s2BIT(15)

Definition at line 803 of file s2io-regs.h.

#define RTS_PN_CAM_CTRL_WE   s2BIT(7)

Definition at line 802 of file s2io-regs.h.

#define RTS_PN_CAM_DATA_PORT (   val)    vBIT(val,8,16)

Definition at line 808 of file s2io-regs.h.

#define RTS_PN_CAM_DATA_SCW (   val)    vBIT(val,24,8)

Definition at line 809 of file s2io-regs.h.

#define RTS_PN_CAM_DATA_TCP_SELECT   s2BIT(7)

Definition at line 807 of file s2io-regs.h.

#define RX_MAT_SET (   ring,
  msi 
)    vBIT(msi, (8 * ring), 8)

Definition at line 246 of file s2io-regs.h.

#define RX_MAX_RINGS   8

Definition at line 560 of file s2io-regs.h.

#define RX_PA_CFG_IGNORE_FRM_ERR   s2BIT(1)

Definition at line 621 of file s2io-regs.h.

#define RX_PA_CFG_IGNORE_L2_ERR   s2BIT(6)

Definition at line 624 of file s2io-regs.h.

#define RX_PA_CFG_IGNORE_LLC_CTRL   s2BIT(3)

Definition at line 623 of file s2io-regs.h.

#define RX_PA_CFG_IGNORE_SNAP_OUI   s2BIT(2)

Definition at line 622 of file s2io-regs.h.

#define RX_PA_CFG_STRIP_VLAN_TAG   s2BIT(15)

Definition at line 462 of file s2io-regs.h.

#define RX_QUEUE_0_PRIORITY (   val)    vBIT(val,5,3)

Definition at line 535 of file s2io-regs.h.

#define RX_QUEUE_1_PRIORITY (   val)    vBIT(val,13,3)

Definition at line 536 of file s2io-regs.h.

#define RX_QUEUE_2_PRIORITY (   val)    vBIT(val,21,3)

Definition at line 537 of file s2io-regs.h.

#define RX_QUEUE_3_PRIORITY (   val)    vBIT(val,29,3)

Definition at line 538 of file s2io-regs.h.

#define RX_QUEUE_4_PRIORITY (   val)    vBIT(val,37,3)

Definition at line 539 of file s2io-regs.h.

#define RX_QUEUE_5_PRIORITY (   val)    vBIT(val,45,3)

Definition at line 540 of file s2io-regs.h.

#define RX_QUEUE_6_PRIORITY (   val)    vBIT(val,53,3)

Definition at line 541 of file s2io-regs.h.

#define RX_QUEUE_7_PRIORITY (   val)    vBIT(val,61,3)

Definition at line 542 of file s2io-regs.h.

#define RX_QUEUE_CFG_Q0_SZ (   n)    vBIT(n,0,8)

Definition at line 852 of file s2io-regs.h.

#define RX_QUEUE_CFG_Q1_SZ (   n)    vBIT(n,8,8)

Definition at line 853 of file s2io-regs.h.

#define RX_QUEUE_CFG_Q2_SZ (   n)    vBIT(n,16,8)

Definition at line 854 of file s2io-regs.h.

#define RX_QUEUE_CFG_Q3_SZ (   n)    vBIT(n,24,8)

Definition at line 855 of file s2io-regs.h.

#define RX_QUEUE_CFG_Q4_SZ (   n)    vBIT(n,32,8)

Definition at line 856 of file s2io-regs.h.

#define RX_QUEUE_CFG_Q5_SZ (   n)    vBIT(n,40,8)

Definition at line 857 of file s2io-regs.h.

#define RX_QUEUE_CFG_Q6_SZ (   n)    vBIT(n,48,8)

Definition at line 858 of file s2io-regs.h.

#define RX_QUEUE_CFG_Q7_SZ (   n)    vBIT(n,56,8)

Definition at line 859 of file s2io-regs.h.

#define RX_QUEUE_PRI_0   0 /* highest */

Definition at line 544 of file s2io-regs.h.

#define RX_QUEUE_PRI_1   1

Definition at line 545 of file s2io-regs.h.

#define RX_QUEUE_PRI_2   2

Definition at line 546 of file s2io-regs.h.

#define RX_QUEUE_PRI_3   3

Definition at line 547 of file s2io-regs.h.

#define RX_QUEUE_PRI_4   4

Definition at line 548 of file s2io-regs.h.

#define RX_QUEUE_PRI_5   5

Definition at line 549 of file s2io-regs.h.

#define RX_QUEUE_PRI_6   6

Definition at line 550 of file s2io-regs.h.

#define RX_QUEUE_PRI_7   7 /* lowest */

Definition at line 551 of file s2io-regs.h.

#define RX_TRAFFIC_INT_n (   n)    s2BIT(n)

Definition at line 186 of file s2io-regs.h.

#define RXDMA_INT_RC_INT_M   s2BIT(0)

Definition at line 476 of file s2io-regs.h.

#define RXDMA_INT_RDA_INT_M   s2BIT(2)

Definition at line 478 of file s2io-regs.h.

#define RXDMA_INT_RPA_INT_M   s2BIT(1)

Definition at line 477 of file s2io-regs.h.

#define RXDMA_INT_RTI_INT_M   s2BIT(3)

Definition at line 479 of file s2io-regs.h.

#define RXGXS_ESTORE_OFLOW   s2BIT(7)

Definition at line 927 of file s2io-regs.h.

#define RXGXS_RX_SM_ERR   s2BIT(39)

Definition at line 928 of file s2io-regs.h.

#define S2IO_HERC_MAX_MAC_ADDRESSES   64

Definition at line 727 of file s2io-regs.h.

#define S2IO_HERC_MAX_MC_ADDRESSES   256

Definition at line 724 of file s2io-regs.h.

#define S2IO_HERC_MC_ADDR_START_OFFSET   64

Definition at line 730 of file s2io-regs.h.

#define S2IO_MAC_ADDR_START_OFFSET   0

Definition at line 721 of file s2io-regs.h.

#define S2IO_XENA_MAX_MAC_ADDRESSES   16

Definition at line 726 of file s2io-regs.h.

#define S2IO_XENA_MAX_MC_ADDRESSES   64 /* multicast addresses */

Definition at line 723 of file s2io-regs.h.

#define S2IO_XENA_MC_ADDR_START_OFFSET   16

Definition at line 729 of file s2io-regs.h.

#define SCHED_INT_CTRL_INT2MSI (   val)    vBIT(val,10,6)

Definition at line 224 of file s2io-regs.h.

#define SCHED_INT_CTRL_ONE_SHOT   s2BIT(1)

Definition at line 223 of file s2io-regs.h.

#define SCHED_INT_CTRL_TIMER_EN   s2BIT(0)

Definition at line 222 of file s2io-regs.h.

#define SCHED_INT_PERIOD   TBD

Definition at line 225 of file s2io-regs.h.

#define SERR_SOURCE_ANY
Value:
(SERR_SOURCE_PIC | \
SERR_SOURCE_TXDMA | \
SERR_SOURCE_RXDMA | \
SERR_SOURCE_MAC | \
SERR_SOURCE_MC | \
SERR_SOURCE_XGXS)

Definition at line 88 of file s2io-regs.h.

#define SERR_SOURCE_MAC   s2BIT(3)

Definition at line 85 of file s2io-regs.h.

#define SERR_SOURCE_MC   s2BIT(4)

Definition at line 86 of file s2io-regs.h.

#define SERR_SOURCE_PIC   s2BIT(0)

Definition at line 82 of file s2io-regs.h.

#define SERR_SOURCE_RXDMA   s2BIT(2)

Definition at line 84 of file s2io-regs.h.

#define SERR_SOURCE_TXDMA   s2BIT(1)

Definition at line 83 of file s2io-regs.h.

#define SERR_SOURCE_XGXS   s2BIT(5)

Definition at line 87 of file s2io-regs.h.

#define SET_UPDT_CLICKS (   val)    vBIT(val, 32, 32)

Definition at line 266 of file s2io-regs.h.

#define SET_UPDT_PERIOD (   n)    vBIT((PER_SEC*n),32,32)

Definition at line 265 of file s2io-regs.h.

#define SM_SM_ERR_ALARM   s2BIT(15)

Definition at line 383 of file s2io-regs.h.

#define SPI_CONTROL_ADDR (   addr)    vBIT(addr,40,24)

Definition at line 946 of file s2io-regs.h.

#define SPI_CONTROL_BYTECNT (   cnt)    vBIT(cnt,29,3)

Definition at line 944 of file s2io-regs.h.

#define SPI_CONTROL_CMD (   cmd)    vBIT(cmd,32,8)

Definition at line 945 of file s2io-regs.h.

#define SPI_CONTROL_DONE   s2BIT(6)

Definition at line 950 of file s2io-regs.h.

#define SPI_CONTROL_KEY (   key)    vBIT(key,0,4)

Definition at line 943 of file s2io-regs.h.

#define SPI_CONTROL_NACK   s2BIT(5)

Definition at line 949 of file s2io-regs.h.

#define SPI_CONTROL_REQ   s2BIT(7)

Definition at line 948 of file s2io-regs.h.

#define SPI_CONTROL_SEL1   s2BIT(4)

Definition at line 947 of file s2io-regs.h.

#define SPI_DATA_WRITE (   data,
  len 
)    vBIT(data,0,len)

Definition at line 952 of file s2io-regs.h.

#define STAT_BC (   n)    vBIT(n,4,12)

Definition at line 255 of file s2io-regs.h.

#define STAT_CFG_ONE_SHOT_EN   s2BIT(1)

Definition at line 260 of file s2io-regs.h.

#define STAT_CFG_STAT_EN   s2BIT(0)

Definition at line 259 of file s2io-regs.h.

#define STAT_CFG_STAT_NS_EN   s2BIT(8)

Definition at line 261 of file s2io-regs.h.

#define STAT_CFG_STAT_RO   s2BIT(9)

Definition at line 262 of file s2io-regs.h.

#define STAT_TRSF_PER (   n)    TBD

Definition at line 263 of file s2io-regs.h.

#define STATREQTO_EN   s2BIT(63)

Definition at line 233 of file s2io-regs.h.

#define STATREQTO_VAL (   n)    TBD

Definition at line 232 of file s2io-regs.h.

#define SW_RESET_ALL
Value:
(SW_RESET_XENA | \
SW_RESET_FLASH | \
SW_RESET_EOI)

Definition at line 49 of file s2io-regs.h.

#define SW_RESET_EOI   vBIT(0xA5,16,8)

Definition at line 48 of file s2io-regs.h.

#define SW_RESET_FLASH   vBIT(0xA5,8,8)

Definition at line 47 of file s2io-regs.h.

#define SW_RESET_RAW_VAL   0xA5000000

Definition at line 53 of file s2io-regs.h.

#define SW_RESET_XENA   vBIT(0xA5,0,8)

Definition at line 46 of file s2io-regs.h.

#define SWAPPER_CTRL_PIF_R_FE   s2BIT(0)

Definition at line 195 of file s2io-regs.h.

#define SWAPPER_CTRL_PIF_R_SE   s2BIT(1)

Definition at line 196 of file s2io-regs.h.

#define SWAPPER_CTRL_PIF_W_FE   s2BIT(8)

Definition at line 197 of file s2io-regs.h.

#define SWAPPER_CTRL_PIF_W_SE   s2BIT(9)

Definition at line 198 of file s2io-regs.h.

#define SWAPPER_CTRL_RXD_R_FE   s2BIT(32)

Definition at line 207 of file s2io-regs.h.

#define SWAPPER_CTRL_RXD_R_SE   s2BIT(33)

Definition at line 208 of file s2io-regs.h.

#define SWAPPER_CTRL_RXD_W_FE   s2BIT(34)

Definition at line 209 of file s2io-regs.h.

#define SWAPPER_CTRL_RXD_W_SE   s2BIT(35)

Definition at line 210 of file s2io-regs.h.

#define SWAPPER_CTRL_RXF_W_FE   s2BIT(36)

Definition at line 211 of file s2io-regs.h.

#define SWAPPER_CTRL_RXF_W_SE   s2BIT(37)

Definition at line 212 of file s2io-regs.h.

#define SWAPPER_CTRL_STATS_FE   s2BIT(48)

Definition at line 215 of file s2io-regs.h.

#define SWAPPER_CTRL_STATS_SE   s2BIT(49)

Definition at line 216 of file s2io-regs.h.

#define SWAPPER_CTRL_TXD_R_FE   s2BIT(18)

Definition at line 201 of file s2io-regs.h.

#define SWAPPER_CTRL_TXD_R_SE   s2BIT(19)

Definition at line 202 of file s2io-regs.h.

#define SWAPPER_CTRL_TXD_W_FE   s2BIT(20)

Definition at line 203 of file s2io-regs.h.

#define SWAPPER_CTRL_TXD_W_SE   s2BIT(21)

Definition at line 204 of file s2io-regs.h.

#define SWAPPER_CTRL_TXF_R_FE   s2BIT(22)

Definition at line 205 of file s2io-regs.h.

#define SWAPPER_CTRL_TXF_R_SE   s2BIT(23)

Definition at line 206 of file s2io-regs.h.

#define SWAPPER_CTRL_TXP_FE   s2BIT(16)

Definition at line 199 of file s2io-regs.h.

#define SWAPPER_CTRL_TXP_SE   s2BIT(17)

Definition at line 200 of file s2io-regs.h.

#define SWAPPER_CTRL_XMSI_FE   s2BIT(40)

Definition at line 213 of file s2io-regs.h.

#define SWAPPER_CTRL_XMSI_SE   s2BIT(41)

Definition at line 214 of file s2io-regs.h.

#define TBD   0

Definition at line 16 of file s2io-regs.h.

#define TDA_Fn_ECC_DB_ERR   vBIT(0xff,8,8)

Definition at line 335 of file s2io-regs.h.

#define TDA_Fn_ECC_SG_ERR   vBIT(0xff,0,8)

Definition at line 334 of file s2io-regs.h.

#define TDA_PCIX_ERR   s2BIT(39)

Definition at line 338 of file s2io-regs.h.

#define TDA_SM0_ERR_ALARM   s2BIT(22)

Definition at line 336 of file s2io-regs.h.

#define TDA_SM1_ERR_ALARM   s2BIT(23)

Definition at line 337 of file s2io-regs.h.

#define TMAC_AVG_IPG (   val)    vBIT(val,0,8)

Definition at line 701 of file s2io-regs.h.

#define TMAC_DESC_ECC_DB_ERR   s2BIT(55)

Definition at line 650 of file s2io-regs.h.

#define TMAC_DESC_ECC_SG_ERR   s2BIT(47)

Definition at line 649 of file s2io-regs.h.

#define TMAC_ECC_DB_ERR   s2BIT(15)

Definition at line 645 of file s2io-regs.h.

#define TMAC_ECC_SG_ERR   s2BIT(7)

Definition at line 644 of file s2io-regs.h.

#define TMAC_TX_BUF_OVRN   s2BIT(23)

Definition at line 646 of file s2io-regs.h.

#define TMAC_TX_CRI_ERR   s2BIT(31)

Definition at line 647 of file s2io-regs.h.

#define TMAC_TX_SM_ERR   s2BIT(39)

Definition at line 648 of file s2io-regs.h.

#define TPA_SM_ERR_ALARM   s2BIT(23)

Definition at line 377 of file s2io-regs.h.

#define TPA_TX_FRM_DROP   s2BIT(7)

Definition at line 376 of file s2io-regs.h.

#define TTI_CMD_MEM_OFFSET (   n)    vBIT(n,26,6)

Definition at line 439 of file s2io-regs.h.

#define TTI_CMD_MEM_STROBE_BEING_EXECUTED   s2BIT(15)

Definition at line 438 of file s2io-regs.h.

#define TTI_CMD_MEM_STROBE_NEW_CMD   s2BIT(15)

Definition at line 437 of file s2io-regs.h.

#define TTI_CMD_MEM_WE   s2BIT(7)

Definition at line 436 of file s2io-regs.h.

#define TTI_DATA1_MEM_TX_TIMER_AC_CI (   n)    vBIT(n,38,2)

Definition at line 443 of file s2io-regs.h.

#define TTI_DATA1_MEM_TX_TIMER_AC_EN   s2BIT(38)

Definition at line 444 of file s2io-regs.h.

#define TTI_DATA1_MEM_TX_TIMER_CI_EN   s2BIT(39)

Definition at line 445 of file s2io-regs.h.

#define TTI_DATA1_MEM_TX_TIMER_VAL (   n)    vBIT(n,6,26)

Definition at line 442 of file s2io-regs.h.

#define TTI_DATA1_MEM_TX_URNG_A (   n)    vBIT(n,41,7)

Definition at line 446 of file s2io-regs.h.

#define TTI_DATA1_MEM_TX_URNG_B (   n)    vBIT(n,49,7)

Definition at line 447 of file s2io-regs.h.

#define TTI_DATA1_MEM_TX_URNG_C (   n)    vBIT(n,57,7)

Definition at line 448 of file s2io-regs.h.

#define TTI_DATA2_MEM_TX_UFC_A (   n)    vBIT(n,0,16)

Definition at line 451 of file s2io-regs.h.

#define TTI_DATA2_MEM_TX_UFC_B (   n)    vBIT(n,16,16)

Definition at line 452 of file s2io-regs.h.

#define TTI_DATA2_MEM_TX_UFC_C (   n)    vBIT(n,32,16)

Definition at line 453 of file s2io-regs.h.

#define TTI_DATA2_MEM_TX_UFC_D (   n)    vBIT(n,48,16)

Definition at line 454 of file s2io-regs.h.

#define TTI_ECC_DB_ERR   s2BIT(15)

Definition at line 360 of file s2io-regs.h.

#define TTI_ECC_SG_ERR   s2BIT(7)

Definition at line 359 of file s2io-regs.h.

#define TTI_SM_ERR_ALARM   s2BIT(23)

Definition at line 361 of file s2io-regs.h.

#define TX_FIFO_PARTITION_0_LEN (   val)    vBIT(val,19,13)

Definition at line 398 of file s2io-regs.h.

#define TX_FIFO_PARTITION_0_PRI (   val)    vBIT(val,5,3)

Definition at line 397 of file s2io-regs.h.

#define TX_FIFO_PARTITION_1_LEN (   val)    vBIT(val,51,13 )

Definition at line 400 of file s2io-regs.h.

#define TX_FIFO_PARTITION_1_PRI (   val)    vBIT(val,37,3)

Definition at line 399 of file s2io-regs.h.

#define TX_FIFO_PARTITION_2_LEN (   val)    vBIT(val,19,13)

Definition at line 404 of file s2io-regs.h.

#define TX_FIFO_PARTITION_2_PRI (   val)    vBIT(val,5,3)

Definition at line 403 of file s2io-regs.h.

#define TX_FIFO_PARTITION_3_LEN (   val)    vBIT(val,51,13)

Definition at line 406 of file s2io-regs.h.

#define TX_FIFO_PARTITION_3_PRI (   val)    vBIT(val,37,3)

Definition at line 405 of file s2io-regs.h.

#define TX_FIFO_PARTITION_4_LEN (   val)    vBIT(val,19,13)

Definition at line 410 of file s2io-regs.h.

#define TX_FIFO_PARTITION_4_PRI (   val)    vBIT(val,5,3)

Definition at line 409 of file s2io-regs.h.

#define TX_FIFO_PARTITION_5_LEN (   val)    vBIT(val,51,13)

Definition at line 412 of file s2io-regs.h.

#define TX_FIFO_PARTITION_5_PRI (   val)    vBIT(val,37,3)

Definition at line 411 of file s2io-regs.h.

#define TX_FIFO_PARTITION_6_LEN (   val)    vBIT(val,19,13)

Definition at line 416 of file s2io-regs.h.

#define TX_FIFO_PARTITION_6_PRI (   val)    vBIT(val,5,3)

Definition at line 415 of file s2io-regs.h.

#define TX_FIFO_PARTITION_7_LEN (   val)    vBIT(val,51,13)

Definition at line 418 of file s2io-regs.h.

#define TX_FIFO_PARTITION_7_PRI (   val)    vBIT(val,37,3)

Definition at line 417 of file s2io-regs.h.

#define TX_FIFO_PARTITION_EN   s2BIT(0)

Definition at line 396 of file s2io-regs.h.

#define TX_FIFO_PARTITION_PRI_0   0 /* highest */

Definition at line 420 of file s2io-regs.h.

#define TX_FIFO_PARTITION_PRI_1   1

Definition at line 421 of file s2io-regs.h.

#define TX_FIFO_PARTITION_PRI_2   2

Definition at line 422 of file s2io-regs.h.

#define TX_FIFO_PARTITION_PRI_3   3

Definition at line 423 of file s2io-regs.h.

#define TX_FIFO_PARTITION_PRI_4   4

Definition at line 424 of file s2io-regs.h.

#define TX_FIFO_PARTITION_PRI_5   5

Definition at line 425 of file s2io-regs.h.

#define TX_FIFO_PARTITION_PRI_6   6

Definition at line 426 of file s2io-regs.h.

#define TX_FIFO_PARTITION_PRI_7   7 /* lowest */

Definition at line 427 of file s2io-regs.h.

#define TX_MAT_SET (   fifo,
  msi 
)    vBIT(msi, (8 * fifo), 8)

Definition at line 251 of file s2io-regs.h.

#define TX_PA_CFG_IGNORE_FRM_ERR   s2BIT(1)

Definition at line 458 of file s2io-regs.h.

#define TX_PA_CFG_IGNORE_L2_ERR   s2BIT(6)

Definition at line 461 of file s2io-regs.h.

#define TX_PA_CFG_IGNORE_LLC_CTRL   s2BIT(3)

Definition at line 460 of file s2io-regs.h.

#define TX_PA_CFG_IGNORE_SNAP_OUI   s2BIT(2)

Definition at line 459 of file s2io-regs.h.

#define TX_TRAFFIC_INT_n (   n)    s2BIT(n)

Definition at line 182 of file s2io-regs.h.

#define TXDMA_LSO_INT   s2BIT(4)

Definition at line 320 of file s2io-regs.h.

#define TXDMA_PCC_INT   s2BIT(2)

Definition at line 318 of file s2io-regs.h.

#define TXDMA_PFC_INT   s2BIT(0)

Definition at line 316 of file s2io-regs.h.

#define TXDMA_SM_INT   s2BIT(6)

Definition at line 322 of file s2io-regs.h.

#define TXDMA_TDA_INT   s2BIT(1)

Definition at line 317 of file s2io-regs.h.

#define TXDMA_TPA_INT   s2BIT(5)

Definition at line 321 of file s2io-regs.h.

#define TXDMA_TTI_INT   s2BIT(3)

Definition at line 319 of file s2io-regs.h.

#define TXGXS_ECC_DB_ERR   s2BIT(15)

Definition at line 919 of file s2io-regs.h.

#define TXGXS_ECC_SG_ERR   s2BIT(7)

Definition at line 918 of file s2io-regs.h.

#define TXGXS_ESTORE_UFLOW   s2BIT(31)

Definition at line 920 of file s2io-regs.h.

#define TXGXS_TX_SM_ERR   s2BIT(39)

Definition at line 921 of file s2io-regs.h.

#define TXREQTO_EN   s2BIT(63)

Definition at line 229 of file s2io-regs.h.

#define TXREQTO_VAL (   val)    vBIT(val,0,32)

Definition at line 228 of file s2io-regs.h.

#define WREQ_SPLIT_MASK_SET_MASK (   val)    vBIT(val, 52, 12)

Definition at line 309 of file s2io-regs.h.

#define X_FIFO_MAX_LEN   0x1FFF /*8191 */

Definition at line 394 of file s2io-regs.h.

#define X_MAX_FIFOS   8

Definition at line 393 of file s2io-regs.h.

#define XENA_EEPROM_SPACE   (0x01 << 11)

Definition at line 956 of file s2io-regs.h.

#define XENA_REG_SPACE   sizeof(struct XENA_dev_config)

Definition at line 955 of file s2io-regs.h.

#define XGXS_INT_MASK_RXGXS   s2BIT(1)

Definition at line 915 of file s2io-regs.h.

#define XGXS_INT_MASK_TXGXS   s2BIT(0)

Definition at line 914 of file s2io-regs.h.

#define XGXS_INT_STATUS_RXGXS   s2BIT(1)

Definition at line 912 of file s2io-regs.h.

#define XGXS_INT_STATUS_TXGXS   s2BIT(0)

Definition at line 911 of file s2io-regs.h.

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