|
| #define | TBD 0 |
| |
| #define | s2BIT(loc) (0x8000000000000000ULL >> (loc)) |
| |
| #define | vBIT(val, loc, sz) (((u64)val) << (64-loc-sz)) |
| |
| #define | INV(d) ((d&0xff)<<24) | (((d>>8)&0xff)<<16) | (((d>>16)&0xff)<<8)| ((d>>24)&0xff) |
| |
| #define | SUCCESS 0 |
| |
| #define | FAILURE -1 |
| |
| #define | S2IO_MINUS_ONE 0xFFFFFFFFFFFFFFFFULL |
| |
| #define | S2IO_DISABLE_MAC_ENTRY 0xFFFFFFFFFFFFULL |
| |
| #define | S2IO_MAX_PCI_CONFIG_SPACE_REINIT 100 |
| |
| #define | S2IO_BIT_RESET 1 |
| |
| #define | S2IO_BIT_SET 2 |
| |
| #define | CHECKBIT(value, nbit) (value & (1 << nbit)) |
| |
| #define | MAX_FLICKER_TIME 60000 /* 60 Secs */ |
| |
| #define | XENA_MAX_OUTSTANDING_SPLITS(n) (n << 4) |
| |
| #define | WATCH_DOG_TIMEOUT 15*HZ |
| |
| #define | EFILL 0x1234 |
| |
| #define | ALIGN_SIZE 127 |
| |
| #define | PCIX_COMMAND_REGISTER 0x62 |
| |
| #define | ERR_DBG 0 |
| |
| #define | INIT_DBG 1 |
| |
| #define | INFO_DBG 2 |
| |
| #define | TX_DBG 3 |
| |
| #define | INTR_DBG 4 |
| |
| #define | DBG_PRINT(dbg_level, fmt, args...) |
| |
| #define | L3_CKSUM_OK 0xFFFF |
| |
| #define | L4_CKSUM_OK 0xFFFF |
| |
| #define | S2IO_JUMBO_SIZE 9600 |
| |
| #define | NO_STRIP_IN_PROMISC 2 |
| |
| #define | MAX_TX_FIFOS 8 |
| |
| #define | MAX_RX_RINGS 8 |
| |
| #define | FIFO_DEFAULT_NUM 5 |
| |
| #define | FIFO_UDP_MAX_NUM 2 /* 0 - even, 1 -odd ports */ |
| |
| #define | FIFO_OTHER_MAX_NUM 1 |
| |
| #define | MAX_RX_DESC_1 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 128) |
| |
| #define | MAX_RX_DESC_2 (MAX_RX_RINGS * MAX_RX_BLOCKS_PER_RING * 86) |
| |
| #define | MAX_TX_DESC (MAX_AVAILABLE_TXDS) |
| |
| #define | MAX_AVAILABLE_TXDS 8192 |
| |
| #define | TX_FIFO_PRI_0 0 /*Highest */ |
| |
| #define | TX_FIFO_PRI_1 1 |
| |
| #define | TX_FIFO_PRI_2 2 |
| |
| #define | TX_FIFO_PRI_3 3 |
| |
| #define | TX_FIFO_PRI_4 4 |
| |
| #define | TX_FIFO_PRI_5 5 |
| |
| #define | TX_FIFO_PRI_6 6 |
| |
| #define | TX_FIFO_PRI_7 7 /*lowest */ |
| |
| #define | NO_SNOOP_TXD 0x01 |
| |
| #define | NO_SNOOP_TXD_BUFFER 0x02 |
| |
| #define | RX_RING_PRI_0 0 /* highest */ |
| |
| #define | RX_RING_PRI_1 1 |
| |
| #define | RX_RING_PRI_2 2 |
| |
| #define | RX_RING_PRI_3 3 |
| |
| #define | RX_RING_PRI_4 4 |
| |
| #define | RX_RING_PRI_5 5 |
| |
| #define | RX_RING_PRI_6 6 |
| |
| #define | RX_RING_PRI_7 7 /* lowest */ |
| |
| #define | RING_ORG_BUFF1 0x01 |
| |
| #define | RX_RING_ORG_BUFF3 0x03 |
| |
| #define | RX_RING_ORG_BUFF5 0x05 |
| |
| #define | NO_SNOOP_RXD 0x01 |
| |
| #define | NO_SNOOP_RXD_BUFFER 0x02 |
| |
| #define | NO_STEERING 0 |
| |
| #define | TX_PRIORITY_STEERING 0x1 |
| |
| #define | TX_DEFAULT_STEERING 0x2 |
| |
| #define | INTA 0 |
| |
| #define | MSI_X 2 |
| |
| #define | MAX_RX_BLOCKS_PER_RING 150 |
| |
| #define | HEADER_ETHERNET_II_802_3_SIZE 14 |
| |
| #define | HEADER_802_2_SIZE 3 |
| |
| #define | HEADER_SNAP_SIZE 5 |
| |
| #define | HEADER_VLAN_SIZE 4 |
| |
| #define | MIN_MTU 46 |
| |
| #define | MAX_PYLD 1500 |
| |
| #define | MAX_MTU (MAX_PYLD+18) |
| |
| #define | MAX_MTU_VLAN (MAX_PYLD+22) |
| |
| #define | MAX_PYLD_JUMBO 9600 |
| |
| #define | MAX_MTU_JUMBO (MAX_PYLD_JUMBO+18) |
| |
| #define | MAX_MTU_JUMBO_VLAN (MAX_PYLD_JUMBO+22) |
| |
| #define | TX_FIFO_LAST_TXD_NUM(val) vBIT(val,0,8) |
| |
| #define | TX_FIFO_FIRST_LIST s2BIT(14) |
| |
| #define | TX_FIFO_LAST_LIST s2BIT(15) |
| |
| #define | TX_FIFO_FIRSTNLAST_LIST vBIT(3,14,2) |
| |
| #define | TX_FIFO_SPECIAL_FUNC s2BIT(23) |
| |
| #define | TX_FIFO_DS_NO_SNOOP s2BIT(31) |
| |
| #define | TX_FIFO_BUFF_NO_SNOOP s2BIT(30) |
| |
| #define | TXD_LIST_OWN_XENA s2BIT(7) |
| |
| #define | TXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15)) |
| |
| #define | TXD_T_CODE_OK(val) (|(val & TXD_T_CODE)) |
| |
| #define | GET_TXD_T_CODE(val) ((val & TXD_T_CODE)<<12) |
| |
| #define | TXD_GATHER_CODE (s2BIT(22) | s2BIT(23)) |
| |
| #define | TXD_GATHER_CODE_FIRST s2BIT(22) |
| |
| #define | TXD_GATHER_CODE_LAST s2BIT(23) |
| |
| #define | TXD_TCP_LSO_EN s2BIT(30) |
| |
| #define | TXD_UDP_COF_EN s2BIT(31) |
| |
| #define | TXD_UFO_EN s2BIT(31) | s2BIT(30) |
| |
| #define | TXD_TCP_LSO_MSS(val) vBIT(val,34,14) |
| |
| #define | TXD_UFO_MSS(val) vBIT(val,34,14) |
| |
| #define | TXD_BUFFER0_SIZE(val) vBIT(val,48,16) |
| |
| #define | TXD_TX_CKO_CONTROL (s2BIT(5)|s2BIT(6)|s2BIT(7)) |
| |
| #define | TXD_TX_CKO_IPV4_EN s2BIT(5) |
| |
| #define | TXD_TX_CKO_TCP_EN s2BIT(6) |
| |
| #define | TXD_TX_CKO_UDP_EN s2BIT(7) |
| |
| #define | TXD_VLAN_ENABLE s2BIT(15) |
| |
| #define | TXD_VLAN_TAG(val) vBIT(val,16,16) |
| |
| #define | TXD_INT_NUMBER(val) vBIT(val,34,6) |
| |
| #define | TXD_INT_TYPE_PER_LIST s2BIT(47) |
| |
| #define | TXD_INT_TYPE_UTILZ s2BIT(46) |
| |
| #define | TXD_SET_MARKER vBIT(0x6,0,4) |
| |
| #define | RXD_OWN_XENA s2BIT(7) |
| |
| #define | RXD_T_CODE (s2BIT(12)|s2BIT(13)|s2BIT(14)|s2BIT(15)) |
| |
| #define | RXD_FRAME_PROTO vBIT(0xFFFF,24,8) |
| |
| #define | RXD_FRAME_VLAN_TAG s2BIT(24) |
| |
| #define | RXD_FRAME_PROTO_IPV4 s2BIT(27) |
| |
| #define | RXD_FRAME_PROTO_IPV6 s2BIT(28) |
| |
| #define | RXD_FRAME_IP_FRAG s2BIT(29) |
| |
| #define | RXD_FRAME_PROTO_TCP s2BIT(30) |
| |
| #define | RXD_FRAME_PROTO_UDP s2BIT(31) |
| |
| #define | TCP_OR_UDP_FRAME (RXD_FRAME_PROTO_TCP | RXD_FRAME_PROTO_UDP) |
| |
| #define | RXD_GET_L3_CKSUM(val) ((u16)(val>> 16) & 0xFFFF) |
| |
| #define | RXD_GET_L4_CKSUM(val) ((u16)(val) & 0xFFFF) |
| |
| #define | THE_RXD_MARK 0x3 |
| |
| #define | SET_RXD_MARKER vBIT(THE_RXD_MARK, 0, 2) |
| |
| #define | GET_RXD_MARKER(ctrl) ((ctrl & SET_RXD_MARKER) >> 62) |
| |
| #define | MASK_VLAN_TAG vBIT(0xFFFF,48,16) |
| |
| #define | SET_VLAN_TAG(val) vBIT(val,48,16) |
| |
| #define | SET_NUM_TAG(val) vBIT(val,16,32) |
| |
| #define | MASK_BUFFER0_SIZE_1 vBIT(0x3FFF,2,14) |
| |
| #define | SET_BUFFER0_SIZE_1(val) vBIT(val,2,14) |
| |
| #define | RXD_GET_BUFFER0_SIZE_1(_Control_2) (u16)((_Control_2 & MASK_BUFFER0_SIZE_1) >> 48) |
| |
| #define | MASK_BUFFER0_SIZE_3 vBIT(0xFF,2,14) |
| |
| #define | MASK_BUFFER1_SIZE_3 vBIT(0xFFFF,16,16) |
| |
| #define | MASK_BUFFER2_SIZE_3 vBIT(0xFFFF,32,16) |
| |
| #define | SET_BUFFER0_SIZE_3(val) vBIT(val,8,8) |
| |
| #define | SET_BUFFER1_SIZE_3(val) vBIT(val,16,16) |
| |
| #define | SET_BUFFER2_SIZE_3(val) vBIT(val,32,16) |
| |
| #define | RXD_GET_BUFFER0_SIZE_3(Control_2) (u8)((Control_2 & MASK_BUFFER0_SIZE_3) >> 48) |
| |
| #define | RXD_GET_BUFFER1_SIZE_3(Control_2) (u16)((Control_2 & MASK_BUFFER1_SIZE_3) >> 32) |
| |
| #define | RXD_GET_BUFFER2_SIZE_3(Control_2) (u16)((Control_2 & MASK_BUFFER2_SIZE_3) >> 16) |
| |
| #define | BUF0_LEN 40 |
| |
| #define | BUF1_LEN 1 |
| |
| #define | MAX_RXDS_PER_BLOCK_1 127 |
| |
| #define | END_OF_BLOCK 0xFEFFFFFFFFFFFFFFULL |
| |
| #define | SIZE_OF_BLOCK 4096 |
| |
| #define | RXD_MODE_1 0 /* One Buffer mode */ |
| |
| #define | RXD_MODE_3B 1 /* Two Buffer mode */ |
| |
| #define | MAX_LRO_SESSIONS 32 |
| |
| #define | FIFO_QUEUE_START 0 |
| |
| #define | FIFO_QUEUE_STOP 1 |
| |
| #define | DEFAULT_FIFO_0_LEN 4096 |
| |
| #define | DEFAULT_FIFO_1_7_LEN 512 |
| |
| #define | SMALL_BLK_CNT 30 |
| |
| #define | LARGE_BLK_CNT 100 |
| |
| #define | MAX_REQUESTED_MSI_X 9 |
| |
| #define | MSIX_ALARM_TYPE 1 |
| |
| #define | MSIX_RING_TYPE 2 |
| |
| #define | MSIX_REGISTERED_SUCCESS 0xAA |
| |
| #define | MAX_MAC_SUPPORTED 16 |
| |
| #define | MAX_SUPPORTED_MULTICASTS MAX_MAC_SUPPORTED |
| |
| #define | PROMISC 1 |
| |
| #define | ALL_MULTI 2 |
| |
| #define | MAX_ADDRS_SUPPORTED 64 |
| |
| #define | LINK_DOWN 1 |
| |
| #define | LINK_UP 2 |
| |
| #define | MSIX_FLG 0xA5 |
| |
| #define | XFRAME_I_DEVICE 1 |
| |
| #define | XFRAME_II_DEVICE 2 |
| |
| #define | VPD_STRING_LEN 80 |
| |
| #define | RESET_ERROR 1 |
| |
| #define | CMD_ERROR 2 |
| |
| #define | UF 1 |
| |
| #define | LF 2 |
| |
| #define | ENABLE_INTRS 1 |
| |
| #define | DISABLE_INTRS 2 |
| |
| #define | TX_PIC_INTR (0x0001<<0) |
| |
| #define | TX_DMA_INTR (0x0001<<1) |
| |
| #define | TX_MAC_INTR (0x0001<<2) |
| |
| #define | TX_XGXS_INTR (0x0001<<3) |
| |
| #define | TX_TRAFFIC_INTR (0x0001<<4) |
| |
| #define | RX_PIC_INTR (0x0001<<5) |
| |
| #define | RX_DMA_INTR (0x0001<<6) |
| |
| #define | RX_MAC_INTR (0x0001<<7) |
| |
| #define | RX_XGXS_INTR (0x0001<<8) |
| |
| #define | RX_TRAFFIC_INTR (0x0001<<9) |
| |
| #define | MC_INTR (0x0001<<10) |
| |
| #define | ENA_ALL_INTRS |
| |
| #define | DISABLE_ALL_INTRS 0xFFFFFFFFFFFFFFFFULL |
| |
| #define | TXPIC_INT_M s2BIT(0) |
| |
| #define | TXDMA_INT_M s2BIT(1) |
| |
| #define | TXMAC_INT_M s2BIT(2) |
| |
| #define | TXXGXS_INT_M s2BIT(3) |
| |
| #define | TXTRAFFIC_INT_M s2BIT(8) |
| |
| #define | PIC_RX_INT_M s2BIT(32) |
| |
| #define | RXDMA_INT_M s2BIT(33) |
| |
| #define | RXMAC_INT_M s2BIT(34) |
| |
| #define | MC_INT_M s2BIT(35) |
| |
| #define | RXXGXS_INT_M s2BIT(36) |
| |
| #define | RXTRAFFIC_INT_M s2BIT(40) |
| |
| #define | TXDMA_PFC_INT_M s2BIT(0) |
| |
| #define | TXDMA_PCC_INT_M s2BIT(2) |
| |
| #define | PFC_MISC_ERR_1 s2BIT(0) /* Interrupt to indicate FIFO full */ |
| |
| #define | PCC_FB_ECC_ERR |
| |
| #define | RXD_GET_VLAN_TAG(Control_2) (u16)(Control_2 & MASK_VLAN_TAG) |
| |
| #define | s2io_tcp_mss(skb) skb_shinfo(skb)->gso_size |
| |
| #define | s2io_udp_mss(skb) skb_shinfo(skb)->gso_size |
| |
| #define | s2io_offload_type(skb) skb_shinfo(skb)->gso_type |
| |
| #define | S2IO_PARM_INT(X, def_val) |
| |
1.8.2