enum | {
MMIO_BAR_PCI = 5,
MMIO_BAR_CARDBUS = 1,
NR_PORTS = 2,
IDMA_CPB_TBL_SIZE = 4 * 32,
INIC_DMA_BOUNDARY = 0xffffff,
HOST_ACTRL = 0x08,
HOST_CTL = 0x7c,
HOST_STAT = 0x7e,
HOST_IRQ_STAT = 0xbc,
HOST_IRQ_MASK = 0xbe,
PORT_SIZE = 0x40,
PORT_TF_DATA = 0x00,
PORT_TF_FEATURE = 0x01,
PORT_TF_NSECT = 0x02,
PORT_TF_LBAL = 0x03,
PORT_TF_LBAM = 0x04,
PORT_TF_LBAH = 0x05,
PORT_TF_DEVICE = 0x06,
PORT_TF_COMMAND = 0x07,
PORT_TF_ALT_STAT = 0x08,
PORT_IRQ_STAT = 0x09,
PORT_IRQ_MASK = 0x0a,
PORT_PRD_CTL = 0x0b,
PORT_PRD_ADDR = 0x0c,
PORT_PRD_XFERLEN = 0x10,
PORT_CPB_CPBLAR = 0x18,
PORT_CPB_PTQFIFO = 0x1c,
PORT_IDMA_CTL = 0x14,
PORT_IDMA_STAT = 0x16,
PORT_RPQ_FIFO = 0x1e,
PORT_RPQ_CNT = 0x1f,
PORT_SCR = 0x20,
HCTL_LEDEN = (1 << 3),
HCTL_IRQOFF = (1 << 8),
HCTL_FTHD0 = (1 << 10),
HCTL_FTHD1 = (1 << 11),
HCTL_PWRDWN = (1 << 12),
HCTL_SOFTRST = (1 << 13),
HCTL_RPGSEL = (1 << 15),
HCTL_KNOWN_BITS,
HIRQ_PORT0 = (1 << 0),
HIRQ_PORT1 = (1 << 1),
HIRQ_SOFT = (1 << 14),
HIRQ_GLOBAL = (1 << 15),
PIRQ_OFFLINE = (1 << 0),
PIRQ_ONLINE = (1 << 1),
PIRQ_COMPLETE = (1 << 2),
PIRQ_FATAL = (1 << 3),
PIRQ_ATA = (1 << 4),
PIRQ_REPLY = (1 << 5),
PIRQ_PENDING = (1 << 7),
PIRQ_ERR = PIRQ_OFFLINE | PIRQ_ONLINE | PIRQ_FATAL,
PIRQ_MASK_DEFAULT = PIRQ_REPLY | PIRQ_ATA,
PIRQ_MASK_FREEZE = 0xff,
PRD_CTL_START = (1 << 0),
PRD_CTL_WR = (1 << 3),
PRD_CTL_DMAEN = (1 << 7),
IDMA_CTL_RST_ATA = (1 << 2),
IDMA_CTL_RST_IDMA = (1 << 5),
IDMA_CTL_GO = (1 << 7),
IDMA_CTL_ATA_NIEN = (1 << 8),
IDMA_STAT_PERR = (1 << 0),
IDMA_STAT_CPBERR = (1 << 1),
IDMA_STAT_LGCY = (1 << 3),
IDMA_STAT_UIRQ = (1 << 4),
IDMA_STAT_STPD = (1 << 5),
IDMA_STAT_PSD = (1 << 6),
IDMA_STAT_DONE = (1 << 7),
IDMA_STAT_ERR = IDMA_STAT_PERR | IDMA_STAT_CPBERR,
CPB_CTL_VALID = (1 << 0),
CPB_CTL_QUEUED = (1 << 1),
CPB_CTL_DATA = (1 << 2),
CPB_CTL_IEN = (1 << 3),
CPB_CTL_DEVDIR = (1 << 4),
CPB_RESP_DONE = (1 << 0),
CPB_RESP_REL = (1 << 1),
CPB_RESP_IGNORED = (1 << 2),
CPB_RESP_ATA_ERR = (1 << 3),
CPB_RESP_SPURIOUS = (1 << 4),
CPB_RESP_UNDERFLOW = (1 << 5),
CPB_RESP_OVERFLOW = (1 << 6),
CPB_RESP_CPB_ERR = (1 << 7),
PRD_DRAIN = (1 << 1),
PRD_CDB = (1 << 2),
PRD_DIRECT_INTR = (1 << 3),
PRD_DMA = (1 << 4),
PRD_WRITE = (1 << 5),
PRD_IOM = (1 << 6),
PRD_END = (1 << 7)
} |