| enum | {
PDC_MAX_PORTS = 4,
PDC_MMIO_BAR = 3,
PDC_MAX_PRD = LIBATA_MAX_PRD - 1,
PDC_INT_SEQMASK = 0x40,
PDC_FLASH_CTL = 0x44,
PDC_PCI_CTL = 0x48,
PDC_SATA_PLUG_CSR = 0x6C,
PDC2_SATA_PLUG_CSR = 0x60,
PDC_TBG_MODE = 0x41C,
PDC_SLEW_CTL = 0x470,
PDC_FEATURE = 0x04,
PDC_SECTOR_COUNT = 0x08,
PDC_SECTOR_NUMBER = 0x0C,
PDC_CYLINDER_LOW = 0x10,
PDC_CYLINDER_HIGH = 0x14,
PDC_DEVICE = 0x18,
PDC_COMMAND = 0x1C,
PDC_ALTSTATUS = 0x38,
PDC_PKT_SUBMIT = 0x40,
PDC_GLOBAL_CTL = 0x48,
PDC_CTLSTAT = 0x60,
PDC_SATA_ERROR = 0x04,
PDC_PHYMODE4 = 0x14,
PDC_LINK_LAYER_ERRORS = 0x6C,
PDC_FPDMA_CTLSTAT = 0xD8,
PDC_INTERNAL_DEBUG_1 = 0xF8,
PDC_INTERNAL_DEBUG_2 = 0xFC,
PDC_FPDMA_CTLSTAT_RESET = 1 << 3,
PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG = 1 << 10,
PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG = 1 << 11,
PDC_PH_ERR = (1 << 8),
PDC_SH_ERR = (1 << 9),
PDC_DH_ERR = (1 << 10),
PDC2_HTO_ERR = (1 << 12),
PDC2_ATA_HBA_ERR = (1 << 13),
PDC2_ATA_DMA_CNT_ERR = (1 << 14),
PDC_OVERRUN_ERR = (1 << 19),
PDC_UNDERRUN_ERR = (1 << 20),
PDC_DRIVE_ERR = (1 << 21),
PDC_PCI_SYS_ERR = (1 << 22),
PDC1_PCI_PARITY_ERR = (1 << 23),
PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR,
PDC2_ERR_MASK,
PDC_ERR_MASK,
board_2037x = 0,
board_2037x_pata = 1,
board_20319 = 2,
board_20619 = 3,
board_2057x = 4,
board_2057x_pata = 5,
board_40518 = 6,
PDC_HAS_PATA = (1 << 1),
PDC_SEQCNTRL_INT_MASK = (1 << 5),
PDC_FEATURE_ATAPI_PIO = 0x00,
PDC_FEATURE_ATAPI_DMA = 0x01,
PDC_DEVICE_SATA = 0xE0,
PDC_DMA_ENABLE = (1 << 7),
PDC_IRQ_DISABLE = (1 << 10),
PDC_RESET = (1 << 11),
PDC_COMMON_FLAGS = ATA_FLAG_PIO_POLLING,
PDC_FLAG_GEN_II = (1 << 24),
PDC_FLAG_SATA_PATA = (1 << 25),
PDC_FLAG_4_PORTS = (1 << 26)
} |
1.8.2