|
| #define | BFI_MEM_DMA_SEG_SZ (131072) |
| |
| #define | BFI_MEM_DMA_NSEGS(_num_reqs, _req_sz) |
| |
| #define | BFI_MEM_NREQS_SEG(_rqsz) (BFI_MEM_DMA_SEG_SZ / (_rqsz)) |
| |
| #define | BFI_MEM_SEG_FROM_TAG(_tag, _rqsz) ((_tag) / BFI_MEM_NREQS_SEG(_rqsz)) |
| |
| #define | BFI_MEM_SEG_REQ_OFFSET(_tag, _sz) ((_tag) - (BFI_MEM_SEG_FROM_TAG(_tag, _sz) * BFI_MEM_NREQS_SEG(_sz))) |
| |
| #define | BFI_FLASH_CHUNK_SZ 256 /* Flash chunk size */ |
| |
| #define | BFI_FLASH_CHUNK_SZ_WORDS (BFI_FLASH_CHUNK_SZ/sizeof(u32)) |
| |
| #define | bfi_fn_lpu(__fn, __lpu) ((__fn) << 1 | (__lpu)) |
| |
| #define | bfi_mhdr_2_fn(_mh) ((_mh)->mtag.h2i.fn_lpu >> 1) |
| |
| #define | bfi_h2i_set(_mh, _mc, _op, _fn_lpu) |
| |
| #define | bfi_i2h_set(_mh, _mc, _op, _i2htok) |
| |
| #define | BFI_I2H_OPCODE_BASE 128 |
| |
| #define | BFA_I2HM(_x) ((_x) + BFI_I2H_OPCODE_BASE) |
| |
| #define | BFI_SGE_INLINE 1 |
| |
| #define | BFI_SGE_INLINE_MAX (BFI_SGE_INLINE + 1) |
| |
| #define | BFI_SGPG_DATA_SGES 7 |
| |
| #define | BFI_SGPG_SGES_MAX (BFI_SGPG_DATA_SGES + 1) |
| |
| #define | BFI_SGPG_RSVD_WD_LEN 8 |
| |
| #define | BFI_IO_MAX (2000) |
| |
| #define | BFI_IOIM_SNSLEN (256) |
| |
| #define | BFI_IOIM_SNSBUF_SEGS BFI_MEM_DMA_NSEGS(BFI_IO_MAX, BFI_IOIM_SNSLEN) |
| |
| #define | BFI_LMSG_SZ 128 |
| |
| #define | BFI_LMSG_PL_WSZ ((BFI_LMSG_SZ - sizeof(struct bfi_mhdr_s)) / 4) |
| |
| #define | BFI_MBMSG_SZ 7 |
| |
| #define | BFI_IOC_MAX_CQS 4 |
| |
| #define | BFI_IOC_MAX_CQS_ASIC 8 |
| |
| #define | BFI_IOC_MSGLEN_MAX 32 /* 32 bytes */ |
| |
| #define | BFI_IOC_SMEM_PG0_CB (0x40) |
| |
| #define | BFI_IOC_SMEM_PG0_CT (0x180) |
| |
| #define | BFI_IOC_FWSTATS_OFF (0x6B40) |
| |
| #define | BFI_IOC_FWSTATS_SZ (4096) |
| |
| #define | BFI_IOC_TRC_OFF (0x4b00) |
| |
| #define | BFI_IOC_TRC_ENTS 256 |
| |
| #define | BFI_IOC_FW_SIGNATURE (0xbfadbfad) |
| |
| #define | BFI_IOC_MD5SUM_SZ 4 |
| |
| #define | BFI_FWBOOT_DEVMODE_OFF 4 |
| |
| #define | BFI_FWBOOT_TYPE_OFF 8 |
| |
| #define | BFI_FWBOOT_ENV_OFF 12 |
| |
| #define | BFI_FWBOOT_DEVMODE(__asic_gen, __asic_mode, __p0_mode, __p1_mode) |
| |
| #define | BFI_FWBOOT_TYPE_NORMAL 0 |
| |
| #define | BFI_FWBOOT_TYPE_MEMTEST 2 |
| |
| #define | BFI_FWBOOT_ENV_OS 0 |
| |
| #define | BFI_IOC_ENDIAN_SIG 0x12345678 |
| |
| #define | BFI_ADAPTER_GETP(__prop, __adap_prop) |
| |
| #define | BFI_ADAPTER_SETP(__prop, __val) ((__val) << BFI_ADAPTER_ ## __prop ## _SH) |
| |
| #define | BFI_ADAPTER_IS_PROTO(__adap_type) ((__adap_type) & BFI_ADAPTER_PROTO) |
| |
| #define | BFI_ADAPTER_IS_TTV(__adap_type) ((__adap_type) & BFI_ADAPTER_TTV) |
| |
| #define | BFI_ADAPTER_IS_UNSUPP(__adap_type) ((__adap_type) & BFI_ADAPTER_UNSUPP) |
| |
| #define | BFI_ADAPTER_IS_SPECIAL(__adap_type) |
| |
| #define | bfi_ioc_enable_req_t struct bfi_ioc_ctrl_req_s; |
| |
| #define | bfi_ioc_disable_req_t struct bfi_ioc_ctrl_req_s; |
| |
| #define | bfi_ioc_enable_reply_t struct bfi_ioc_ctrl_reply_s; |
| |
| #define | bfi_ioc_disable_reply_t struct bfi_ioc_ctrl_reply_s; |
| |
| #define | BFI_IOC_MSGSZ 8 |
| |
| #define | BFI_PBC_MAX_BLUNS 8 |
| |
| #define | BFI_PBC_MAX_VPORTS 16 |
| |
| #define | BFI_PBC_PORT_DISABLED 2 |
| |
| #define | BFI_MSGQ_FULL(_q) (((_q->pi + 1) % _q->q_depth) == _q->ci) |
| |
| #define | BFI_MSGQ_EMPTY(_q) (_q->pi == _q->ci) |
| |
| #define | BFI_MSGQ_UPDATE_CI(_q) (_q->ci = (_q->ci + 1) % _q->q_depth) |
| |
| #define | BFI_MSGQ_UPDATE_PI(_q) (_q->pi = (_q->pi + 1) % _q->q_depth) |
| |
| #define | BFI_MSGQ_FREE_CNT(_q) ((_q->ci - _q->pi - 1) & (_q->q_depth - 1)) |
| |
| #define | bfi_msgq_mhdr_set(_mh, _mc, _mid, _tok, _enet_id) |
| |
| #define | BFI_MSGQ_CMD_ENTRY_SIZE (64) /* TBD */ |
| |
| #define | BFI_MSGQ_RSP_ENTRY_SIZE (64) /* TBD */ |
| |
| #define | BFI_MSGQ_MSG_SIZE_MAX (2048) /* TBD */ |
| |
| #define | BFI_DIAG_MAX_SGES 2 |
| |
| #define | BFI_DIAG_DMA_BUF_SZ (2 * 1024) |
| |
| #define | BFI_BOOT_MEMTEST_RES_ADDR 0x900 |
| |
| #define | BFI_BOOT_MEMTEST_RES_SIG 0xA0A1A2A3 |
| |
| #define | bfi_diag_ts_rsp_t struct bfi_diag_ts_req_s |
| |
| #define | bfi_diag_qtest_rsp_t struct bfi_diag_qtest_req_s |
| |
| #define | bfi_diag_dport_rsp_t struct bfi_diag_dport_req_s |
| |
|
| enum | {
BFI_SGE_DATA = 0,
BFI_SGE_DATA_CPL = 1,
BFI_SGE_DATA_LAST = 3,
BFI_SGE_LINK = 2,
BFI_SGE_PGDLEN = 2
} |
| |
| enum | bfi_pcifn_class { BFI_PCIFN_CLASS_FC = 0x0c04,
BFI_PCIFN_CLASS_ETH = 0x0200,
BFI_PCIFN_CLASS_FC = 0x0c04,
BFI_PCIFN_CLASS_ETH = 0x0200
} |
| |
| enum | bfi_mclass {
BFI_MC_IOC = 1,
BFI_MC_DIAG = 2,
BFI_MC_FLASH = 3,
BFI_MC_CEE = 4,
BFI_MC_FCPORT = 5,
BFI_MC_IOCFC = 6,
BFI_MC_LL = 7,
BFI_MC_UF = 8,
BFI_MC_FCXP = 9,
BFI_MC_LPS = 10,
BFI_MC_RPORT = 11,
BFI_MC_ITNIM = 12,
BFI_MC_IOIM_READ = 13,
BFI_MC_IOIM_WRITE = 14,
BFI_MC_IOIM_IO = 15,
BFI_MC_IOIM = 16,
BFI_MC_IOIM_IOCOM = 17,
BFI_MC_TSKIM = 18,
BFI_MC_SBOOT = 19,
BFI_MC_IPFC = 20,
BFI_MC_PORT = 21,
BFI_MC_SFP = 22,
BFI_MC_MSGQ = 23,
BFI_MC_ENET = 24,
BFI_MC_PHY = 25,
BFI_MC_NBOOT = 26,
BFI_MC_TIO_READ = 27,
BFI_MC_TIO_WRITE = 28,
BFI_MC_TIO_DATA_XFERED = 29,
BFI_MC_TIO_IO = 30,
BFI_MC_TIO = 31,
BFI_MC_MFG = 32,
BFI_MC_EDMA = 33,
BFI_MC_MAX = 34,
BFI_MC_IOC = 1,
BFI_MC_DIAG = 2,
BFI_MC_FLASH = 3,
BFI_MC_CEE = 4,
BFI_MC_FCPORT = 5,
BFI_MC_IOCFC = 6,
BFI_MC_ABLK = 7,
BFI_MC_UF = 8,
BFI_MC_FCXP = 9,
BFI_MC_LPS = 10,
BFI_MC_RPORT = 11,
BFI_MC_ITN = 12,
BFI_MC_IOIM_READ = 13,
BFI_MC_IOIM_WRITE = 14,
BFI_MC_IOIM_IO = 15,
BFI_MC_IOIM = 16,
BFI_MC_IOIM_IOCOM = 17,
BFI_MC_TSKIM = 18,
BFI_MC_PORT = 21,
BFI_MC_SFP = 22,
BFI_MC_PHY = 25,
BFI_MC_FRU = 34,
BFI_MC_MAX = 35
} |
| |
| enum | bfi_asic_gen {
BFI_ASIC_GEN_CB = 1,
BFI_ASIC_GEN_CT = 2,
BFI_ASIC_GEN_CT2 = 3,
BFI_ASIC_GEN_CB = 1,
BFI_ASIC_GEN_CT = 2,
BFI_ASIC_GEN_CT2 = 3
} |
| |
| enum | bfi_asic_mode {
BFI_ASIC_MODE_FC = 1,
BFI_ASIC_MODE_FC16 = 2,
BFI_ASIC_MODE_ETH = 3,
BFI_ASIC_MODE_COMBO = 4,
BFI_ASIC_MODE_FC = 1,
BFI_ASIC_MODE_FC16 = 2,
BFI_ASIC_MODE_ETH = 3,
BFI_ASIC_MODE_COMBO = 4
} |
| |
| enum | bfi_ioc_h2i_msgs {
BFI_IOC_H2I_ENABLE_REQ = 1,
BFI_IOC_H2I_DISABLE_REQ = 2,
BFI_IOC_H2I_GETATTR_REQ = 3,
BFI_IOC_H2I_DBG_SYNC = 4,
BFI_IOC_H2I_DBG_DUMP = 5,
BFI_IOC_H2I_ENABLE_REQ = 1,
BFI_IOC_H2I_DISABLE_REQ = 2,
BFI_IOC_H2I_GETATTR_REQ = 3,
BFI_IOC_H2I_DBG_SYNC = 4,
BFI_IOC_H2I_DBG_DUMP = 5
} |
| |
| enum | bfi_ioc_i2h_msgs {
BFI_IOC_I2H_ENABLE_REPLY = BFA_I2HM(1),
BFI_IOC_I2H_DISABLE_REPLY = BFA_I2HM(2),
BFI_IOC_I2H_GETATTR_REPLY = BFA_I2HM(3),
BFI_IOC_I2H_HBEAT = BFA_I2HM(4),
BFI_IOC_I2H_ENABLE_REPLY = BFA_I2HM(1),
BFI_IOC_I2H_DISABLE_REPLY = BFA_I2HM(2),
BFI_IOC_I2H_GETATTR_REPLY = BFA_I2HM(3),
BFI_IOC_I2H_HBEAT = BFA_I2HM(4),
BFI_IOC_I2H_ACQ_ADDR_REPLY = BFA_I2HM(5)
} |
| |
| enum | bfi_port_mode { BFI_PORT_MODE_FC = 1,
BFI_PORT_MODE_ETH = 2,
BFI_PORT_MODE_FC = 1,
BFI_PORT_MODE_ETH = 2
} |
| |
| enum | bfi_ioc_state {
BFI_IOC_UNINIT = 0,
BFI_IOC_INITING = 1,
BFI_IOC_HWINIT = 2,
BFI_IOC_CFG = 3,
BFI_IOC_OP = 4,
BFI_IOC_DISABLING = 5,
BFI_IOC_DISABLED = 6,
BFI_IOC_CFG_DISABLED = 7,
BFI_IOC_FAIL = 8,
BFI_IOC_MEMTEST = 9,
BFI_IOC_UNINIT = 0,
BFI_IOC_INITING = 1,
BFI_IOC_HWINIT = 2,
BFI_IOC_CFG = 3,
BFI_IOC_OP = 4,
BFI_IOC_DISABLING = 5,
BFI_IOC_DISABLED = 6,
BFI_IOC_CFG_DISABLED = 7,
BFI_IOC_FAIL = 8,
BFI_IOC_MEMTEST = 9
} |
| |
| enum | {
BFI_ADAPTER_TYPE_FC = 0x01,
BFI_ADAPTER_TYPE_MK = 0x0f0000,
BFI_ADAPTER_TYPE_SH = 16,
BFI_ADAPTER_NPORTS_MK = 0xff00,
BFI_ADAPTER_NPORTS_SH = 8,
BFI_ADAPTER_SPEED_MK = 0xff,
BFI_ADAPTER_SPEED_SH = 0,
BFI_ADAPTER_PROTO = 0x100000,
BFI_ADAPTER_TTV = 0x200000,
BFI_ADAPTER_UNSUPP = 0x400000
} |
| |
| enum | bfi_msgq_h2i_msgs_e { BFI_MSGQ_H2I_INIT_REQ = 1,
BFI_MSGQ_H2I_DOORBELL = 2,
BFI_MSGQ_H2I_SHUTDOWN = 3
} |
| |
| enum | bfi_msgq_i2h_msgs_e { BFI_MSGQ_I2H_INIT_RSP = 1,
BFI_MSGQ_I2H_DOORBELL = 2
} |
| |
| enum | bfi_port_h2i {
BFI_PORT_H2I_ENABLE_REQ = (1),
BFI_PORT_H2I_DISABLE_REQ = (2),
BFI_PORT_H2I_GET_STATS_REQ = (3),
BFI_PORT_H2I_CLEAR_STATS_REQ = (4),
BFI_PORT_H2I_ENABLE_REQ = (1),
BFI_PORT_H2I_DISABLE_REQ = (2),
BFI_PORT_H2I_GET_STATS_REQ = (3),
BFI_PORT_H2I_CLEAR_STATS_REQ = (4)
} |
| |
| enum | bfi_port_i2h {
BFI_PORT_I2H_ENABLE_RSP = BFA_I2HM(1),
BFI_PORT_I2H_DISABLE_RSP = BFA_I2HM(2),
BFI_PORT_I2H_GET_STATS_RSP = BFA_I2HM(3),
BFI_PORT_I2H_CLEAR_STATS_RSP = BFA_I2HM(4),
BFI_PORT_I2H_ENABLE_RSP = BFA_I2HM(1),
BFI_PORT_I2H_DISABLE_RSP = BFA_I2HM(2),
BFI_PORT_I2H_GET_STATS_RSP = BFA_I2HM(3),
BFI_PORT_I2H_CLEAR_STATS_RSP = BFA_I2HM(4)
} |
| |
| enum | bfi_ablk_h2i_msgs_e {
BFI_ABLK_H2I_QUERY = 1,
BFI_ABLK_H2I_ADPT_CONFIG = 2,
BFI_ABLK_H2I_PORT_CONFIG = 3,
BFI_ABLK_H2I_PF_CREATE = 4,
BFI_ABLK_H2I_PF_DELETE = 5,
BFI_ABLK_H2I_PF_UPDATE = 6,
BFI_ABLK_H2I_OPTROM_ENABLE = 7,
BFI_ABLK_H2I_OPTROM_DISABLE = 8
} |
| |
| enum | bfi_ablk_i2h_msgs_e {
BFI_ABLK_I2H_QUERY = BFA_I2HM(BFI_ABLK_H2I_QUERY),
BFI_ABLK_I2H_ADPT_CONFIG = BFA_I2HM(BFI_ABLK_H2I_ADPT_CONFIG),
BFI_ABLK_I2H_PORT_CONFIG = BFA_I2HM(BFI_ABLK_H2I_PORT_CONFIG),
BFI_ABLK_I2H_PF_CREATE = BFA_I2HM(BFI_ABLK_H2I_PF_CREATE),
BFI_ABLK_I2H_PF_DELETE = BFA_I2HM(BFI_ABLK_H2I_PF_DELETE),
BFI_ABLK_I2H_PF_UPDATE = BFA_I2HM(BFI_ABLK_H2I_PF_UPDATE),
BFI_ABLK_I2H_OPTROM_ENABLE = BFA_I2HM(BFI_ABLK_H2I_OPTROM_ENABLE),
BFI_ABLK_I2H_OPTROM_DISABLE = BFA_I2HM(BFI_ABLK_H2I_OPTROM_DISABLE)
} |
| |
| enum | bfi_cee_h2i_msgs_e { BFI_CEE_H2I_GET_CFG_REQ = 1,
BFI_CEE_H2I_RESET_STATS = 2,
BFI_CEE_H2I_GET_STATS_REQ = 3
} |
| |
| enum | bfi_cee_i2h_msgs_e { BFI_CEE_I2H_GET_CFG_RSP = BFA_I2HM(1),
BFI_CEE_I2H_RESET_STATS_RSP = BFA_I2HM(2),
BFI_CEE_I2H_GET_STATS_RSP = BFA_I2HM(3)
} |
| |
| enum | bfi_sfp_h2i_e { BFI_SFP_H2I_SHOW = 1,
BFI_SFP_H2I_SCN = 2
} |
| |
| enum | bfi_sfp_i2h_e { BFI_SFP_I2H_SHOW = BFA_I2HM(BFI_SFP_H2I_SHOW),
BFI_SFP_I2H_SCN = BFA_I2HM(BFI_SFP_H2I_SCN)
} |
| |
| enum | bfa_sfp_stat_e {
BFA_SFP_STATE_INIT = 0,
BFA_SFP_STATE_REMOVED = 1,
BFA_SFP_STATE_INSERTED = 2,
BFA_SFP_STATE_VALID = 3,
BFA_SFP_STATE_UNSUPPORT = 4,
BFA_SFP_STATE_FAILED = 5
} |
| |
| enum | bfi_sfp_mem_e { BFI_SFP_MEM_ALL = 0x1,
BFI_SFP_MEM_DIAGEXT = 0x2
} |
| |
| enum | bfi_flash_h2i_msgs {
BFI_FLASH_H2I_QUERY_REQ = 1,
BFI_FLASH_H2I_ERASE_REQ = 2,
BFI_FLASH_H2I_WRITE_REQ = 3,
BFI_FLASH_H2I_READ_REQ = 4,
BFI_FLASH_H2I_BOOT_VER_REQ = 5,
BFI_FLASH_H2I_QUERY_REQ = 1,
BFI_FLASH_H2I_ERASE_REQ = 2,
BFI_FLASH_H2I_WRITE_REQ = 3,
BFI_FLASH_H2I_READ_REQ = 4,
BFI_FLASH_H2I_BOOT_VER_REQ = 5
} |
| |
| enum | bfi_flash_i2h_msgs {
BFI_FLASH_I2H_QUERY_RSP = BFA_I2HM(1),
BFI_FLASH_I2H_ERASE_RSP = BFA_I2HM(2),
BFI_FLASH_I2H_WRITE_RSP = BFA_I2HM(3),
BFI_FLASH_I2H_READ_RSP = BFA_I2HM(4),
BFI_FLASH_I2H_BOOT_VER_RSP = BFA_I2HM(5),
BFI_FLASH_I2H_EVENT = BFA_I2HM(127),
BFI_FLASH_I2H_QUERY_RSP = BFA_I2HM(1),
BFI_FLASH_I2H_ERASE_RSP = BFA_I2HM(2),
BFI_FLASH_I2H_WRITE_RSP = BFA_I2HM(3),
BFI_FLASH_I2H_READ_RSP = BFA_I2HM(4),
BFI_FLASH_I2H_BOOT_VER_RSP = BFA_I2HM(5),
BFI_FLASH_I2H_EVENT = BFA_I2HM(127)
} |
| |
| enum | bfi_diag_h2i {
BFI_DIAG_H2I_PORTBEACON = 1,
BFI_DIAG_H2I_LOOPBACK = 2,
BFI_DIAG_H2I_FWPING = 3,
BFI_DIAG_H2I_TEMPSENSOR = 4,
BFI_DIAG_H2I_LEDTEST = 5,
BFI_DIAG_H2I_QTEST = 6,
BFI_DIAG_H2I_DPORT = 7
} |
| |
| enum | bfi_diag_i2h {
BFI_DIAG_I2H_PORTBEACON = BFA_I2HM(BFI_DIAG_H2I_PORTBEACON),
BFI_DIAG_I2H_LOOPBACK = BFA_I2HM(BFI_DIAG_H2I_LOOPBACK),
BFI_DIAG_I2H_FWPING = BFA_I2HM(BFI_DIAG_H2I_FWPING),
BFI_DIAG_I2H_TEMPSENSOR = BFA_I2HM(BFI_DIAG_H2I_TEMPSENSOR),
BFI_DIAG_I2H_LEDTEST = BFA_I2HM(BFI_DIAG_H2I_LEDTEST),
BFI_DIAG_I2H_QTEST = BFA_I2HM(BFI_DIAG_H2I_QTEST),
BFI_DIAG_I2H_DPORT = BFA_I2HM(BFI_DIAG_H2I_DPORT)
} |
| |
| enum | bfi_dport_req { BFI_DPORT_DISABLE = 0,
BFI_DPORT_ENABLE = 1
} |
| |
| enum | bfi_phy_h2i_msgs_e { BFI_PHY_H2I_QUERY_REQ = 1,
BFI_PHY_H2I_STATS_REQ = 2,
BFI_PHY_H2I_WRITE_REQ = 3,
BFI_PHY_H2I_READ_REQ = 4
} |
| |
| enum | bfi_phy_i2h_msgs_e { BFI_PHY_I2H_QUERY_RSP = BFA_I2HM(1),
BFI_PHY_I2H_STATS_RSP = BFA_I2HM(2),
BFI_PHY_I2H_WRITE_RSP = BFA_I2HM(3),
BFI_PHY_I2H_READ_RSP = BFA_I2HM(4)
} |
| |
| enum | bfi_fru_h2i_msgs { BFI_FRUVPD_H2I_WRITE_REQ = 1,
BFI_FRUVPD_H2I_READ_REQ = 2,
BFI_TFRU_H2I_WRITE_REQ = 3,
BFI_TFRU_H2I_READ_REQ = 4
} |
| |
| enum | bfi_fru_i2h_msgs { BFI_FRUVPD_I2H_WRITE_RSP = BFA_I2HM(1),
BFI_FRUVPD_I2H_READ_RSP = BFA_I2HM(2),
BFI_TFRU_I2H_WRITE_RSP = BFA_I2HM(3),
BFI_TFRU_I2H_READ_RSP = BFA_I2HM(4)
} |
| |
1.8.2