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#define | SH_CLK_DIV_MSK(div) ((1 << (div)) - 1) |
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#define | SH_CLK_DIV4_MSK SH_CLK_DIV_MSK(4) |
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#define | SH_CLK_DIV6_MSK SH_CLK_DIV_MSK(6) |
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#define | CLK_ENABLE_ON_INIT BIT(0) |
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#define | CLK_ENABLE_REG_32BIT BIT(1) /* default access size */ |
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#define | CLK_ENABLE_REG_16BIT BIT(2) |
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#define | CLK_ENABLE_REG_8BIT BIT(3) |
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#define | CLK_MASK_DIV_ON_DISABLE BIT(4) |
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#define | CLK_ENABLE_REG_MASK |
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#define | SH_CLK_MSTP(_parent, _enable_reg, _enable_bit, _flags) |
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#define | SH_CLK_MSTP32(_p, _r, _b, _f) SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_32BIT) |
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#define | SH_CLK_MSTP16(_p, _r, _b, _f) SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_16BIT) |
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#define | SH_CLK_MSTP8(_p, _r, _b, _f) SH_CLK_MSTP(_p, _r, _b, _f | CLK_ENABLE_REG_8BIT) |
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#define | SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) |
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#define | clk_div4_table clk_div_table |
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#define | SH_CLK_DIV6_EXT(_reg, _flags, _parents,_num_parents, _src_shift, _src_width) |
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#define | SH_CLK_DIV6(_parent, _reg, _flags) |
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#define | CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } |
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#define | CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk } |
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#define | CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk } |
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unsigned long | followparent_recalc (struct clk *) |
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void | recalculate_root_clocks (void) |
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void | propagate_rate (struct clk *) |
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int | clk_reparent (struct clk *child, struct clk *parent) |
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int | clk_register (struct clk *) |
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void | clk_unregister (struct clk *) |
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void | clk_enable_init_clocks (void) |
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void | clk_rate_table_build (struct clk *clk, struct cpufreq_frequency_table *freq_table, int nr_freqs, struct clk_div_mult_table *src_table, unsigned long *bitmap) |
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long | clk_rate_table_round (struct clk *clk, struct cpufreq_frequency_table *freq_table, unsigned long rate) |
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int | clk_rate_table_find (struct clk *clk, struct cpufreq_frequency_table *freq_table, unsigned long rate) |
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long | clk_rate_div_range_round (struct clk *clk, unsigned int div_min, unsigned int div_max, unsigned long rate) |
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long | clk_rate_mult_range_round (struct clk *clk, unsigned int mult_min, unsigned int mult_max, unsigned long rate) |
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long | clk_round_parent (struct clk *clk, unsigned long target, unsigned long *best_freq, unsigned long *parent_freq, unsigned int div_min, unsigned int div_max) |
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int | sh_clk_mstp_register (struct clk *clks, int nr) |
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int | sh_clk_div4_register (struct clk *clks, int nr, struct clk_div4_table *table) |
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int | sh_clk_div4_enable_register (struct clk *clks, int nr, struct clk_div4_table *table) |
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int | sh_clk_div4_reparent_register (struct clk *clks, int nr, struct clk_div4_table *table) |
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int | sh_clk_div6_register (struct clk *clks, int nr) |
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int | sh_clk_div6_reparent_register (struct clk *clks, int nr) |
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