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Linux Kernel
3.7.1
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Linux Kernel
3.7.1
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Go to the source code of this file.
Variables | |
| unsigned int | sni_brd_type |
| void(* | sni_hwint )(void) |
| struct irqaction | sni_isa_irq |
| #define A20R_PT_CLOCK_BASE CKSEG1ADDR(0xbc040000) |
| #define A20R_PT_TIM0_ACK CKSEG1ADDR(0xbc050000) |
| #define A20R_PT_TIM1_ACK CKSEG1ADDR(0xbc060000) |
| #define PCIMT_ASIC_ID CKSEG1ADDR(0xbfff007c) /* read */ |
| #define PCIMT_AUTO_PO_DIS CKSEG1ADDR(0xbfd50000) |
| #define PCIMT_AUTO_PO_EN CKSEG1ADDR(0xbfd30000) |
| #define PCIMT_CACHECONF CKSEG1ADDR(0xbfff009c) |
| #define PCIMT_CLR_TEMP CKSEG1ADDR(0xbfd40000) |
| #define PCIMT_CLRPOFF CKSEG1ADDR(0xbfdd0000) |
| #define PCIMT_CONFIG_ADDRESS CKSEG1ADDR(0xbfff0074) |
| #define PCIMT_CSITPEND CKSEG1ADDR(0xbfd20000) |
| #define PCIMT_CSLED CKSEG1ADDR(0xbfda0000) |
| #define PCIMT_CSMAPISA CKSEG1ADDR(0xbfdb0000) |
| #define PCIMT_CSMSR CKSEG1ADDR(0xbfd00000) |
| #define PCIMT_CSRSTBP CKSEG1ADDR(0xbfdc0000) |
| #define PCIMT_CSSWITCH CKSEG1ADDR(0xbfd10000) |
| #define PCIMT_CSTIMER CKSEG1ADDR(0xbfde0000) |
| #define PCIMT_CSWCSM CKSEG1ADDR(0xbfd80000) |
| #define PCIMT_DMAACCESS CKSEG1ADDR(0xbfff002c) |
| #define PCIMT_DMAHIT CKSEG1ADDR(0xbfff0034) |
| #define PCIMT_ECCREG CKSEG1ADDR(0xbfff006c) |
| #define PCIMT_EISA_BASE CKSEG1ADDR(0xb0000000) |
| #define PCIMT_ERRADDR CKSEG1ADDR(0xbfff0044) |
| #define PCIMT_ERRSTATUS CKSEG1ADDR(0xbfff003c) |
| #define PCIMT_EXMSR CKSEG1ADDR(0xbfd60000) |
| #define PCIMT_INT_ACKNOWLEDGE CKSEG1ADDR(0xba000000) |
| #define PCIMT_INVSPACE CKSEG1ADDR(0xbfff00a4) |
| #define PCIMT_IOADTIMEOUT1 CKSEG1ADDR(0xbfff0024) |
| #define PCIMT_IOADTIMEOUT2 CKSEG1ADDR(0xbfff000c) |
| #define PCIMT_IOMEMCONF CKSEG1ADDR(0xbfff0014) |
| #define PCIMT_IOMMU CKSEG1ADDR(0xbfff001c) |
| #define PCIMT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE+6) |
| #define PCIMT_IRQSEL CKSEG1ADDR(0xbfff005c) |
| #define PCIMT_ITPEND CKSEG1ADDR(0xbfff0054) |
| #define PCIMT_PCI_CONF CKSEG1ADDR(0xbfff0100) |
| #define PCIMT_PIA_DATAIN CKSEG1ADDR(0xbfff0094) |
| #define PCIMT_PIA_DATAOUT CKSEG1ADDR(0xbfff008c) |
| #define PCIMT_PIA_OE CKSEG1ADDR(0xbfff0084) |
| #define PCIMT_PWDN CKSEG1ADDR(0xbfdf0000) |
| #define PCIMT_SOFT_RESET CKSEG1ADDR(0xbfff007c) /* write */ |
| #define PCIMT_SYNDROME CKSEG1ADDR(0xbfff004c) |
| #define PCIMT_TESTMEM CKSEG1ADDR(0xbfff0064) |
| #define PCIMT_UCONF CKSEG1ADDR(0xbfff0004) |
| #define PCIMT_UNUSED1 CKSEG1ADDR(0xbfd70000) |
| #define PCIMT_UNUSED2 CKSEG1ADDR(0xbfd90000) |
| #define PCIT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE + 5) |
| #define PCIT_IRQ_INTA (SNI_PCIT_INT_START + 0) |
| #define PCIT_IRQ_INTB (SNI_PCIT_INT_START + 1) |
| #define PCIT_IRQ_INTC (SNI_PCIT_INT_START + 2) |
| #define PCIT_IRQ_INTD (SNI_PCIT_INT_START + 3) |
| #define PCIT_IRQ_SCSI0 (SNI_PCIT_INT_START + 4) |
| #define PCIT_IRQ_SCSI1 (SNI_PCIT_INT_START + 5) |
| #define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE |
| #define SNI_A20R_IRQ_TIMER (SNI_A20R_IRQ_BASE+5) |
| #define SNI_IDPROM_BASE CKSEG1ADDR(0x1ff00000) |
| #define SNI_IDPROM_BRDTYPE (SNI_IDPROM_BASE + (0x29 ^ __SNI_END)) |
| #define SNI_IDPROM_CPUTYPE (SNI_IDPROM_BASE + (0x30 ^ __SNI_END)) |
| #define SNI_IDPROM_MEMSIZE (SNI_IDPROM_BASE + (0x28 ^ __SNI_END)) |
| #define SNI_PCIT_INT_REG CKSEG1ADDR(0xbfff000c) |
| #define SNI_PORT_BASE CKSEG1ADDR(0xb4000000) |
1.8.2