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spear320.c
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1 /*
2  * arch/arm/mach-spear3xx/spear320.c
3  *
4  * SPEAr320 machine source file
5  *
6  * Copyright (C) 2009-2012 ST Microelectronics
7  * Viresh Kumar <[email protected]>
8  *
9  * This file is licensed under the terms of the GNU General Public
10  * License version 2. This program is licensed "as is" without any
11  * warranty of any kind, whether express or implied.
12  */
13 
14 #define pr_fmt(fmt) "SPEAr320: " fmt
15 
16 #include <linux/amba/pl022.h>
17 #include <linux/amba/pl08x.h>
18 #include <linux/amba/serial.h>
19 #include <linux/of_platform.h>
20 #include <asm/hardware/vic.h>
21 #include <asm/mach/arch.h>
22 #include <plat/shirq.h>
23 #include <mach/generic.h>
24 #include <mach/spear.h>
25 
26 #define SPEAR320_UART1_BASE UL(0xA3000000)
27 #define SPEAR320_UART2_BASE UL(0xA4000000)
28 #define SPEAR320_SSP0_BASE UL(0xA5000000)
29 #define SPEAR320_SSP1_BASE UL(0xA6000000)
30 
31 /* Interrupt registers offsets and masks */
32 #define SPEAR320_INT_STS_MASK_REG 0x04
33 #define SPEAR320_INT_CLR_MASK_REG 0x04
34 #define SPEAR320_INT_ENB_MASK_REG 0x08
35 #define SPEAR320_GPIO_IRQ_MASK (1 << 0)
36 #define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
37 #define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
38 #define SPEAR320_EMI_IRQ_MASK (1 << 7)
39 #define SPEAR320_CLCD_IRQ_MASK (1 << 8)
40 #define SPEAR320_SPP_IRQ_MASK (1 << 9)
41 #define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
42 #define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
43 #define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
44 #define SPEAR320_UART1_IRQ_MASK (1 << 13)
45 #define SPEAR320_UART2_IRQ_MASK (1 << 14)
46 #define SPEAR320_SSP1_IRQ_MASK (1 << 15)
47 #define SPEAR320_SSP2_IRQ_MASK (1 << 16)
48 #define SPEAR320_SMII0_IRQ_MASK (1 << 17)
49 #define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
50 #define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
51 #define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
52 #define SPEAR320_I2C1_IRQ_MASK (1 << 21)
53 
54 #define SPEAR320_SHIRQ_RAS1_MASK 0x000380
55 #define SPEAR320_SHIRQ_RAS3_MASK 0x000007
56 #define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
57 
58 /* SPEAr320 Virtual irq definitions */
59 /* IRQs sharing IRQ_GEN_RAS_1 */
60 #define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0)
61 #define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1)
62 #define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2)
63 
64 /* IRQs sharing IRQ_GEN_RAS_2 */
65 #define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2
66 
67 /* IRQs sharing IRQ_GEN_RAS_3 */
68 #define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3)
69 #define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4)
70 #define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5)
71 
72 /* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
73 #define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6)
74 #define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7)
75 #define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
76 #define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
77 #define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10)
78 #define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11)
79 #define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12)
80 #define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13)
81 #define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14)
82 #define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
83 #define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
84 
85 /* spear3xx shared irq */
86 static struct shirq_dev_config shirq_ras1_config[] = {
87  {
88  .virq = SPEAR320_VIRQ_EMI,
89  .status_mask = SPEAR320_EMI_IRQ_MASK,
90  .clear_mask = SPEAR320_EMI_IRQ_MASK,
91  }, {
92  .virq = SPEAR320_VIRQ_CLCD,
93  .status_mask = SPEAR320_CLCD_IRQ_MASK,
94  .clear_mask = SPEAR320_CLCD_IRQ_MASK,
95  }, {
96  .virq = SPEAR320_VIRQ_SPP,
97  .status_mask = SPEAR320_SPP_IRQ_MASK,
98  .clear_mask = SPEAR320_SPP_IRQ_MASK,
99  },
100 };
101 
102 static struct spear_shirq shirq_ras1 = {
103  .irq = SPEAR3XX_IRQ_GEN_RAS_1,
104  .dev_config = shirq_ras1_config,
105  .dev_count = ARRAY_SIZE(shirq_ras1_config),
106  .regs = {
107  .enb_reg = -1,
108  .status_reg = SPEAR320_INT_STS_MASK_REG,
109  .status_reg_mask = SPEAR320_SHIRQ_RAS1_MASK,
110  .clear_reg = SPEAR320_INT_CLR_MASK_REG,
111  .reset_to_clear = 1,
112  },
113 };
114 
115 static struct shirq_dev_config shirq_ras3_config[] = {
116  {
117  .virq = SPEAR320_VIRQ_PLGPIO,
118  .enb_mask = SPEAR320_GPIO_IRQ_MASK,
119  .status_mask = SPEAR320_GPIO_IRQ_MASK,
120  .clear_mask = SPEAR320_GPIO_IRQ_MASK,
121  }, {
122  .virq = SPEAR320_VIRQ_I2S_PLAY,
123  .enb_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
124  .status_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
125  .clear_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
126  }, {
127  .virq = SPEAR320_VIRQ_I2S_REC,
128  .enb_mask = SPEAR320_I2S_REC_IRQ_MASK,
129  .status_mask = SPEAR320_I2S_REC_IRQ_MASK,
130  .clear_mask = SPEAR320_I2S_REC_IRQ_MASK,
131  },
132 };
133 
134 static struct spear_shirq shirq_ras3 = {
135  .irq = SPEAR3XX_IRQ_GEN_RAS_3,
136  .dev_config = shirq_ras3_config,
137  .dev_count = ARRAY_SIZE(shirq_ras3_config),
138  .regs = {
139  .enb_reg = SPEAR320_INT_ENB_MASK_REG,
140  .reset_to_enb = 1,
141  .status_reg = SPEAR320_INT_STS_MASK_REG,
142  .status_reg_mask = SPEAR320_SHIRQ_RAS3_MASK,
143  .clear_reg = SPEAR320_INT_CLR_MASK_REG,
144  .reset_to_clear = 1,
145  },
146 };
147 
148 static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
149  {
150  .virq = SPEAR320_VIRQ_CANU,
151  .status_mask = SPEAR320_CAN_U_IRQ_MASK,
152  .clear_mask = SPEAR320_CAN_U_IRQ_MASK,
153  }, {
154  .virq = SPEAR320_VIRQ_CANL,
155  .status_mask = SPEAR320_CAN_L_IRQ_MASK,
156  .clear_mask = SPEAR320_CAN_L_IRQ_MASK,
157  }, {
158  .virq = SPEAR320_VIRQ_UART1,
159  .status_mask = SPEAR320_UART1_IRQ_MASK,
160  .clear_mask = SPEAR320_UART1_IRQ_MASK,
161  }, {
162  .virq = SPEAR320_VIRQ_UART2,
163  .status_mask = SPEAR320_UART2_IRQ_MASK,
164  .clear_mask = SPEAR320_UART2_IRQ_MASK,
165  }, {
166  .virq = SPEAR320_VIRQ_SSP1,
167  .status_mask = SPEAR320_SSP1_IRQ_MASK,
168  .clear_mask = SPEAR320_SSP1_IRQ_MASK,
169  }, {
170  .virq = SPEAR320_VIRQ_SSP2,
171  .status_mask = SPEAR320_SSP2_IRQ_MASK,
172  .clear_mask = SPEAR320_SSP2_IRQ_MASK,
173  }, {
174  .virq = SPEAR320_VIRQ_SMII0,
175  .status_mask = SPEAR320_SMII0_IRQ_MASK,
176  .clear_mask = SPEAR320_SMII0_IRQ_MASK,
177  }, {
178  .virq = SPEAR320_VIRQ_MII1_SMII1,
179  .status_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
180  .clear_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
181  }, {
182  .virq = SPEAR320_VIRQ_WAKEUP_SMII0,
183  .status_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
184  .clear_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
185  }, {
186  .virq = SPEAR320_VIRQ_WAKEUP_MII1_SMII1,
187  .status_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
188  .clear_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
189  }, {
190  .virq = SPEAR320_VIRQ_I2C1,
191  .status_mask = SPEAR320_I2C1_IRQ_MASK,
192  .clear_mask = SPEAR320_I2C1_IRQ_MASK,
193  },
194 };
195 
196 static struct spear_shirq shirq_intrcomm_ras = {
197  .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
198  .dev_config = shirq_intrcomm_ras_config,
199  .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
200  .regs = {
201  .enb_reg = -1,
202  .status_reg = SPEAR320_INT_STS_MASK_REG,
203  .status_reg_mask = SPEAR320_SHIRQ_INTRCOMM_RAS_MASK,
204  .clear_reg = SPEAR320_INT_CLR_MASK_REG,
205  .reset_to_clear = 1,
206  },
207 };
208 
209 /* DMAC platform data's slave info */
210 struct pl08x_channel_data spear320_dma_info[] = {
211  {
212  .bus_id = "uart0_rx",
213  .min_signal = 2,
214  .max_signal = 2,
215  .muxval = 0,
216  .periph_buses = PL08X_AHB1,
217  }, {
218  .bus_id = "uart0_tx",
219  .min_signal = 3,
220  .max_signal = 3,
221  .muxval = 0,
222  .periph_buses = PL08X_AHB1,
223  }, {
224  .bus_id = "ssp0_rx",
225  .min_signal = 8,
226  .max_signal = 8,
227  .muxval = 0,
228  .periph_buses = PL08X_AHB1,
229  }, {
230  .bus_id = "ssp0_tx",
231  .min_signal = 9,
232  .max_signal = 9,
233  .muxval = 0,
234  .periph_buses = PL08X_AHB1,
235  }, {
236  .bus_id = "i2c0_rx",
237  .min_signal = 10,
238  .max_signal = 10,
239  .muxval = 0,
240  .periph_buses = PL08X_AHB1,
241  }, {
242  .bus_id = "i2c0_tx",
243  .min_signal = 11,
244  .max_signal = 11,
245  .muxval = 0,
246  .periph_buses = PL08X_AHB1,
247  }, {
248  .bus_id = "irda",
249  .min_signal = 12,
250  .max_signal = 12,
251  .muxval = 0,
252  .periph_buses = PL08X_AHB1,
253  }, {
254  .bus_id = "adc",
255  .min_signal = 13,
256  .max_signal = 13,
257  .muxval = 0,
258  .periph_buses = PL08X_AHB1,
259  }, {
260  .bus_id = "to_jpeg",
261  .min_signal = 14,
262  .max_signal = 14,
263  .muxval = 0,
264  .periph_buses = PL08X_AHB1,
265  }, {
266  .bus_id = "from_jpeg",
267  .min_signal = 15,
268  .max_signal = 15,
269  .muxval = 0,
270  .periph_buses = PL08X_AHB1,
271  }, {
272  .bus_id = "ssp1_rx",
273  .min_signal = 0,
274  .max_signal = 0,
275  .muxval = 1,
276  .periph_buses = PL08X_AHB2,
277  }, {
278  .bus_id = "ssp1_tx",
279  .min_signal = 1,
280  .max_signal = 1,
281  .muxval = 1,
282  .periph_buses = PL08X_AHB2,
283  }, {
284  .bus_id = "ssp2_rx",
285  .min_signal = 2,
286  .max_signal = 2,
287  .muxval = 1,
288  .periph_buses = PL08X_AHB2,
289  }, {
290  .bus_id = "ssp2_tx",
291  .min_signal = 3,
292  .max_signal = 3,
293  .muxval = 1,
294  .periph_buses = PL08X_AHB2,
295  }, {
296  .bus_id = "uart1_rx",
297  .min_signal = 4,
298  .max_signal = 4,
299  .muxval = 1,
300  .periph_buses = PL08X_AHB2,
301  }, {
302  .bus_id = "uart1_tx",
303  .min_signal = 5,
304  .max_signal = 5,
305  .muxval = 1,
306  .periph_buses = PL08X_AHB2,
307  }, {
308  .bus_id = "uart2_rx",
309  .min_signal = 6,
310  .max_signal = 6,
311  .muxval = 1,
312  .periph_buses = PL08X_AHB2,
313  }, {
314  .bus_id = "uart2_tx",
315  .min_signal = 7,
316  .max_signal = 7,
317  .muxval = 1,
318  .periph_buses = PL08X_AHB2,
319  }, {
320  .bus_id = "i2c1_rx",
321  .min_signal = 8,
322  .max_signal = 8,
323  .muxval = 1,
324  .periph_buses = PL08X_AHB2,
325  }, {
326  .bus_id = "i2c1_tx",
327  .min_signal = 9,
328  .max_signal = 9,
329  .muxval = 1,
330  .periph_buses = PL08X_AHB2,
331  }, {
332  .bus_id = "i2c2_rx",
333  .min_signal = 10,
334  .max_signal = 10,
335  .muxval = 1,
336  .periph_buses = PL08X_AHB2,
337  }, {
338  .bus_id = "i2c2_tx",
339  .min_signal = 11,
340  .max_signal = 11,
341  .muxval = 1,
342  .periph_buses = PL08X_AHB2,
343  }, {
344  .bus_id = "i2s_rx",
345  .min_signal = 12,
346  .max_signal = 12,
347  .muxval = 1,
348  .periph_buses = PL08X_AHB2,
349  }, {
350  .bus_id = "i2s_tx",
351  .min_signal = 13,
352  .max_signal = 13,
353  .muxval = 1,
354  .periph_buses = PL08X_AHB2,
355  }, {
356  .bus_id = "rs485_rx",
357  .min_signal = 14,
358  .max_signal = 14,
359  .muxval = 1,
360  .periph_buses = PL08X_AHB2,
361  }, {
362  .bus_id = "rs485_tx",
363  .min_signal = 15,
364  .max_signal = 15,
365  .muxval = 1,
366  .periph_buses = PL08X_AHB2,
367  },
368 };
369 
370 static struct pl022_ssp_controller spear320_ssp_data[] = {
371  {
372  .bus_id = 1,
373  .enable_dma = 1,
374  .dma_filter = pl08x_filter_id,
375  .dma_tx_param = "ssp1_tx",
376  .dma_rx_param = "ssp1_rx",
377  .num_chipselect = 2,
378  }, {
379  .bus_id = 2,
380  .enable_dma = 1,
381  .dma_filter = pl08x_filter_id,
382  .dma_tx_param = "ssp2_tx",
383  .dma_rx_param = "ssp2_rx",
384  .num_chipselect = 2,
385  }
386 };
387 
388 static struct amba_pl011_data spear320_uart_data[] = {
389  {
390  .dma_filter = pl08x_filter_id,
391  .dma_tx_param = "uart1_tx",
392  .dma_rx_param = "uart1_rx",
393  }, {
394  .dma_filter = pl08x_filter_id,
395  .dma_tx_param = "uart2_tx",
396  .dma_rx_param = "uart2_rx",
397  },
398 };
399 
400 /* Add SPEAr310 auxdata to pass platform data */
401 static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
402  OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
403  &pl022_plat_data),
404  OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
405  &pl080_plat_data),
406  OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
407  &spear320_ssp_data[0]),
408  OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL,
409  &spear320_ssp_data[1]),
410  OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL,
411  &spear320_uart_data[0]),
412  OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL,
413  &spear320_uart_data[1]),
414  {}
415 };
416 
417 static void __init spear320_dt_init(void)
418 {
419  void __iomem *base;
420  int ret;
421 
422  pl080_plat_data.slave_channels = spear320_dma_info;
423  pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
424 
425  of_platform_populate(NULL, of_default_bus_match_table,
426  spear320_auxdata_lookup, NULL);
427 
428  /* shared irq registration */
429  base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
430  if (base) {
431  /* shirq 1 */
432  shirq_ras1.regs.base = base;
433  ret = spear_shirq_register(&shirq_ras1);
434  if (ret)
435  pr_err("Error registering Shared IRQ 1\n");
436 
437  /* shirq 3 */
438  shirq_ras3.regs.base = base;
439  ret = spear_shirq_register(&shirq_ras3);
440  if (ret)
441  pr_err("Error registering Shared IRQ 3\n");
442 
443  /* shirq 4 */
444  shirq_intrcomm_ras.regs.base = base;
445  ret = spear_shirq_register(&shirq_intrcomm_ras);
446  if (ret)
447  pr_err("Error registering Shared IRQ 4\n");
448  }
449 }
450 
451 static const char * const spear320_dt_board_compat[] = {
452  "st,spear320",
453  "st,spear320-evb",
454  NULL,
455 };
456 
457 struct map_desc spear320_io_desc[] __initdata = {
458  {
459  .virtual = VA_SPEAR320_SOC_CONFIG_BASE,
460  .pfn = __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE),
461  .length = SZ_16M,
462  .type = MT_DEVICE
463  },
464 };
465 
466 static void __init spear320_map_io(void)
467 {
468  iotable_init(spear320_io_desc, ARRAY_SIZE(spear320_io_desc));
469  spear3xx_map_io();
470 }
471 
472 DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
473  .map_io = spear320_map_io,
474  .init_irq = spear3xx_dt_init_irq,
475  .handle_irq = vic_handle_irq,
476  .timer = &spear3xx_timer,
477  .init_machine = spear320_dt_init,
478  .restart = spear_restart,
479  .dt_compat = spear320_dt_board_compat,
480 MACHINE_END
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