Linux Kernel
3.7.1
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#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/err.h>
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/param.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/spear_smi.h>
#include <linux/mutex.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/wait.h>
#include <linux/of.h>
#include <linux/of_address.h>
Go to the source code of this file.
Data Structures | |
struct | flash_device |
struct | spear_smi |
struct | spear_snor_flash |
Macros | |
#define | SMI_MAX_CLOCK_FREQ 50000000 /* 50 MHz */ |
#define | SMI_PROBE_TIMEOUT (HZ / 10) |
#define | SMI_MAX_TIME_OUT (3 * HZ) |
#define | SMI_CMD_TIMEOUT (HZ / 10) |
#define | SMI_CR1 0x0 /* SMI control register 1 */ |
#define | SMI_CR2 0x4 /* SMI control register 2 */ |
#define | SMI_SR 0x8 /* SMI status register */ |
#define | SMI_TR 0xC /* SMI transmit register */ |
#define | SMI_RR 0x10 /* SMI receive register */ |
#define | BANK_EN (0xF << 0) /* enables all banks */ |
#define | DSEL_TIME (0x6 << 4) /* Deselect time 6 + 1 SMI_CK periods */ |
#define | SW_MODE (0x1 << 28) /* enables SW Mode */ |
#define | WB_MODE (0x1 << 29) /* Write Burst Mode */ |
#define | FAST_MODE (0x1 << 15) /* Fast Mode */ |
#define | HOLD1 (0x1 << 16) /* Clock Hold period selection */ |
#define | SEND (0x1 << 7) /* Send data */ |
#define | TFIE (0x1 << 8) /* Transmission Flag Interrupt Enable */ |
#define | WCIE (0x1 << 9) /* Write Complete Interrupt Enable */ |
#define | RD_STATUS_REG (0x1 << 10) /* reads status reg */ |
#define | WE (0x1 << 11) /* Write Enable */ |
#define | TX_LEN_SHIFT 0 |
#define | RX_LEN_SHIFT 4 |
#define | BANK_SHIFT 12 |
#define | SR_WIP 0x1 /* Write in progress */ |
#define | SR_WEL 0x2 /* Write enable latch */ |
#define | SR_BP0 0x4 /* Block protect 0 */ |
#define | SR_BP1 0x8 /* Block protect 1 */ |
#define | SR_BP2 0x10 /* Block protect 2 */ |
#define | SR_SRWD 0x80 /* SR write protect */ |
#define | TFF 0x100 /* Transfer Finished Flag */ |
#define | WCF 0x200 /* Transfer Finished Flag */ |
#define | ERF1 0x400 /* Forbidden Write Request */ |
#define | ERF2 0x800 /* Forbidden Access */ |
#define | WM_SHIFT 12 |
#define | OPCODE_RDID 0x9f /* Read JEDEC ID */ |
#define | FLASH_ID(n, es, id, psize, ssize, size) |
Functions | |
module_init (spear_smi_init) | |
module_exit (spear_smi_exit) | |
MODULE_LICENSE ("GPL") | |
MODULE_AUTHOR ("Ashish Priyadarshi, Shiraz Hashim <[email protected]>") | |
MODULE_DESCRIPTION ("MTD SMI driver for serial nor flash chips") | |
#define BANK_EN (0xF << 0) /* enables all banks */ |
Definition at line 58 of file spear_smi.c.
#define BANK_SHIFT 12 |
Definition at line 74 of file spear_smi.c.
#define DSEL_TIME (0x6 << 4) /* Deselect time 6 + 1 SMI_CK periods */ |
Definition at line 59 of file spear_smi.c.
#define ERF1 0x400 /* Forbidden Write Request */ |
Definition at line 85 of file spear_smi.c.
#define ERF2 0x800 /* Forbidden Access */ |
Definition at line 86 of file spear_smi.c.
#define FAST_MODE (0x1 << 15) /* Fast Mode */ |
Definition at line 62 of file spear_smi.c.
#define HOLD1 (0x1 << 16) /* Clock Hold period selection */ |
Definition at line 63 of file spear_smi.c.
#define OPCODE_RDID 0x9f /* Read JEDEC ID */ |
Definition at line 91 of file spear_smi.c.
#define RD_STATUS_REG (0x1 << 10) /* reads status reg */ |
Definition at line 69 of file spear_smi.c.
#define RX_LEN_SHIFT 4 |
Definition at line 73 of file spear_smi.c.
#define SEND (0x1 << 7) /* Send data */ |
Definition at line 66 of file spear_smi.c.
#define SMI_CMD_TIMEOUT (HZ / 10) |
Definition at line 48 of file spear_smi.c.
#define SMI_CR1 0x0 /* SMI control register 1 */ |
Definition at line 51 of file spear_smi.c.
#define SMI_CR2 0x4 /* SMI control register 2 */ |
Definition at line 52 of file spear_smi.c.
#define SMI_MAX_CLOCK_FREQ 50000000 /* 50 MHz */ |
Definition at line 41 of file spear_smi.c.
#define SMI_MAX_TIME_OUT (3 * HZ) |
Definition at line 45 of file spear_smi.c.
#define SMI_PROBE_TIMEOUT (HZ / 10) |
Definition at line 44 of file spear_smi.c.
#define SMI_RR 0x10 /* SMI receive register */ |
Definition at line 55 of file spear_smi.c.
#define SMI_SR 0x8 /* SMI status register */ |
Definition at line 53 of file spear_smi.c.
#define SMI_TR 0xC /* SMI transmit register */ |
Definition at line 54 of file spear_smi.c.
#define SR_BP0 0x4 /* Block protect 0 */ |
Definition at line 79 of file spear_smi.c.
#define SR_BP1 0x8 /* Block protect 1 */ |
Definition at line 80 of file spear_smi.c.
#define SR_BP2 0x10 /* Block protect 2 */ |
Definition at line 81 of file spear_smi.c.
#define SR_SRWD 0x80 /* SR write protect */ |
Definition at line 82 of file spear_smi.c.
#define SR_WEL 0x2 /* Write enable latch */ |
Definition at line 78 of file spear_smi.c.
#define SR_WIP 0x1 /* Write in progress */ |
Definition at line 77 of file spear_smi.c.
#define SW_MODE (0x1 << 28) /* enables SW Mode */ |
Definition at line 60 of file spear_smi.c.
#define TFF 0x100 /* Transfer Finished Flag */ |
Definition at line 83 of file spear_smi.c.
#define TFIE (0x1 << 8) /* Transmission Flag Interrupt Enable */ |
Definition at line 67 of file spear_smi.c.
#define TX_LEN_SHIFT 0 |
Definition at line 72 of file spear_smi.c.
#define WB_MODE (0x1 << 29) /* Write Burst Mode */ |
Definition at line 61 of file spear_smi.c.
#define WCF 0x200 /* Transfer Finished Flag */ |
Definition at line 84 of file spear_smi.c.
#define WCIE (0x1 << 9) /* Write Complete Interrupt Enable */ |
Definition at line 68 of file spear_smi.c.
#define WE (0x1 << 11) /* Write Enable */ |
Definition at line 70 of file spear_smi.c.
#define WM_SHIFT 12 |
Definition at line 88 of file spear_smi.c.
MODULE_AUTHOR | ( | "Ashish | Priyadarshi, |
Shiraz Hashim< shiraz.hashim @st.com >" | |||
) |
module_exit | ( | spear_smi_exit | ) |
module_init | ( | spear_smi_init | ) |
MODULE_LICENSE | ( | "GPL" | ) |