Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
spi-dw.h
Go to the documentation of this file.
1 #ifndef DW_SPI_HEADER_H
2 #define DW_SPI_HEADER_H
3 
4 #include <linux/io.h>
5 #include <linux/scatterlist.h>
6 
7 /* Register offsets */
8 #define DW_SPI_CTRL0 0x00
9 #define DW_SPI_CTRL1 0x04
10 #define DW_SPI_SSIENR 0x08
11 #define DW_SPI_MWCR 0x0c
12 #define DW_SPI_SER 0x10
13 #define DW_SPI_BAUDR 0x14
14 #define DW_SPI_TXFLTR 0x18
15 #define DW_SPI_RXFLTR 0x1c
16 #define DW_SPI_TXFLR 0x20
17 #define DW_SPI_RXFLR 0x24
18 #define DW_SPI_SR 0x28
19 #define DW_SPI_IMR 0x2c
20 #define DW_SPI_ISR 0x30
21 #define DW_SPI_RISR 0x34
22 #define DW_SPI_TXOICR 0x38
23 #define DW_SPI_RXOICR 0x3c
24 #define DW_SPI_RXUICR 0x40
25 #define DW_SPI_MSTICR 0x44
26 #define DW_SPI_ICR 0x48
27 #define DW_SPI_DMACR 0x4c
28 #define DW_SPI_DMATDLR 0x50
29 #define DW_SPI_DMARDLR 0x54
30 #define DW_SPI_IDR 0x58
31 #define DW_SPI_VERSION 0x5c
32 #define DW_SPI_DR 0x60
33 
34 /* Bit fields in CTRLR0 */
35 #define SPI_DFS_OFFSET 0
36 
37 #define SPI_FRF_OFFSET 4
38 #define SPI_FRF_SPI 0x0
39 #define SPI_FRF_SSP 0x1
40 #define SPI_FRF_MICROWIRE 0x2
41 #define SPI_FRF_RESV 0x3
42 
43 #define SPI_MODE_OFFSET 6
44 #define SPI_SCPH_OFFSET 6
45 #define SPI_SCOL_OFFSET 7
46 
47 #define SPI_TMOD_OFFSET 8
48 #define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET)
49 #define SPI_TMOD_TR 0x0 /* xmit & recv */
50 #define SPI_TMOD_TO 0x1 /* xmit only */
51 #define SPI_TMOD_RO 0x2 /* recv only */
52 #define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
53 
54 #define SPI_SLVOE_OFFSET 10
55 #define SPI_SRL_OFFSET 11
56 #define SPI_CFS_OFFSET 12
57 
58 /* Bit fields in SR, 7 bits */
59 #define SR_MASK 0x7f /* cover 7 bits */
60 #define SR_BUSY (1 << 0)
61 #define SR_TF_NOT_FULL (1 << 1)
62 #define SR_TF_EMPT (1 << 2)
63 #define SR_RF_NOT_EMPT (1 << 3)
64 #define SR_RF_FULL (1 << 4)
65 #define SR_TX_ERR (1 << 5)
66 #define SR_DCOL (1 << 6)
67 
68 /* Bit fields in ISR, IMR, RISR, 7 bits */
69 #define SPI_INT_TXEI (1 << 0)
70 #define SPI_INT_TXOI (1 << 1)
71 #define SPI_INT_RXUI (1 << 2)
72 #define SPI_INT_RXOI (1 << 3)
73 #define SPI_INT_RXFI (1 << 4)
74 #define SPI_INT_MSTI (1 << 5)
75 
76 /* TX RX interrupt level threshold, max can be 256 */
77 #define SPI_INT_THRESHOLD 32
78 
79 enum dw_ssi_type {
80  SSI_MOTO_SPI = 0,
81  SSI_TI_SSP,
82  SSI_NS_MICROWIRE,
83 };
84 
85 struct dw_spi;
86 struct dw_spi_dma_ops {
87  int (*dma_init)(struct dw_spi *dws);
88  void (*dma_exit)(struct dw_spi *dws);
89  int (*dma_transfer)(struct dw_spi *dws, int cs_change);
90 };
91 
92 struct dw_spi {
93  struct spi_master *master;
94  struct spi_device *cur_dev;
95  struct device *parent_dev;
96  enum dw_ssi_type type;
97  char name[16];
98 
99  void __iomem *regs;
100  unsigned long paddr;
101  u32 iolen;
102  int irq;
103  u32 fifo_len; /* depth of the FIFO buffer */
104  u32 max_freq; /* max bus freq supported */
105 
106  u16 bus_num;
107  u16 num_cs; /* supported slave numbers */
108 
109  /* Driver message queue */
110  struct workqueue_struct *workqueue;
111  struct work_struct pump_messages;
112  spinlock_t lock;
113  struct list_head queue;
114  int busy;
115  int run;
116 
117  /* Message Transfer pump */
118  struct tasklet_struct pump_transfers;
119 
120  /* Current message transfer state info */
121  struct spi_message *cur_msg;
122  struct spi_transfer *cur_transfer;
123  struct chip_data *cur_chip;
124  struct chip_data *prev_chip;
125  size_t len;
126  void *tx;
127  void *tx_end;
128  void *rx;
129  void *rx_end;
130  int dma_mapped;
131  dma_addr_t rx_dma;
132  dma_addr_t tx_dma;
133  size_t rx_map_len;
134  size_t tx_map_len;
135  u8 n_bytes; /* current is a 1/2 bytes op */
136  u8 max_bits_per_word; /* maxim is 16b */
137  u32 dma_width;
138  int cs_change;
139  irqreturn_t (*transfer_handler)(struct dw_spi *dws);
140  void (*cs_control)(u32 command);
141 
142  /* Dma info */
143  int dma_inited;
144  struct dma_chan *txchan;
145  struct scatterlist tx_sgl;
146  struct dma_chan *rxchan;
147  struct scatterlist rx_sgl;
148  int dma_chan_done;
149  struct device *dma_dev;
150  dma_addr_t dma_addr; /* phy address of the Data register */
151  struct dw_spi_dma_ops *dma_ops;
152  void *dma_priv; /* platform relate info */
153  struct pci_dev *dmac;
154 
155  /* Bus interface info */
156  void *priv;
157 #ifdef CONFIG_DEBUG_FS
158  struct dentry *debugfs;
159 #endif
160 };
161 
162 static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
163 {
164  return __raw_readl(dws->regs + offset);
165 }
166 
167 static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
168 {
169  __raw_writel(val, dws->regs + offset);
170 }
171 
172 static inline u16 dw_readw(struct dw_spi *dws, u32 offset)
173 {
174  return __raw_readw(dws->regs + offset);
175 }
176 
177 static inline void dw_writew(struct dw_spi *dws, u32 offset, u16 val)
178 {
179  __raw_writew(val, dws->regs + offset);
180 }
181 
182 static inline void spi_enable_chip(struct dw_spi *dws, int enable)
183 {
184  dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
185 }
186 
187 static inline void spi_set_clk(struct dw_spi *dws, u16 div)
188 {
189  dw_writel(dws, DW_SPI_BAUDR, div);
190 }
191 
192 static inline void spi_chip_sel(struct dw_spi *dws, u16 cs)
193 {
194  if (cs > dws->num_cs)
195  return;
196 
197  if (dws->cs_control)
198  dws->cs_control(1);
199 
200  dw_writel(dws, DW_SPI_SER, 1 << cs);
201 }
202 
203 /* Disable IRQ bits */
204 static inline void spi_mask_intr(struct dw_spi *dws, u32 mask)
205 {
206  u32 new_mask;
207 
208  new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;
209  dw_writel(dws, DW_SPI_IMR, new_mask);
210 }
211 
212 /* Enable IRQ bits */
213 static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
214 {
215  u32 new_mask;
216 
217  new_mask = dw_readl(dws, DW_SPI_IMR) | mask;
218  dw_writel(dws, DW_SPI_IMR, new_mask);
219 }
220 
221 /*
222  * Each SPI slave device to work with dw_api controller should
223  * has such a structure claiming its working mode (PIO/DMA etc),
224  * which can be save in the "controller_data" member of the
225  * struct spi_device
226  */
227 struct dw_spi_chip {
228  u8 poll_mode; /* 0 for contoller polling mode */
229  u8 type; /* SPI/SSP/Micrwire */
230  u8 enable_dma;
231  void (*cs_control)(u32 command);
232 };
233 
234 extern int dw_spi_add_host(struct dw_spi *dws);
235 extern void dw_spi_remove_host(struct dw_spi *dws);
236 extern int dw_spi_suspend_host(struct dw_spi *dws);
237 extern int dw_spi_resume_host(struct dw_spi *dws);
238 extern void dw_spi_xfer_done(struct dw_spi *dws);
239 
240 /* platform related setup */
241 extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */
242 #endif /* DW_SPI_HEADER_H */
Generated on Thu Jan 10 2013 14:25:33 for Linux Kernel by   doxygen 1.8.2