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sr030pc30.c
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1 /*
2  * Driver for SiliconFile SR030PC30 VGA (1/10-Inch) Image Sensor with ISP
3  *
4  * Copyright (C) 2010 Samsung Electronics Co., Ltd
5  * Author: Sylwester Nawrocki, [email protected]
6  *
7  * Based on original driver authored by Dongsoo Nathaniel Kim
8  * and HeungJun Kim <[email protected]>.
9  *
10  * Based on mt9v011 Micron Digital Image Sensor driver
11  * Copyright (c) 2009 Mauro Carvalho Chehab ([email protected])
12  *
13  * This program is free software; you can redistribute it and/or modify
14  * it under the terms of the GNU General Public License as published by
15  * the Free Software Foundation; either version 2 of the License, or
16  * (at your option) any later version.
17  */
18 
19 #include <linux/i2c.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/module.h>
23 #include <media/v4l2-device.h>
24 #include <media/v4l2-subdev.h>
25 #include <media/v4l2-mediabus.h>
26 #include <media/sr030pc30.h>
27 
28 static int debug;
29 module_param(debug, int, 0644);
30 
31 #define MODULE_NAME "SR030PC30"
32 
33 /*
34  * Register offsets within a page
35  * b15..b8 - page id, b7..b0 - register address
36  */
37 #define POWER_CTRL_REG 0x0001
38 #define PAGEMODE_REG 0x03
39 #define DEVICE_ID_REG 0x0004
40 #define NOON010PC30_ID 0x86
41 #define SR030PC30_ID 0x8C
42 #define VDO_CTL1_REG 0x0010
43 #define SUBSAMPL_NONE_VGA 0
44 #define SUBSAMPL_QVGA 0x10
45 #define SUBSAMPL_QQVGA 0x20
46 #define VDO_CTL2_REG 0x0011
47 #define SYNC_CTL_REG 0x0012
48 #define WIN_ROWH_REG 0x0020
49 #define WIN_ROWL_REG 0x0021
50 #define WIN_COLH_REG 0x0022
51 #define WIN_COLL_REG 0x0023
52 #define WIN_HEIGHTH_REG 0x0024
53 #define WIN_HEIGHTL_REG 0x0025
54 #define WIN_WIDTHH_REG 0x0026
55 #define WIN_WIDTHL_REG 0x0027
56 #define HBLANKH_REG 0x0040
57 #define HBLANKL_REG 0x0041
58 #define VSYNCH_REG 0x0042
59 #define VSYNCL_REG 0x0043
60 /* page 10 */
61 #define ISP_CTL_REG(n) (0x1010 + (n))
62 #define YOFS_REG 0x1040
63 #define DARK_YOFS_REG 0x1041
64 #define AG_ABRTH_REG 0x1050
65 #define SAT_CTL_REG 0x1060
66 #define BSAT_REG 0x1061
67 #define RSAT_REG 0x1062
68 #define AG_SAT_TH_REG 0x1063
69 /* page 11 */
70 #define ZLPF_CTRL_REG 0x1110
71 #define ZLPF_CTRL2_REG 0x1112
72 #define ZLPF_AGH_THR_REG 0x1121
73 #define ZLPF_THR_REG 0x1160
74 #define ZLPF_DYN_THR_REG 0x1160
75 /* page 12 */
76 #define YCLPF_CTL1_REG 0x1240
77 #define YCLPF_CTL2_REG 0x1241
78 #define YCLPF_THR_REG 0x1250
79 #define BLPF_CTL_REG 0x1270
80 #define BLPF_THR1_REG 0x1274
81 #define BLPF_THR2_REG 0x1275
82 /* page 14 - Lens Shading Compensation */
83 #define LENS_CTRL_REG 0x1410
84 #define LENS_XCEN_REG 0x1420
85 #define LENS_YCEN_REG 0x1421
86 #define LENS_R_COMP_REG 0x1422
87 #define LENS_G_COMP_REG 0x1423
88 #define LENS_B_COMP_REG 0x1424
89 /* page 15 - Color correction */
90 #define CMC_CTL_REG 0x1510
91 #define CMC_OFSGH_REG 0x1514
92 #define CMC_OFSGL_REG 0x1516
93 #define CMC_SIGN_REG 0x1517
94 /* Color correction coefficients */
95 #define CMC_COEF_REG(n) (0x1530 + (n))
96 /* Color correction offset coefficients */
97 #define CMC_OFS_REG(n) (0x1540 + (n))
98 /* page 16 - Gamma correction */
99 #define GMA_CTL_REG 0x1610
100 /* Gamma correction coefficients 0.14 */
101 #define GMA_COEF_REG(n) (0x1630 + (n))
102 /* page 20 - Auto Exposure */
103 #define AE_CTL1_REG 0x2010
104 #define AE_CTL2_REG 0x2011
105 #define AE_FRM_CTL_REG 0x2020
106 #define AE_FINE_CTL_REG(n) (0x2028 + (n))
107 #define EXP_TIMEH_REG 0x2083
108 #define EXP_TIMEM_REG 0x2084
109 #define EXP_TIMEL_REG 0x2085
110 #define EXP_MMINH_REG 0x2086
111 #define EXP_MMINL_REG 0x2087
112 #define EXP_MMAXH_REG 0x2088
113 #define EXP_MMAXM_REG 0x2089
114 #define EXP_MMAXL_REG 0x208A
115 /* page 22 - Auto White Balance */
116 #define AWB_CTL1_REG 0x2210
117 #define AWB_ENABLE 0x80
118 #define AWB_CTL2_REG 0x2211
119 #define MWB_ENABLE 0x01
120 /* RGB gain control (manual WB) when AWB_CTL1[7]=0 */
121 #define AWB_RGAIN_REG 0x2280
122 #define AWB_GGAIN_REG 0x2281
123 #define AWB_BGAIN_REG 0x2282
124 #define AWB_RMAX_REG 0x2283
125 #define AWB_RMIN_REG 0x2284
126 #define AWB_BMAX_REG 0x2285
127 #define AWB_BMIN_REG 0x2286
128 /* R, B gain range in bright light conditions */
129 #define AWB_RMAXB_REG 0x2287
130 #define AWB_RMINB_REG 0x2288
131 #define AWB_BMAXB_REG 0x2289
132 #define AWB_BMINB_REG 0x228A
133 /* manual white balance, when AWB_CTL2[0]=1 */
134 #define MWB_RGAIN_REG 0x22B2
135 #define MWB_BGAIN_REG 0x22B3
136 /* the token to mark an array end */
137 #define REG_TERM 0xFFFF
138 
139 /* Minimum and maximum exposure time in ms */
140 #define EXPOS_MIN_MS 1
141 #define EXPOS_MAX_MS 125
142 
143 struct sr030pc30_info {
144  struct v4l2_subdev sd;
145  const struct sr030pc30_platform_data *pdata;
146  const struct sr030pc30_format *curr_fmt;
147  const struct sr030pc30_frmsize *curr_win;
148  unsigned int auto_wb:1;
149  unsigned int auto_exp:1;
150  unsigned int hflip:1;
151  unsigned int vflip:1;
152  unsigned int sleep:1;
153  unsigned int exposure;
154  u8 blue_balance;
155  u8 red_balance;
156  u8 i2c_reg_page;
157 };
158 
159 struct sr030pc30_format {
160  enum v4l2_mbus_pixelcode code;
161  enum v4l2_colorspace colorspace;
162  u16 ispctl1_reg;
163 };
164 
165 struct sr030pc30_frmsize {
166  u16 width;
167  u16 height;
168  int vid_ctl1;
169 };
170 
171 struct i2c_regval {
172  u16 addr;
173  u16 val;
174 };
175 
176 static const struct v4l2_queryctrl sr030pc30_ctrl[] = {
177  {
178  .id = V4L2_CID_AUTO_WHITE_BALANCE,
179  .type = V4L2_CTRL_TYPE_BOOLEAN,
180  .name = "Auto White Balance",
181  .minimum = 0,
182  .maximum = 1,
183  .step = 1,
184  .default_value = 1,
185  }, {
186  .id = V4L2_CID_RED_BALANCE,
187  .type = V4L2_CTRL_TYPE_INTEGER,
188  .name = "Red Balance",
189  .minimum = 0,
190  .maximum = 127,
191  .step = 1,
192  .default_value = 64,
193  .flags = 0,
194  }, {
195  .id = V4L2_CID_BLUE_BALANCE,
196  .type = V4L2_CTRL_TYPE_INTEGER,
197  .name = "Blue Balance",
198  .minimum = 0,
199  .maximum = 127,
200  .step = 1,
201  .default_value = 64,
202  }, {
203  .id = V4L2_CID_EXPOSURE_AUTO,
204  .type = V4L2_CTRL_TYPE_INTEGER,
205  .name = "Auto Exposure",
206  .minimum = 0,
207  .maximum = 1,
208  .step = 1,
209  .default_value = 1,
210  }, {
211  .id = V4L2_CID_EXPOSURE,
212  .type = V4L2_CTRL_TYPE_INTEGER,
213  .name = "Exposure",
214  .minimum = EXPOS_MIN_MS,
215  .maximum = EXPOS_MAX_MS,
216  .step = 1,
217  .default_value = 1,
218  }, {
219  }
220 };
221 
222 /* supported resolutions */
223 static const struct sr030pc30_frmsize sr030pc30_sizes[] = {
224  {
225  .width = 640,
226  .height = 480,
227  .vid_ctl1 = SUBSAMPL_NONE_VGA,
228  }, {
229  .width = 320,
230  .height = 240,
231  .vid_ctl1 = SUBSAMPL_QVGA,
232  }, {
233  .width = 160,
234  .height = 120,
235  .vid_ctl1 = SUBSAMPL_QQVGA,
236  },
237 };
238 
239 /* supported pixel formats */
240 static const struct sr030pc30_format sr030pc30_formats[] = {
241  {
242  .code = V4L2_MBUS_FMT_YUYV8_2X8,
243  .colorspace = V4L2_COLORSPACE_JPEG,
244  .ispctl1_reg = 0x03,
245  }, {
246  .code = V4L2_MBUS_FMT_YVYU8_2X8,
247  .colorspace = V4L2_COLORSPACE_JPEG,
248  .ispctl1_reg = 0x02,
249  }, {
250  .code = V4L2_MBUS_FMT_VYUY8_2X8,
251  .colorspace = V4L2_COLORSPACE_JPEG,
252  .ispctl1_reg = 0,
253  }, {
254  .code = V4L2_MBUS_FMT_UYVY8_2X8,
255  .colorspace = V4L2_COLORSPACE_JPEG,
256  .ispctl1_reg = 0x01,
257  }, {
258  .code = V4L2_MBUS_FMT_RGB565_2X8_BE,
259  .colorspace = V4L2_COLORSPACE_JPEG,
260  .ispctl1_reg = 0x40,
261  },
262 };
263 
264 static const struct i2c_regval sr030pc30_base_regs[] = {
265  /* Window size and position within pixel matrix */
266  { WIN_ROWH_REG, 0x00 }, { WIN_ROWL_REG, 0x06 },
267  { WIN_COLH_REG, 0x00 }, { WIN_COLL_REG, 0x06 },
268  { WIN_HEIGHTH_REG, 0x01 }, { WIN_HEIGHTL_REG, 0xE0 },
269  { WIN_WIDTHH_REG, 0x02 }, { WIN_WIDTHL_REG, 0x80 },
270  { HBLANKH_REG, 0x01 }, { HBLANKL_REG, 0x50 },
271  { VSYNCH_REG, 0x00 }, { VSYNCL_REG, 0x14 },
272  { SYNC_CTL_REG, 0 },
273  /* Color corection and saturation */
274  { ISP_CTL_REG(0), 0x30 }, { YOFS_REG, 0x80 },
275  { DARK_YOFS_REG, 0x04 }, { AG_ABRTH_REG, 0x78 },
276  { SAT_CTL_REG, 0x1F }, { BSAT_REG, 0x90 },
277  { AG_SAT_TH_REG, 0xF0 }, { 0x1064, 0x80 },
278  { CMC_CTL_REG, 0x03 }, { CMC_OFSGH_REG, 0x3C },
279  { CMC_OFSGL_REG, 0x2C }, { CMC_SIGN_REG, 0x2F },
280  { CMC_COEF_REG(0), 0xCB }, { CMC_OFS_REG(0), 0x87 },
281  { CMC_COEF_REG(1), 0x61 }, { CMC_OFS_REG(1), 0x18 },
282  { CMC_COEF_REG(2), 0x16 }, { CMC_OFS_REG(2), 0x91 },
283  { CMC_COEF_REG(3), 0x23 }, { CMC_OFS_REG(3), 0x94 },
284  { CMC_COEF_REG(4), 0xCE }, { CMC_OFS_REG(4), 0x9f },
285  { CMC_COEF_REG(5), 0x2B }, { CMC_OFS_REG(5), 0x33 },
286  { CMC_COEF_REG(6), 0x01 }, { CMC_OFS_REG(6), 0x00 },
287  { CMC_COEF_REG(7), 0x34 }, { CMC_OFS_REG(7), 0x94 },
288  { CMC_COEF_REG(8), 0x75 }, { CMC_OFS_REG(8), 0x14 },
289  /* Color corection coefficients */
290  { GMA_CTL_REG, 0x03 }, { GMA_COEF_REG(0), 0x00 },
291  { GMA_COEF_REG(1), 0x19 }, { GMA_COEF_REG(2), 0x26 },
292  { GMA_COEF_REG(3), 0x3B }, { GMA_COEF_REG(4), 0x5D },
293  { GMA_COEF_REG(5), 0x79 }, { GMA_COEF_REG(6), 0x8E },
294  { GMA_COEF_REG(7), 0x9F }, { GMA_COEF_REG(8), 0xAF },
295  { GMA_COEF_REG(9), 0xBD }, { GMA_COEF_REG(10), 0xCA },
296  { GMA_COEF_REG(11), 0xDD }, { GMA_COEF_REG(12), 0xEC },
297  { GMA_COEF_REG(13), 0xF7 }, { GMA_COEF_REG(14), 0xFF },
298  /* Noise reduction, Z-LPF, YC-LPF and BLPF filters setup */
299  { ZLPF_CTRL_REG, 0x99 }, { ZLPF_CTRL2_REG, 0x0E },
300  { ZLPF_AGH_THR_REG, 0x29 }, { ZLPF_THR_REG, 0x0F },
301  { ZLPF_DYN_THR_REG, 0x63 }, { YCLPF_CTL1_REG, 0x23 },
302  { YCLPF_CTL2_REG, 0x3B }, { YCLPF_THR_REG, 0x05 },
303  { BLPF_CTL_REG, 0x1D }, { BLPF_THR1_REG, 0x05 },
304  { BLPF_THR2_REG, 0x04 },
305  /* Automatic white balance */
306  { AWB_CTL1_REG, 0xFB }, { AWB_CTL2_REG, 0x26 },
307  { AWB_RMAX_REG, 0x54 }, { AWB_RMIN_REG, 0x2B },
308  { AWB_BMAX_REG, 0x57 }, { AWB_BMIN_REG, 0x29 },
309  { AWB_RMAXB_REG, 0x50 }, { AWB_RMINB_REG, 0x43 },
310  { AWB_BMAXB_REG, 0x30 }, { AWB_BMINB_REG, 0x22 },
311  /* Auto exposure */
312  { AE_CTL1_REG, 0x8C }, { AE_CTL2_REG, 0x04 },
313  { AE_FRM_CTL_REG, 0x01 }, { AE_FINE_CTL_REG(0), 0x3F },
314  { AE_FINE_CTL_REG(1), 0xA3 }, { AE_FINE_CTL_REG(3), 0x34 },
315  /* Lens shading compensation */
316  { LENS_CTRL_REG, 0x01 }, { LENS_XCEN_REG, 0x80 },
317  { LENS_YCEN_REG, 0x70 }, { LENS_R_COMP_REG, 0x53 },
318  { LENS_G_COMP_REG, 0x40 }, { LENS_B_COMP_REG, 0x3e },
319  { REG_TERM, 0 },
320 };
321 
322 static inline struct sr030pc30_info *to_sr030pc30(struct v4l2_subdev *sd)
323 {
324  return container_of(sd, struct sr030pc30_info, sd);
325 }
326 
327 static inline int set_i2c_page(struct sr030pc30_info *info,
328  struct i2c_client *client, unsigned int reg)
329 {
330  int ret = 0;
331  u32 page = reg >> 8 & 0xFF;
332 
333  if (info->i2c_reg_page != page && (reg & 0xFF) != 0x03) {
334  ret = i2c_smbus_write_byte_data(client, PAGEMODE_REG, page);
335  if (!ret)
336  info->i2c_reg_page = page;
337  }
338  return ret;
339 }
340 
341 static int cam_i2c_read(struct v4l2_subdev *sd, u32 reg_addr)
342 {
343  struct i2c_client *client = v4l2_get_subdevdata(sd);
344  struct sr030pc30_info *info = to_sr030pc30(sd);
345 
346  int ret = set_i2c_page(info, client, reg_addr);
347  if (!ret)
348  ret = i2c_smbus_read_byte_data(client, reg_addr & 0xFF);
349  return ret;
350 }
351 
352 static int cam_i2c_write(struct v4l2_subdev *sd, u32 reg_addr, u32 val)
353 {
354  struct i2c_client *client = v4l2_get_subdevdata(sd);
355  struct sr030pc30_info *info = to_sr030pc30(sd);
356 
357  int ret = set_i2c_page(info, client, reg_addr);
358  if (!ret)
359  ret = i2c_smbus_write_byte_data(
360  client, reg_addr & 0xFF, val);
361  return ret;
362 }
363 
364 static inline int sr030pc30_bulk_write_reg(struct v4l2_subdev *sd,
365  const struct i2c_regval *msg)
366 {
367  while (msg->addr != REG_TERM) {
368  int ret = cam_i2c_write(sd, msg->addr, msg->val);
369  if (ret)
370  return ret;
371  msg++;
372  }
373  return 0;
374 }
375 
376 /* Device reset and sleep mode control */
377 static int sr030pc30_pwr_ctrl(struct v4l2_subdev *sd,
378  bool reset, bool sleep)
379 {
380  struct sr030pc30_info *info = to_sr030pc30(sd);
381  u8 reg = sleep ? 0xF1 : 0xF0;
382  int ret = 0;
383 
384  if (reset)
385  ret = cam_i2c_write(sd, POWER_CTRL_REG, reg | 0x02);
386  if (!ret) {
387  ret = cam_i2c_write(sd, POWER_CTRL_REG, reg);
388  if (!ret) {
389  info->sleep = sleep;
390  if (reset)
391  info->i2c_reg_page = -1;
392  }
393  }
394  return ret;
395 }
396 
397 static inline int sr030pc30_enable_autoexposure(struct v4l2_subdev *sd, int on)
398 {
399  struct sr030pc30_info *info = to_sr030pc30(sd);
400  /* auto anti-flicker is also enabled here */
401  int ret = cam_i2c_write(sd, AE_CTL1_REG, on ? 0xDC : 0x0C);
402  if (!ret)
403  info->auto_exp = on;
404  return ret;
405 }
406 
407 static int sr030pc30_set_exposure(struct v4l2_subdev *sd, int value)
408 {
409  struct sr030pc30_info *info = to_sr030pc30(sd);
410 
411  unsigned long expos = value * info->pdata->clk_rate / (8 * 1000);
412 
413  int ret = cam_i2c_write(sd, EXP_TIMEH_REG, expos >> 16 & 0xFF);
414  if (!ret)
415  ret = cam_i2c_write(sd, EXP_TIMEM_REG, expos >> 8 & 0xFF);
416  if (!ret)
417  ret = cam_i2c_write(sd, EXP_TIMEL_REG, expos & 0xFF);
418  if (!ret) { /* Turn off AE */
419  info->exposure = value;
420  ret = sr030pc30_enable_autoexposure(sd, 0);
421  }
422  return ret;
423 }
424 
425 /* Automatic white balance control */
426 static int sr030pc30_enable_autowhitebalance(struct v4l2_subdev *sd, int on)
427 {
428  struct sr030pc30_info *info = to_sr030pc30(sd);
429 
430  int ret = cam_i2c_write(sd, AWB_CTL2_REG, on ? 0x2E : 0x2F);
431  if (!ret)
432  ret = cam_i2c_write(sd, AWB_CTL1_REG, on ? 0xFB : 0x7B);
433  if (!ret)
434  info->auto_wb = on;
435 
436  return ret;
437 }
438 
439 static int sr030pc30_set_flip(struct v4l2_subdev *sd)
440 {
441  struct sr030pc30_info *info = to_sr030pc30(sd);
442 
443  s32 reg = cam_i2c_read(sd, VDO_CTL2_REG);
444  if (reg < 0)
445  return reg;
446 
447  reg &= 0x7C;
448  if (info->hflip)
449  reg |= 0x01;
450  if (info->vflip)
451  reg |= 0x02;
452  return cam_i2c_write(sd, VDO_CTL2_REG, reg | 0x80);
453 }
454 
455 /* Configure resolution, color format and image flip */
456 static int sr030pc30_set_params(struct v4l2_subdev *sd)
457 {
458  struct sr030pc30_info *info = to_sr030pc30(sd);
459  int ret;
460 
461  if (!info->curr_win)
462  return -EINVAL;
463 
464  /* Configure the resolution through subsampling */
465  ret = cam_i2c_write(sd, VDO_CTL1_REG,
466  info->curr_win->vid_ctl1);
467 
468  if (!ret && info->curr_fmt)
469  ret = cam_i2c_write(sd, ISP_CTL_REG(0),
470  info->curr_fmt->ispctl1_reg);
471  if (!ret)
472  ret = sr030pc30_set_flip(sd);
473 
474  return ret;
475 }
476 
477 /* Find nearest matching image pixel size. */
478 static int sr030pc30_try_frame_size(struct v4l2_mbus_framefmt *mf)
479 {
480  unsigned int min_err = ~0;
481  int i = ARRAY_SIZE(sr030pc30_sizes);
482  const struct sr030pc30_frmsize *fsize = &sr030pc30_sizes[0],
483  *match = NULL;
484  while (i--) {
485  int err = abs(fsize->width - mf->width)
486  + abs(fsize->height - mf->height);
487  if (err < min_err) {
488  min_err = err;
489  match = fsize;
490  }
491  fsize++;
492  }
493  if (match) {
494  mf->width = match->width;
495  mf->height = match->height;
496  return 0;
497  }
498  return -EINVAL;
499 }
500 
501 static int sr030pc30_queryctrl(struct v4l2_subdev *sd,
502  struct v4l2_queryctrl *qc)
503 {
504  int i;
505 
506  for (i = 0; i < ARRAY_SIZE(sr030pc30_ctrl); i++)
507  if (qc->id == sr030pc30_ctrl[i].id) {
508  *qc = sr030pc30_ctrl[i];
509  v4l2_dbg(1, debug, sd, "%s id: %d\n",
510  __func__, qc->id);
511  return 0;
512  }
513 
514  return -EINVAL;
515 }
516 
517 static inline int sr030pc30_set_bluebalance(struct v4l2_subdev *sd, int value)
518 {
519  int ret = cam_i2c_write(sd, MWB_BGAIN_REG, value);
520  if (!ret)
521  to_sr030pc30(sd)->blue_balance = value;
522  return ret;
523 }
524 
525 static inline int sr030pc30_set_redbalance(struct v4l2_subdev *sd, int value)
526 {
527  int ret = cam_i2c_write(sd, MWB_RGAIN_REG, value);
528  if (!ret)
529  to_sr030pc30(sd)->red_balance = value;
530  return ret;
531 }
532 
533 static int sr030pc30_s_ctrl(struct v4l2_subdev *sd,
534  struct v4l2_control *ctrl)
535 {
536  int i, ret = 0;
537 
538  for (i = 0; i < ARRAY_SIZE(sr030pc30_ctrl); i++)
539  if (ctrl->id == sr030pc30_ctrl[i].id)
540  break;
541 
542  if (i == ARRAY_SIZE(sr030pc30_ctrl))
543  return -EINVAL;
544 
545  if (ctrl->value < sr030pc30_ctrl[i].minimum ||
546  ctrl->value > sr030pc30_ctrl[i].maximum)
547  return -ERANGE;
548 
549  v4l2_dbg(1, debug, sd, "%s: ctrl_id: %d, value: %d\n",
550  __func__, ctrl->id, ctrl->value);
551 
552  switch (ctrl->id) {
553  case V4L2_CID_AUTO_WHITE_BALANCE:
554  sr030pc30_enable_autowhitebalance(sd, ctrl->value);
555  break;
556  case V4L2_CID_BLUE_BALANCE:
557  ret = sr030pc30_set_bluebalance(sd, ctrl->value);
558  break;
559  case V4L2_CID_RED_BALANCE:
560  ret = sr030pc30_set_redbalance(sd, ctrl->value);
561  break;
562  case V4L2_CID_EXPOSURE_AUTO:
563  sr030pc30_enable_autoexposure(sd,
564  ctrl->value == V4L2_EXPOSURE_AUTO);
565  break;
566  case V4L2_CID_EXPOSURE:
567  ret = sr030pc30_set_exposure(sd, ctrl->value);
568  break;
569  default:
570  return -EINVAL;
571  }
572 
573  return ret;
574 }
575 
576 static int sr030pc30_g_ctrl(struct v4l2_subdev *sd,
577  struct v4l2_control *ctrl)
578 {
579  struct sr030pc30_info *info = to_sr030pc30(sd);
580 
581  v4l2_dbg(1, debug, sd, "%s: id: %d\n", __func__, ctrl->id);
582 
583  switch (ctrl->id) {
584  case V4L2_CID_AUTO_WHITE_BALANCE:
585  ctrl->value = info->auto_wb;
586  break;
587  case V4L2_CID_BLUE_BALANCE:
588  ctrl->value = info->blue_balance;
589  break;
590  case V4L2_CID_RED_BALANCE:
591  ctrl->value = info->red_balance;
592  break;
593  case V4L2_CID_EXPOSURE_AUTO:
594  ctrl->value = info->auto_exp;
595  break;
596  case V4L2_CID_EXPOSURE:
597  ctrl->value = info->exposure;
598  break;
599  default:
600  return -EINVAL;
601  }
602  return 0;
603 }
604 
605 static int sr030pc30_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
606  enum v4l2_mbus_pixelcode *code)
607 {
608  if (!code || index >= ARRAY_SIZE(sr030pc30_formats))
609  return -EINVAL;
610 
611  *code = sr030pc30_formats[index].code;
612  return 0;
613 }
614 
615 static int sr030pc30_g_fmt(struct v4l2_subdev *sd,
616  struct v4l2_mbus_framefmt *mf)
617 {
618  struct sr030pc30_info *info = to_sr030pc30(sd);
619  int ret;
620 
621  if (!mf)
622  return -EINVAL;
623 
624  if (!info->curr_win || !info->curr_fmt) {
625  ret = sr030pc30_set_params(sd);
626  if (ret)
627  return ret;
628  }
629 
630  mf->width = info->curr_win->width;
631  mf->height = info->curr_win->height;
632  mf->code = info->curr_fmt->code;
633  mf->colorspace = info->curr_fmt->colorspace;
634  mf->field = V4L2_FIELD_NONE;
635 
636  return 0;
637 }
638 
639 /* Return nearest media bus frame format. */
640 static const struct sr030pc30_format *try_fmt(struct v4l2_subdev *sd,
641  struct v4l2_mbus_framefmt *mf)
642 {
643  int i = ARRAY_SIZE(sr030pc30_formats);
644 
645  sr030pc30_try_frame_size(mf);
646 
647  while (i--)
648  if (mf->code == sr030pc30_formats[i].code)
649  break;
650 
651  mf->code = sr030pc30_formats[i].code;
652 
653  return &sr030pc30_formats[i];
654 }
655 
656 /* Return nearest media bus frame format. */
657 static int sr030pc30_try_fmt(struct v4l2_subdev *sd,
658  struct v4l2_mbus_framefmt *mf)
659 {
660  if (!sd || !mf)
661  return -EINVAL;
662 
663  try_fmt(sd, mf);
664  return 0;
665 }
666 
667 static int sr030pc30_s_fmt(struct v4l2_subdev *sd,
668  struct v4l2_mbus_framefmt *mf)
669 {
670  struct sr030pc30_info *info = to_sr030pc30(sd);
671 
672  if (!sd || !mf)
673  return -EINVAL;
674 
675  info->curr_fmt = try_fmt(sd, mf);
676 
677  return sr030pc30_set_params(sd);
678 }
679 
680 static int sr030pc30_base_config(struct v4l2_subdev *sd)
681 {
682  struct sr030pc30_info *info = to_sr030pc30(sd);
683  int ret;
684  unsigned long expmin, expmax;
685 
686  ret = sr030pc30_bulk_write_reg(sd, sr030pc30_base_regs);
687  if (!ret) {
688  info->curr_fmt = &sr030pc30_formats[0];
689  info->curr_win = &sr030pc30_sizes[0];
690  ret = sr030pc30_set_params(sd);
691  }
692  if (!ret)
693  ret = sr030pc30_pwr_ctrl(sd, false, false);
694 
695  if (!ret && !info->pdata)
696  return ret;
697 
698  expmin = EXPOS_MIN_MS * info->pdata->clk_rate / (8 * 1000);
699  expmax = EXPOS_MAX_MS * info->pdata->clk_rate / (8 * 1000);
700 
701  v4l2_dbg(1, debug, sd, "%s: expmin= %lx, expmax= %lx", __func__,
702  expmin, expmax);
703 
704  /* Setting up manual exposure time range */
705  ret = cam_i2c_write(sd, EXP_MMINH_REG, expmin >> 8 & 0xFF);
706  if (!ret)
707  ret = cam_i2c_write(sd, EXP_MMINL_REG, expmin & 0xFF);
708  if (!ret)
709  ret = cam_i2c_write(sd, EXP_MMAXH_REG, expmax >> 16 & 0xFF);
710  if (!ret)
711  ret = cam_i2c_write(sd, EXP_MMAXM_REG, expmax >> 8 & 0xFF);
712  if (!ret)
713  ret = cam_i2c_write(sd, EXP_MMAXL_REG, expmax & 0xFF);
714 
715  return ret;
716 }
717 
718 static int sr030pc30_s_power(struct v4l2_subdev *sd, int on)
719 {
720  struct i2c_client *client = v4l2_get_subdevdata(sd);
721  struct sr030pc30_info *info = to_sr030pc30(sd);
722  const struct sr030pc30_platform_data *pdata = info->pdata;
723  int ret;
724 
725  if (pdata == NULL) {
726  WARN(1, "No platform data!\n");
727  return -EINVAL;
728  }
729 
730  /*
731  * Put sensor into power sleep mode before switching off
732  * power and disabling MCLK.
733  */
734  if (!on)
735  sr030pc30_pwr_ctrl(sd, false, true);
736 
737  /* set_power controls sensor's power and clock */
738  if (pdata->set_power) {
739  ret = pdata->set_power(&client->dev, on);
740  if (ret)
741  return ret;
742  }
743 
744  if (on) {
745  ret = sr030pc30_base_config(sd);
746  } else {
747  ret = 0;
748  info->curr_win = NULL;
749  info->curr_fmt = NULL;
750  }
751 
752  return ret;
753 }
754 
755 static const struct v4l2_subdev_core_ops sr030pc30_core_ops = {
756  .s_power = sr030pc30_s_power,
757  .queryctrl = sr030pc30_queryctrl,
758  .s_ctrl = sr030pc30_s_ctrl,
759  .g_ctrl = sr030pc30_g_ctrl,
760 };
761 
762 static const struct v4l2_subdev_video_ops sr030pc30_video_ops = {
763  .g_mbus_fmt = sr030pc30_g_fmt,
764  .s_mbus_fmt = sr030pc30_s_fmt,
765  .try_mbus_fmt = sr030pc30_try_fmt,
766  .enum_mbus_fmt = sr030pc30_enum_fmt,
767 };
768 
769 static const struct v4l2_subdev_ops sr030pc30_ops = {
770  .core = &sr030pc30_core_ops,
771  .video = &sr030pc30_video_ops,
772 };
773 
774 /*
775  * Detect sensor type. Return 0 if SR030PC30 was detected
776  * or -ENODEV otherwise.
777  */
778 static int sr030pc30_detect(struct i2c_client *client)
779 {
780  const struct sr030pc30_platform_data *pdata
781  = client->dev.platform_data;
782  int ret;
783 
784  /* Enable sensor's power and clock */
785  if (pdata->set_power) {
786  ret = pdata->set_power(&client->dev, 1);
787  if (ret)
788  return ret;
789  }
790 
791  ret = i2c_smbus_read_byte_data(client, DEVICE_ID_REG);
792 
793  if (pdata->set_power)
794  pdata->set_power(&client->dev, 0);
795 
796  if (ret < 0) {
797  dev_err(&client->dev, "%s: I2C read failed\n", __func__);
798  return ret;
799  }
800 
801  return ret == SR030PC30_ID ? 0 : -ENODEV;
802 }
803 
804 
805 static int sr030pc30_probe(struct i2c_client *client,
806  const struct i2c_device_id *id)
807 {
808  struct sr030pc30_info *info;
809  struct v4l2_subdev *sd;
810  const struct sr030pc30_platform_data *pdata
811  = client->dev.platform_data;
812  int ret;
813 
814  if (!pdata) {
815  dev_err(&client->dev, "No platform data!");
816  return -EIO;
817  }
818 
819  ret = sr030pc30_detect(client);
820  if (ret)
821  return ret;
822 
823  info = kzalloc(sizeof(*info), GFP_KERNEL);
824  if (!info)
825  return -ENOMEM;
826 
827  sd = &info->sd;
828  strcpy(sd->name, MODULE_NAME);
829  info->pdata = client->dev.platform_data;
830 
831  v4l2_i2c_subdev_init(sd, client, &sr030pc30_ops);
832 
833  info->i2c_reg_page = -1;
834  info->hflip = 1;
835  info->auto_exp = 1;
836  info->exposure = 30;
837 
838  return 0;
839 }
840 
841 static int sr030pc30_remove(struct i2c_client *client)
842 {
843  struct v4l2_subdev *sd = i2c_get_clientdata(client);
844  struct sr030pc30_info *info = to_sr030pc30(sd);
845 
846  v4l2_device_unregister_subdev(sd);
847  kfree(info);
848  return 0;
849 }
850 
851 static const struct i2c_device_id sr030pc30_id[] = {
852  { MODULE_NAME, 0 },
853  { },
854 };
855 MODULE_DEVICE_TABLE(i2c, sr030pc30_id);
856 
857 
858 static struct i2c_driver sr030pc30_i2c_driver = {
859  .driver = {
860  .name = MODULE_NAME
861  },
862  .probe = sr030pc30_probe,
863  .remove = sr030pc30_remove,
864  .id_table = sr030pc30_id,
865 };
866 
867 module_i2c_driver(sr030pc30_i2c_driver);
868 
869 MODULE_DESCRIPTION("Siliconfile SR030PC30 camera driver");
870 MODULE_AUTHOR("Sylwester Nawrocki <[email protected]>");
871 MODULE_LICENSE("GPL");
Generated on Thu Jan 10 2013 13:46:54 for Linux Kernel by   doxygen 1.8.2