Linux Kernel  3.7.1
 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
driver_chipcommon.c
Go to the documentation of this file.
1 /*
2  * Sonics Silicon Backplane
3  * Broadcom ChipCommon core driver
4  *
5  * Copyright 2005, Broadcom Corporation
6  * Copyright 2006, 2007, Michael Buesch <[email protected]>
7  *
8  * Licensed under the GNU/GPL. See COPYING for details.
9  */
10 
11 #include <linux/ssb/ssb.h>
12 #include <linux/ssb/ssb_regs.h>
13 #include <linux/export.h>
14 #include <linux/pci.h>
15 
16 #include "ssb_private.h"
17 
18 
19 /* Clock sources */
20 enum ssb_clksrc {
21  /* PCI clock */
22  SSB_CHIPCO_CLKSRC_PCI,
23  /* Crystal slow clock oscillator */
24  SSB_CHIPCO_CLKSRC_XTALOS,
25  /* Low power oscillator */
26  SSB_CHIPCO_CLKSRC_LOPWROS,
27 };
28 
29 
30 static inline u32 chipco_write32_masked(struct ssb_chipcommon *cc, u16 offset,
31  u32 mask, u32 value)
32 {
33  value &= mask;
34  value |= chipco_read32(cc, offset) & ~mask;
35  chipco_write32(cc, offset, value);
36 
37  return value;
38 }
39 
40 void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
41  enum ssb_clkmode mode)
42 {
43  struct ssb_device *ccdev = cc->dev;
44  struct ssb_bus *bus;
45  u32 tmp;
46 
47  if (!ccdev)
48  return;
49  bus = ccdev->bus;
50 
51  /* We support SLOW only on 6..9 */
52  if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
53  mode = SSB_CLKMODE_DYNAMIC;
54 
55  if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
56  return; /* PMU controls clockmode, separated function needed */
57  SSB_WARN_ON(ccdev->id.revision >= 20);
58 
59  /* chipcommon cores prior to rev6 don't support dynamic clock control */
60  if (ccdev->id.revision < 6)
61  return;
62 
63  /* ChipCommon cores rev10+ need testing */
64  if (ccdev->id.revision >= 10)
65  return;
66 
67  if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
68  return;
69 
70  switch (mode) {
71  case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
72  tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
73  tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
74  chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
75  break;
76  case SSB_CLKMODE_FAST:
77  if (ccdev->id.revision < 10) {
78  ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
79  tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
80  tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
81  tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
82  chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
83  } else {
84  chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
85  (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
86  SSB_CHIPCO_SYSCLKCTL_FORCEHT));
87  /* udelay(150); TODO: not available in early init */
88  }
89  break;
90  case SSB_CLKMODE_DYNAMIC:
91  if (ccdev->id.revision < 10) {
92  tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
93  tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
94  tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
95  tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
96  if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
97  SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
98  tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
99  chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
100 
101  /* For dynamic control, we have to release our xtal_pu
102  * "force on" */
103  if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
104  ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
105  } else {
106  chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
107  (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
108  ~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
109  }
110  break;
111  default:
112  SSB_WARN_ON(1);
113  }
114 }
115 
116 /* Get the Slow Clock Source */
117 static enum ssb_clksrc chipco_pctl_get_slowclksrc(struct ssb_chipcommon *cc)
118 {
119  struct ssb_bus *bus = cc->dev->bus;
120  u32 uninitialized_var(tmp);
121 
122  if (cc->dev->id.revision < 6) {
123  if (bus->bustype == SSB_BUSTYPE_SSB ||
124  bus->bustype == SSB_BUSTYPE_PCMCIA)
125  return SSB_CHIPCO_CLKSRC_XTALOS;
126  if (bus->bustype == SSB_BUSTYPE_PCI) {
127  pci_read_config_dword(bus->host_pci, SSB_GPIO_OUT, &tmp);
128  if (tmp & 0x10)
129  return SSB_CHIPCO_CLKSRC_PCI;
130  return SSB_CHIPCO_CLKSRC_XTALOS;
131  }
132  }
133  if (cc->dev->id.revision < 10) {
134  tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
135  tmp &= 0x7;
136  if (tmp == 0)
137  return SSB_CHIPCO_CLKSRC_LOPWROS;
138  if (tmp == 1)
139  return SSB_CHIPCO_CLKSRC_XTALOS;
140  if (tmp == 2)
141  return SSB_CHIPCO_CLKSRC_PCI;
142  }
143 
144  return SSB_CHIPCO_CLKSRC_XTALOS;
145 }
146 
147 /* Get maximum or minimum (depending on get_max flag) slowclock frequency. */
148 static int chipco_pctl_clockfreqlimit(struct ssb_chipcommon *cc, int get_max)
149 {
150  int uninitialized_var(limit);
151  enum ssb_clksrc clocksrc;
152  int divisor = 1;
153  u32 tmp;
154 
155  clocksrc = chipco_pctl_get_slowclksrc(cc);
156  if (cc->dev->id.revision < 6) {
157  switch (clocksrc) {
158  case SSB_CHIPCO_CLKSRC_PCI:
159  divisor = 64;
160  break;
161  case SSB_CHIPCO_CLKSRC_XTALOS:
162  divisor = 32;
163  break;
164  default:
165  SSB_WARN_ON(1);
166  }
167  } else if (cc->dev->id.revision < 10) {
168  switch (clocksrc) {
169  case SSB_CHIPCO_CLKSRC_LOPWROS:
170  break;
171  case SSB_CHIPCO_CLKSRC_XTALOS:
172  case SSB_CHIPCO_CLKSRC_PCI:
173  tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
174  divisor = (tmp >> 16) + 1;
175  divisor *= 4;
176  break;
177  }
178  } else {
179  tmp = chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL);
180  divisor = (tmp >> 16) + 1;
181  divisor *= 4;
182  }
183 
184  switch (clocksrc) {
185  case SSB_CHIPCO_CLKSRC_LOPWROS:
186  if (get_max)
187  limit = 43000;
188  else
189  limit = 25000;
190  break;
191  case SSB_CHIPCO_CLKSRC_XTALOS:
192  if (get_max)
193  limit = 20200000;
194  else
195  limit = 19800000;
196  break;
197  case SSB_CHIPCO_CLKSRC_PCI:
198  if (get_max)
199  limit = 34000000;
200  else
201  limit = 25000000;
202  break;
203  }
204  limit /= divisor;
205 
206  return limit;
207 }
208 
209 static void chipco_powercontrol_init(struct ssb_chipcommon *cc)
210 {
211  struct ssb_bus *bus = cc->dev->bus;
212 
213  if (bus->chip_id == 0x4321) {
214  if (bus->chip_rev == 0)
215  chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0x3A4);
216  else if (bus->chip_rev == 1)
217  chipco_write32(cc, SSB_CHIPCO_CHIPCTL, 0xA4);
218  }
219 
220  if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
221  return;
222 
223  if (cc->dev->id.revision >= 10) {
224  /* Set Idle Power clock rate to 1Mhz */
225  chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
226  (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
227  0x0000FFFF) | 0x00040000);
228  } else {
229  int maxfreq;
230 
231  maxfreq = chipco_pctl_clockfreqlimit(cc, 1);
232  chipco_write32(cc, SSB_CHIPCO_PLLONDELAY,
233  (maxfreq * 150 + 999999) / 1000000);
234  chipco_write32(cc, SSB_CHIPCO_FREFSELDELAY,
235  (maxfreq * 15 + 999999) / 1000000);
236  }
237 }
238 
239 /* http://bcm-v4.sipsolutions.net/802.11/PmuFastPwrupDelay */
240 static u16 pmu_fast_powerup_delay(struct ssb_chipcommon *cc)
241 {
242  struct ssb_bus *bus = cc->dev->bus;
243 
244  switch (bus->chip_id) {
245  case 0x4312:
246  case 0x4322:
247  case 0x4328:
248  return 7000;
249  case 0x4325:
250  /* TODO: */
251  default:
252  return 15000;
253  }
254 }
255 
256 /* http://bcm-v4.sipsolutions.net/802.11/ClkctlFastPwrupDelay */
257 static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
258 {
259  struct ssb_bus *bus = cc->dev->bus;
260  int minfreq;
261  unsigned int tmp;
262  u32 pll_on_delay;
263 
264  if (bus->bustype != SSB_BUSTYPE_PCI)
265  return;
266 
267  if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
268  cc->fast_pwrup_delay = pmu_fast_powerup_delay(cc);
269  return;
270  }
271 
272  if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
273  return;
274 
275  minfreq = chipco_pctl_clockfreqlimit(cc, 0);
276  pll_on_delay = chipco_read32(cc, SSB_CHIPCO_PLLONDELAY);
277  tmp = (((pll_on_delay + 2) * 1000000) + (minfreq - 1)) / minfreq;
278  SSB_WARN_ON(tmp & ~0xFFFF);
279 
280  cc->fast_pwrup_delay = tmp;
281 }
282 
283 void ssb_chipcommon_init(struct ssb_chipcommon *cc)
284 {
285  if (!cc->dev)
286  return; /* We don't have a ChipCommon */
287  if (cc->dev->id.revision >= 11)
288  cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
289  ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
290 
291  if (cc->dev->id.revision >= 20) {
292  chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
293  chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
294  }
295 
296  ssb_pmu_init(cc);
297  chipco_powercontrol_init(cc);
298  ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
299  calc_fast_powerup_delay(cc);
300 }
301 
302 void ssb_chipco_suspend(struct ssb_chipcommon *cc)
303 {
304  if (!cc->dev)
305  return;
306  ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
307 }
308 
309 void ssb_chipco_resume(struct ssb_chipcommon *cc)
310 {
311  if (!cc->dev)
312  return;
313  chipco_powercontrol_init(cc);
314  ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
315 }
316 
317 /* Get the processor clock */
318 void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc,
319  u32 *plltype, u32 *n, u32 *m)
320 {
321  *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
322  *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
323  switch (*plltype) {
324  case SSB_PLLTYPE_2:
325  case SSB_PLLTYPE_4:
326  case SSB_PLLTYPE_6:
327  case SSB_PLLTYPE_7:
328  *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
329  break;
330  case SSB_PLLTYPE_3:
331  /* 5350 uses m2 to control mips */
332  *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
333  break;
334  default:
335  *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
336  break;
337  }
338 }
339 
340 /* Get the bus clock */
341 void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc,
342  u32 *plltype, u32 *n, u32 *m)
343 {
344  *n = chipco_read32(cc, SSB_CHIPCO_CLOCK_N);
345  *plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
346  switch (*plltype) {
347  case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
348  *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_MIPS);
349  break;
350  case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
351  if (cc->dev->bus->chip_id != 0x5365) {
352  *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_M2);
353  break;
354  }
355  /* Fallthough */
356  default:
357  *m = chipco_read32(cc, SSB_CHIPCO_CLOCK_SB);
358  }
359 }
360 
361 void ssb_chipco_timing_init(struct ssb_chipcommon *cc,
362  unsigned long ns)
363 {
364  struct ssb_device *dev = cc->dev;
365  struct ssb_bus *bus = dev->bus;
366  u32 tmp;
367 
368  /* set register for external IO to control LED. */
369  chipco_write32(cc, SSB_CHIPCO_PROG_CFG, 0x11);
370  tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */
371  tmp |= DIV_ROUND_UP(40, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 40ns */
372  tmp |= DIV_ROUND_UP(240, ns); /* Waitcount-0 = 240ns */
373  chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
374 
375  /* Set timing for the flash */
376  tmp = DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_3_SHIFT; /* Waitcount-3 = 10nS */
377  tmp |= DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_1_SHIFT; /* Waitcount-1 = 10nS */
378  tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120nS */
379  if ((bus->chip_id == 0x5365) ||
380  (dev->id.revision < 9))
381  chipco_write32(cc, SSB_CHIPCO_FLASH_WAITCNT, tmp);
382  if ((bus->chip_id == 0x5365) ||
383  (dev->id.revision < 9) ||
384  ((bus->chip_id == 0x5350) && (bus->chip_rev == 0)))
385  chipco_write32(cc, SSB_CHIPCO_PCMCIA_MEMWAIT, tmp);
386 
387  if (bus->chip_id == 0x5350) {
388  /* Enable EXTIF */
389  tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */
390  tmp |= DIV_ROUND_UP(20, ns) << SSB_PROG_WCNT_2_SHIFT; /* Waitcount-2 = 20ns */
391  tmp |= DIV_ROUND_UP(100, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 100ns */
392  tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120ns */
393  chipco_write32(cc, SSB_CHIPCO_PROG_WAITCNT, tmp); /* 0x01020a0c for a 100Mhz clock */
394  }
395 }
396 
397 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
398 void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
399 {
400  /* instant NMI */
401  chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
402 }
403 
404 void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
405 {
406  chipco_write32_masked(cc, SSB_CHIPCO_IRQMASK, mask, value);
407 }
408 
409 u32 ssb_chipco_irq_status(struct ssb_chipcommon *cc, u32 mask)
410 {
411  return chipco_read32(cc, SSB_CHIPCO_IRQSTAT) & mask;
412 }
413 
414 u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask)
415 {
416  return chipco_read32(cc, SSB_CHIPCO_GPIOIN) & mask;
417 }
418 
419 u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
420 {
421  return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
422 }
423 
424 u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
425 {
426  return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
427 }
428 
429 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
430 {
431  return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
432 }
433 EXPORT_SYMBOL(ssb_chipco_gpio_control);
434 
435 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
436 {
437  return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
438 }
439 
440 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
441 {
442  return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
443 }
444 
445 #ifdef CONFIG_SSB_SERIAL
446 int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
447  struct ssb_serial_port *ports)
448 {
449  struct ssb_bus *bus = cc->dev->bus;
450  int nr_ports = 0;
451  u32 plltype;
452  unsigned int irq;
453  u32 baud_base, div;
454  u32 i, n;
455  unsigned int ccrev = cc->dev->id.revision;
456 
457  plltype = (cc->capabilities & SSB_CHIPCO_CAP_PLLT);
458  irq = ssb_mips_irq(cc->dev);
459 
460  if (plltype == SSB_PLLTYPE_1) {
461  /* PLL clock */
462  baud_base = ssb_calc_clock_rate(plltype,
463  chipco_read32(cc, SSB_CHIPCO_CLOCK_N),
464  chipco_read32(cc, SSB_CHIPCO_CLOCK_M2));
465  div = 1;
466  } else {
467  if (ccrev == 20) {
468  /* BCM5354 uses constant 25MHz clock */
469  baud_base = 25000000;
470  div = 48;
471  /* Set the override bit so we don't divide it */
472  chipco_write32(cc, SSB_CHIPCO_CORECTL,
473  chipco_read32(cc, SSB_CHIPCO_CORECTL)
474  | SSB_CHIPCO_CORECTL_UARTCLK0);
475  } else if ((ccrev >= 11) && (ccrev != 15)) {
476  /* Fixed ALP clock */
477  baud_base = 20000000;
478  if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
479  /* FIXME: baud_base is different for devices with a PMU */
480  SSB_WARN_ON(1);
481  }
482  div = 1;
483  if (ccrev >= 21) {
484  /* Turn off UART clock before switching clocksource. */
485  chipco_write32(cc, SSB_CHIPCO_CORECTL,
486  chipco_read32(cc, SSB_CHIPCO_CORECTL)
487  & ~SSB_CHIPCO_CORECTL_UARTCLKEN);
488  }
489  /* Set the override bit so we don't divide it */
490  chipco_write32(cc, SSB_CHIPCO_CORECTL,
491  chipco_read32(cc, SSB_CHIPCO_CORECTL)
492  | SSB_CHIPCO_CORECTL_UARTCLK0);
493  if (ccrev >= 21) {
494  /* Re-enable the UART clock. */
495  chipco_write32(cc, SSB_CHIPCO_CORECTL,
496  chipco_read32(cc, SSB_CHIPCO_CORECTL)
497  | SSB_CHIPCO_CORECTL_UARTCLKEN);
498  }
499  } else if (ccrev >= 3) {
500  /* Internal backplane clock */
501  baud_base = ssb_clockspeed(bus);
502  div = chipco_read32(cc, SSB_CHIPCO_CLKDIV)
503  & SSB_CHIPCO_CLKDIV_UART;
504  } else {
505  /* Fixed internal backplane clock */
506  baud_base = 88000000;
507  div = 48;
508  }
509 
510  /* Clock source depends on strapping if UartClkOverride is unset */
511  if ((ccrev > 0) &&
512  !(chipco_read32(cc, SSB_CHIPCO_CORECTL) & SSB_CHIPCO_CORECTL_UARTCLK0)) {
513  if ((cc->capabilities & SSB_CHIPCO_CAP_UARTCLK) ==
514  SSB_CHIPCO_CAP_UARTCLK_INT) {
515  /* Internal divided backplane clock */
516  baud_base /= div;
517  } else {
518  /* Assume external clock of 1.8432 MHz */
519  baud_base = 1843200;
520  }
521  }
522  }
523 
524  /* Determine the registers of the UARTs */
525  n = (cc->capabilities & SSB_CHIPCO_CAP_NRUART);
526  for (i = 0; i < n; i++) {
527  void __iomem *cc_mmio;
528  void __iomem *uart_regs;
529 
530  cc_mmio = cc->dev->bus->mmio + (cc->dev->core_index * SSB_CORE_SIZE);
531  uart_regs = cc_mmio + SSB_CHIPCO_UART0_DATA;
532  /* Offset changed at after rev 0 */
533  if (ccrev == 0)
534  uart_regs += (i * 8);
535  else
536  uart_regs += (i * 256);
537 
538  nr_ports++;
539  ports[i].regs = uart_regs;
540  ports[i].irq = irq;
541  ports[i].baud_base = baud_base;
542  ports[i].reg_shift = 0;
543  }
544 
545  return nr_ports;
546 }
547 #endif /* CONFIG_SSB_SERIAL */
Generated on Thu Jan 10 2013 13:25:56 for Linux Kernel by   doxygen 1.8.2