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ssb_driver_chipcommon.h File Reference

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Data Structures

struct  ssb_chipcommon_pmu
 
struct  ssb_chipcommon
 

Macros

#define SSB_CHIPCO_CHIPID   0x0000
 
#define SSB_CHIPCO_IDMASK   0x0000FFFF
 
#define SSB_CHIPCO_REVMASK   0x000F0000
 
#define SSB_CHIPCO_REVSHIFT   16
 
#define SSB_CHIPCO_PACKMASK   0x00F00000
 
#define SSB_CHIPCO_PACKSHIFT   20
 
#define SSB_CHIPCO_NRCORESMASK   0x0F000000
 
#define SSB_CHIPCO_NRCORESSHIFT   24
 
#define SSB_CHIPCO_CAP   0x0004 /* Capabilities */
 
#define SSB_CHIPCO_CAP_NRUART   0x00000003 /* # of UARTs */
 
#define SSB_CHIPCO_CAP_MIPSEB   0x00000004 /* MIPS in BigEndian Mode */
 
#define SSB_CHIPCO_CAP_UARTCLK   0x00000018 /* UART clock select */
 
#define SSB_CHIPCO_CAP_UARTCLK_INT   0x00000008 /* UARTs are driven by internal divided clock */
 
#define SSB_CHIPCO_CAP_UARTGPIO   0x00000020 /* UARTs on GPIO 15-12 */
 
#define SSB_CHIPCO_CAP_EXTBUS   0x000000C0 /* External buses present */
 
#define SSB_CHIPCO_CAP_FLASHT   0x00000700 /* Flash Type */
 
#define SSB_CHIPCO_FLASHT_NONE   0x00000000 /* No flash */
 
#define SSB_CHIPCO_FLASHT_STSER   0x00000100 /* ST serial flash */
 
#define SSB_CHIPCO_FLASHT_ATSER   0x00000200 /* Atmel serial flash */
 
#define SSB_CHIPCO_FLASHT_PARA   0x00000700 /* Parallel flash */
 
#define SSB_CHIPCO_CAP_PLLT   0x00038000 /* PLL Type */
 
#define SSB_PLLTYPE_NONE   0x00000000
 
#define SSB_PLLTYPE_1   0x00010000 /* 48Mhz base, 3 dividers */
 
#define SSB_PLLTYPE_2   0x00020000 /* 48Mhz, 4 dividers */
 
#define SSB_PLLTYPE_3   0x00030000 /* 25Mhz, 2 dividers */
 
#define SSB_PLLTYPE_4   0x00008000 /* 48Mhz, 4 dividers */
 
#define SSB_PLLTYPE_5   0x00018000 /* 25Mhz, 4 dividers */
 
#define SSB_PLLTYPE_6   0x00028000 /* 100/200 or 120/240 only */
 
#define SSB_PLLTYPE_7   0x00038000 /* 25Mhz, 4 dividers */
 
#define SSB_CHIPCO_CAP_PCTL   0x00040000 /* Power Control */
 
#define SSB_CHIPCO_CAP_OTPS   0x00380000 /* OTP size */
 
#define SSB_CHIPCO_CAP_OTPS_SHIFT   19
 
#define SSB_CHIPCO_CAP_OTPS_BASE   5
 
#define SSB_CHIPCO_CAP_JTAGM   0x00400000 /* JTAG master present */
 
#define SSB_CHIPCO_CAP_BROM   0x00800000 /* Internal boot ROM active */
 
#define SSB_CHIPCO_CAP_64BIT   0x08000000 /* 64-bit Backplane */
 
#define SSB_CHIPCO_CAP_PMU   0x10000000 /* PMU available (rev >= 20) */
 
#define SSB_CHIPCO_CAP_ECI   0x20000000 /* ECI available (rev >= 20) */
 
#define SSB_CHIPCO_CAP_SPROM   0x40000000 /* SPROM present */
 
#define SSB_CHIPCO_CORECTL   0x0008
 
#define SSB_CHIPCO_CORECTL_UARTCLK0   0x00000001 /* Drive UART with internal clock */
 
#define SSB_CHIPCO_CORECTL_SE   0x00000002 /* sync clk out enable (corerev >= 3) */
 
#define SSB_CHIPCO_CORECTL_UARTCLKEN   0x00000008 /* UART clock enable (rev >= 21) */
 
#define SSB_CHIPCO_BIST   0x000C
 
#define SSB_CHIPCO_OTPS   0x0010 /* OTP status */
 
#define SSB_CHIPCO_OTPS_PROGFAIL   0x80000000
 
#define SSB_CHIPCO_OTPS_PROTECT   0x00000007
 
#define SSB_CHIPCO_OTPS_HW_PROTECT   0x00000001
 
#define SSB_CHIPCO_OTPS_SW_PROTECT   0x00000002
 
#define SSB_CHIPCO_OTPS_CID_PROTECT   0x00000004
 
#define SSB_CHIPCO_OTPC   0x0014 /* OTP control */
 
#define SSB_CHIPCO_OTPC_RECWAIT   0xFF000000
 
#define SSB_CHIPCO_OTPC_PROGWAIT   0x00FFFF00
 
#define SSB_CHIPCO_OTPC_PRW_SHIFT   8
 
#define SSB_CHIPCO_OTPC_MAXFAIL   0x00000038
 
#define SSB_CHIPCO_OTPC_VSEL   0x00000006
 
#define SSB_CHIPCO_OTPC_SELVL   0x00000001
 
#define SSB_CHIPCO_OTPP   0x0018 /* OTP prog */
 
#define SSB_CHIPCO_OTPP_COL   0x000000FF
 
#define SSB_CHIPCO_OTPP_ROW   0x0000FF00
 
#define SSB_CHIPCO_OTPP_ROW_SHIFT   8
 
#define SSB_CHIPCO_OTPP_READERR   0x10000000
 
#define SSB_CHIPCO_OTPP_VALUE   0x20000000
 
#define SSB_CHIPCO_OTPP_READ   0x40000000
 
#define SSB_CHIPCO_OTPP_START   0x80000000
 
#define SSB_CHIPCO_OTPP_BUSY   0x80000000
 
#define SSB_CHIPCO_IRQSTAT   0x0020
 
#define SSB_CHIPCO_IRQMASK   0x0024
 
#define SSB_CHIPCO_IRQ_GPIO   0x00000001 /* gpio intr */
 
#define SSB_CHIPCO_IRQ_EXT   0x00000002 /* ro: ext intr pin (corerev >= 3) */
 
#define SSB_CHIPCO_IRQ_WDRESET   0x80000000 /* watchdog reset occurred */
 
#define SSB_CHIPCO_CHIPCTL   0x0028 /* Rev >= 11 only */
 
#define SSB_CHIPCO_CHIPSTAT   0x002C /* Rev >= 11 only */
 
#define SSB_CHIPCO_JCMD   0x0030 /* Rev >= 10 only */
 
#define SSB_CHIPCO_JCMD_START   0x80000000
 
#define SSB_CHIPCO_JCMD_BUSY   0x80000000
 
#define SSB_CHIPCO_JCMD_PAUSE   0x40000000
 
#define SSB_CHIPCO_JCMD0_ACC_MASK   0x0000F000
 
#define SSB_CHIPCO_JCMD0_ACC_IRDR   0x00000000
 
#define SSB_CHIPCO_JCMD0_ACC_DR   0x00001000
 
#define SSB_CHIPCO_JCMD0_ACC_IR   0x00002000
 
#define SSB_CHIPCO_JCMD0_ACC_RESET   0x00003000
 
#define SSB_CHIPCO_JCMD0_ACC_IRPDR   0x00004000
 
#define SSB_CHIPCO_JCMD0_ACC_PDR   0x00005000
 
#define SSB_CHIPCO_JCMD0_IRW_MASK   0x00000F00
 
#define SSB_CHIPCO_JCMD_ACC_MASK   0x000F0000 /* Changes for corerev 11 */
 
#define SSB_CHIPCO_JCMD_ACC_IRDR   0x00000000
 
#define SSB_CHIPCO_JCMD_ACC_DR   0x00010000
 
#define SSB_CHIPCO_JCMD_ACC_IR   0x00020000
 
#define SSB_CHIPCO_JCMD_ACC_RESET   0x00030000
 
#define SSB_CHIPCO_JCMD_ACC_IRPDR   0x00040000
 
#define SSB_CHIPCO_JCMD_ACC_PDR   0x00050000
 
#define SSB_CHIPCO_JCMD_IRW_MASK   0x00001F00
 
#define SSB_CHIPCO_JCMD_IRW_SHIFT   8
 
#define SSB_CHIPCO_JCMD_DRW_MASK   0x0000003F
 
#define SSB_CHIPCO_JIR   0x0034 /* Rev >= 10 only */
 
#define SSB_CHIPCO_JDR   0x0038 /* Rev >= 10 only */
 
#define SSB_CHIPCO_JCTL   0x003C /* Rev >= 10 only */
 
#define SSB_CHIPCO_JCTL_FORCE_CLK   4 /* Force clock */
 
#define SSB_CHIPCO_JCTL_EXT_EN   2 /* Enable external targets */
 
#define SSB_CHIPCO_JCTL_EN   1 /* Enable Jtag master */
 
#define SSB_CHIPCO_FLASHCTL   0x0040
 
#define SSB_CHIPCO_FLASHCTL_START   0x80000000
 
#define SSB_CHIPCO_FLASHCTL_BUSY   SSB_CHIPCO_FLASHCTL_START
 
#define SSB_CHIPCO_FLASHADDR   0x0044
 
#define SSB_CHIPCO_FLASHDATA   0x0048
 
#define SSB_CHIPCO_BCAST_ADDR   0x0050
 
#define SSB_CHIPCO_BCAST_DATA   0x0054
 
#define SSB_CHIPCO_GPIOPULLUP   0x0058 /* Rev >= 20 only */
 
#define SSB_CHIPCO_GPIOPULLDOWN   0x005C /* Rev >= 20 only */
 
#define SSB_CHIPCO_GPIOIN   0x0060
 
#define SSB_CHIPCO_GPIOOUT   0x0064
 
#define SSB_CHIPCO_GPIOOUTEN   0x0068
 
#define SSB_CHIPCO_GPIOCTL   0x006C
 
#define SSB_CHIPCO_GPIOPOL   0x0070
 
#define SSB_CHIPCO_GPIOIRQ   0x0074
 
#define SSB_CHIPCO_WATCHDOG   0x0080
 
#define SSB_CHIPCO_GPIOTIMER   0x0088 /* LED powersave (corerev >= 16) */
 
#define SSB_CHIPCO_GPIOTIMER_OFFTIME   0x0000FFFF
 
#define SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT   0
 
#define SSB_CHIPCO_GPIOTIMER_ONTIME   0xFFFF0000
 
#define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT   16
 
#define SSB_CHIPCO_GPIOTOUTM   0x008C /* LED powersave (corerev >= 16) */
 
#define SSB_CHIPCO_CLOCK_N   0x0090
 
#define SSB_CHIPCO_CLOCK_SB   0x0094
 
#define SSB_CHIPCO_CLOCK_PCI   0x0098
 
#define SSB_CHIPCO_CLOCK_M2   0x009C
 
#define SSB_CHIPCO_CLOCK_MIPS   0x00A0
 
#define SSB_CHIPCO_CLKDIV   0x00A4 /* Rev >= 3 only */
 
#define SSB_CHIPCO_CLKDIV_SFLASH   0x0F000000
 
#define SSB_CHIPCO_CLKDIV_SFLASH_SHIFT   24
 
#define SSB_CHIPCO_CLKDIV_OTP   0x000F0000
 
#define SSB_CHIPCO_CLKDIV_OTP_SHIFT   16
 
#define SSB_CHIPCO_CLKDIV_JTAG   0x00000F00
 
#define SSB_CHIPCO_CLKDIV_JTAG_SHIFT   8
 
#define SSB_CHIPCO_CLKDIV_UART   0x000000FF
 
#define SSB_CHIPCO_PLLONDELAY   0x00B0 /* Rev >= 4 only */
 
#define SSB_CHIPCO_FREFSELDELAY   0x00B4 /* Rev >= 4 only */
 
#define SSB_CHIPCO_SLOWCLKCTL   0x00B8 /* 6 <= Rev <= 9 only */
 
#define SSB_CHIPCO_SLOWCLKCTL_SRC   0x00000007 /* slow clock source mask */
 
#define SSB_CHIPCO_SLOWCLKCTL_SRC_LPO   0x00000000 /* source of slow clock is LPO */
 
#define SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL   0x00000001 /* source of slow clock is crystal */
 
#define SSB_CHIPCO_SLOECLKCTL_SRC_PCI   0x00000002 /* source of slow clock is PCI */
 
#define SSB_CHIPCO_SLOWCLKCTL_LPOFREQ   0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
 
#define SSB_CHIPCO_SLOWCLKCTL_LPOPD   0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
 
#define SSB_CHIPCO_SLOWCLKCTL_FSLOW   0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
 
#define SSB_CHIPCO_SLOWCLKCTL_IPLL   0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
 
#define SSB_CHIPCO_SLOWCLKCTL_ENXTAL   0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
 
#define SSB_CHIPCO_SLOWCLKCTL_XTALPU   0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
 
#define SSB_CHIPCO_SLOWCLKCTL_CLKDIV   0xFFFF0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
 
#define SSB_CHIPCO_SLOWCLKCTL_CLKDIV_SHIFT   16
 
#define SSB_CHIPCO_SYSCLKCTL   0x00C0 /* Rev >= 3 only */
 
#define SSB_CHIPCO_SYSCLKCTL_IDLPEN   0x00000001 /* ILPen: Enable Idle Low Power */
 
#define SSB_CHIPCO_SYSCLKCTL_ALPEN   0x00000002 /* ALPen: Enable Active Low Power */
 
#define SSB_CHIPCO_SYSCLKCTL_PLLEN   0x00000004 /* ForcePLLOn */
 
#define SSB_CHIPCO_SYSCLKCTL_FORCEALP   0x00000008 /* Force ALP (or HT if ALPen is not set */
 
#define SSB_CHIPCO_SYSCLKCTL_FORCEHT   0x00000010 /* Force HT */
 
#define SSB_CHIPCO_SYSCLKCTL_CLKDIV   0xFFFF0000 /* ClkDiv (ILP = 1/(4+divisor)) */
 
#define SSB_CHIPCO_SYSCLKCTL_CLKDIV_SHIFT   16
 
#define SSB_CHIPCO_CLKSTSTR   0x00C4 /* Rev >= 3 only */
 
#define SSB_CHIPCO_PCMCIA_CFG   0x0100
 
#define SSB_CHIPCO_PCMCIA_MEMWAIT   0x0104
 
#define SSB_CHIPCO_PCMCIA_ATTRWAIT   0x0108
 
#define SSB_CHIPCO_PCMCIA_IOWAIT   0x010C
 
#define SSB_CHIPCO_IDE_CFG   0x0110
 
#define SSB_CHIPCO_IDE_MEMWAIT   0x0114
 
#define SSB_CHIPCO_IDE_ATTRWAIT   0x0118
 
#define SSB_CHIPCO_IDE_IOWAIT   0x011C
 
#define SSB_CHIPCO_PROG_CFG   0x0120
 
#define SSB_CHIPCO_PROG_WAITCNT   0x0124
 
#define SSB_CHIPCO_FLASH_CFG   0x0128
 
#define SSB_CHIPCO_FLASH_WAITCNT   0x012C
 
#define SSB_CHIPCO_CLKCTLST   0x01E0 /* Clock control and status (rev >= 20) */
 
#define SSB_CHIPCO_CLKCTLST_FORCEALP   0x00000001 /* Force ALP request */
 
#define SSB_CHIPCO_CLKCTLST_FORCEHT   0x00000002 /* Force HT request */
 
#define SSB_CHIPCO_CLKCTLST_FORCEILP   0x00000004 /* Force ILP request */
 
#define SSB_CHIPCO_CLKCTLST_HAVEALPREQ   0x00000008 /* ALP available request */
 
#define SSB_CHIPCO_CLKCTLST_HAVEHTREQ   0x00000010 /* HT available request */
 
#define SSB_CHIPCO_CLKCTLST_HWCROFF   0x00000020 /* Force HW clock request off */
 
#define SSB_CHIPCO_CLKCTLST_HAVEALP   0x00010000 /* ALP available */
 
#define SSB_CHIPCO_CLKCTLST_HAVEHT   0x00020000 /* HT available */
 
#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT   0x00010000 /* 4328a0 has reversed bits */
 
#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP   0x00020000 /* 4328a0 has reversed bits */
 
#define SSB_CHIPCO_HW_WORKAROUND   0x01E4 /* Hardware workaround (rev >= 20) */
 
#define SSB_CHIPCO_UART0_DATA   0x0300
 
#define SSB_CHIPCO_UART0_IMR   0x0304
 
#define SSB_CHIPCO_UART0_FCR   0x0308
 
#define SSB_CHIPCO_UART0_LCR   0x030C
 
#define SSB_CHIPCO_UART0_MCR   0x0310
 
#define SSB_CHIPCO_UART0_LSR   0x0314
 
#define SSB_CHIPCO_UART0_MSR   0x0318
 
#define SSB_CHIPCO_UART0_SCRATCH   0x031C
 
#define SSB_CHIPCO_UART1_DATA   0x0400
 
#define SSB_CHIPCO_UART1_IMR   0x0404
 
#define SSB_CHIPCO_UART1_FCR   0x0408
 
#define SSB_CHIPCO_UART1_LCR   0x040C
 
#define SSB_CHIPCO_UART1_MCR   0x0410
 
#define SSB_CHIPCO_UART1_LSR   0x0414
 
#define SSB_CHIPCO_UART1_MSR   0x0418
 
#define SSB_CHIPCO_UART1_SCRATCH   0x041C
 
#define SSB_CHIPCO_PMU_CTL   0x0600 /* PMU control */
 
#define SSB_CHIPCO_PMU_CTL_ILP_DIV   0xFFFF0000 /* ILP div mask */
 
#define SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT   16
 
#define SSB_CHIPCO_PMU_CTL_NOILPONW   0x00000200 /* No ILP on wait */
 
#define SSB_CHIPCO_PMU_CTL_HTREQEN   0x00000100 /* HT req enable */
 
#define SSB_CHIPCO_PMU_CTL_ALPREQEN   0x00000080 /* ALP req enable */
 
#define SSB_CHIPCO_PMU_CTL_XTALFREQ   0x0000007C /* Crystal freq */
 
#define SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT   2
 
#define SSB_CHIPCO_PMU_CTL_ILPDIVEN   0x00000002 /* ILP div enable */
 
#define SSB_CHIPCO_PMU_CTL_LPOSEL   0x00000001 /* LPO sel */
 
#define SSB_CHIPCO_PMU_CAP   0x0604 /* PMU capabilities */
 
#define SSB_CHIPCO_PMU_CAP_REVISION   0x000000FF /* Revision mask */
 
#define SSB_CHIPCO_PMU_STAT   0x0608 /* PMU status */
 
#define SSB_CHIPCO_PMU_STAT_INTPEND   0x00000040 /* Interrupt pending */
 
#define SSB_CHIPCO_PMU_STAT_SBCLKST   0x00000030 /* Backplane clock status? */
 
#define SSB_CHIPCO_PMU_STAT_HAVEALP   0x00000008 /* ALP available */
 
#define SSB_CHIPCO_PMU_STAT_HAVEHT   0x00000004 /* HT available */
 
#define SSB_CHIPCO_PMU_STAT_RESINIT   0x00000003 /* Res init */
 
#define SSB_CHIPCO_PMU_RES_STAT   0x060C /* PMU res status */
 
#define SSB_CHIPCO_PMU_RES_PEND   0x0610 /* PMU res pending */
 
#define SSB_CHIPCO_PMU_TIMER   0x0614 /* PMU timer */
 
#define SSB_CHIPCO_PMU_MINRES_MSK   0x0618 /* PMU min res mask */
 
#define SSB_CHIPCO_PMU_MAXRES_MSK   0x061C /* PMU max res mask */
 
#define SSB_CHIPCO_PMU_RES_TABSEL   0x0620 /* PMU res table sel */
 
#define SSB_CHIPCO_PMU_RES_DEPMSK   0x0624 /* PMU res dep mask */
 
#define SSB_CHIPCO_PMU_RES_UPDNTM   0x0628 /* PMU res updown timer */
 
#define SSB_CHIPCO_PMU_RES_TIMER   0x062C /* PMU res timer */
 
#define SSB_CHIPCO_PMU_CLKSTRETCH   0x0630 /* PMU clockstretch */
 
#define SSB_CHIPCO_PMU_WATCHDOG   0x0634 /* PMU watchdog */
 
#define SSB_CHIPCO_PMU_RES_REQTS   0x0640 /* PMU res req timer sel */
 
#define SSB_CHIPCO_PMU_RES_REQT   0x0644 /* PMU res req timer */
 
#define SSB_CHIPCO_PMU_RES_REQM   0x0648 /* PMU res req mask */
 
#define SSB_CHIPCO_CHIPCTL_ADDR   0x0650
 
#define SSB_CHIPCO_CHIPCTL_DATA   0x0654
 
#define SSB_CHIPCO_REGCTL_ADDR   0x0658
 
#define SSB_CHIPCO_REGCTL_DATA   0x065C
 
#define SSB_CHIPCO_PLLCTL_ADDR   0x0660
 
#define SSB_CHIPCO_PLLCTL_DATA   0x0664
 
#define SSB_PMU0_PLLCTL0   0
 
#define SSB_PMU0_PLLCTL0_PDIV_MSK   0x00000001
 
#define SSB_PMU0_PLLCTL0_PDIV_FREQ   25000 /* kHz */
 
#define SSB_PMU0_PLLCTL1   1
 
#define SSB_PMU0_PLLCTL1_WILD_IMSK   0xF0000000 /* Wild int mask (low nibble) */
 
#define SSB_PMU0_PLLCTL1_WILD_IMSK_SHIFT   28
 
#define SSB_PMU0_PLLCTL1_WILD_FMSK   0x0FFFFF00 /* Wild frac mask */
 
#define SSB_PMU0_PLLCTL1_WILD_FMSK_SHIFT   8
 
#define SSB_PMU0_PLLCTL1_STOPMOD   0x00000040 /* Stop mod */
 
#define SSB_PMU0_PLLCTL2   2
 
#define SSB_PMU0_PLLCTL2_WILD_IMSKHI   0x0000000F /* Wild int mask (high nibble) */
 
#define SSB_PMU0_PLLCTL2_WILD_IMSKHI_SHIFT   0
 
#define SSB_PMU1_PLLCTL0   0
 
#define SSB_PMU1_PLLCTL0_P1DIV   0x00F00000 /* P1 div */
 
#define SSB_PMU1_PLLCTL0_P1DIV_SHIFT   20
 
#define SSB_PMU1_PLLCTL0_P2DIV   0x0F000000 /* P2 div */
 
#define SSB_PMU1_PLLCTL0_P2DIV_SHIFT   24
 
#define SSB_PMU1_PLLCTL1   1
 
#define SSB_PMU1_PLLCTL1_M1DIV   0x000000FF /* M1 div */
 
#define SSB_PMU1_PLLCTL1_M1DIV_SHIFT   0
 
#define SSB_PMU1_PLLCTL1_M2DIV   0x0000FF00 /* M2 div */
 
#define SSB_PMU1_PLLCTL1_M2DIV_SHIFT   8
 
#define SSB_PMU1_PLLCTL1_M3DIV   0x00FF0000 /* M3 div */
 
#define SSB_PMU1_PLLCTL1_M3DIV_SHIFT   16
 
#define SSB_PMU1_PLLCTL1_M4DIV   0xFF000000 /* M4 div */
 
#define SSB_PMU1_PLLCTL1_M4DIV_SHIFT   24
 
#define SSB_PMU1_PLLCTL2   2
 
#define SSB_PMU1_PLLCTL2_M5DIV   0x000000FF /* M5 div */
 
#define SSB_PMU1_PLLCTL2_M5DIV_SHIFT   0
 
#define SSB_PMU1_PLLCTL2_M6DIV   0x0000FF00 /* M6 div */
 
#define SSB_PMU1_PLLCTL2_M6DIV_SHIFT   8
 
#define SSB_PMU1_PLLCTL2_NDIVMODE   0x000E0000 /* NDIV mode */
 
#define SSB_PMU1_PLLCTL2_NDIVMODE_SHIFT   17
 
#define SSB_PMU1_PLLCTL2_NDIVINT   0x1FF00000 /* NDIV int */
 
#define SSB_PMU1_PLLCTL2_NDIVINT_SHIFT   20
 
#define SSB_PMU1_PLLCTL3   3
 
#define SSB_PMU1_PLLCTL3_NDIVFRAC   0x00FFFFFF /* NDIV frac */
 
#define SSB_PMU1_PLLCTL3_NDIVFRAC_SHIFT   0
 
#define SSB_PMU1_PLLCTL4   4
 
#define SSB_PMU1_PLLCTL5   5
 
#define SSB_PMU1_PLLCTL5_CLKDRV   0xFFFFFF00 /* clk drv */
 
#define SSB_PMU1_PLLCTL5_CLKDRV_SHIFT   8
 
#define SSB_PMURES_4312_SWITCHER_BURST   0
 
#define SSB_PMURES_4312_SWITCHER_PWM   1
 
#define SSB_PMURES_4312_PA_REF_LDO   2
 
#define SSB_PMURES_4312_CORE_LDO_BURST   3
 
#define SSB_PMURES_4312_CORE_LDO_PWM   4
 
#define SSB_PMURES_4312_RADIO_LDO   5
 
#define SSB_PMURES_4312_ILP_REQUEST   6
 
#define SSB_PMURES_4312_BG_FILTBYP   7
 
#define SSB_PMURES_4312_TX_FILTBYP   8
 
#define SSB_PMURES_4312_RX_FILTBYP   9
 
#define SSB_PMURES_4312_XTAL_PU   10
 
#define SSB_PMURES_4312_ALP_AVAIL   11
 
#define SSB_PMURES_4312_BB_PLL_FILTBYP   12
 
#define SSB_PMURES_4312_RF_PLL_FILTBYP   13
 
#define SSB_PMURES_4312_HT_AVAIL   14
 
#define SSB_PMURES_4325_BUCK_BOOST_BURST   0
 
#define SSB_PMURES_4325_CBUCK_BURST   1
 
#define SSB_PMURES_4325_CBUCK_PWM   2
 
#define SSB_PMURES_4325_CLDO_CBUCK_BURST   3
 
#define SSB_PMURES_4325_CLDO_CBUCK_PWM   4
 
#define SSB_PMURES_4325_BUCK_BOOST_PWM   5
 
#define SSB_PMURES_4325_ILP_REQUEST   6
 
#define SSB_PMURES_4325_ABUCK_BURST   7
 
#define SSB_PMURES_4325_ABUCK_PWM   8
 
#define SSB_PMURES_4325_LNLDO1_PU   9
 
#define SSB_PMURES_4325_LNLDO2_PU   10
 
#define SSB_PMURES_4325_LNLDO3_PU   11
 
#define SSB_PMURES_4325_LNLDO4_PU   12
 
#define SSB_PMURES_4325_XTAL_PU   13
 
#define SSB_PMURES_4325_ALP_AVAIL   14
 
#define SSB_PMURES_4325_RX_PWRSW_PU   15
 
#define SSB_PMURES_4325_TX_PWRSW_PU   16
 
#define SSB_PMURES_4325_RFPLL_PWRSW_PU   17
 
#define SSB_PMURES_4325_LOGEN_PWRSW_PU   18
 
#define SSB_PMURES_4325_AFE_PWRSW_PU   19
 
#define SSB_PMURES_4325_BBPLL_PWRSW_PU   20
 
#define SSB_PMURES_4325_HT_AVAIL   21
 
#define SSB_PMURES_4328_EXT_SWITCHER_PWM   0
 
#define SSB_PMURES_4328_BB_SWITCHER_PWM   1
 
#define SSB_PMURES_4328_BB_SWITCHER_BURST   2
 
#define SSB_PMURES_4328_BB_EXT_SWITCHER_BURST   3
 
#define SSB_PMURES_4328_ILP_REQUEST   4
 
#define SSB_PMURES_4328_RADIO_SWITCHER_PWM   5
 
#define SSB_PMURES_4328_RADIO_SWITCHER_BURST   6
 
#define SSB_PMURES_4328_ROM_SWITCH   7
 
#define SSB_PMURES_4328_PA_REF_LDO   8
 
#define SSB_PMURES_4328_RADIO_LDO   9
 
#define SSB_PMURES_4328_AFE_LDO   10
 
#define SSB_PMURES_4328_PLL_LDO   11
 
#define SSB_PMURES_4328_BG_FILTBYP   12
 
#define SSB_PMURES_4328_TX_FILTBYP   13
 
#define SSB_PMURES_4328_RX_FILTBYP   14
 
#define SSB_PMURES_4328_XTAL_PU   15
 
#define SSB_PMURES_4328_XTAL_EN   16
 
#define SSB_PMURES_4328_BB_PLL_FILTBYP   17
 
#define SSB_PMURES_4328_RF_PLL_FILTBYP   18
 
#define SSB_PMURES_4328_BB_PLL_PU   19
 
#define SSB_PMURES_5354_EXT_SWITCHER_PWM   0
 
#define SSB_PMURES_5354_BB_SWITCHER_PWM   1
 
#define SSB_PMURES_5354_BB_SWITCHER_BURST   2
 
#define SSB_PMURES_5354_BB_EXT_SWITCHER_BURST   3
 
#define SSB_PMURES_5354_ILP_REQUEST   4
 
#define SSB_PMURES_5354_RADIO_SWITCHER_PWM   5
 
#define SSB_PMURES_5354_RADIO_SWITCHER_BURST   6
 
#define SSB_PMURES_5354_ROM_SWITCH   7
 
#define SSB_PMURES_5354_PA_REF_LDO   8
 
#define SSB_PMURES_5354_RADIO_LDO   9
 
#define SSB_PMURES_5354_AFE_LDO   10
 
#define SSB_PMURES_5354_PLL_LDO   11
 
#define SSB_PMURES_5354_BG_FILTBYP   12
 
#define SSB_PMURES_5354_TX_FILTBYP   13
 
#define SSB_PMURES_5354_RX_FILTBYP   14
 
#define SSB_PMURES_5354_XTAL_PU   15
 
#define SSB_PMURES_5354_XTAL_EN   16
 
#define SSB_PMURES_5354_BB_PLL_FILTBYP   17
 
#define SSB_PMURES_5354_RF_PLL_FILTBYP   18
 
#define SSB_PMURES_5354_BB_PLL_PU   19
 
#define SSB_CHIPCO_CHST_4322_SPROM_EXISTS   0x00000040 /* SPROM present */
 
#define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL   0x00000003
 
#define SSB_CHIPCO_CHST_4325_DEFCIS_SEL   0 /* OTP is powered up, use def. CIS, no SPROM */
 
#define SSB_CHIPCO_CHST_4325_SPROM_SEL   1 /* OTP is powered up, SPROM is present */
 
#define SSB_CHIPCO_CHST_4325_OTP_SEL   2 /* OTP is powered up, no SPROM */
 
#define SSB_CHIPCO_CHST_4325_OTP_PWRDN   3 /* OTP is powered down, SPROM is present */
 
#define SSB_CHIPCO_CHST_4325_SDIO_USB_MODE   0x00000004
 
#define SSB_CHIPCO_CHST_4325_SDIO_USB_MODE_SHIFT   2
 
#define SSB_CHIPCO_CHST_4325_RCAL_VALID   0x00000008
 
#define SSB_CHIPCO_CHST_4325_RCAL_VALID_SHIFT   3
 
#define SSB_CHIPCO_CHST_4325_RCAL_VALUE   0x000001F0
 
#define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT   4
 
#define SSB_CHIPCO_CHST_4325_PMUTOP_2B   0x00000200 /* 1 for 2b, 0 for to 2a */
 
#define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status)
 
#define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status)   (status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS)
 
#define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status)
 
#define SSB_CHIPCO_CLK_N1   0x0000003F /* n1 control */
 
#define SSB_CHIPCO_CLK_N2   0x00003F00 /* n2 control */
 
#define SSB_CHIPCO_CLK_N2_SHIFT   8
 
#define SSB_CHIPCO_CLK_PLLC   0x000F0000 /* pll control */
 
#define SSB_CHIPCO_CLK_PLLC_SHIFT   16
 
#define SSB_CHIPCO_CLK_M1   0x0000003F /* m1 control */
 
#define SSB_CHIPCO_CLK_M2   0x00003F00 /* m2 control */
 
#define SSB_CHIPCO_CLK_M2_SHIFT   8
 
#define SSB_CHIPCO_CLK_M3   0x003F0000 /* m3 control */
 
#define SSB_CHIPCO_CLK_M3_SHIFT   16
 
#define SSB_CHIPCO_CLK_MC   0x1F000000 /* mux control */
 
#define SSB_CHIPCO_CLK_MC_SHIFT   24
 
#define SSB_CHIPCO_CLK_F6_2   0x02 /* A factor of 2 in */
 
#define SSB_CHIPCO_CLK_F6_3   0x03 /* 6-bit fields like */
 
#define SSB_CHIPCO_CLK_F6_4   0x05 /* N1, M1 or M3 */
 
#define SSB_CHIPCO_CLK_F6_5   0x09
 
#define SSB_CHIPCO_CLK_F6_6   0x11
 
#define SSB_CHIPCO_CLK_F6_7   0x21
 
#define SSB_CHIPCO_CLK_F5_BIAS   5 /* 5-bit fields get this added */
 
#define SSB_CHIPCO_CLK_MC_BYPASS   0x08
 
#define SSB_CHIPCO_CLK_MC_M1   0x04
 
#define SSB_CHIPCO_CLK_MC_M1M2   0x02
 
#define SSB_CHIPCO_CLK_MC_M1M2M3   0x01
 
#define SSB_CHIPCO_CLK_MC_M1M3   0x11
 
#define SSB_CHIPCO_CLK_T2_BIAS   2 /* n1, n2, m1 & m3 bias */
 
#define SSB_CHIPCO_CLK_T2M2_BIAS   3 /* m2 bias */
 
#define SSB_CHIPCO_CLK_T2MC_M1BYP   1
 
#define SSB_CHIPCO_CLK_T2MC_M2BYP   2
 
#define SSB_CHIPCO_CLK_T2MC_M3BYP   4
 
#define SSB_CHIPCO_CLK_T6_MMASK   1 /* bits of interest in m */
 
#define SSB_CHIPCO_CLK_T6_M0   120000000 /* sb clock for m = 0 */
 
#define SSB_CHIPCO_CLK_T6_M1   100000000 /* sb clock for m = 1 */
 
#define SSB_CHIPCO_CLK_SB2MIPS_T6(sb)   (2 * (sb))
 
#define SSB_CHIPCO_CLK_BASE1   24000000 /* Half the clock freq */
 
#define SSB_CHIPCO_CLK_BASE2   12500000 /* Alternate crystal on some PLL's */
 
#define SSB_CHIPCO_CLK_5350_N   0x0311
 
#define SSB_CHIPCO_CLK_5350_M   0x04020009
 
#define SSB_CHIPCO_CFG_EN   0x0001 /* Enable */
 
#define SSB_CHIPCO_CFG_EXTM   0x000E /* Extif Mode */
 
#define SSB_CHIPCO_CFG_EXTM_ASYNC   0x0002 /* Async/Parallel flash */
 
#define SSB_CHIPCO_CFG_EXTM_SYNC   0x0004 /* Synchronous */
 
#define SSB_CHIPCO_CFG_EXTM_PCMCIA   0x0008 /* PCMCIA */
 
#define SSB_CHIPCO_CFG_EXTM_IDE   0x000A /* IDE */
 
#define SSB_CHIPCO_CFG_DS16   0x0010 /* Data size, 0=8bit, 1=16bit */
 
#define SSB_CHIPCO_CFG_CLKDIV   0x0060 /* Sync: Clock divisor */
 
#define SSB_CHIPCO_CFG_CLKEN   0x0080 /* Sync: Clock enable */
 
#define SSB_CHIPCO_CFG_BSTRO   0x0100 /* Sync: Size/Bytestrobe */
 
#define SSB_CHIPCO_FLASHCTL_ST_WREN   0x0006 /* Write Enable */
 
#define SSB_CHIPCO_FLASHCTL_ST_WRDIS   0x0004 /* Write Disable */
 
#define SSB_CHIPCO_FLASHCTL_ST_RDSR   0x0105 /* Read Status Register */
 
#define SSB_CHIPCO_FLASHCTL_ST_WRSR   0x0101 /* Write Status Register */
 
#define SSB_CHIPCO_FLASHCTL_ST_READ   0x0303 /* Read Data Bytes */
 
#define SSB_CHIPCO_FLASHCTL_ST_PP   0x0302 /* Page Program */
 
#define SSB_CHIPCO_FLASHCTL_ST_SE   0x02D8 /* Sector Erase */
 
#define SSB_CHIPCO_FLASHCTL_ST_BE   0x00C7 /* Bulk Erase */
 
#define SSB_CHIPCO_FLASHCTL_ST_DP   0x00B9 /* Deep Power-down */
 
#define SSB_CHIPCO_FLASHCTL_ST_RES   0x03AB /* Read Electronic Signature */
 
#define SSB_CHIPCO_FLASHCTL_ST_CSA   0x1000 /* Keep chip select asserted */
 
#define SSB_CHIPCO_FLASHCTL_ST_SSE   0x0220 /* Sub-sector Erase */
 
#define SSB_CHIPCO_FLASHSTA_ST_WIP   0x01 /* Write In Progress */
 
#define SSB_CHIPCO_FLASHSTA_ST_WEL   0x02 /* Write Enable Latch */
 
#define SSB_CHIPCO_FLASHSTA_ST_BP   0x1C /* Block Protect */
 
#define SSB_CHIPCO_FLASHSTA_ST_BP_SHIFT   2
 
#define SSB_CHIPCO_FLASHSTA_ST_SRWD   0x80 /* Status Register Write Disable */
 
#define SSB_CHIPCO_FLASHCTL_AT_READ   0x07E8
 
#define SSB_CHIPCO_FLASHCTL_AT_PAGE_READ   0x07D2
 
#define SSB_CHIPCO_FLASHCTL_AT_BUF1_READ   /* FIXME */
 
#define SSB_CHIPCO_FLASHCTL_AT_BUF2_READ   /* FIXME */
 
#define SSB_CHIPCO_FLASHCTL_AT_STATUS   0x01D7
 
#define SSB_CHIPCO_FLASHCTL_AT_BUF1_WRITE   0x0384
 
#define SSB_CHIPCO_FLASHCTL_AT_BUF2_WRITE   0x0387
 
#define SSB_CHIPCO_FLASHCTL_AT_BUF1_ERASE_PRGM   0x0283 /* Erase program */
 
#define SSB_CHIPCO_FLASHCTL_AT_BUF2_ERASE_PRGM   0x0286 /* Erase program */
 
#define SSB_CHIPCO_FLASHCTL_AT_BUF1_PROGRAM   0x0288
 
#define SSB_CHIPCO_FLASHCTL_AT_BUF2_PROGRAM   0x0289
 
#define SSB_CHIPCO_FLASHCTL_AT_PAGE_ERASE   0x0281
 
#define SSB_CHIPCO_FLASHCTL_AT_BLOCK_ERASE   0x0250
 
#define SSB_CHIPCO_FLASHCTL_AT_BUF1_WRER_PRGM   0x0382 /* Write erase program */
 
#define SSB_CHIPCO_FLASHCTL_AT_BUF2_WRER_PRGM   0x0385 /* Write erase program */
 
#define SSB_CHIPCO_FLASHCTL_AT_BUF1_LOAD   0x0253
 
#define SSB_CHIPCO_FLASHCTL_AT_BUF2_LOAD   0x0255
 
#define SSB_CHIPCO_FLASHCTL_AT_BUF1_COMPARE   0x0260
 
#define SSB_CHIPCO_FLASHCTL_AT_BUF2_COMPARE   0x0261
 
#define SSB_CHIPCO_FLASHCTL_AT_BUF1_REPROGRAM   0x0258
 
#define SSB_CHIPCO_FLASHCTL_AT_BUF2_REPROGRAM   0x0259
 
#define SSB_CHIPCO_FLASHSTA_AT_READY   0x80
 
#define SSB_CHIPCO_FLASHSTA_AT_MISMATCH   0x40
 
#define SSB_CHIPCO_FLASHSTA_AT_ID   0x38
 
#define SSB_CHIPCO_FLASHSTA_AT_ID_SHIFT   3
 
#define SSB_CHIPCO_OTP_HW_REGION   SSB_CHIPCO_OTPS_HW_PROTECT
 
#define SSB_CHIPCO_OTP_SW_REGION   SSB_CHIPCO_OTPS_SW_PROTECT
 
#define SSB_CHIPCO_OTP_CID_REGION   SSB_CHIPCO_OTPS_CID_PROTECT
 
#define SSB_CHIPCO_OTP_SWLIM_OFF   (-8)
 
#define SSB_CHIPCO_OTP_CIDBASE_OFF   0
 
#define SSB_CHIPCO_OTP_CIDLIM_OFF   8
 
#define SSB_CHIPCO_OTP_BOUNDARY_OFF   (-4)
 
#define SSB_CHIPCO_OTP_HWSIGN_OFF   (-3)
 
#define SSB_CHIPCO_OTP_SWSIGN_OFF   (-2)
 
#define SSB_CHIPCO_OTP_CIDSIGN_OFF   (-1)
 
#define SSB_CHIPCO_OTP_CID_OFF   0
 
#define SSB_CHIPCO_OTP_PKG_OFF   1
 
#define SSB_CHIPCO_OTP_FID_OFF   2
 
#define SSB_CHIPCO_OTP_RSV_OFF   3
 
#define SSB_CHIPCO_OTP_LIM_OFF   4
 
#define SSB_CHIPCO_OTP_SIGNATURE   0x578A
 
#define SSB_CHIPCO_OTP_MAGIC   0x4E56
 
#define chipco_read32(cc, offset)   ssb_read32((cc)->dev, offset)
 
#define chipco_write32(cc, offset, val)   ssb_write32((cc)->dev, offset, val)
 
#define chipco_mask32(cc, offset, mask)   chipco_write32(cc, offset, chipco_read32(cc, offset) & (mask))
 
#define chipco_set32(cc, offset, set)   chipco_write32(cc, offset, chipco_read32(cc, offset) | (set))
 
#define chipco_maskset32(cc, offset, mask, set)   chipco_write32(cc, offset, (chipco_read32(cc, offset) & (mask)) | (set))
 

Enumerations

enum  ssb_clkmode { SSB_CLKMODE_SLOW, SSB_CLKMODE_FAST, SSB_CLKMODE_DYNAMIC }
 
enum  ssb_pmu_ldo_volt_id { LDO_PAREF = 0, LDO_VOLT1, LDO_VOLT2, LDO_VOLT3 }
 

Functions

void ssb_chipcommon_init (struct ssb_chipcommon *cc)
 
void ssb_chipco_suspend (struct ssb_chipcommon *cc)
 
void ssb_chipco_resume (struct ssb_chipcommon *cc)
 
void ssb_chipco_get_clockcpu (struct ssb_chipcommon *cc, u32 *plltype, u32 *n, u32 *m)
 
void ssb_chipco_get_clockcontrol (struct ssb_chipcommon *cc, u32 *plltype, u32 *n, u32 *m)
 
void ssb_chipco_timing_init (struct ssb_chipcommon *cc, unsigned long ns_per_cycle)
 
void ssb_chipco_set_clockmode (struct ssb_chipcommon *cc, enum ssb_clkmode mode)
 
void ssb_chipco_watchdog_timer_set (struct ssb_chipcommon *cc, u32 ticks)
 
void ssb_chipco_irq_mask (struct ssb_chipcommon *cc, u32 mask, u32 value)
 
u32 ssb_chipco_irq_status (struct ssb_chipcommon *cc, u32 mask)
 
u32 ssb_chipco_gpio_in (struct ssb_chipcommon *cc, u32 mask)
 
u32 ssb_chipco_gpio_out (struct ssb_chipcommon *cc, u32 mask, u32 value)
 
u32 ssb_chipco_gpio_outen (struct ssb_chipcommon *cc, u32 mask, u32 value)
 
u32 ssb_chipco_gpio_control (struct ssb_chipcommon *cc, u32 mask, u32 value)
 
u32 ssb_chipco_gpio_intmask (struct ssb_chipcommon *cc, u32 mask, u32 value)
 
u32 ssb_chipco_gpio_polarity (struct ssb_chipcommon *cc, u32 mask, u32 value)
 
void ssb_pmu_init (struct ssb_chipcommon *cc)
 
void ssb_pmu_set_ldo_voltage (struct ssb_chipcommon *cc, enum ssb_pmu_ldo_volt_id id, u32 voltage)
 
void ssb_pmu_set_ldo_paref (struct ssb_chipcommon *cc, bool on)
 

Macro Definition Documentation

#define chipco_mask32 (   cc,
  offset,
  mask 
)    chipco_write32(cc, offset, chipco_read32(cc, offset) & (mask))

Definition at line 605 of file ssb_driver_chipcommon.h.

#define chipco_maskset32 (   cc,
  offset,
  mask,
  set 
)    chipco_write32(cc, offset, (chipco_read32(cc, offset) & (mask)) | (set))

Definition at line 609 of file ssb_driver_chipcommon.h.

#define chipco_read32 (   cc,
  offset 
)    ssb_read32((cc)->dev, offset)

Definition at line 602 of file ssb_driver_chipcommon.h.

#define chipco_set32 (   cc,
  offset,
  set 
)    chipco_write32(cc, offset, chipco_read32(cc, offset) | (set))

Definition at line 607 of file ssb_driver_chipcommon.h.

#define chipco_write32 (   cc,
  offset,
  val 
)    ssb_write32((cc)->dev, offset, val)

Definition at line 603 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_BCAST_ADDR   0x0050

Definition at line 124 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_BCAST_DATA   0x0054

Definition at line 125 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_BIST   0x000C

Definition at line 61 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CAP   0x0004 /* Capabilities */

Definition at line 26 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CAP_64BIT   0x08000000 /* 64-bit Backplane */

Definition at line 53 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CAP_BROM   0x00800000 /* Internal boot ROM active */

Definition at line 52 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CAP_ECI   0x20000000 /* ECI available (rev >= 20) */

Definition at line 55 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CAP_EXTBUS   0x000000C0 /* External buses present */

Definition at line 32 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CAP_FLASHT   0x00000700 /* Flash Type */

Definition at line 33 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CAP_JTAGM   0x00400000 /* JTAG master present */

Definition at line 51 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CAP_MIPSEB   0x00000004 /* MIPS in BigEndian Mode */

Definition at line 28 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CAP_NRUART   0x00000003 /* # of UARTs */

Definition at line 27 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CAP_OTPS   0x00380000 /* OTP size */

Definition at line 48 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CAP_OTPS_BASE   5

Definition at line 50 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CAP_OTPS_SHIFT   19

Definition at line 49 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CAP_PCTL   0x00040000 /* Power Control */

Definition at line 47 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CAP_PLLT   0x00038000 /* PLL Type */

Definition at line 38 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CAP_PMU   0x10000000 /* PMU available (rev >= 20) */

Definition at line 54 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CAP_SPROM   0x40000000 /* SPROM present */

Definition at line 56 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CAP_UARTCLK   0x00000018 /* UART clock select */

Definition at line 29 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CAP_UARTCLK_INT   0x00000008 /* UARTs are driven by internal divided clock */

Definition at line 30 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CAP_UARTGPIO   0x00000020 /* UARTs on GPIO 15-12 */

Definition at line 31 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CFG_BSTRO   0x0100 /* Sync: Size/Bytestrobe */

Definition at line 492 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CFG_CLKDIV   0x0060 /* Sync: Clock divisor */

Definition at line 490 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CFG_CLKEN   0x0080 /* Sync: Clock enable */

Definition at line 491 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CFG_DS16   0x0010 /* Data size, 0=8bit, 1=16bit */

Definition at line 489 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CFG_EN   0x0001 /* Enable */

Bits in the config registers

Definition at line 483 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CFG_EXTM   0x000E /* Extif Mode */

Definition at line 484 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CFG_EXTM_ASYNC   0x0002 /* Async/Parallel flash */

Definition at line 485 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CFG_EXTM_IDE   0x000A /* IDE */

Definition at line 488 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CFG_EXTM_PCMCIA   0x0008 /* PCMCIA */

Definition at line 487 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CFG_EXTM_SYNC   0x0004 /* Synchronous */

Definition at line 486 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CHIPCTL   0x0028 /* Rev >= 11 only */

Definition at line 89 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CHIPCTL_ADDR   0x0650

Definition at line 251 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CHIPCTL_DATA   0x0654

Definition at line 252 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CHIPID   0x0000

ChipCommon core registers.

Definition at line 18 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CHIPSTAT   0x002C /* Rev >= 11 only */

Definition at line 90 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CHST_4312_SPROM_PRESENT (   status)
Value:
((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
SSB_CHIPCO_CHST_4325_OTP_SEL)

Macros to determine SPROM presence based on Chip-Status register.

Definition at line 411 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CHST_4322_SPROM_EXISTS   0x00000040 /* SPROM present */

Chip specific Chip-Status register contents.

Definition at line 396 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CHST_4322_SPROM_PRESENT (   status)    (status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS)

Definition at line 414 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CHST_4325_DEFCIS_SEL   0 /* OTP is powered up, use def. CIS, no SPROM */

Definition at line 398 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CHST_4325_OTP_PWRDN   3 /* OTP is powered down, SPROM is present */

Definition at line 401 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CHST_4325_OTP_SEL   2 /* OTP is powered up, no SPROM */

Definition at line 400 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CHST_4325_PMUTOP_2B   0x00000200 /* 1 for 2b, 0 for to 2a */

Definition at line 408 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CHST_4325_RCAL_VALID   0x00000008

Definition at line 404 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CHST_4325_RCAL_VALID_SHIFT   3

Definition at line 405 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CHST_4325_RCAL_VALUE   0x000001F0

Definition at line 406 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT   4

Definition at line 407 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CHST_4325_SDIO_USB_MODE   0x00000004

Definition at line 402 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CHST_4325_SDIO_USB_MODE_SHIFT   2

Definition at line 403 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL   0x00000003

Definition at line 397 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CHST_4325_SPROM_PRESENT (   status)
Value:
(((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
SSB_CHIPCO_CHST_4325_DEFCIS_SEL) && \
((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
SSB_CHIPCO_CHST_4325_OTP_SEL))

Definition at line 416 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CHST_4325_SPROM_SEL   1 /* OTP is powered up, SPROM is present */

Definition at line 399 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_5350_M   0x04020009

Definition at line 478 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_5350_N   0x0311

Definition at line 477 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_BASE1   24000000 /* Half the clock freq */

Definition at line 473 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_BASE2   12500000 /* Alternate crystal on some PLL's */

Definition at line 474 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_F5_BIAS   5 /* 5-bit fields get this added */

Definition at line 450 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_F6_2   0x02 /* A factor of 2 in */

Definition at line 443 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_F6_3   0x03 /* 6-bit fields like */

Definition at line 444 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_F6_4   0x05 /* N1, M1 or M3 */

Definition at line 445 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_F6_5   0x09

Definition at line 446 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_F6_6   0x11

Definition at line 447 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_F6_7   0x21

Definition at line 448 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_M1   0x0000003F /* m1 control */

Definition at line 434 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_M2   0x00003F00 /* m2 control */

Definition at line 435 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_M2_SHIFT   8

Definition at line 436 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_M3   0x003F0000 /* m3 control */

Definition at line 437 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_M3_SHIFT   16

Definition at line 438 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_MC   0x1F000000 /* mux control */

Definition at line 439 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_MC_BYPASS   0x08

Definition at line 452 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_MC_M1   0x04

Definition at line 453 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_MC_M1M2   0x02

Definition at line 454 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_MC_M1M2M3   0x01

Definition at line 455 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_MC_M1M3   0x11

Definition at line 456 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_MC_SHIFT   24

Definition at line 440 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_N1   0x0000003F /* n1 control */

Clockcontrol masks and values

Definition at line 427 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_N2   0x00003F00 /* n2 control */

Definition at line 428 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_N2_SHIFT   8

Definition at line 429 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_PLLC   0x000F0000 /* pll control */

Definition at line 430 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_PLLC_SHIFT   16

Definition at line 431 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_SB2MIPS_T6 (   sb)    (2 * (sb))

Definition at line 470 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_T2_BIAS   2 /* n1, n2, m1 & m3 bias */

Definition at line 459 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_T2M2_BIAS   3 /* m2 bias */

Definition at line 460 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_T2MC_M1BYP   1

Definition at line 462 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_T2MC_M2BYP   2

Definition at line 463 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_T2MC_M3BYP   4

Definition at line 464 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_T6_M0   120000000 /* sb clock for m = 0 */

Definition at line 468 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_T6_M1   100000000 /* sb clock for m = 1 */

Definition at line 469 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLK_T6_MMASK   1 /* bits of interest in m */

Definition at line 467 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLKCTLST   0x01E0 /* Clock control and status (rev >= 20) */

Definition at line 190 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP   0x00020000 /* 4328a0 has reversed bits */

Definition at line 200 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT   0x00010000 /* 4328a0 has reversed bits */

Definition at line 199 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLKCTLST_FORCEALP   0x00000001 /* Force ALP request */

Definition at line 191 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLKCTLST_FORCEHT   0x00000002 /* Force HT request */

Definition at line 192 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLKCTLST_FORCEILP   0x00000004 /* Force ILP request */

Definition at line 193 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLKCTLST_HAVEALP   0x00010000 /* ALP available */

Definition at line 197 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLKCTLST_HAVEALPREQ   0x00000008 /* ALP available request */

Definition at line 194 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLKCTLST_HAVEHT   0x00020000 /* HT available */

Definition at line 198 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLKCTLST_HAVEHTREQ   0x00000010 /* HT available request */

Definition at line 195 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLKCTLST_HWCROFF   0x00000020 /* Force HW clock request off */

Definition at line 196 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLKDIV   0x00A4 /* Rev >= 3 only */

Definition at line 146 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLKDIV_JTAG   0x00000F00

Definition at line 151 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLKDIV_JTAG_SHIFT   8

Definition at line 152 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLKDIV_OTP   0x000F0000

Definition at line 149 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLKDIV_OTP_SHIFT   16

Definition at line 150 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLKDIV_SFLASH   0x0F000000

Definition at line 147 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLKDIV_SFLASH_SHIFT   24

Definition at line 148 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLKDIV_UART   0x000000FF

Definition at line 153 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLKSTSTR   0x00C4 /* Rev >= 3 only */

Definition at line 177 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLOCK_M2   0x009C

Definition at line 144 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLOCK_MIPS   0x00A0

Definition at line 145 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLOCK_N   0x0090

Definition at line 141 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLOCK_PCI   0x0098

Definition at line 143 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CLOCK_SB   0x0094

Definition at line 142 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CORECTL   0x0008

Definition at line 57 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CORECTL_SE   0x00000002 /* sync clk out enable (corerev >= 3) */

Definition at line 59 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CORECTL_UARTCLK0   0x00000001 /* Drive UART with internal clock */

Definition at line 58 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_CORECTL_UARTCLKEN   0x00000008 /* UART clock enable (rev >= 21) */

Definition at line 60 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASH_CFG   0x0128

Definition at line 188 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASH_WAITCNT   0x012C

Definition at line 189 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHADDR   0x0044

Definition at line 122 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL   0x0040

Definition at line 119 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_AT_BLOCK_ERASE   0x0250

Definition at line 531 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_AT_BUF1_COMPARE   0x0260

Definition at line 536 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_AT_BUF1_ERASE_PRGM   0x0283 /* Erase program */

Definition at line 526 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_AT_BUF1_LOAD   0x0253

Definition at line 534 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_AT_BUF1_PROGRAM   0x0288

Definition at line 528 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_AT_BUF1_READ   /* FIXME */

Definition at line 521 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_AT_BUF1_REPROGRAM   0x0258

Definition at line 538 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_AT_BUF1_WRER_PRGM   0x0382 /* Write erase program */

Definition at line 532 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_AT_BUF1_WRITE   0x0384

Definition at line 524 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_AT_BUF2_COMPARE   0x0261

Definition at line 537 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_AT_BUF2_ERASE_PRGM   0x0286 /* Erase program */

Definition at line 527 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_AT_BUF2_LOAD   0x0255

Definition at line 535 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_AT_BUF2_PROGRAM   0x0289

Definition at line 529 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_AT_BUF2_READ   /* FIXME */

Definition at line 522 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_AT_BUF2_REPROGRAM   0x0259

Definition at line 539 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_AT_BUF2_WRER_PRGM   0x0385 /* Write erase program */

Definition at line 533 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_AT_BUF2_WRITE   0x0387

Definition at line 525 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_AT_PAGE_ERASE   0x0281

Definition at line 530 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_AT_PAGE_READ   0x07D2

Definition at line 520 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_AT_READ   0x07E8

Definition at line 519 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_AT_STATUS   0x01D7

Definition at line 523 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_BUSY   SSB_CHIPCO_FLASHCTL_START

Definition at line 121 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_ST_BE   0x00C7 /* Bulk Erase */

Definition at line 505 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_ST_CSA   0x1000 /* Keep chip select asserted */

Definition at line 508 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_ST_DP   0x00B9 /* Deep Power-down */

Definition at line 506 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_ST_PP   0x0302 /* Page Program */

Definition at line 503 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_ST_RDSR   0x0105 /* Read Status Register */

Definition at line 500 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_ST_READ   0x0303 /* Read Data Bytes */

Definition at line 502 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_ST_RES   0x03AB /* Read Electronic Signature */

Definition at line 507 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_ST_SE   0x02D8 /* Sector Erase */

Definition at line 504 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_ST_SSE   0x0220 /* Sub-sector Erase */

Definition at line 509 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_ST_WRDIS   0x0004 /* Write Disable */

Definition at line 499 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_ST_WREN   0x0006 /* Write Enable */

Flash-specific control/status values

Definition at line 498 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_ST_WRSR   0x0101 /* Write Status Register */

Definition at line 501 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHCTL_START   0x80000000

Definition at line 120 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHDATA   0x0048

Definition at line 123 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHSTA_AT_ID   0x38

Definition at line 544 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHSTA_AT_ID_SHIFT   3

Definition at line 545 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHSTA_AT_MISMATCH   0x40

Definition at line 543 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHSTA_AT_READY   0x80

Definition at line 542 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHSTA_ST_BP   0x1C /* Block Protect */

Definition at line 514 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHSTA_ST_BP_SHIFT   2

Definition at line 515 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHSTA_ST_SRWD   0x80 /* Status Register Write Disable */

Definition at line 516 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHSTA_ST_WEL   0x02 /* Write Enable Latch */

Definition at line 513 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHSTA_ST_WIP   0x01 /* Write In Progress */

Definition at line 512 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHT_ATSER   0x00000200 /* Atmel serial flash */

Definition at line 36 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHT_NONE   0x00000000 /* No flash */

Definition at line 34 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHT_PARA   0x00000700 /* Parallel flash */

Definition at line 37 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FLASHT_STSER   0x00000100 /* ST serial flash */

Definition at line 35 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_FREFSELDELAY   0x00B4 /* Rev >= 4 only */

Definition at line 155 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_GPIOCTL   0x006C

Definition at line 131 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_GPIOIN   0x0060

Definition at line 128 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_GPIOIRQ   0x0074

Definition at line 133 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_GPIOOUT   0x0064

Definition at line 129 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_GPIOOUTEN   0x0068

Definition at line 130 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_GPIOPOL   0x0070

Definition at line 132 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_GPIOPULLDOWN   0x005C /* Rev >= 20 only */

Definition at line 127 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_GPIOPULLUP   0x0058 /* Rev >= 20 only */

Definition at line 126 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_GPIOTIMER   0x0088 /* LED powersave (corerev >= 16) */

Definition at line 135 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_GPIOTIMER_OFFTIME   0x0000FFFF

Definition at line 136 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT   0

Definition at line 137 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_GPIOTIMER_ONTIME   0xFFFF0000

Definition at line 138 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT   16

Definition at line 139 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_GPIOTOUTM   0x008C /* LED powersave (corerev >= 16) */

Definition at line 140 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_HW_WORKAROUND   0x01E4 /* Hardware workaround (rev >= 20) */

Definition at line 201 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_IDE_ATTRWAIT   0x0118

Definition at line 184 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_IDE_CFG   0x0110

Definition at line 182 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_IDE_IOWAIT   0x011C

Definition at line 185 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_IDE_MEMWAIT   0x0114

Definition at line 183 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_IDMASK   0x0000FFFF

Definition at line 19 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_IRQ_EXT   0x00000002 /* ro: ext intr pin (corerev >= 3) */

Definition at line 87 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_IRQ_GPIO   0x00000001 /* gpio intr */

Definition at line 86 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_IRQ_WDRESET   0x80000000 /* watchdog reset occurred */

Definition at line 88 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_IRQMASK   0x0024

Definition at line 85 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_IRQSTAT   0x0020

Definition at line 84 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_JCMD   0x0030 /* Rev >= 10 only */

Definition at line 91 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_JCMD0_ACC_DR   0x00001000

Definition at line 97 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_JCMD0_ACC_IR   0x00002000

Definition at line 98 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_JCMD0_ACC_IRDR   0x00000000

Definition at line 96 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_JCMD0_ACC_IRPDR   0x00004000

Definition at line 100 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_JCMD0_ACC_MASK   0x0000F000

Definition at line 95 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_JCMD0_ACC_PDR   0x00005000

Definition at line 101 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_JCMD0_ACC_RESET   0x00003000

Definition at line 99 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_JCMD0_IRW_MASK   0x00000F00

Definition at line 102 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_JCMD_ACC_DR   0x00010000

Definition at line 105 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_JCMD_ACC_IR   0x00020000

Definition at line 106 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_JCMD_ACC_IRDR   0x00000000

Definition at line 104 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_JCMD_ACC_IRPDR   0x00040000

Definition at line 108 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_JCMD_ACC_MASK   0x000F0000 /* Changes for corerev 11 */

Definition at line 103 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_JCMD_ACC_PDR   0x00050000

Definition at line 109 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_JCMD_ACC_RESET   0x00030000

Definition at line 107 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_JCMD_BUSY   0x80000000

Definition at line 93 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_JCMD_DRW_MASK   0x0000003F

Definition at line 112 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_JCMD_IRW_MASK   0x00001F00

Definition at line 110 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_JCMD_IRW_SHIFT   8

Definition at line 111 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_JCMD_PAUSE   0x40000000

Definition at line 94 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_JCMD_START   0x80000000

Definition at line 92 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_JCTL   0x003C /* Rev >= 10 only */

Definition at line 115 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_JCTL_EN   1 /* Enable Jtag master */

Definition at line 118 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_JCTL_EXT_EN   2 /* Enable external targets */

Definition at line 117 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_JCTL_FORCE_CLK   4 /* Force clock */

Definition at line 116 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_JDR   0x0038 /* Rev >= 10 only */

Definition at line 114 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_JIR   0x0034 /* Rev >= 10 only */

Definition at line 113 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_NRCORESMASK   0x0F000000

Definition at line 24 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_NRCORESSHIFT   24

Definition at line 25 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTP_BOUNDARY_OFF   (-4)

Definition at line 561 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTP_CID_OFF   0

Definition at line 566 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTP_CID_REGION   SSB_CHIPCO_OTPS_CID_PROTECT

Definition at line 553 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTP_CIDBASE_OFF   0

Definition at line 557 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTP_CIDLIM_OFF   8

Definition at line 558 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTP_CIDSIGN_OFF   (-1)

Definition at line 564 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTP_FID_OFF   2

Definition at line 568 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTP_HW_REGION   SSB_CHIPCO_OTPS_HW_PROTECT

OTP

Definition at line 551 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTP_HWSIGN_OFF   (-3)

Definition at line 562 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTP_LIM_OFF   4

Definition at line 570 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTP_MAGIC   0x4E56

Definition at line 573 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTP_PKG_OFF   1

Definition at line 567 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTP_RSV_OFF   3

Definition at line 569 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTP_SIGNATURE   0x578A

Definition at line 572 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTP_SW_REGION   SSB_CHIPCO_OTPS_SW_PROTECT

Definition at line 552 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTP_SWLIM_OFF   (-8)

Definition at line 556 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTP_SWSIGN_OFF   (-2)

Definition at line 563 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTPC   0x0014 /* OTP control */

Definition at line 68 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTPC_MAXFAIL   0x00000038

Definition at line 72 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTPC_PROGWAIT   0x00FFFF00

Definition at line 70 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTPC_PRW_SHIFT   8

Definition at line 71 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTPC_RECWAIT   0xFF000000

Definition at line 69 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTPC_SELVL   0x00000001

Definition at line 74 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTPC_VSEL   0x00000006

Definition at line 73 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTPP   0x0018 /* OTP prog */

Definition at line 75 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTPP_BUSY   0x80000000

Definition at line 83 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTPP_COL   0x000000FF

Definition at line 76 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTPP_READ   0x40000000

Definition at line 81 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTPP_READERR   0x10000000

Definition at line 79 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTPP_ROW   0x0000FF00

Definition at line 77 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTPP_ROW_SHIFT   8

Definition at line 78 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTPP_START   0x80000000

Definition at line 82 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTPP_VALUE   0x20000000

Definition at line 80 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTPS   0x0010 /* OTP status */

Definition at line 62 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTPS_CID_PROTECT   0x00000004

Definition at line 67 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTPS_HW_PROTECT   0x00000001

Definition at line 65 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTPS_PROGFAIL   0x80000000

Definition at line 63 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTPS_PROTECT   0x00000007

Definition at line 64 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_OTPS_SW_PROTECT   0x00000002

Definition at line 66 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PACKMASK   0x00F00000

Definition at line 22 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PACKSHIFT   20

Definition at line 23 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PCMCIA_ATTRWAIT   0x0108

Definition at line 180 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PCMCIA_CFG   0x0100

Definition at line 178 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PCMCIA_IOWAIT   0x010C

Definition at line 181 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PCMCIA_MEMWAIT   0x0104

Definition at line 179 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PLLCTL_ADDR   0x0660

Definition at line 255 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PLLCTL_DATA   0x0664

Definition at line 256 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PLLONDELAY   0x00B0 /* Rev >= 4 only */

Definition at line 154 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_CAP   0x0604 /* PMU capabilities */

Definition at line 229 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_CAP_REVISION   0x000000FF /* Revision mask */

Definition at line 230 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_CLKSTRETCH   0x0630 /* PMU clockstretch */

Definition at line 246 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_CTL   0x0600 /* PMU control */

Definition at line 219 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_CTL_ALPREQEN   0x00000080 /* ALP req enable */

Definition at line 224 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_CTL_HTREQEN   0x00000100 /* HT req enable */

Definition at line 223 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_CTL_ILP_DIV   0xFFFF0000 /* ILP div mask */

Definition at line 220 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT   16

Definition at line 221 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_CTL_ILPDIVEN   0x00000002 /* ILP div enable */

Definition at line 227 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_CTL_LPOSEL   0x00000001 /* LPO sel */

Definition at line 228 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_CTL_NOILPONW   0x00000200 /* No ILP on wait */

Definition at line 222 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_CTL_XTALFREQ   0x0000007C /* Crystal freq */

Definition at line 225 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT   2

Definition at line 226 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_MAXRES_MSK   0x061C /* PMU max res mask */

Definition at line 241 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_MINRES_MSK   0x0618 /* PMU min res mask */

Definition at line 240 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_RES_DEPMSK   0x0624 /* PMU res dep mask */

Definition at line 243 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_RES_PEND   0x0610 /* PMU res pending */

Definition at line 238 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_RES_REQM   0x0648 /* PMU res req mask */

Definition at line 250 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_RES_REQT   0x0644 /* PMU res req timer */

Definition at line 249 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_RES_REQTS   0x0640 /* PMU res req timer sel */

Definition at line 248 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_RES_STAT   0x060C /* PMU res status */

Definition at line 237 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_RES_TABSEL   0x0620 /* PMU res table sel */

Definition at line 242 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_RES_TIMER   0x062C /* PMU res timer */

Definition at line 245 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_RES_UPDNTM   0x0628 /* PMU res updown timer */

Definition at line 244 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_STAT   0x0608 /* PMU status */

Definition at line 231 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_STAT_HAVEALP   0x00000008 /* ALP available */

Definition at line 234 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_STAT_HAVEHT   0x00000004 /* HT available */

Definition at line 235 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_STAT_INTPEND   0x00000040 /* Interrupt pending */

Definition at line 232 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_STAT_RESINIT   0x00000003 /* Res init */

Definition at line 236 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_STAT_SBCLKST   0x00000030 /* Backplane clock status? */

Definition at line 233 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_TIMER   0x0614 /* PMU timer */

Definition at line 239 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PMU_WATCHDOG   0x0634 /* PMU watchdog */

Definition at line 247 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PROG_CFG   0x0120

Definition at line 186 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_PROG_WAITCNT   0x0124

Definition at line 187 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_REGCTL_ADDR   0x0658

Definition at line 253 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_REGCTL_DATA   0x065C

Definition at line 254 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_REVMASK   0x000F0000

Definition at line 20 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_REVSHIFT   16

Definition at line 21 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_SLOECLKCTL_SRC_PCI   0x00000002 /* source of slow clock is PCI */

Definition at line 160 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_SLOWCLKCTL   0x00B8 /* 6 <= Rev <= 9 only */

Definition at line 156 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_SLOWCLKCTL_CLKDIV   0xFFFF0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */

Definition at line 167 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_SLOWCLKCTL_CLKDIV_SHIFT   16

Definition at line 168 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_SLOWCLKCTL_ENXTAL   0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */

Definition at line 165 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_SLOWCLKCTL_FSLOW   0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */

Definition at line 163 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_SLOWCLKCTL_IPLL   0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */

Definition at line 164 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_SLOWCLKCTL_LPOFREQ   0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */

Definition at line 161 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_SLOWCLKCTL_LPOPD   0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */

Definition at line 162 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_SLOWCLKCTL_SRC   0x00000007 /* slow clock source mask */

Definition at line 157 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_SLOWCLKCTL_SRC_LPO   0x00000000 /* source of slow clock is LPO */

Definition at line 158 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL   0x00000001 /* source of slow clock is crystal */

Definition at line 159 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_SLOWCLKCTL_XTALPU   0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */

Definition at line 166 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_SYSCLKCTL   0x00C0 /* Rev >= 3 only */

Definition at line 169 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_SYSCLKCTL_ALPEN   0x00000002 /* ALPen: Enable Active Low Power */

Definition at line 171 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_SYSCLKCTL_CLKDIV   0xFFFF0000 /* ClkDiv (ILP = 1/(4+divisor)) */

Definition at line 175 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_SYSCLKCTL_CLKDIV_SHIFT   16

Definition at line 176 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_SYSCLKCTL_FORCEALP   0x00000008 /* Force ALP (or HT if ALPen is not set */

Definition at line 173 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_SYSCLKCTL_FORCEHT   0x00000010 /* Force HT */

Definition at line 174 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_SYSCLKCTL_IDLPEN   0x00000001 /* ILPen: Enable Idle Low Power */

Definition at line 170 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_SYSCLKCTL_PLLEN   0x00000004 /* ForcePLLOn */

Definition at line 172 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_UART0_DATA   0x0300

Definition at line 202 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_UART0_FCR   0x0308

Definition at line 204 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_UART0_IMR   0x0304

Definition at line 203 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_UART0_LCR   0x030C

Definition at line 205 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_UART0_LSR   0x0314

Definition at line 207 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_UART0_MCR   0x0310

Definition at line 206 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_UART0_MSR   0x0318

Definition at line 208 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_UART0_SCRATCH   0x031C

Definition at line 209 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_UART1_DATA   0x0400

Definition at line 210 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_UART1_FCR   0x0408

Definition at line 212 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_UART1_IMR   0x0404

Definition at line 211 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_UART1_LCR   0x040C

Definition at line 213 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_UART1_LSR   0x0414

Definition at line 215 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_UART1_MCR   0x0410

Definition at line 214 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_UART1_MSR   0x0418

Definition at line 216 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_UART1_SCRATCH   0x041C

Definition at line 217 of file ssb_driver_chipcommon.h.

#define SSB_CHIPCO_WATCHDOG   0x0080

Definition at line 134 of file ssb_driver_chipcommon.h.

#define SSB_PLLTYPE_1   0x00010000 /* 48Mhz base, 3 dividers */

Definition at line 40 of file ssb_driver_chipcommon.h.

#define SSB_PLLTYPE_2   0x00020000 /* 48Mhz, 4 dividers */

Definition at line 41 of file ssb_driver_chipcommon.h.

#define SSB_PLLTYPE_3   0x00030000 /* 25Mhz, 2 dividers */

Definition at line 42 of file ssb_driver_chipcommon.h.

#define SSB_PLLTYPE_4   0x00008000 /* 48Mhz, 4 dividers */

Definition at line 43 of file ssb_driver_chipcommon.h.

#define SSB_PLLTYPE_5   0x00018000 /* 25Mhz, 4 dividers */

Definition at line 44 of file ssb_driver_chipcommon.h.

#define SSB_PLLTYPE_6   0x00028000 /* 100/200 or 120/240 only */

Definition at line 45 of file ssb_driver_chipcommon.h.

#define SSB_PLLTYPE_7   0x00038000 /* 25Mhz, 4 dividers */

Definition at line 46 of file ssb_driver_chipcommon.h.

#define SSB_PLLTYPE_NONE   0x00000000

Definition at line 39 of file ssb_driver_chipcommon.h.

#define SSB_PMU0_PLLCTL0   0

PMU PLL registers

Definition at line 263 of file ssb_driver_chipcommon.h.

#define SSB_PMU0_PLLCTL0_PDIV_FREQ   25000 /* kHz */

Definition at line 265 of file ssb_driver_chipcommon.h.

#define SSB_PMU0_PLLCTL0_PDIV_MSK   0x00000001

Definition at line 264 of file ssb_driver_chipcommon.h.

#define SSB_PMU0_PLLCTL1   1

Definition at line 266 of file ssb_driver_chipcommon.h.

#define SSB_PMU0_PLLCTL1_STOPMOD   0x00000040 /* Stop mod */

Definition at line 271 of file ssb_driver_chipcommon.h.

#define SSB_PMU0_PLLCTL1_WILD_FMSK   0x0FFFFF00 /* Wild frac mask */

Definition at line 269 of file ssb_driver_chipcommon.h.

#define SSB_PMU0_PLLCTL1_WILD_FMSK_SHIFT   8

Definition at line 270 of file ssb_driver_chipcommon.h.

#define SSB_PMU0_PLLCTL1_WILD_IMSK   0xF0000000 /* Wild int mask (low nibble) */

Definition at line 267 of file ssb_driver_chipcommon.h.

#define SSB_PMU0_PLLCTL1_WILD_IMSK_SHIFT   28

Definition at line 268 of file ssb_driver_chipcommon.h.

#define SSB_PMU0_PLLCTL2   2

Definition at line 272 of file ssb_driver_chipcommon.h.

#define SSB_PMU0_PLLCTL2_WILD_IMSKHI   0x0000000F /* Wild int mask (high nibble) */

Definition at line 273 of file ssb_driver_chipcommon.h.

#define SSB_PMU0_PLLCTL2_WILD_IMSKHI_SHIFT   0

Definition at line 274 of file ssb_driver_chipcommon.h.

#define SSB_PMU1_PLLCTL0   0

Definition at line 277 of file ssb_driver_chipcommon.h.

#define SSB_PMU1_PLLCTL0_P1DIV   0x00F00000 /* P1 div */

Definition at line 278 of file ssb_driver_chipcommon.h.

#define SSB_PMU1_PLLCTL0_P1DIV_SHIFT   20

Definition at line 279 of file ssb_driver_chipcommon.h.

#define SSB_PMU1_PLLCTL0_P2DIV   0x0F000000 /* P2 div */

Definition at line 280 of file ssb_driver_chipcommon.h.

#define SSB_PMU1_PLLCTL0_P2DIV_SHIFT   24

Definition at line 281 of file ssb_driver_chipcommon.h.

#define SSB_PMU1_PLLCTL1   1

Definition at line 282 of file ssb_driver_chipcommon.h.

#define SSB_PMU1_PLLCTL1_M1DIV   0x000000FF /* M1 div */

Definition at line 283 of file ssb_driver_chipcommon.h.

#define SSB_PMU1_PLLCTL1_M1DIV_SHIFT   0

Definition at line 284 of file ssb_driver_chipcommon.h.

#define SSB_PMU1_PLLCTL1_M2DIV   0x0000FF00 /* M2 div */

Definition at line 285 of file ssb_driver_chipcommon.h.

#define SSB_PMU1_PLLCTL1_M2DIV_SHIFT   8

Definition at line 286 of file ssb_driver_chipcommon.h.

#define SSB_PMU1_PLLCTL1_M3DIV   0x00FF0000 /* M3 div */

Definition at line 287 of file ssb_driver_chipcommon.h.

#define SSB_PMU1_PLLCTL1_M3DIV_SHIFT   16

Definition at line 288 of file ssb_driver_chipcommon.h.

#define SSB_PMU1_PLLCTL1_M4DIV   0xFF000000 /* M4 div */

Definition at line 289 of file ssb_driver_chipcommon.h.

#define SSB_PMU1_PLLCTL1_M4DIV_SHIFT   24

Definition at line 290 of file ssb_driver_chipcommon.h.

#define SSB_PMU1_PLLCTL2   2

Definition at line 291 of file ssb_driver_chipcommon.h.

#define SSB_PMU1_PLLCTL2_M5DIV   0x000000FF /* M5 div */

Definition at line 292 of file ssb_driver_chipcommon.h.

#define SSB_PMU1_PLLCTL2_M5DIV_SHIFT   0

Definition at line 293 of file ssb_driver_chipcommon.h.

#define SSB_PMU1_PLLCTL2_M6DIV   0x0000FF00 /* M6 div */

Definition at line 294 of file ssb_driver_chipcommon.h.

#define SSB_PMU1_PLLCTL2_M6DIV_SHIFT   8

Definition at line 295 of file ssb_driver_chipcommon.h.

#define SSB_PMU1_PLLCTL2_NDIVINT   0x1FF00000 /* NDIV int */

Definition at line 298 of file ssb_driver_chipcommon.h.

#define SSB_PMU1_PLLCTL2_NDIVINT_SHIFT   20

Definition at line 299 of file ssb_driver_chipcommon.h.

#define SSB_PMU1_PLLCTL2_NDIVMODE   0x000E0000 /* NDIV mode */

Definition at line 296 of file ssb_driver_chipcommon.h.

#define SSB_PMU1_PLLCTL2_NDIVMODE_SHIFT   17

Definition at line 297 of file ssb_driver_chipcommon.h.

#define SSB_PMU1_PLLCTL3   3

Definition at line 300 of file ssb_driver_chipcommon.h.

#define SSB_PMU1_PLLCTL3_NDIVFRAC   0x00FFFFFF /* NDIV frac */

Definition at line 301 of file ssb_driver_chipcommon.h.

#define SSB_PMU1_PLLCTL3_NDIVFRAC_SHIFT   0

Definition at line 302 of file ssb_driver_chipcommon.h.

#define SSB_PMU1_PLLCTL4   4

Definition at line 303 of file ssb_driver_chipcommon.h.

#define SSB_PMU1_PLLCTL5   5

Definition at line 304 of file ssb_driver_chipcommon.h.

#define SSB_PMU1_PLLCTL5_CLKDRV   0xFFFFFF00 /* clk drv */

Definition at line 305 of file ssb_driver_chipcommon.h.

#define SSB_PMU1_PLLCTL5_CLKDRV_SHIFT   8

Definition at line 306 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4312_ALP_AVAIL   11

Definition at line 320 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4312_BB_PLL_FILTBYP   12

Definition at line 321 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4312_BG_FILTBYP   7

Definition at line 316 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4312_CORE_LDO_BURST   3

Definition at line 312 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4312_CORE_LDO_PWM   4

Definition at line 313 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4312_HT_AVAIL   14

Definition at line 323 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4312_ILP_REQUEST   6

Definition at line 315 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4312_PA_REF_LDO   2

Definition at line 311 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4312_RADIO_LDO   5

Definition at line 314 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4312_RF_PLL_FILTBYP   13

Definition at line 322 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4312_RX_FILTBYP   9

Definition at line 318 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4312_SWITCHER_BURST   0

Definition at line 309 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4312_SWITCHER_PWM   1

Definition at line 310 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4312_TX_FILTBYP   8

Definition at line 317 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4312_XTAL_PU   10

Definition at line 319 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4325_ABUCK_BURST   7

Definition at line 333 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4325_ABUCK_PWM   8

Definition at line 334 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4325_AFE_PWRSW_PU   19

Definition at line 345 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4325_ALP_AVAIL   14

Definition at line 340 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4325_BBPLL_PWRSW_PU   20

Definition at line 346 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4325_BUCK_BOOST_BURST   0

Definition at line 326 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4325_BUCK_BOOST_PWM   5

Definition at line 331 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4325_CBUCK_BURST   1

Definition at line 327 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4325_CBUCK_PWM   2

Definition at line 328 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4325_CLDO_CBUCK_BURST   3

Definition at line 329 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4325_CLDO_CBUCK_PWM   4

Definition at line 330 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4325_HT_AVAIL   21

Definition at line 347 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4325_ILP_REQUEST   6

Definition at line 332 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4325_LNLDO1_PU   9

Definition at line 335 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4325_LNLDO2_PU   10

Definition at line 336 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4325_LNLDO3_PU   11

Definition at line 337 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4325_LNLDO4_PU   12

Definition at line 338 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4325_LOGEN_PWRSW_PU   18

Definition at line 344 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4325_RFPLL_PWRSW_PU   17

Definition at line 343 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4325_RX_PWRSW_PU   15

Definition at line 341 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4325_TX_PWRSW_PU   16

Definition at line 342 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4325_XTAL_PU   13

Definition at line 339 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4328_AFE_LDO   10

Definition at line 360 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4328_BB_EXT_SWITCHER_BURST   3

Definition at line 353 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4328_BB_PLL_FILTBYP   17

Definition at line 367 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4328_BB_PLL_PU   19

Definition at line 369 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4328_BB_SWITCHER_BURST   2

Definition at line 352 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4328_BB_SWITCHER_PWM   1

Definition at line 351 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4328_BG_FILTBYP   12

Definition at line 362 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4328_EXT_SWITCHER_PWM   0

Definition at line 350 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4328_ILP_REQUEST   4

Definition at line 354 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4328_PA_REF_LDO   8

Definition at line 358 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4328_PLL_LDO   11

Definition at line 361 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4328_RADIO_LDO   9

Definition at line 359 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4328_RADIO_SWITCHER_BURST   6

Definition at line 356 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4328_RADIO_SWITCHER_PWM   5

Definition at line 355 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4328_RF_PLL_FILTBYP   18

Definition at line 368 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4328_ROM_SWITCH   7

Definition at line 357 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4328_RX_FILTBYP   14

Definition at line 364 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4328_TX_FILTBYP   13

Definition at line 363 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4328_XTAL_EN   16

Definition at line 366 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_4328_XTAL_PU   15

Definition at line 365 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_5354_AFE_LDO   10

Definition at line 382 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_5354_BB_EXT_SWITCHER_BURST   3

Definition at line 375 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_5354_BB_PLL_FILTBYP   17

Definition at line 389 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_5354_BB_PLL_PU   19

Definition at line 391 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_5354_BB_SWITCHER_BURST   2

Definition at line 374 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_5354_BB_SWITCHER_PWM   1

Definition at line 373 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_5354_BG_FILTBYP   12

Definition at line 384 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_5354_EXT_SWITCHER_PWM   0

Definition at line 372 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_5354_ILP_REQUEST   4

Definition at line 376 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_5354_PA_REF_LDO   8

Definition at line 380 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_5354_PLL_LDO   11

Definition at line 383 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_5354_RADIO_LDO   9

Definition at line 381 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_5354_RADIO_SWITCHER_BURST   6

Definition at line 378 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_5354_RADIO_SWITCHER_PWM   5

Definition at line 377 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_5354_RF_PLL_FILTBYP   18

Definition at line 390 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_5354_ROM_SWITCH   7

Definition at line 379 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_5354_RX_FILTBYP   14

Definition at line 386 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_5354_TX_FILTBYP   13

Definition at line 385 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_5354_XTAL_EN   16

Definition at line 388 of file ssb_driver_chipcommon.h.

#define SSB_PMURES_5354_XTAL_PU   15

Definition at line 387 of file ssb_driver_chipcommon.h.

Enumeration Type Documentation

enum ssb_clkmode
Enumerator:
SSB_CLKMODE_SLOW 
SSB_CLKMODE_FAST 
SSB_CLKMODE_DYNAMIC 

Definition at line 624 of file ssb_driver_chipcommon.h.

enum ssb_pmu_ldo_volt_id
Enumerator:
LDO_PAREF 
LDO_VOLT1 
LDO_VOLT2 
LDO_VOLT3 

Definition at line 656 of file ssb_driver_chipcommon.h.

Function Documentation

void ssb_chipco_get_clockcontrol ( struct ssb_chipcommon *  cc,
u32 *  plltype,
u32 *  n,
u32 *  m 
)

Definition at line 341 of file driver_chipcommon.c.

void ssb_chipco_get_clockcpu ( struct ssb_chipcommon *  cc,
u32 *  plltype,
u32 *  n,
u32 *  m 
)

Definition at line 318 of file driver_chipcommon.c.

u32 ssb_chipco_gpio_control ( struct ssb_chipcommon *  cc,
u32  mask,
u32  value 
)

Definition at line 429 of file driver_chipcommon.c.

u32 ssb_chipco_gpio_in ( struct ssb_chipcommon *  cc,
u32  mask 
)

Definition at line 414 of file driver_chipcommon.c.

u32 ssb_chipco_gpio_intmask ( struct ssb_chipcommon *  cc,
u32  mask,
u32  value 
)

Definition at line 435 of file driver_chipcommon.c.

u32 ssb_chipco_gpio_out ( struct ssb_chipcommon *  cc,
u32  mask,
u32  value 
)

Definition at line 419 of file driver_chipcommon.c.

u32 ssb_chipco_gpio_outen ( struct ssb_chipcommon *  cc,
u32  mask,
u32  value 
)

Definition at line 424 of file driver_chipcommon.c.

u32 ssb_chipco_gpio_polarity ( struct ssb_chipcommon *  cc,
u32  mask,
u32  value 
)

Definition at line 440 of file driver_chipcommon.c.

void ssb_chipco_irq_mask ( struct ssb_chipcommon *  cc,
u32  mask,
u32  value 
)

Definition at line 404 of file driver_chipcommon.c.

u32 ssb_chipco_irq_status ( struct ssb_chipcommon *  cc,
u32  mask 
)

Definition at line 409 of file driver_chipcommon.c.

void ssb_chipco_resume ( struct ssb_chipcommon *  cc)

Definition at line 309 of file driver_chipcommon.c.

void ssb_chipco_set_clockmode ( struct ssb_chipcommon *  cc,
enum ssb_clkmode  mode 
)

Definition at line 40 of file driver_chipcommon.c.

void ssb_chipco_suspend ( struct ssb_chipcommon *  cc)

Definition at line 302 of file driver_chipcommon.c.

void ssb_chipco_timing_init ( struct ssb_chipcommon *  cc,
unsigned long  ns_per_cycle 
)

Definition at line 361 of file driver_chipcommon.c.

void ssb_chipco_watchdog_timer_set ( struct ssb_chipcommon *  cc,
u32  ticks 
)

Definition at line 398 of file driver_chipcommon.c.

void ssb_chipcommon_init ( struct ssb_chipcommon *  cc)

Definition at line 283 of file driver_chipcommon.c.

void ssb_pmu_init ( struct ssb_chipcommon *  cc)

Definition at line 516 of file driver_chipcommon_pmu.c.

void ssb_pmu_set_ldo_paref ( struct ssb_chipcommon *  cc,
bool  on 
)

Definition at line 589 of file driver_chipcommon_pmu.c.

void ssb_pmu_set_ldo_voltage ( struct ssb_chipcommon *  cc,
enum ssb_pmu_ldo_volt_id  id,
u32  voltage 
)

Definition at line 539 of file driver_chipcommon_pmu.c.

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