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sd.c
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1 /* Driver for Realtek PCI-Express card reader
2  *
3  * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of the GNU General Public License as published by the
7  * Free Software Foundation; either version 2, or (at your option) any
8  * later version.
9  *
10  * This program is distributed in the hope that it will be useful, but
11  * WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13  * General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License along
16  * with this program; if not, see <http://www.gnu.org/licenses/>.
17  *
18  * Author:
19  * wwang ([email protected])
20  * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21  */
22 
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
26 
27 #include "rtsx.h"
28 #include "rtsx_transport.h"
29 #include "rtsx_scsi.h"
30 #include "rtsx_card.h"
31 #include "sd.h"
32 
33 #define SD_MAX_RETRY_COUNT 3
34 
35 static u16 REG_SD_CFG1;
36 static u16 REG_SD_CFG2;
37 static u16 REG_SD_CFG3;
38 static u16 REG_SD_STAT1;
39 static u16 REG_SD_STAT2;
40 static u16 REG_SD_BUS_STAT;
41 static u16 REG_SD_PAD_CTL;
42 static u16 REG_SD_SAMPLE_POINT_CTL;
43 static u16 REG_SD_PUSH_POINT_CTL;
44 static u16 REG_SD_CMD0;
45 static u16 REG_SD_CMD1;
46 static u16 REG_SD_CMD2;
47 static u16 REG_SD_CMD3;
48 static u16 REG_SD_CMD4;
49 static u16 REG_SD_CMD5;
50 static u16 REG_SD_BYTE_CNT_L;
51 static u16 REG_SD_BYTE_CNT_H;
52 static u16 REG_SD_BLOCK_CNT_L;
53 static u16 REG_SD_BLOCK_CNT_H;
54 static u16 REG_SD_TRANSFER;
55 static u16 REG_SD_VPCLK0_CTL;
56 static u16 REG_SD_VPCLK1_CTL;
57 static u16 REG_SD_DCMPS0_CTL;
58 static u16 REG_SD_DCMPS1_CTL;
59 
60 static inline void sd_set_err_code(struct rtsx_chip *chip, u8 err_code)
61 {
62  struct sd_info *sd_card = &(chip->sd_card);
63 
64  sd_card->err_code |= err_code;
65 }
66 
67 static inline void sd_clr_err_code(struct rtsx_chip *chip)
68 {
69  struct sd_info *sd_card = &(chip->sd_card);
70 
71  sd_card->err_code = 0;
72 }
73 
74 static inline int sd_check_err_code(struct rtsx_chip *chip, u8 err_code)
75 {
76  struct sd_info *sd_card = &(chip->sd_card);
77 
78  return sd_card->err_code & err_code;
79 }
80 
81 static void sd_init_reg_addr(struct rtsx_chip *chip)
82 {
83  if (CHECK_PID(chip, 0x5209)) {
84  REG_SD_CFG1 = SD_CFG1;
85  REG_SD_CFG2 = SD_CFG2;
86  REG_SD_CFG3 = SD_CFG3;
87  REG_SD_STAT1 = SD_STAT1;
88  REG_SD_STAT2 = SD_STAT2;
89  REG_SD_BUS_STAT = SD_BUS_STAT;
90  REG_SD_PAD_CTL = SD_PAD_CTL;
91  REG_SD_SAMPLE_POINT_CTL = SD_SAMPLE_POINT_CTL;
92  REG_SD_PUSH_POINT_CTL = SD_PUSH_POINT_CTL;
93  REG_SD_CMD0 = SD_CMD0;
94  REG_SD_CMD1 = SD_CMD1;
95  REG_SD_CMD2 = SD_CMD2;
96  REG_SD_CMD3 = SD_CMD3;
97  REG_SD_CMD4 = SD_CMD4;
98  REG_SD_CMD5 = SD_CMD5;
99  REG_SD_BYTE_CNT_L = SD_BYTE_CNT_L;
100  REG_SD_BYTE_CNT_H = SD_BYTE_CNT_H;
101  REG_SD_BLOCK_CNT_L = SD_BLOCK_CNT_L;
102  REG_SD_BLOCK_CNT_H = SD_BLOCK_CNT_H;
103  REG_SD_TRANSFER = SD_TRANSFER;
104  REG_SD_VPCLK0_CTL = SD_VPCLK0_CTL;
105  REG_SD_VPCLK1_CTL = SD_VPCLK1_CTL;
106  REG_SD_DCMPS0_CTL = SD_DCMPS0_CTL;
107  REG_SD_DCMPS1_CTL = SD_DCMPS1_CTL;
108  } else {
109  REG_SD_CFG1 = 0xFD31;
110  REG_SD_CFG2 = 0xFD33;
111  REG_SD_CFG3 = 0xFD3E;
112  REG_SD_STAT1 = 0xFD30;
113  REG_SD_STAT2 = 0;
114  REG_SD_BUS_STAT = 0;
115  REG_SD_PAD_CTL = 0;
116  REG_SD_SAMPLE_POINT_CTL = 0;
117  REG_SD_PUSH_POINT_CTL = 0;
118  REG_SD_CMD0 = 0xFD34;
119  REG_SD_CMD1 = 0xFD35;
120  REG_SD_CMD2 = 0xFD36;
121  REG_SD_CMD3 = 0xFD37;
122  REG_SD_CMD4 = 0xFD38;
123  REG_SD_CMD5 = 0xFD5A;
124  REG_SD_BYTE_CNT_L = 0xFD39;
125  REG_SD_BYTE_CNT_H = 0xFD3A;
126  REG_SD_BLOCK_CNT_L = 0xFD3B;
127  REG_SD_BLOCK_CNT_H = 0xFD3C;
128  REG_SD_TRANSFER = 0xFD32;
129  REG_SD_VPCLK0_CTL = 0;
130  REG_SD_VPCLK1_CTL = 0;
131  REG_SD_DCMPS0_CTL = 0;
132  REG_SD_DCMPS1_CTL = 0;
133  }
134 }
135 
136 static int sd_check_data0_status(struct rtsx_chip *chip)
137 {
138  u8 stat;
139 
140  if (CHECK_PID(chip, 0x5209))
141  RTSX_READ_REG(chip, REG_SD_BUS_STAT, &stat);
142  else
143  RTSX_READ_REG(chip, REG_SD_STAT1, &stat);
144 
145  if (!(stat & SD_DAT0_STATUS)) {
146  sd_set_err_code(chip, SD_BUSY);
147  TRACE_RET(chip, STATUS_FAIL);
148  }
149 
150  return STATUS_SUCCESS;
151 }
152 
153 static int sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx,
154  u32 arg, u8 rsp_type, u8 *rsp, int rsp_len)
155 {
156  struct sd_info *sd_card = &(chip->sd_card);
157  int retval;
158  int timeout = 100;
159  u16 reg_addr;
160  u8 *ptr;
161  int stat_idx = 0;
162  int rty_cnt = 0;
163 
164  sd_clr_err_code(chip);
165 
166  RTSX_DEBUGP("SD/MMC CMD %d, arg = 0x%08x\n", cmd_idx, arg);
167 
168  if (rsp_type == SD_RSP_TYPE_R1b)
169  timeout = 3000;
170 
171 RTY_SEND_CMD:
172 
173  rtsx_init_cmd(chip);
174 
175  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
176  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24));
177  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16));
178  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8));
179  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg);
180 
181  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
182  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
183  0x01, PINGPONG_BUFFER);
184  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
185  0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
186  rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
187  SD_TRANSFER_END | SD_STAT_IDLE, SD_TRANSFER_END | SD_STAT_IDLE);
188 
189  if (rsp_type == SD_RSP_TYPE_R2) {
190  for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; reg_addr++)
191  rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
192 
193  stat_idx = 16;
194  } else if (rsp_type != SD_RSP_TYPE_R0) {
195  for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4; reg_addr++)
196  rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
197 
198  stat_idx = 5;
199  }
200 
201  rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0);
202 
203  retval = rtsx_send_cmd(chip, SD_CARD, timeout);
204  if (retval < 0) {
205  u8 val;
206 
207  rtsx_read_register(chip, REG_SD_STAT1, &val);
208  RTSX_DEBUGP("SD_STAT1: 0x%x\n", val);
209 
210  if (CHECK_PID(chip, 0x5209)) {
211  rtsx_read_register(chip, REG_SD_STAT2, &val);
212  RTSX_DEBUGP("SD_STAT2: 0x%x\n", val);
213 
214  if (val & SD_RSP_80CLK_TIMEOUT) {
215  rtsx_clear_sd_error(chip);
216  sd_set_err_code(chip, SD_RSP_TIMEOUT);
217  TRACE_RET(chip, STATUS_FAIL);
218  }
219 
220  rtsx_read_register(chip, REG_SD_BUS_STAT, &val);
221  RTSX_DEBUGP("SD_BUS_STAT: 0x%x\n", val);
222  } else {
223  rtsx_read_register(chip, REG_SD_CFG3, &val);
224  RTSX_DEBUGP("SD_CFG3: 0x%x\n", val);
225  }
226 
227  if (retval == -ETIMEDOUT) {
228  if (rsp_type & SD_WAIT_BUSY_END) {
229  retval = sd_check_data0_status(chip);
230  if (retval != STATUS_SUCCESS) {
231  rtsx_clear_sd_error(chip);
232  TRACE_RET(chip, retval);
233  }
234  } else {
235  sd_set_err_code(chip, SD_TO_ERR);
236  }
237  retval = STATUS_TIMEDOUT;
238  } else {
239  retval = STATUS_FAIL;
240  }
241  rtsx_clear_sd_error(chip);
242 
243  TRACE_RET(chip, retval);
244  }
245 
246  if (rsp_type == SD_RSP_TYPE_R0)
247  return STATUS_SUCCESS;
248 
249  ptr = rtsx_get_cmd_data(chip) + 1;
250 
251  if ((ptr[0] & 0xC0) != 0) {
252  sd_set_err_code(chip, SD_STS_ERR);
253  TRACE_RET(chip, STATUS_FAIL);
254  }
255 
256  if (!(rsp_type & SD_NO_CHECK_CRC7)) {
257  if (ptr[stat_idx] & SD_CRC7_ERR) {
258  if (cmd_idx == WRITE_MULTIPLE_BLOCK) {
259  sd_set_err_code(chip, SD_CRC_ERR);
260  TRACE_RET(chip, STATUS_FAIL);
261  }
262  if (rty_cnt < SD_MAX_RETRY_COUNT) {
263  wait_timeout(20);
264  rty_cnt++;
265  goto RTY_SEND_CMD;
266  } else {
267  sd_set_err_code(chip, SD_CRC_ERR);
268  TRACE_RET(chip, STATUS_FAIL);
269  }
270  }
271  }
272 
273  if ((rsp_type == SD_RSP_TYPE_R1) || (rsp_type == SD_RSP_TYPE_R1b)) {
274  if ((cmd_idx != SEND_RELATIVE_ADDR) && (cmd_idx != SEND_IF_COND)) {
275  if (cmd_idx != STOP_TRANSMISSION) {
276  if (ptr[1] & 0x80)
277  TRACE_RET(chip, STATUS_FAIL);
278  }
279 #ifdef SUPPORT_SD_LOCK
280  if (ptr[1] & 0x7D)
281 #else
282  if (ptr[1] & 0x7F)
283 #endif
284  {
285  RTSX_DEBUGP("ptr[1]: 0x%02x\n", ptr[1]);
286  TRACE_RET(chip, STATUS_FAIL);
287  }
288  if (ptr[2] & 0xFF) {
289  RTSX_DEBUGP("ptr[2]: 0x%02x\n", ptr[2]);
290  TRACE_RET(chip, STATUS_FAIL);
291  }
292  if (ptr[3] & 0x80) {
293  RTSX_DEBUGP("ptr[3]: 0x%02x\n", ptr[3]);
294  TRACE_RET(chip, STATUS_FAIL);
295  }
296  if (ptr[3] & 0x01)
297  sd_card->sd_data_buf_ready = 1;
298  else
299  sd_card->sd_data_buf_ready = 0;
300  }
301  }
302 
303  if (rsp && rsp_len)
304  memcpy(rsp, ptr, rsp_len);
305 
306  return STATUS_SUCCESS;
307 }
308 
309 static int sd_read_data(struct rtsx_chip *chip,
310  u8 trans_mode, u8 *cmd, int cmd_len, u16 byte_cnt,
311  u16 blk_cnt, u8 bus_width, u8 *buf, int buf_len,
312  int timeout)
313 {
314  struct sd_info *sd_card = &(chip->sd_card);
315  int retval;
316  int i;
317 
318  sd_clr_err_code(chip);
319 
320  if (!buf)
321  buf_len = 0;
322 
323  if (buf_len > 512)
324  TRACE_RET(chip, STATUS_FAIL);
325 
326  rtsx_init_cmd(chip);
327 
328  if (cmd_len) {
329  RTSX_DEBUGP("SD/MMC CMD %d\n", cmd[0] - 0x40);
330  for (i = 0; i < (cmd_len < 6 ? cmd_len : 6); i++)
331  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0 + i, 0xFF, cmd[i]);
332  }
333  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
334  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, (u8)(byte_cnt >> 8));
335  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, (u8)blk_cnt);
336  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, (u8)(blk_cnt >> 8));
337 
338  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
339 
340  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
341  SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
342  SD_CHECK_CRC7 | SD_RSP_LEN_6);
343  if (trans_mode != SD_TM_AUTO_TUNING)
344  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
345 
346  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, trans_mode | SD_TRANSFER_START);
347  rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
348 
349  retval = rtsx_send_cmd(chip, SD_CARD, timeout);
350  if (retval < 0) {
351  if (retval == -ETIMEDOUT) {
352  sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
353  SD_RSP_TYPE_R1, NULL, 0);
354  }
355 
356  TRACE_RET(chip, STATUS_FAIL);
357  }
358 
359  if (buf && buf_len) {
360  retval = rtsx_read_ppbuf(chip, buf, buf_len);
361  if (retval != STATUS_SUCCESS)
362  TRACE_RET(chip, STATUS_FAIL);
363  }
364 
365  return STATUS_SUCCESS;
366 }
367 
368 static int sd_write_data(struct rtsx_chip *chip, u8 trans_mode,
369  u8 *cmd, int cmd_len, u16 byte_cnt, u16 blk_cnt, u8 bus_width,
370  u8 *buf, int buf_len, int timeout)
371 {
372  struct sd_info *sd_card = &(chip->sd_card);
373  int retval;
374  int i;
375 
376  sd_clr_err_code(chip);
377 
378  if (!buf)
379  buf_len = 0;
380 
381  if (buf_len > 512) {
382  /* This function can't write data more than one page */
383  TRACE_RET(chip, STATUS_FAIL);
384  }
385 
386  if (buf && buf_len) {
387  retval = rtsx_write_ppbuf(chip, buf, buf_len);
388  if (retval != STATUS_SUCCESS)
389  TRACE_RET(chip, STATUS_FAIL);
390  }
391 
392  rtsx_init_cmd(chip);
393 
394  if (cmd_len) {
395  RTSX_DEBUGP("SD/MMC CMD %d\n", cmd[0] - 0x40);
396  for (i = 0; i < (cmd_len < 6 ? cmd_len : 6); i++) {
397  rtsx_add_cmd(chip, WRITE_REG_CMD,
398  REG_SD_CMD0 + i, 0xFF, cmd[i]);
399  }
400  }
401  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt);
402  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, (u8)(byte_cnt >> 8));
403  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, (u8)blk_cnt);
404  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, (u8)(blk_cnt >> 8));
405 
406  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
407 
408  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
409  SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
410  SD_CHECK_CRC7 | SD_RSP_LEN_6);
411 
412  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, trans_mode | SD_TRANSFER_START);
413  rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
414 
415  retval = rtsx_send_cmd(chip, SD_CARD, timeout);
416  if (retval < 0) {
417  if (retval == -ETIMEDOUT) {
418  sd_send_cmd_get_rsp(chip, SEND_STATUS,
419  sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
420  }
421 
422  TRACE_RET(chip, STATUS_FAIL);
423  }
424 
425  return STATUS_SUCCESS;
426 }
427 
428 static int sd_check_csd(struct rtsx_chip *chip, char check_wp)
429 {
430  struct sd_info *sd_card = &(chip->sd_card);
431  int retval;
432  int i;
433  u8 csd_ver, trans_speed;
434  u8 rsp[16];
435 
436  for (i = 0; i < 6; i++) {
437  if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
438  sd_set_err_code(chip, SD_NO_CARD);
439  TRACE_RET(chip, STATUS_FAIL);
440  }
441 
442  retval = sd_send_cmd_get_rsp(chip, SEND_CSD, sd_card->sd_addr, SD_RSP_TYPE_R2, rsp, 16);
443  if (retval == STATUS_SUCCESS)
444  break;
445  }
446 
447  if (i == 6)
448  TRACE_RET(chip, STATUS_FAIL);
449 
450  memcpy(sd_card->raw_csd, rsp + 1, 15);
451 
452  if (CHECK_PID(chip, 0x5209))
453  RTSX_READ_REG(chip, REG_SD_CMD5, sd_card->raw_csd + 15);
454 
455  RTSX_DEBUGP("CSD Response:\n");
456  RTSX_DUMP(sd_card->raw_csd, 16);
457 
458  csd_ver = (rsp[1] & 0xc0) >> 6;
459  RTSX_DEBUGP("csd_ver = %d\n", csd_ver);
460 
461  trans_speed = rsp[4];
462  if ((trans_speed & 0x07) == 0x02) {
463  if ((trans_speed & 0xf8) >= 0x30) {
464  if (chip->asic_code)
465  sd_card->sd_clock = 47;
466  else
467  sd_card->sd_clock = CLK_50;
468 
469  } else if ((trans_speed & 0xf8) == 0x28) {
470  if (chip->asic_code)
471  sd_card->sd_clock = 39;
472  else
473  sd_card->sd_clock = CLK_40;
474 
475  } else if ((trans_speed & 0xf8) == 0x20) {
476  if (chip->asic_code)
477  sd_card->sd_clock = 29;
478  else
479  sd_card->sd_clock = CLK_30;
480 
481  } else if ((trans_speed & 0xf8) >= 0x10) {
482  if (chip->asic_code)
483  sd_card->sd_clock = 23;
484  else
485  sd_card->sd_clock = CLK_20;
486 
487  } else if ((trans_speed & 0x08) >= 0x08) {
488  if (chip->asic_code)
489  sd_card->sd_clock = 19;
490  else
491  sd_card->sd_clock = CLK_20;
492  } else {
493  TRACE_RET(chip, STATUS_FAIL);
494  }
495  } else {
496  TRACE_RET(chip, STATUS_FAIL);
497  }
498 
499  if (CHK_MMC_SECTOR_MODE(sd_card)) {
500  sd_card->capacity = 0;
501  } else {
502  if ((!CHK_SD_HCXC(sd_card)) || (csd_ver == 0)) {
503  u8 blk_size, c_size_mult;
504  u16 c_size;
505  blk_size = rsp[6] & 0x0F;
506  c_size = ((u16)(rsp[7] & 0x03) << 10)
507  + ((u16)rsp[8] << 2)
508  + ((u16)(rsp[9] & 0xC0) >> 6);
509  c_size_mult = (u8)((rsp[10] & 0x03) << 1);
510  c_size_mult += (rsp[11] & 0x80) >> 7;
511  sd_card->capacity = (((u32)(c_size + 1)) * (1 << (c_size_mult + 2))) << (blk_size - 9);
512  } else {
513  u32 total_sector = 0;
514  total_sector = (((u32)rsp[8] & 0x3f) << 16) |
515  ((u32)rsp[9] << 8) | (u32)rsp[10];
516  sd_card->capacity = (total_sector + 1) << 10;
517  }
518  }
519 
520  if (check_wp) {
521  if (rsp[15] & 0x30)
522  chip->card_wp |= SD_CARD;
523 
524  RTSX_DEBUGP("CSD WP Status: 0x%x\n", rsp[15]);
525  }
526 
527  return STATUS_SUCCESS;
528 }
529 
530 static int sd_set_sample_push_timing(struct rtsx_chip *chip)
531 {
532  struct sd_info *sd_card = &(chip->sd_card);
533 
534  if (CHECK_PID(chip, 0x5209)) {
535  if (CHK_SD_SDR104(sd_card) || CHK_SD_SDR50(sd_card)) {
536  RTSX_WRITE_REG(chip, SD_CFG1, 0x0C | SD_ASYNC_FIFO_NOT_RST,
537  SD_30_MODE | SD_ASYNC_FIFO_NOT_RST);
538  RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
539  RTSX_WRITE_REG(chip, CARD_CLK_SOURCE, 0xFF,
540  CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
541  RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0);
542  } else if (CHK_SD_DDR50(sd_card) || CHK_MMC_DDR52(sd_card)) {
543  RTSX_WRITE_REG(chip, SD_CFG1, 0x0C | SD_ASYNC_FIFO_NOT_RST,
544  SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST);
545  RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
546  RTSX_WRITE_REG(chip, CARD_CLK_SOURCE, 0xFF,
547  CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1);
548  RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0);
549  RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, DDR_VAR_TX_CMD_DAT,
550  DDR_VAR_TX_CMD_DAT);
551  RTSX_WRITE_REG(chip, SD_SAMPLE_POINT_CTL, DDR_VAR_RX_DAT | DDR_VAR_RX_CMD,
552  DDR_VAR_RX_DAT | DDR_VAR_RX_CMD);
553  } else {
554  u8 val = 0;
555 
556  RTSX_WRITE_REG(chip, SD_CFG1, 0x0C, SD_20_MODE);
557  RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
558  RTSX_WRITE_REG(chip, CARD_CLK_SOURCE, 0xFF,
559  CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1);
560  RTSX_WRITE_REG(chip, CLK_CTL, CLK_LOW_FREQ, 0);
561 
562  if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_AUTO)
563  val = SD20_TX_NEG_EDGE;
564  else if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_DELAY)
565  val = SD20_TX_14_AHEAD;
566  else
567  val = SD20_TX_NEG_EDGE;
568 
569  RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, SD20_TX_SEL_MASK, val);
570 
571  if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_AUTO) {
572  if (chip->asic_code) {
573  if (CHK_SD_HS(sd_card) || CHK_MMC_52M(sd_card))
574  val = SD20_RX_14_DELAY;
575  else
576  val = SD20_RX_POS_EDGE;
577  } else {
578  val = SD20_RX_14_DELAY;
579  }
580  } else if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_DELAY) {
581  val = SD20_RX_14_DELAY;
582  } else {
583  val = SD20_RX_POS_EDGE;
584  }
585  RTSX_WRITE_REG(chip, SD_SAMPLE_POINT_CTL, SD20_RX_SEL_MASK, val);
586  }
587  } else {
588  u8 val = 0;
589 
590  if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_DELAY)
591  val |= 0x10;
592 
593  if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_AUTO) {
594  if (chip->asic_code) {
595  if (CHK_SD_HS(sd_card) || CHK_MMC_52M(sd_card)) {
596  if (val & 0x10)
597  val |= 0x04;
598  else
599  val |= 0x08;
600  }
601  } else {
602  if (val & 0x10)
603  val |= 0x04;
604  else
605  val |= 0x08;
606  }
607  } else if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_DELAY) {
608  if (val & 0x10)
609  val |= 0x04;
610  else
611  val |= 0x08;
612  }
613 
614  RTSX_WRITE_REG(chip, REG_SD_CFG1, 0x1C, val);
615  }
616 
617  return STATUS_SUCCESS;
618 }
619 
620 static void sd_choose_proper_clock(struct rtsx_chip *chip)
621 {
622  struct sd_info *sd_card = &(chip->sd_card);
623 
624  if (CHK_SD_SDR104(sd_card)) {
625  if (chip->asic_code)
626  sd_card->sd_clock = chip->asic_sd_sdr104_clk;
627  else
628  sd_card->sd_clock = chip->fpga_sd_sdr104_clk;
629 
630  } else if (CHK_SD_DDR50(sd_card)) {
631  if (chip->asic_code)
632  sd_card->sd_clock = chip->asic_sd_ddr50_clk;
633  else
634  sd_card->sd_clock = chip->fpga_sd_ddr50_clk;
635 
636  } else if (CHK_SD_SDR50(sd_card)) {
637  if (chip->asic_code)
638  sd_card->sd_clock = chip->asic_sd_sdr50_clk;
639  else
640  sd_card->sd_clock = chip->fpga_sd_sdr50_clk;
641 
642  } else if (CHK_SD_HS(sd_card)) {
643  if (chip->asic_code)
644  sd_card->sd_clock = chip->asic_sd_hs_clk;
645  else
646  sd_card->sd_clock = chip->fpga_sd_hs_clk;
647 
648  } else if (CHK_MMC_52M(sd_card) || CHK_MMC_DDR52(sd_card)) {
649  if (chip->asic_code)
650  sd_card->sd_clock = chip->asic_mmc_52m_clk;
651  else
652  sd_card->sd_clock = chip->fpga_mmc_52m_clk;
653 
654  } else if (CHK_MMC_26M(sd_card)) {
655  if (chip->asic_code)
656  sd_card->sd_clock = 48;
657  else
658  sd_card->sd_clock = CLK_50;
659  }
660 }
661 
662 static int sd_set_clock_divider(struct rtsx_chip *chip, u8 clk_div)
663 {
664  u8 mask = 0, val = 0;
665 
666  if (CHECK_PID(chip, 0x5209)) {
667  mask = SD_CLK_DIVIDE_MASK;
668  val = clk_div;
669  } else {
670  mask = 0x60;
671  if (clk_div == SD_CLK_DIVIDE_0)
672  val = 0x00;
673  else if (clk_div == SD_CLK_DIVIDE_128)
674  val = 0x40;
675  else if (clk_div == SD_CLK_DIVIDE_256)
676  val = 0x20;
677  }
678 
679  RTSX_WRITE_REG(chip, REG_SD_CFG1, mask, val);
680 
681  return STATUS_SUCCESS;
682 }
683 
684 static int sd_set_init_para(struct rtsx_chip *chip)
685 {
686  struct sd_info *sd_card = &(chip->sd_card);
687  int retval;
688 
689  retval = sd_set_sample_push_timing(chip);
690  if (retval != STATUS_SUCCESS)
691  TRACE_RET(chip, STATUS_FAIL);
692 
693  sd_choose_proper_clock(chip);
694 
695  retval = switch_clock(chip, sd_card->sd_clock);
696  if (retval != STATUS_SUCCESS)
697  TRACE_RET(chip, STATUS_FAIL);
698 
699  return STATUS_SUCCESS;
700 }
701 
702 int sd_select_card(struct rtsx_chip *chip, int select)
703 {
704  struct sd_info *sd_card = &(chip->sd_card);
705  int retval;
706  u8 cmd_idx, cmd_type;
707  u32 addr;
708 
709  if (select) {
710  cmd_idx = SELECT_CARD;
711  cmd_type = SD_RSP_TYPE_R1;
712  addr = sd_card->sd_addr;
713  } else {
714  cmd_idx = DESELECT_CARD;
715  cmd_type = SD_RSP_TYPE_R0;
716  addr = 0;
717  }
718 
719  retval = sd_send_cmd_get_rsp(chip, cmd_idx, addr, cmd_type, NULL, 0);
720  if (retval != STATUS_SUCCESS)
721  TRACE_RET(chip, STATUS_FAIL);
722 
723  return STATUS_SUCCESS;
724 }
725 
726 #ifdef SUPPORT_SD_LOCK
727 static int sd_update_lock_status(struct rtsx_chip *chip)
728 {
729  struct sd_info *sd_card = &(chip->sd_card);
730  int retval;
731  u8 rsp[5];
732 
733  retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, rsp, 5);
734  if (retval != STATUS_SUCCESS)
735  TRACE_RET(chip, STATUS_FAIL);
736 
737  if (rsp[1] & 0x02)
738  sd_card->sd_lock_status |= SD_LOCKED;
739  else
740  sd_card->sd_lock_status &= ~SD_LOCKED;
741 
742  RTSX_DEBUGP("sd_card->sd_lock_status = 0x%x\n", sd_card->sd_lock_status);
743 
744  if (rsp[1] & 0x01)
745  TRACE_RET(chip, STATUS_FAIL);
746 
747  return STATUS_SUCCESS;
748 }
749 #endif
750 
751 static int sd_wait_state_data_ready(struct rtsx_chip *chip, u8 state, u8 data_ready, int polling_cnt)
752 {
753  struct sd_info *sd_card = &(chip->sd_card);
754  int retval, i;
755  u8 rsp[5];
756 
757  for (i = 0; i < polling_cnt; i++) {
758  retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
759  sd_card->sd_addr, SD_RSP_TYPE_R1, rsp, 5);
760  if (retval != STATUS_SUCCESS)
761  TRACE_RET(chip, STATUS_FAIL);
762 
763  if (((rsp[3] & 0x1E) == state) && ((rsp[3] & 0x01) == data_ready))
764  return STATUS_SUCCESS;
765  }
766 
767  TRACE_RET(chip, STATUS_FAIL);
768 }
769 
770 static int sd_change_bank_voltage(struct rtsx_chip *chip, u8 voltage)
771 {
772  int retval;
773 
774  if (voltage == SD_IO_3V3) {
775  if (chip->asic_code) {
776  retval = rtsx_write_phy_register(chip, 0x08, 0x4FC0 | chip->phy_voltage);
777  if (retval != STATUS_SUCCESS)
778  TRACE_RET(chip, STATUS_FAIL);
779  } else {
780  RTSX_WRITE_REG(chip, SD_PAD_CTL, SD_IO_USING_1V8, 0);
781  }
782  } else if (voltage == SD_IO_1V8) {
783  if (chip->asic_code) {
784  retval = rtsx_write_phy_register(chip, 0x08, 0x4C40 | chip->phy_voltage);
785  if (retval != STATUS_SUCCESS)
786  TRACE_RET(chip, STATUS_FAIL);
787  } else {
788  RTSX_WRITE_REG(chip, SD_PAD_CTL, SD_IO_USING_1V8, SD_IO_USING_1V8);
789  }
790  } else {
791  TRACE_RET(chip, STATUS_FAIL);
792  }
793 
794  return STATUS_SUCCESS;
795 }
796 
797 static int sd_voltage_switch(struct rtsx_chip *chip)
798 {
799  int retval;
800  u8 stat;
801 
802  RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, SD_CLK_TOGGLE_EN);
803 
804  retval = sd_send_cmd_get_rsp(chip, VOLTAGE_SWITCH, 0, SD_RSP_TYPE_R1, NULL, 0);
805  if (retval != STATUS_SUCCESS)
806  TRACE_RET(chip, STATUS_FAIL);
807 
808  udelay(chip->sd_voltage_switch_delay);
809 
810  RTSX_READ_REG(chip, SD_BUS_STAT, &stat);
811  if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
812  SD_DAT1_STATUS | SD_DAT0_STATUS)) {
813  TRACE_RET(chip, STATUS_FAIL);
814  }
815 
816  RTSX_WRITE_REG(chip, SD_BUS_STAT, 0xFF, SD_CLK_FORCE_STOP);
817  retval = sd_change_bank_voltage(chip, SD_IO_1V8);
818  if (retval != STATUS_SUCCESS)
819  TRACE_RET(chip, STATUS_FAIL);
820 
821  wait_timeout(50);
822 
823  RTSX_WRITE_REG(chip, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN);
824  wait_timeout(10);
825 
826  RTSX_READ_REG(chip, SD_BUS_STAT, &stat);
827  if ((stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
828  SD_DAT1_STATUS | SD_DAT0_STATUS)) !=
829  (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
830  SD_DAT1_STATUS | SD_DAT0_STATUS)) {
831  RTSX_DEBUGP("SD_BUS_STAT: 0x%x\n", stat);
832  rtsx_write_register(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
833  rtsx_write_register(chip, CARD_CLK_EN, 0xFF, 0);
834  TRACE_RET(chip, STATUS_FAIL);
835  }
836 
837  RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
838 
839  return STATUS_SUCCESS;
840 }
841 
842 static int sd_reset_dcm(struct rtsx_chip *chip, u8 tune_dir)
843 {
844  if (tune_dir == TUNE_RX) {
845  RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RESET | DCM_RX);
846  RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RX);
847  } else {
848  RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_RESET | DCM_TX);
849  RTSX_WRITE_REG(chip, DCM_DRP_CTL, 0xFF, DCM_TX);
850  }
851 
852  return STATUS_SUCCESS;
853 }
854 
855 static int sd_change_phase(struct rtsx_chip *chip, u8 sample_point, u8 tune_dir)
856 {
857  struct sd_info *sd_card = &(chip->sd_card);
858  u16 SD_VP_CTL, SD_DCMPS_CTL;
859  u8 val;
860  int retval;
861  int ddr_rx = 0;
862 
863  RTSX_DEBUGP("sd_change_phase (sample_point = %d, tune_dir = %d)\n",
864  sample_point, tune_dir);
865 
866  if (tune_dir == TUNE_RX) {
867  SD_VP_CTL = SD_VPRX_CTL;
868  SD_DCMPS_CTL = SD_DCMPS_RX_CTL;
869  if (CHK_SD_DDR50(sd_card))
870  ddr_rx = 1;
871  } else {
872  SD_VP_CTL = SD_VPTX_CTL;
873  SD_DCMPS_CTL = SD_DCMPS_TX_CTL;
874  }
875 
876  if (chip->asic_code) {
877  RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
878  RTSX_WRITE_REG(chip, SD_VP_CTL, 0x1F, sample_point);
879  RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0);
880  RTSX_WRITE_REG(chip, SD_VPCLK0_CTL, PHASE_NOT_RESET, PHASE_NOT_RESET);
881  RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, 0);
882  } else {
883 #ifdef CONFIG_RTS_PSTOR_DEBUG
884  rtsx_read_register(chip, SD_VP_CTL, &val);
885  RTSX_DEBUGP("SD_VP_CTL: 0x%x\n", val);
886  rtsx_read_register(chip, SD_DCMPS_CTL, &val);
887  RTSX_DEBUGP("SD_DCMPS_CTL: 0x%x\n", val);
888 #endif
889 
890  if (ddr_rx) {
891  RTSX_WRITE_REG(chip, SD_VP_CTL, PHASE_CHANGE, PHASE_CHANGE);
892  udelay(50);
893  RTSX_WRITE_REG(chip, SD_VP_CTL, 0xFF,
894  PHASE_CHANGE | PHASE_NOT_RESET | sample_point);
895  } else {
896  RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, CHANGE_CLK);
897  udelay(50);
898  RTSX_WRITE_REG(chip, SD_VP_CTL, 0xFF,
899  PHASE_NOT_RESET | sample_point);
900  }
901  udelay(100);
902 
903  rtsx_init_cmd(chip);
904  rtsx_add_cmd(chip, WRITE_REG_CMD, SD_DCMPS_CTL, DCMPS_CHANGE, DCMPS_CHANGE);
905  rtsx_add_cmd(chip, CHECK_REG_CMD, SD_DCMPS_CTL, DCMPS_CHANGE_DONE, DCMPS_CHANGE_DONE);
906  retval = rtsx_send_cmd(chip, SD_CARD, 100);
907  if (retval != STATUS_SUCCESS)
908  TRACE_GOTO(chip, Fail);
909 
910  val = *rtsx_get_cmd_data(chip);
911  if (val & DCMPS_ERROR)
912  TRACE_GOTO(chip, Fail);
913 
914  if ((val & DCMPS_CURRENT_PHASE) != sample_point)
915  TRACE_GOTO(chip, Fail);
916 
917  RTSX_WRITE_REG(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0);
918  if (ddr_rx)
919  RTSX_WRITE_REG(chip, SD_VP_CTL, PHASE_CHANGE, 0);
920  else
921  RTSX_WRITE_REG(chip, CLK_CTL, CHANGE_CLK, 0);
922 
923  udelay(50);
924  }
925 
926  RTSX_WRITE_REG(chip, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
927 
928  return STATUS_SUCCESS;
929 
930 Fail:
931 #ifdef CONFIG_RTS_PSTOR_DEBUG
932  rtsx_read_register(chip, SD_VP_CTL, &val);
933  RTSX_DEBUGP("SD_VP_CTL: 0x%x\n", val);
934  rtsx_read_register(chip, SD_DCMPS_CTL, &val);
935  RTSX_DEBUGP("SD_DCMPS_CTL: 0x%x\n", val);
936 #endif
937 
938  rtsx_write_register(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0);
939  rtsx_write_register(chip, SD_VP_CTL, PHASE_CHANGE, 0);
940  wait_timeout(10);
941  sd_reset_dcm(chip, tune_dir);
942  return STATUS_FAIL;
943 }
944 
945 static int sd_check_spec(struct rtsx_chip *chip, u8 bus_width)
946 {
947  struct sd_info *sd_card = &(chip->sd_card);
948  int retval;
949  u8 cmd[5], buf[8];
950 
951  retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
952  if (retval != STATUS_SUCCESS)
953  TRACE_RET(chip, STATUS_FAIL);
954 
955  cmd[0] = 0x40 | SEND_SCR;
956  cmd[1] = 0;
957  cmd[2] = 0;
958  cmd[3] = 0;
959  cmd[4] = 0;
960 
961  retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 8, 1, bus_width, buf, 8, 250);
962  if (retval != STATUS_SUCCESS) {
963  rtsx_clear_sd_error(chip);
964  TRACE_RET(chip, STATUS_FAIL);
965  }
966 
967  memcpy(sd_card->raw_scr, buf, 8);
968 
969  if ((buf[0] & 0x0F) == 0)
970  TRACE_RET(chip, STATUS_FAIL);
971 
972  return STATUS_SUCCESS;
973 }
974 
975 static int sd_query_switch_result(struct rtsx_chip *chip, u8 func_group, u8 func_to_switch,
976  u8 *buf, int buf_len)
977 {
978  u8 support_mask = 0, query_switch = 0, switch_busy = 0;
979  int support_offset = 0, query_switch_offset = 0, check_busy_offset = 0;
980 
981  if (func_group == SD_FUNC_GROUP_1) {
982  support_offset = FUNCTION_GROUP1_SUPPORT_OFFSET;
983  query_switch_offset = FUNCTION_GROUP1_QUERY_SWITCH_OFFSET;
984  check_busy_offset = FUNCTION_GROUP1_CHECK_BUSY_OFFSET;
985 
986  switch (func_to_switch) {
987  case HS_SUPPORT:
988  support_mask = HS_SUPPORT_MASK;
989  query_switch = HS_QUERY_SWITCH_OK;
990  switch_busy = HS_SWITCH_BUSY;
991  break;
992 
993  case SDR50_SUPPORT:
994  support_mask = SDR50_SUPPORT_MASK;
995  query_switch = SDR50_QUERY_SWITCH_OK;
996  switch_busy = SDR50_SWITCH_BUSY;
997  break;
998 
999  case SDR104_SUPPORT:
1000  support_mask = SDR104_SUPPORT_MASK;
1001  query_switch = SDR104_QUERY_SWITCH_OK;
1002  switch_busy = SDR104_SWITCH_BUSY;
1003  break;
1004 
1005  case DDR50_SUPPORT:
1006  support_mask = DDR50_SUPPORT_MASK;
1007  query_switch = DDR50_QUERY_SWITCH_OK;
1008  switch_busy = DDR50_SWITCH_BUSY;
1009  break;
1010 
1011  default:
1012  TRACE_RET(chip, STATUS_FAIL);
1013  }
1014  } else if (func_group == SD_FUNC_GROUP_3) {
1015  support_offset = FUNCTION_GROUP3_SUPPORT_OFFSET;
1016  query_switch_offset = FUNCTION_GROUP3_QUERY_SWITCH_OFFSET;
1017  check_busy_offset = FUNCTION_GROUP3_CHECK_BUSY_OFFSET;
1018 
1019  switch (func_to_switch) {
1020  case DRIVING_TYPE_A:
1021  support_mask = DRIVING_TYPE_A_MASK;
1022  query_switch = TYPE_A_QUERY_SWITCH_OK;
1023  switch_busy = TYPE_A_SWITCH_BUSY;
1024  break;
1025 
1026  case DRIVING_TYPE_C:
1027  support_mask = DRIVING_TYPE_C_MASK;
1028  query_switch = TYPE_C_QUERY_SWITCH_OK;
1029  switch_busy = TYPE_C_SWITCH_BUSY;
1030  break;
1031 
1032  case DRIVING_TYPE_D:
1033  support_mask = DRIVING_TYPE_D_MASK;
1034  query_switch = TYPE_D_QUERY_SWITCH_OK;
1035  switch_busy = TYPE_D_SWITCH_BUSY;
1036  break;
1037 
1038  default:
1039  TRACE_RET(chip, STATUS_FAIL);
1040  }
1041  } else if (func_group == SD_FUNC_GROUP_4) {
1042  support_offset = FUNCTION_GROUP4_SUPPORT_OFFSET;
1043  query_switch_offset = FUNCTION_GROUP4_QUERY_SWITCH_OFFSET;
1044  check_busy_offset = FUNCTION_GROUP4_CHECK_BUSY_OFFSET;
1045 
1046  switch (func_to_switch) {
1047  case CURRENT_LIMIT_400:
1048  support_mask = CURRENT_LIMIT_400_MASK;
1049  query_switch = CURRENT_LIMIT_400_QUERY_SWITCH_OK;
1050  switch_busy = CURRENT_LIMIT_400_SWITCH_BUSY;
1051  break;
1052 
1053  case CURRENT_LIMIT_600:
1054  support_mask = CURRENT_LIMIT_600_MASK;
1055  query_switch = CURRENT_LIMIT_600_QUERY_SWITCH_OK;
1056  switch_busy = CURRENT_LIMIT_600_SWITCH_BUSY;
1057  break;
1058 
1059  case CURRENT_LIMIT_800:
1060  support_mask = CURRENT_LIMIT_800_MASK;
1061  query_switch = CURRENT_LIMIT_800_QUERY_SWITCH_OK;
1062  switch_busy = CURRENT_LIMIT_800_SWITCH_BUSY;
1063  break;
1064 
1065  default:
1066  TRACE_RET(chip, STATUS_FAIL);
1067  }
1068  } else {
1069  TRACE_RET(chip, STATUS_FAIL);
1070  }
1071 
1072  if (func_group == SD_FUNC_GROUP_1) {
1073  if (!(buf[support_offset] & support_mask) ||
1074  ((buf[query_switch_offset] & 0x0F) != query_switch)) {
1075  TRACE_RET(chip, STATUS_FAIL);
1076  }
1077  }
1078 
1079  /* Check 'Busy Status' */
1080  if ((buf[DATA_STRUCTURE_VER_OFFSET] == 0x01) &&
1081  ((buf[check_busy_offset] & switch_busy) == switch_busy)) {
1082  TRACE_RET(chip, STATUS_FAIL);
1083  }
1084 
1085  return STATUS_SUCCESS;
1086 }
1087 
1088 static int sd_check_switch_mode(struct rtsx_chip *chip, u8 mode,
1089  u8 func_group, u8 func_to_switch, u8 bus_width)
1090 {
1091  struct sd_info *sd_card = &(chip->sd_card);
1092  int retval;
1093  u8 cmd[5], buf[64];
1094 
1095  RTSX_DEBUGP("sd_check_switch_mode (mode = %d, func_group = %d, func_to_switch = %d)\n",
1096  mode, func_group, func_to_switch);
1097 
1098  cmd[0] = 0x40 | SWITCH;
1099  cmd[1] = mode;
1100 
1101  if (func_group == SD_FUNC_GROUP_1) {
1102  cmd[2] = 0xFF;
1103  cmd[3] = 0xFF;
1104  cmd[4] = 0xF0 + func_to_switch;
1105  } else if (func_group == SD_FUNC_GROUP_3) {
1106  cmd[2] = 0xFF;
1107  cmd[3] = 0xF0 + func_to_switch;
1108  cmd[4] = 0xFF;
1109  } else if (func_group == SD_FUNC_GROUP_4) {
1110  cmd[2] = 0xFF;
1111  cmd[3] = 0x0F + (func_to_switch << 4);
1112  cmd[4] = 0xFF;
1113  } else {
1114  cmd[1] = SD_CHECK_MODE;
1115  cmd[2] = 0xFF;
1116  cmd[3] = 0xFF;
1117  cmd[4] = 0xFF;
1118  }
1119 
1120  retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1, bus_width, buf, 64, 250);
1121  if (retval != STATUS_SUCCESS) {
1122  rtsx_clear_sd_error(chip);
1123  TRACE_RET(chip, STATUS_FAIL);
1124  }
1125 
1126  RTSX_DUMP(buf, 64);
1127 
1128  if (func_group == NO_ARGUMENT) {
1129  sd_card->func_group1_mask = buf[0x0D];
1130  sd_card->func_group2_mask = buf[0x0B];
1131  sd_card->func_group3_mask = buf[0x09];
1132  sd_card->func_group4_mask = buf[0x07];
1133 
1134  RTSX_DEBUGP("func_group1_mask = 0x%02x\n", buf[0x0D]);
1135  RTSX_DEBUGP("func_group2_mask = 0x%02x\n", buf[0x0B]);
1136  RTSX_DEBUGP("func_group3_mask = 0x%02x\n", buf[0x09]);
1137  RTSX_DEBUGP("func_group4_mask = 0x%02x\n", buf[0x07]);
1138  } else {
1139  /* Maximum current consumption, check whether current is acceptable;
1140  * bit[511:496] = 0x0000 means some error happened.
1141  */
1142  u16 cc = ((u16)buf[0] << 8) | buf[1];
1143  RTSX_DEBUGP("Maximum current consumption: %dmA\n", cc);
1144  if ((cc == 0) || (cc > 800))
1145  TRACE_RET(chip, STATUS_FAIL);
1146 
1147  retval = sd_query_switch_result(chip, func_group, func_to_switch, buf, 64);
1148  if (retval != STATUS_SUCCESS)
1149  TRACE_RET(chip, STATUS_FAIL);
1150 
1151  if ((cc > 400) || (func_to_switch > CURRENT_LIMIT_400)) {
1152  RTSX_WRITE_REG(chip, OCPPARA2, SD_OCP_THD_MASK, chip->sd_800mA_ocp_thd);
1153  RTSX_WRITE_REG(chip, CARD_PWR_CTL, PMOS_STRG_MASK, PMOS_STRG_800mA);
1154  }
1155  }
1156 
1157  return STATUS_SUCCESS;
1158 }
1159 
1160 static u8 downgrade_switch_mode(u8 func_group, u8 func_to_switch)
1161 {
1162  if (func_group == SD_FUNC_GROUP_1) {
1163  if (func_to_switch > HS_SUPPORT)
1164  func_to_switch--;
1165 
1166  } else if (func_group == SD_FUNC_GROUP_4) {
1167  if (func_to_switch > CURRENT_LIMIT_200)
1168  func_to_switch--;
1169  }
1170 
1171  return func_to_switch;
1172 }
1173 
1174 static int sd_check_switch(struct rtsx_chip *chip,
1175  u8 func_group, u8 func_to_switch, u8 bus_width)
1176 {
1177  int retval;
1178  int i;
1179  int switch_good = 0;
1180 
1181  for (i = 0; i < 3; i++) {
1182  if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1183  sd_set_err_code(chip, SD_NO_CARD);
1184  TRACE_RET(chip, STATUS_FAIL);
1185  }
1186 
1187  retval = sd_check_switch_mode(chip, SD_CHECK_MODE, func_group,
1188  func_to_switch, bus_width);
1189  if (retval == STATUS_SUCCESS) {
1190  u8 stat;
1191 
1192  retval = sd_check_switch_mode(chip, SD_SWITCH_MODE,
1193  func_group, func_to_switch, bus_width);
1194  if (retval == STATUS_SUCCESS) {
1195  switch_good = 1;
1196  break;
1197  }
1198 
1199  RTSX_READ_REG(chip, SD_STAT1, &stat);
1200  if (stat & SD_CRC16_ERR) {
1201  RTSX_DEBUGP("SD CRC16 error when switching mode\n");
1202  TRACE_RET(chip, STATUS_FAIL);
1203  }
1204  }
1205 
1206  func_to_switch = downgrade_switch_mode(func_group, func_to_switch);
1207 
1208  wait_timeout(20);
1209  }
1210 
1211  if (!switch_good)
1212  TRACE_RET(chip, STATUS_FAIL);
1213 
1214  return STATUS_SUCCESS;
1215 }
1216 
1217 static int sd_switch_function(struct rtsx_chip *chip, u8 bus_width)
1218 {
1219  struct sd_info *sd_card = &(chip->sd_card);
1220  int retval;
1221  int i;
1222  u8 func_to_switch = 0;
1223 
1224  /* Get supported functions */
1225  retval = sd_check_switch_mode(chip, SD_CHECK_MODE,
1226  NO_ARGUMENT, NO_ARGUMENT, bus_width);
1227  if (retval != STATUS_SUCCESS)
1228  TRACE_RET(chip, STATUS_FAIL);
1229 
1230  sd_card->func_group1_mask &= ~(sd_card->sd_switch_fail);
1231 
1232  /* Function Group 1: Access Mode */
1233  for (i = 0; i < 4; i++) {
1234  switch ((u8)(chip->sd_speed_prior >> (i*8))) {
1235  case SDR104_SUPPORT:
1236  if ((sd_card->func_group1_mask & SDR104_SUPPORT_MASK)
1237  && chip->sdr104_en) {
1238  func_to_switch = SDR104_SUPPORT;
1239  }
1240  break;
1241 
1242  case DDR50_SUPPORT:
1243  if ((sd_card->func_group1_mask & DDR50_SUPPORT_MASK)
1244  && chip->ddr50_en) {
1245  func_to_switch = DDR50_SUPPORT;
1246  }
1247  break;
1248 
1249  case SDR50_SUPPORT:
1250  if ((sd_card->func_group1_mask & SDR50_SUPPORT_MASK)
1251  && chip->sdr50_en) {
1252  func_to_switch = SDR50_SUPPORT;
1253  }
1254  break;
1255 
1256  case HS_SUPPORT:
1257  if (sd_card->func_group1_mask & HS_SUPPORT_MASK)
1258  func_to_switch = HS_SUPPORT;
1259 
1260  break;
1261 
1262  default:
1263  continue;
1264  }
1265 
1266 
1267  if (func_to_switch)
1268  break;
1269 
1270  }
1271  RTSX_DEBUGP("SD_FUNC_GROUP_1: func_to_switch = 0x%02x", func_to_switch);
1272 
1273 #ifdef SUPPORT_SD_LOCK
1274  if ((sd_card->sd_lock_status & SD_SDR_RST)
1275  && (DDR50_SUPPORT == func_to_switch)
1276  && (sd_card->func_group1_mask & SDR50_SUPPORT_MASK)) {
1277  func_to_switch = SDR50_SUPPORT;
1278  RTSX_DEBUGP("Using SDR50 instead of DDR50 for SD Lock\n");
1279  }
1280 #endif
1281 
1282  if (func_to_switch) {
1283  retval = sd_check_switch(chip, SD_FUNC_GROUP_1, func_to_switch, bus_width);
1284  if (retval != STATUS_SUCCESS) {
1285  if (func_to_switch == SDR104_SUPPORT) {
1286  sd_card->sd_switch_fail = SDR104_SUPPORT_MASK;
1287  } else if (func_to_switch == DDR50_SUPPORT) {
1288  sd_card->sd_switch_fail =
1289  SDR104_SUPPORT_MASK | DDR50_SUPPORT_MASK;
1290  } else if (func_to_switch == SDR50_SUPPORT) {
1291  sd_card->sd_switch_fail =
1292  SDR104_SUPPORT_MASK | DDR50_SUPPORT_MASK |
1293  SDR50_SUPPORT_MASK;
1294  }
1295  TRACE_RET(chip, STATUS_FAIL);
1296  }
1297 
1298  if (func_to_switch == SDR104_SUPPORT)
1299  SET_SD_SDR104(sd_card);
1300  else if (func_to_switch == DDR50_SUPPORT)
1301  SET_SD_DDR50(sd_card);
1302  else if (func_to_switch == SDR50_SUPPORT)
1303  SET_SD_SDR50(sd_card);
1304  else
1305  SET_SD_HS(sd_card);
1306  }
1307 
1308  if (CHK_SD_DDR50(sd_card)) {
1309  RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, 0x06, 0x04);
1310  retval = sd_set_sample_push_timing(chip);
1311  if (retval != STATUS_SUCCESS)
1312  TRACE_RET(chip, STATUS_FAIL);
1313  }
1314 
1315  if (!func_to_switch || (func_to_switch == HS_SUPPORT)) {
1316  /* Do not try to switch current limit if the card doesn't
1317  * support UHS mode or we don't want it to support UHS mode
1318  */
1319  return STATUS_SUCCESS;
1320  }
1321 
1322  /* Function Group 4: Current Limit */
1323  func_to_switch = 0xFF;
1324 
1325  for (i = 0; i < 4; i++) {
1326  switch ((u8)(chip->sd_current_prior >> (i*8))) {
1327  case CURRENT_LIMIT_800:
1328  if (sd_card->func_group4_mask & CURRENT_LIMIT_800_MASK)
1329  func_to_switch = CURRENT_LIMIT_800;
1330 
1331  break;
1332 
1333  case CURRENT_LIMIT_600:
1334  if (sd_card->func_group4_mask & CURRENT_LIMIT_600_MASK)
1335  func_to_switch = CURRENT_LIMIT_600;
1336 
1337  break;
1338 
1339  case CURRENT_LIMIT_400:
1340  if (sd_card->func_group4_mask & CURRENT_LIMIT_400_MASK)
1341  func_to_switch = CURRENT_LIMIT_400;
1342 
1343  break;
1344 
1345  case CURRENT_LIMIT_200:
1346  if (sd_card->func_group4_mask & CURRENT_LIMIT_200_MASK)
1347  func_to_switch = CURRENT_LIMIT_200;
1348 
1349  break;
1350 
1351  default:
1352  continue;
1353  }
1354 
1355  if (func_to_switch != 0xFF)
1356  break;
1357  }
1358 
1359  RTSX_DEBUGP("SD_FUNC_GROUP_4: func_to_switch = 0x%02x", func_to_switch);
1360 
1361  if (func_to_switch <= CURRENT_LIMIT_800) {
1362  retval = sd_check_switch(chip, SD_FUNC_GROUP_4, func_to_switch, bus_width);
1363  if (retval != STATUS_SUCCESS) {
1364  if (sd_check_err_code(chip, SD_NO_CARD))
1365  TRACE_RET(chip, STATUS_FAIL);
1366  }
1367  RTSX_DEBUGP("Switch current limit finished! (%d)\n", retval);
1368  }
1369 
1370  if (CHK_SD_DDR50(sd_card))
1371  RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, 0x06, 0);
1372 
1373  return STATUS_SUCCESS;
1374 }
1375 
1376 static int sd_wait_data_idle(struct rtsx_chip *chip)
1377 {
1378  int retval = STATUS_TIMEDOUT;
1379  int i;
1380  u8 val = 0;
1381 
1382  for (i = 0; i < 100; i++) {
1383  RTSX_READ_REG(chip, SD_DATA_STATE, &val);
1384  if (val & SD_DATA_IDLE) {
1385  retval = STATUS_SUCCESS;
1386  break;
1387  }
1388  udelay(100);
1389  }
1390  RTSX_DEBUGP("SD_DATA_STATE: 0x%02x\n", val);
1391 
1392  return retval;
1393 }
1394 
1395 static int sd_sdr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1396 {
1397  int retval;
1398  u8 cmd[5];
1399 
1400  retval = sd_change_phase(chip, sample_point, TUNE_RX);
1401  if (retval != STATUS_SUCCESS)
1402  TRACE_RET(chip, STATUS_FAIL);
1403 
1404  cmd[0] = 0x40 | SEND_TUNING_PATTERN;
1405  cmd[1] = 0;
1406  cmd[2] = 0;
1407  cmd[3] = 0;
1408  cmd[4] = 0;
1409 
1410  retval = sd_read_data(chip, SD_TM_AUTO_TUNING,
1411  cmd, 5, 0x40, 1, SD_BUS_WIDTH_4, NULL, 0, 100);
1412  if (retval != STATUS_SUCCESS) {
1413  (void)sd_wait_data_idle(chip);
1414 
1415  rtsx_clear_sd_error(chip);
1416  TRACE_RET(chip, STATUS_FAIL);
1417  }
1418 
1419  return STATUS_SUCCESS;
1420 }
1421 
1422 static int sd_ddr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1423 {
1424  struct sd_info *sd_card = &(chip->sd_card);
1425  int retval;
1426  u8 cmd[5];
1427 
1428  retval = sd_change_phase(chip, sample_point, TUNE_RX);
1429  if (retval != STATUS_SUCCESS)
1430  TRACE_RET(chip, STATUS_FAIL);
1431 
1432  RTSX_DEBUGP("sd ddr tuning rx\n");
1433 
1434  retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
1435  if (retval != STATUS_SUCCESS)
1436  TRACE_RET(chip, STATUS_FAIL);
1437 
1438  cmd[0] = 0x40 | SD_STATUS;
1439  cmd[1] = 0;
1440  cmd[2] = 0;
1441  cmd[3] = 0;
1442  cmd[4] = 0;
1443 
1444  retval = sd_read_data(chip, SD_TM_NORMAL_READ,
1445  cmd, 5, 64, 1, SD_BUS_WIDTH_4, NULL, 0, 100);
1446  if (retval != STATUS_SUCCESS) {
1447  (void)sd_wait_data_idle(chip);
1448 
1449  rtsx_clear_sd_error(chip);
1450  TRACE_RET(chip, STATUS_FAIL);
1451  }
1452 
1453  return STATUS_SUCCESS;
1454 }
1455 
1456 static int mmc_ddr_tunning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1457 {
1458  struct sd_info *sd_card = &(chip->sd_card);
1459  int retval;
1460  u8 cmd[5], bus_width;
1461 
1462  if (CHK_MMC_8BIT(sd_card))
1463  bus_width = SD_BUS_WIDTH_8;
1464  else if (CHK_MMC_4BIT(sd_card))
1465  bus_width = SD_BUS_WIDTH_4;
1466  else
1467  bus_width = SD_BUS_WIDTH_1;
1468 
1469  retval = sd_change_phase(chip, sample_point, TUNE_RX);
1470  if (retval != STATUS_SUCCESS)
1471  TRACE_RET(chip, STATUS_FAIL);
1472 
1473  RTSX_DEBUGP("mmc ddr tuning rx\n");
1474 
1475  cmd[0] = 0x40 | SEND_EXT_CSD;
1476  cmd[1] = 0;
1477  cmd[2] = 0;
1478  cmd[3] = 0;
1479  cmd[4] = 0;
1480 
1481  retval = sd_read_data(chip, SD_TM_NORMAL_READ,
1482  cmd, 5, 0x200, 1, bus_width, NULL, 0, 100);
1483  if (retval != STATUS_SUCCESS) {
1484  (void)sd_wait_data_idle(chip);
1485 
1486  rtsx_clear_sd_error(chip);
1487  TRACE_RET(chip, STATUS_FAIL);
1488  }
1489 
1490  return STATUS_SUCCESS;
1491 }
1492 
1493 static int sd_sdr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point)
1494 {
1495  struct sd_info *sd_card = &(chip->sd_card);
1496  int retval;
1497 
1498  retval = sd_change_phase(chip, sample_point, TUNE_TX);
1499  if (retval != STATUS_SUCCESS)
1500  TRACE_RET(chip, STATUS_FAIL);
1501 
1502  RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, SD_RSP_80CLK_TIMEOUT_EN);
1503 
1504  retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
1505  SD_RSP_TYPE_R1, NULL, 0);
1506  if (retval != STATUS_SUCCESS) {
1507  if (sd_check_err_code(chip, SD_RSP_TIMEOUT)) {
1508  rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1509  TRACE_RET(chip, STATUS_FAIL);
1510  }
1511  }
1512 
1513  RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1514 
1515  return STATUS_SUCCESS;
1516 }
1517 
1518 static int sd_ddr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point)
1519 {
1520  struct sd_info *sd_card = &(chip->sd_card);
1521  int retval;
1522  u8 cmd[5], bus_width;
1523 
1524  retval = sd_change_phase(chip, sample_point, TUNE_TX);
1525  if (retval != STATUS_SUCCESS)
1526  TRACE_RET(chip, STATUS_FAIL);
1527 
1528  if (CHK_SD(sd_card)) {
1529  bus_width = SD_BUS_WIDTH_4;
1530  } else {
1531  if (CHK_MMC_8BIT(sd_card))
1532  bus_width = SD_BUS_WIDTH_8;
1533  else if (CHK_MMC_4BIT(sd_card))
1534  bus_width = SD_BUS_WIDTH_4;
1535  else
1536  bus_width = SD_BUS_WIDTH_1;
1537  }
1538 
1539  retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
1540  if (retval != STATUS_SUCCESS)
1541  TRACE_RET(chip, STATUS_FAIL);
1542 
1543  RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, SD_RSP_80CLK_TIMEOUT_EN);
1544 
1545  cmd[0] = 0x40 | PROGRAM_CSD;
1546  cmd[1] = 0;
1547  cmd[2] = 0;
1548  cmd[3] = 0;
1549  cmd[4] = 0;
1550 
1551  retval = sd_write_data(chip, SD_TM_AUTO_WRITE_2,
1552  cmd, 5, 16, 1, bus_width, sd_card->raw_csd, 16, 100);
1553  if (retval != STATUS_SUCCESS) {
1554  rtsx_clear_sd_error(chip);
1555  rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1556  TRACE_RET(chip, STATUS_FAIL);
1557  }
1558 
1559  RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1560 
1561  sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
1562 
1563  return STATUS_SUCCESS;
1564 }
1565 
1566 static u8 sd_search_final_phase(struct rtsx_chip *chip, u32 phase_map, u8 tune_dir)
1567 {
1568  struct sd_info *sd_card = &(chip->sd_card);
1569  struct timing_phase_path path[MAX_PHASE + 1];
1570  int i, j, cont_path_cnt;
1571  int new_block, max_len, final_path_idx;
1572  u8 final_phase = 0xFF;
1573 
1574  if (phase_map == 0xFFFFFFFF) {
1575  if (tune_dir == TUNE_RX)
1576  final_phase = (u8)chip->sd_default_rx_phase;
1577  else
1578  final_phase = (u8)chip->sd_default_tx_phase;
1579 
1580  goto Search_Finish;
1581  }
1582 
1583  cont_path_cnt = 0;
1584  new_block = 1;
1585  j = 0;
1586  for (i = 0; i < MAX_PHASE + 1; i++) {
1587  if (phase_map & (1 << i)) {
1588  if (new_block) {
1589  new_block = 0;
1590  j = cont_path_cnt++;
1591  path[j].start = i;
1592  path[j].end = i;
1593  } else {
1594  path[j].end = i;
1595  }
1596  } else {
1597  new_block = 1;
1598  if (cont_path_cnt) {
1599  int idx = cont_path_cnt - 1;
1600  path[idx].len = path[idx].end - path[idx].start + 1;
1601  path[idx].mid = path[idx].start + path[idx].len / 2;
1602  }
1603  }
1604  }
1605 
1606  if (cont_path_cnt == 0) {
1607  RTSX_DEBUGP("No continuous phase path\n");
1608  goto Search_Finish;
1609  } else {
1610  int idx = cont_path_cnt - 1;
1611  path[idx].len = path[idx].end - path[idx].start + 1;
1612  path[idx].mid = path[idx].start + path[idx].len / 2;
1613  }
1614 
1615  if ((path[0].start == 0) && (path[cont_path_cnt - 1].end == MAX_PHASE)) {
1616  path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1;
1617  path[0].len += path[cont_path_cnt - 1].len;
1618  path[0].mid = path[0].start + path[0].len / 2;
1619  if (path[0].mid < 0)
1620  path[0].mid += MAX_PHASE + 1;
1621 
1622  cont_path_cnt--;
1623  }
1624 
1625  max_len = 0;
1626  final_phase = 0;
1627  final_path_idx = 0;
1628  for (i = 0; i < cont_path_cnt; i++) {
1629  if (path[i].len > max_len) {
1630  max_len = path[i].len;
1631  final_phase = (u8)path[i].mid;
1632  final_path_idx = i;
1633  }
1634 
1635  RTSX_DEBUGP("path[%d].start = %d\n", i, path[i].start);
1636  RTSX_DEBUGP("path[%d].end = %d\n", i, path[i].end);
1637  RTSX_DEBUGP("path[%d].len = %d\n", i, path[i].len);
1638  RTSX_DEBUGP("path[%d].mid = %d\n", i, path[i].mid);
1639  RTSX_DEBUGP("\n");
1640  }
1641 
1642  if (tune_dir == TUNE_TX) {
1643  if (CHK_SD_SDR104(sd_card)) {
1644  if (max_len > 15) {
1645  int temp_mid = (max_len - 16) / 2;
1646  int temp_final_phase =
1647  path[final_path_idx].end - (max_len - (6 + temp_mid));
1648 
1649  if (temp_final_phase < 0)
1650  final_phase = (u8)(temp_final_phase + MAX_PHASE + 1);
1651  else
1652  final_phase = (u8)temp_final_phase;
1653  }
1654  } else if (CHK_SD_SDR50(sd_card)) {
1655  if (max_len > 12) {
1656  int temp_mid = (max_len - 13) / 2;
1657  int temp_final_phase =
1658  path[final_path_idx].end - (max_len - (3 + temp_mid));
1659 
1660  if (temp_final_phase < 0)
1661  final_phase = (u8)(temp_final_phase + MAX_PHASE + 1);
1662  else
1663  final_phase = (u8)temp_final_phase;
1664  }
1665  }
1666  }
1667 
1668 Search_Finish:
1669  RTSX_DEBUGP("Final chosen phase: %d\n", final_phase);
1670  return final_phase;
1671 }
1672 
1673 static int sd_tuning_rx(struct rtsx_chip *chip)
1674 {
1675  struct sd_info *sd_card = &(chip->sd_card);
1676  int retval;
1677  int i, j;
1678  u32 raw_phase_map[3], phase_map;
1679  u8 final_phase;
1680  int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point);
1681 
1682  if (CHK_SD(sd_card)) {
1683  if (CHK_SD_DDR50(sd_card))
1684  tuning_cmd = sd_ddr_tuning_rx_cmd;
1685  else
1686  tuning_cmd = sd_sdr_tuning_rx_cmd;
1687 
1688  } else {
1689  if (CHK_MMC_DDR52(sd_card))
1690  tuning_cmd = mmc_ddr_tunning_rx_cmd;
1691  else
1692  TRACE_RET(chip, STATUS_FAIL);
1693  }
1694 
1695  for (i = 0; i < 3; i++) {
1696  raw_phase_map[i] = 0;
1697  for (j = MAX_PHASE; j >= 0; j--) {
1698  if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1699  sd_set_err_code(chip, SD_NO_CARD);
1700  TRACE_RET(chip, STATUS_FAIL);
1701  }
1702 
1703  retval = tuning_cmd(chip, (u8)j);
1704  if (retval == STATUS_SUCCESS)
1705  raw_phase_map[i] |= 1 << j;
1706  }
1707  }
1708 
1709  phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2];
1710  for (i = 0; i < 3; i++)
1711  RTSX_DEBUGP("RX raw_phase_map[%d] = 0x%08x\n", i, raw_phase_map[i]);
1712 
1713  RTSX_DEBUGP("RX phase_map = 0x%08x\n", phase_map);
1714 
1715  final_phase = sd_search_final_phase(chip, phase_map, TUNE_RX);
1716  if (final_phase == 0xFF)
1717  TRACE_RET(chip, STATUS_FAIL);
1718 
1719  retval = sd_change_phase(chip, final_phase, TUNE_RX);
1720  if (retval != STATUS_SUCCESS)
1721  TRACE_RET(chip, STATUS_FAIL);
1722 
1723  return STATUS_SUCCESS;
1724 }
1725 
1726 static int sd_ddr_pre_tuning_tx(struct rtsx_chip *chip)
1727 {
1728  struct sd_info *sd_card = &(chip->sd_card);
1729  int retval;
1730  int i;
1731  u32 phase_map;
1732  u8 final_phase;
1733 
1734  RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, SD_RSP_80CLK_TIMEOUT_EN);
1735 
1736  phase_map = 0;
1737  for (i = MAX_PHASE; i >= 0; i--) {
1738  if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1739  sd_set_err_code(chip, SD_NO_CARD);
1740  rtsx_write_register(chip, SD_CFG3,
1741  SD_RSP_80CLK_TIMEOUT_EN, 0);
1742  TRACE_RET(chip, STATUS_FAIL);
1743  }
1744 
1745  retval = sd_change_phase(chip, (u8)i, TUNE_TX);
1746  if (retval != STATUS_SUCCESS)
1747  continue;
1748 
1749  retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
1750  SD_RSP_TYPE_R1, NULL, 0);
1751  if ((retval == STATUS_SUCCESS) || !sd_check_err_code(chip, SD_RSP_TIMEOUT))
1752  phase_map |= 1 << i;
1753  }
1754 
1755  RTSX_WRITE_REG(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1756 
1757  RTSX_DEBUGP("DDR TX pre tune phase_map = 0x%08x\n", phase_map);
1758 
1759  final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX);
1760  if (final_phase == 0xFF)
1761  TRACE_RET(chip, STATUS_FAIL);
1762 
1763  retval = sd_change_phase(chip, final_phase, TUNE_TX);
1764  if (retval != STATUS_SUCCESS)
1765  TRACE_RET(chip, STATUS_FAIL);
1766 
1767  RTSX_DEBUGP("DDR TX pre tune phase: %d\n", (int)final_phase);
1768 
1769  return STATUS_SUCCESS;
1770 }
1771 
1772 static int sd_tuning_tx(struct rtsx_chip *chip)
1773 {
1774  struct sd_info *sd_card = &(chip->sd_card);
1775  int retval;
1776  int i, j;
1777  u32 raw_phase_map[3], phase_map;
1778  u8 final_phase;
1779  int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point);
1780 
1781  if (CHK_SD(sd_card)) {
1782  if (CHK_SD_DDR50(sd_card))
1783  tuning_cmd = sd_ddr_tuning_tx_cmd;
1784  else
1785  tuning_cmd = sd_sdr_tuning_tx_cmd;
1786 
1787  } else {
1788  if (CHK_MMC_DDR52(sd_card))
1789  tuning_cmd = sd_ddr_tuning_tx_cmd;
1790  else
1791  TRACE_RET(chip, STATUS_FAIL);
1792  }
1793 
1794  for (i = 0; i < 3; i++) {
1795  raw_phase_map[i] = 0;
1796  for (j = MAX_PHASE; j >= 0; j--) {
1797  if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1798  sd_set_err_code(chip, SD_NO_CARD);
1799  rtsx_write_register(chip, SD_CFG3,
1800  SD_RSP_80CLK_TIMEOUT_EN, 0);
1801  TRACE_RET(chip, STATUS_FAIL);
1802  }
1803 
1804  retval = tuning_cmd(chip, (u8)j);
1805  if (retval == STATUS_SUCCESS)
1806  raw_phase_map[i] |= 1 << j;
1807  }
1808  }
1809 
1810  phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2];
1811  for (i = 0; i < 3; i++)
1812  RTSX_DEBUGP("TX raw_phase_map[%d] = 0x%08x\n", i, raw_phase_map[i]);
1813 
1814  RTSX_DEBUGP("TX phase_map = 0x%08x\n", phase_map);
1815 
1816  final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX);
1817  if (final_phase == 0xFF)
1818  TRACE_RET(chip, STATUS_FAIL);
1819 
1820  retval = sd_change_phase(chip, final_phase, TUNE_TX);
1821  if (retval != STATUS_SUCCESS)
1822  TRACE_RET(chip, STATUS_FAIL);
1823 
1824  return STATUS_SUCCESS;
1825 }
1826 
1827 static int sd_sdr_tuning(struct rtsx_chip *chip)
1828 {
1829  int retval;
1830 
1831  retval = sd_tuning_tx(chip);
1832  if (retval != STATUS_SUCCESS)
1833  TRACE_RET(chip, STATUS_FAIL);
1834 
1835  retval = sd_tuning_rx(chip);
1836  if (retval != STATUS_SUCCESS)
1837  TRACE_RET(chip, STATUS_FAIL);
1838 
1839  return STATUS_SUCCESS;
1840 }
1841 
1842 static int sd_ddr_tuning(struct rtsx_chip *chip)
1843 {
1844  int retval;
1845 
1846  if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) {
1847  retval = sd_ddr_pre_tuning_tx(chip);
1848  if (retval != STATUS_SUCCESS)
1849  TRACE_RET(chip, STATUS_FAIL);
1850  } else {
1851  retval = sd_change_phase(chip, (u8)chip->sd_ddr_tx_phase, TUNE_TX);
1852  if (retval != STATUS_SUCCESS)
1853  TRACE_RET(chip, STATUS_FAIL);
1854  }
1855 
1856  retval = sd_tuning_rx(chip);
1857  if (retval != STATUS_SUCCESS)
1858  TRACE_RET(chip, STATUS_FAIL);
1859 
1860  if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) {
1861  retval = sd_tuning_tx(chip);
1862  if (retval != STATUS_SUCCESS)
1863  TRACE_RET(chip, STATUS_FAIL);
1864  }
1865 
1866  return STATUS_SUCCESS;
1867 }
1868 
1869 static int mmc_ddr_tuning(struct rtsx_chip *chip)
1870 {
1871  int retval;
1872 
1873  if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) {
1874  retval = sd_ddr_pre_tuning_tx(chip);
1875  if (retval != STATUS_SUCCESS)
1876  TRACE_RET(chip, STATUS_FAIL);
1877  } else {
1878  retval = sd_change_phase(chip, (u8)chip->mmc_ddr_tx_phase, TUNE_TX);
1879  if (retval != STATUS_SUCCESS)
1880  TRACE_RET(chip, STATUS_FAIL);
1881  }
1882 
1883  retval = sd_tuning_rx(chip);
1884  if (retval != STATUS_SUCCESS)
1885  TRACE_RET(chip, STATUS_FAIL);
1886 
1887  if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) {
1888  retval = sd_tuning_tx(chip);
1889  if (retval != STATUS_SUCCESS)
1890  TRACE_RET(chip, STATUS_FAIL);
1891  }
1892 
1893  return STATUS_SUCCESS;
1894 }
1895 
1896 int sd_switch_clock(struct rtsx_chip *chip)
1897 {
1898  struct sd_info *sd_card = &(chip->sd_card);
1899  int retval;
1900  int re_tuning = 0;
1901 
1902  retval = select_card(chip, SD_CARD);
1903  if (retval != STATUS_SUCCESS)
1904  TRACE_RET(chip, STATUS_FAIL);
1905 
1906  if (CHECK_PID(chip, 0x5209) &&
1907  (CHK_SD30_SPEED(sd_card) || CHK_MMC_DDR52(sd_card))) {
1908  if (sd_card->need_retune && (sd_card->sd_clock != chip->cur_clk)) {
1909  re_tuning = 1;
1910  sd_card->need_retune = 0;
1911  }
1912  }
1913 
1914  retval = switch_clock(chip, sd_card->sd_clock);
1915  if (retval != STATUS_SUCCESS)
1916  TRACE_RET(chip, STATUS_FAIL);
1917 
1918  if (re_tuning) {
1919  if (CHK_SD(sd_card)) {
1920  if (CHK_SD_DDR50(sd_card))
1921  retval = sd_ddr_tuning(chip);
1922  else
1923  retval = sd_sdr_tuning(chip);
1924  } else {
1925  if (CHK_MMC_DDR52(sd_card))
1926  retval = mmc_ddr_tuning(chip);
1927  }
1928 
1929  if (retval != STATUS_SUCCESS)
1930  TRACE_RET(chip, STATUS_FAIL);
1931  }
1932 
1933  return STATUS_SUCCESS;
1934 }
1935 
1936 static int sd_prepare_reset(struct rtsx_chip *chip)
1937 {
1938  struct sd_info *sd_card = &(chip->sd_card);
1939  int retval;
1940 
1941  if (chip->asic_code)
1942  sd_card->sd_clock = 29;
1943  else
1944  sd_card->sd_clock = CLK_30;
1945 
1946  sd_card->sd_type = 0;
1947  sd_card->seq_mode = 0;
1948  sd_card->sd_data_buf_ready = 0;
1949  sd_card->capacity = 0;
1950 
1951 #ifdef SUPPORT_SD_LOCK
1952  sd_card->sd_lock_status = 0;
1953  sd_card->sd_erase_status = 0;
1954 #endif
1955 
1956  chip->capacity[chip->card2lun[SD_CARD]] = 0;
1957  chip->sd_io = 0;
1958 
1959  retval = sd_set_init_para(chip);
1960  if (retval != STATUS_SUCCESS)
1961  TRACE_RET(chip, retval);
1962 
1963  if (CHECK_PID(chip, 0x5209)) {
1964  RTSX_WRITE_REG(chip, REG_SD_CFG1, 0xFF,
1965  SD_CLK_DIVIDE_128 | SD_20_MODE | SD_BUS_WIDTH_1);
1966  RTSX_WRITE_REG(chip, SD_SAMPLE_POINT_CTL, 0xFF, SD20_RX_POS_EDGE);
1967  RTSX_WRITE_REG(chip, SD_PUSH_POINT_CTL, 0xFF, 0);
1968  } else {
1969  RTSX_WRITE_REG(chip, REG_SD_CFG1, 0xFF, 0x40);
1970  }
1971 
1972  RTSX_WRITE_REG(chip, CARD_STOP, SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
1973 
1974  retval = select_card(chip, SD_CARD);
1975  if (retval != STATUS_SUCCESS)
1976  TRACE_RET(chip, STATUS_FAIL);
1977 
1978  return STATUS_SUCCESS;
1979 }
1980 
1981 static int sd_pull_ctl_disable(struct rtsx_chip *chip)
1982 {
1983  if (CHECK_PID(chip, 0x5209)) {
1984  RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55);
1985  RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55);
1986  RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0xD5);
1987  } else if (CHECK_PID(chip, 0x5208)) {
1988  RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF,
1989  XD_D3_PD | SD_D7_PD | SD_CLK_PD | SD_D5_PD);
1990  RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF,
1991  SD_D6_PD | SD_D0_PD | SD_D1_PD | XD_D5_PD);
1992  RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF,
1993  SD_D4_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
1994  RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF,
1995  XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD);
1996  RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF,
1997  MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
1998  RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF, MS_D5_PD | MS_D4_PD);
1999  } else if (CHECK_PID(chip, 0x5288)) {
2000  if (CHECK_BARO_PKG(chip, QFN)) {
2001  RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55);
2002  RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55);
2003  RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0x4B);
2004  RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x69);
2005  }
2006  }
2007 
2008  return STATUS_SUCCESS;
2009 }
2010 
2011 int sd_pull_ctl_enable(struct rtsx_chip *chip)
2012 {
2013  int retval;
2014 
2015  rtsx_init_cmd(chip);
2016 
2017  if (CHECK_PID(chip, 0x5209)) {
2018  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0xAA);
2019  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0xAA);
2020  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0xE9);
2021  } else if (CHECK_PID(chip, 0x5208)) {
2022  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
2023  XD_D3_PD | SD_DAT7_PU | SD_CLK_NP | SD_D5_PU);
2024  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
2025  SD_D6_PU | SD_D0_PU | SD_D1_PU | XD_D5_PD);
2026  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
2027  SD_D4_PU | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
2028  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
2029  XD_RDY_PD | SD_D3_PU | SD_D2_PU | XD_ALE_PD);
2030  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
2031  MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU);
2032  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, MS_D5_PD | MS_D4_PD);
2033  } else if (CHECK_PID(chip, 0x5288)) {
2034  if (CHECK_BARO_PKG(chip, QFN)) {
2035  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0xA8);
2036  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x5A);
2037  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
2038  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0xAA);
2039  }
2040  }
2041 
2042  retval = rtsx_send_cmd(chip, SD_CARD, 100);
2043  if (retval < 0)
2044  TRACE_RET(chip, STATUS_FAIL);
2045 
2046  return STATUS_SUCCESS;
2047 }
2048 
2049 static int sd_init_power(struct rtsx_chip *chip)
2050 {
2051  int retval;
2052 
2053  if (CHECK_PID(chip, 0x5209))
2054  RTSX_WRITE_REG(chip, PWR_GATE_CTRL, LDO3318_PWR_MASK, LDO_OFF);
2055 
2056  retval = sd_power_off_card3v3(chip);
2057  if (retval != STATUS_SUCCESS)
2058  TRACE_RET(chip, STATUS_FAIL);
2059 
2060  if (!chip->ft2_fast_mode)
2061  wait_timeout(250);
2062 
2063  retval = enable_card_clock(chip, SD_CARD);
2064  if (retval != STATUS_SUCCESS)
2065  TRACE_RET(chip, STATUS_FAIL);
2066 
2067  if (chip->asic_code) {
2068  retval = sd_pull_ctl_enable(chip);
2069  if (retval != STATUS_SUCCESS)
2070  TRACE_RET(chip, STATUS_FAIL);
2071  } else {
2072  RTSX_WRITE_REG(chip, FPGA_PULL_CTL, FPGA_SD_PULL_CTL_BIT | 0x20, 0);
2073  }
2074 
2075  if (chip->ft2_fast_mode) {
2076  if (CHECK_PID(chip, 0x5209))
2077  RTSX_WRITE_REG(chip, PWR_GATE_CTRL, LDO3318_PWR_MASK, LDO_ON);
2078 
2079  } else {
2080  retval = card_power_on(chip, SD_CARD);
2081  if (retval != STATUS_SUCCESS)
2082  TRACE_RET(chip, STATUS_FAIL);
2083 
2084  wait_timeout(260);
2085 
2086 #ifdef SUPPORT_OCP
2087  if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
2088  RTSX_DEBUGP("Over current, OCPSTAT is 0x%x\n", chip->ocp_stat);
2089  TRACE_RET(chip, STATUS_FAIL);
2090  }
2091 #endif
2092  }
2093 
2094  RTSX_WRITE_REG(chip, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN);
2095 
2096  return STATUS_SUCCESS;
2097 }
2098 
2099 static int sd_dummy_clock(struct rtsx_chip *chip)
2100 {
2101  if (CHECK_PID(chip, 0x5209)) {
2102  RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN, SD_CLK_TOGGLE_EN);
2103  wait_timeout(5);
2104  RTSX_WRITE_REG(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN, 0x00);
2105  } else {
2106  RTSX_WRITE_REG(chip, REG_SD_CFG3, 0x01, 0x01);
2107  wait_timeout(5);
2108  RTSX_WRITE_REG(chip, REG_SD_CFG3, 0x01, 0);
2109  }
2110 
2111  return STATUS_SUCCESS;
2112 }
2113 
2114 static int sd_read_lba0(struct rtsx_chip *chip)
2115 {
2116  struct sd_info *sd_card = &(chip->sd_card);
2117  int retval;
2118  u8 cmd[5], bus_width;
2119 
2120  cmd[0] = 0x40 | READ_SINGLE_BLOCK;
2121  cmd[1] = 0;
2122  cmd[2] = 0;
2123  cmd[3] = 0;
2124  cmd[4] = 0;
2125 
2126  if (CHK_SD(sd_card)) {
2127  bus_width = SD_BUS_WIDTH_4;
2128  } else {
2129  if (CHK_MMC_8BIT(sd_card))
2130  bus_width = SD_BUS_WIDTH_8;
2131  else if (CHK_MMC_4BIT(sd_card))
2132  bus_width = SD_BUS_WIDTH_4;
2133  else
2134  bus_width = SD_BUS_WIDTH_1;
2135  }
2136 
2137  retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd,
2138  5, 512, 1, bus_width, NULL, 0, 100);
2139  if (retval != STATUS_SUCCESS) {
2140  rtsx_clear_sd_error(chip);
2141  TRACE_RET(chip, STATUS_FAIL);
2142  }
2143 
2144  return STATUS_SUCCESS;
2145 }
2146 
2147 static int sd_check_wp_state(struct rtsx_chip *chip)
2148 {
2149  struct sd_info *sd_card = &(chip->sd_card);
2150  int retval;
2151  u32 val;
2152  u16 sd_card_type;
2153  u8 cmd[5], buf[64];
2154 
2155  retval = sd_send_cmd_get_rsp(chip, APP_CMD,
2156  sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2157  if (retval != STATUS_SUCCESS)
2158  TRACE_RET(chip, STATUS_FAIL);
2159 
2160  cmd[0] = 0x40 | SD_STATUS;
2161  cmd[1] = 0;
2162  cmd[2] = 0;
2163  cmd[3] = 0;
2164  cmd[4] = 0;
2165 
2166  retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1, SD_BUS_WIDTH_4, buf, 64, 250);
2167  if (retval != STATUS_SUCCESS) {
2168  rtsx_clear_sd_error(chip);
2169 
2170  sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2171  TRACE_RET(chip, STATUS_FAIL);
2172  }
2173 
2174  RTSX_DEBUGP("ACMD13:\n");
2175  RTSX_DUMP(buf, 64);
2176 
2177  sd_card_type = ((u16)buf[2] << 8) | buf[3];
2178  RTSX_DEBUGP("sd_card_type = 0x%04x\n", sd_card_type);
2179  if ((sd_card_type == 0x0001) || (sd_card_type == 0x0002)) {
2180  /* ROM card or OTP */
2181  chip->card_wp |= SD_CARD;
2182  }
2183 
2184  /* Check SD Machanical Write-Protect Switch */
2185  val = rtsx_readl(chip, RTSX_BIPR);
2186  if (val & SD_WRITE_PROTECT)
2187  chip->card_wp |= SD_CARD;
2188 
2189  return STATUS_SUCCESS;
2190 }
2191 
2192 static int reset_sd(struct rtsx_chip *chip)
2193 {
2194  struct sd_info *sd_card = &(chip->sd_card);
2195  int retval, i = 0, j = 0, k = 0, hi_cap_flow = 0;
2196  int sd_dont_switch = 0;
2197  int support_1v8 = 0;
2198  int try_sdio = 1;
2199  u8 rsp[16];
2200  u8 switch_bus_width;
2201  u32 voltage = 0;
2202  int sd20_mode = 0;
2203 
2204  SET_SD(sd_card);
2205 
2206 Switch_Fail:
2207 
2208  i = 0;
2209  j = 0;
2210  k = 0;
2211  hi_cap_flow = 0;
2212 
2213 #ifdef SUPPORT_SD_LOCK
2214  if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON)
2215  goto SD_UNLOCK_ENTRY;
2216 #endif
2217 
2218  retval = sd_prepare_reset(chip);
2219  if (retval != STATUS_SUCCESS)
2220  TRACE_RET(chip, STATUS_FAIL);
2221 
2222  retval = sd_dummy_clock(chip);
2223  if (retval != STATUS_SUCCESS)
2224  TRACE_RET(chip, STATUS_FAIL);
2225 
2226  if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip) && try_sdio) {
2227  int rty_cnt = 0;
2228 
2229  for (; rty_cnt < chip->sdio_retry_cnt; rty_cnt++) {
2230  if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2231  sd_set_err_code(chip, SD_NO_CARD);
2232  TRACE_RET(chip, STATUS_FAIL);
2233  }
2234 
2235  retval = sd_send_cmd_get_rsp(chip, IO_SEND_OP_COND, 0, SD_RSP_TYPE_R4, rsp, 5);
2236  if (retval == STATUS_SUCCESS) {
2237  int func_num = (rsp[1] >> 4) & 0x07;
2238  if (func_num) {
2239  RTSX_DEBUGP("SD_IO card (Function number: %d)!\n", func_num);
2240  chip->sd_io = 1;
2241  TRACE_RET(chip, STATUS_FAIL);
2242  }
2243 
2244  break;
2245  }
2246 
2247  sd_init_power(chip);
2248 
2249  sd_dummy_clock(chip);
2250  }
2251 
2252  RTSX_DEBUGP("Normal card!\n");
2253  }
2254 
2255  /* Start Initialization Process of SD Card */
2256 RTY_SD_RST:
2257  retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0, NULL, 0);
2258  if (retval != STATUS_SUCCESS)
2259  TRACE_RET(chip, STATUS_FAIL);
2260 
2261  wait_timeout(20);
2262 
2263  retval = sd_send_cmd_get_rsp(chip, SEND_IF_COND, 0x000001AA, SD_RSP_TYPE_R7, rsp, 5);
2264  if (retval == STATUS_SUCCESS) {
2265  if ((rsp[4] == 0xAA) && ((rsp[3] & 0x0f) == 0x01)) {
2266  hi_cap_flow = 1;
2267  if (CHECK_PID(chip, 0x5209)) {
2268  if (sd20_mode) {
2269  voltage = SUPPORT_VOLTAGE |
2270  SUPPORT_HIGH_AND_EXTENDED_CAPACITY;
2271  } else {
2272  voltage = SUPPORT_VOLTAGE |
2273  SUPPORT_HIGH_AND_EXTENDED_CAPACITY |
2274  SUPPORT_MAX_POWER_PERMANCE | SUPPORT_1V8;
2275  }
2276  } else {
2277  voltage = SUPPORT_VOLTAGE | 0x40000000;
2278  }
2279  }
2280  }
2281 
2282  if (!hi_cap_flow) {
2283  voltage = SUPPORT_VOLTAGE;
2284 
2285  retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0, NULL, 0);
2286  if (retval != STATUS_SUCCESS)
2287  TRACE_RET(chip, STATUS_FAIL);
2288 
2289  wait_timeout(20);
2290  }
2291 
2292  do {
2293  retval = sd_send_cmd_get_rsp(chip, APP_CMD, 0, SD_RSP_TYPE_R1, NULL, 0);
2294  if (retval != STATUS_SUCCESS) {
2295  if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2296  sd_set_err_code(chip, SD_NO_CARD);
2297  TRACE_RET(chip, STATUS_FAIL);
2298  }
2299 
2300  j++;
2301  if (j < 3)
2302  goto RTY_SD_RST;
2303  else
2304  TRACE_RET(chip, STATUS_FAIL);
2305  }
2306 
2307  retval = sd_send_cmd_get_rsp(chip, SD_APP_OP_COND, voltage, SD_RSP_TYPE_R3, rsp, 5);
2308  if (retval != STATUS_SUCCESS) {
2309  k++;
2310  if (k < 3)
2311  goto RTY_SD_RST;
2312  else
2313  TRACE_RET(chip, STATUS_FAIL);
2314  }
2315 
2316  i++;
2317  wait_timeout(20);
2318  } while (!(rsp[1] & 0x80) && (i < 255));
2319 
2320  if (i == 255)
2321  TRACE_RET(chip, STATUS_FAIL);
2322 
2323  if (hi_cap_flow) {
2324  if (rsp[1] & 0x40)
2325  SET_SD_HCXC(sd_card);
2326  else
2327  CLR_SD_HCXC(sd_card);
2328 
2329  if (CHECK_PID(chip, 0x5209) && CHK_SD_HCXC(sd_card) && !sd20_mode)
2330  support_1v8 = (rsp[1] & 0x01) ? 1 : 0;
2331  else
2332  support_1v8 = 0;
2333  } else {
2334  CLR_SD_HCXC(sd_card);
2335  support_1v8 = 0;
2336  }
2337  RTSX_DEBUGP("support_1v8 = %d\n", support_1v8);
2338 
2339  if (support_1v8) {
2340  retval = sd_voltage_switch(chip);
2341  if (retval != STATUS_SUCCESS)
2342  TRACE_RET(chip, STATUS_FAIL);
2343  }
2344 
2345  retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2, NULL, 0);
2346  if (retval != STATUS_SUCCESS)
2347  TRACE_RET(chip, STATUS_FAIL);
2348 
2349  for (i = 0; i < 3; i++) {
2350  retval = sd_send_cmd_get_rsp(chip, SEND_RELATIVE_ADDR, 0, SD_RSP_TYPE_R6, rsp, 5);
2351  if (retval != STATUS_SUCCESS)
2352  TRACE_RET(chip, STATUS_FAIL);
2353 
2354  sd_card->sd_addr = (u32)rsp[1] << 24;
2355  sd_card->sd_addr += (u32)rsp[2] << 16;
2356 
2357  if (sd_card->sd_addr)
2358  break;
2359  }
2360 
2361  retval = sd_check_csd(chip, 1);
2362  if (retval != STATUS_SUCCESS)
2363  TRACE_RET(chip, STATUS_FAIL);
2364 
2365  retval = sd_select_card(chip, 1);
2366  if (retval != STATUS_SUCCESS)
2367  TRACE_RET(chip, STATUS_FAIL);
2368 
2369 #ifdef SUPPORT_SD_LOCK
2370 SD_UNLOCK_ENTRY:
2371  retval = sd_update_lock_status(chip);
2372  if (retval != STATUS_SUCCESS)
2373  TRACE_RET(chip, STATUS_FAIL);
2374 
2375  if (sd_card->sd_lock_status & SD_LOCKED) {
2376  sd_card->sd_lock_status |= (SD_LOCK_1BIT_MODE | SD_PWD_EXIST);
2377  return STATUS_SUCCESS;
2378  } else if (!(sd_card->sd_lock_status & SD_UNLOCK_POW_ON)) {
2379  sd_card->sd_lock_status &= ~SD_PWD_EXIST;
2380  }
2381 #endif
2382 
2383  retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2384  if (retval != STATUS_SUCCESS)
2385  TRACE_RET(chip, STATUS_FAIL);
2386 
2387  retval = sd_send_cmd_get_rsp(chip, SET_CLR_CARD_DETECT, 0, SD_RSP_TYPE_R1, NULL, 0);
2388  if (retval != STATUS_SUCCESS)
2389  TRACE_RET(chip, STATUS_FAIL);
2390 
2391  if (support_1v8) {
2392  retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2393  if (retval != STATUS_SUCCESS)
2394  TRACE_RET(chip, STATUS_FAIL);
2395 
2396  retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2, SD_RSP_TYPE_R1, NULL, 0);
2397  if (retval != STATUS_SUCCESS)
2398  TRACE_RET(chip, STATUS_FAIL);
2399 
2400  switch_bus_width = SD_BUS_WIDTH_4;
2401  } else {
2402  switch_bus_width = SD_BUS_WIDTH_1;
2403  }
2404 
2405  retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1, NULL, 0);
2406  if (retval != STATUS_SUCCESS)
2407  TRACE_RET(chip, STATUS_FAIL);
2408 
2409  retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
2410  if (retval != STATUS_SUCCESS)
2411  TRACE_RET(chip, STATUS_FAIL);
2412 
2413  if (!(sd_card->raw_csd[4] & 0x40))
2414  sd_dont_switch = 1;
2415 
2416  if (!sd_dont_switch) {
2417  if (sd20_mode) {
2418  /* Set sd_switch_fail here, because we needn't
2419  * switch to UHS mode
2420  */
2421  sd_card->sd_switch_fail = SDR104_SUPPORT_MASK |
2422  DDR50_SUPPORT_MASK | SDR50_SUPPORT_MASK;
2423  }
2424 
2425  /* Check the card whether follow SD1.1 spec or higher */
2426  retval = sd_check_spec(chip, switch_bus_width);
2427  if (retval == STATUS_SUCCESS) {
2428  retval = sd_switch_function(chip, switch_bus_width);
2429  if (retval != STATUS_SUCCESS) {
2430  if (CHECK_PID(chip, 0x5209))
2431  sd_change_bank_voltage(chip, SD_IO_3V3);
2432 
2433  sd_init_power(chip);
2434  sd_dont_switch = 1;
2435  try_sdio = 0;
2436 
2437  goto Switch_Fail;
2438  }
2439  } else {
2440  if (support_1v8) {
2441  if (CHECK_PID(chip, 0x5209))
2442  sd_change_bank_voltage(chip, SD_IO_3V3);
2443 
2444  sd_init_power(chip);
2445  sd_dont_switch = 1;
2446  try_sdio = 0;
2447 
2448  goto Switch_Fail;
2449  }
2450  }
2451  }
2452 
2453  if (!support_1v8) {
2454  retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2455  if (retval != STATUS_SUCCESS)
2456  TRACE_RET(chip, STATUS_FAIL);
2457 
2458  retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2, SD_RSP_TYPE_R1, NULL, 0);
2459  if (retval != STATUS_SUCCESS)
2460  TRACE_RET(chip, STATUS_FAIL);
2461  }
2462 
2463 #ifdef SUPPORT_SD_LOCK
2464  sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2465 #endif
2466 
2467  if (!sd20_mode && CHK_SD30_SPEED(sd_card)) {
2468  int read_lba0 = 1;
2469 
2470  RTSX_WRITE_REG(chip, SD30_DRIVE_SEL, 0x07, chip->sd30_drive_sel_1v8);
2471 
2472  retval = sd_set_init_para(chip);
2473  if (retval != STATUS_SUCCESS)
2474  TRACE_RET(chip, STATUS_FAIL);
2475 
2476  if (CHK_SD_DDR50(sd_card))
2477  retval = sd_ddr_tuning(chip);
2478  else
2479  retval = sd_sdr_tuning(chip);
2480 
2481  if (retval != STATUS_SUCCESS) {
2482  if (sd20_mode) {
2483  TRACE_RET(chip, STATUS_FAIL);
2484  } else {
2485  retval = sd_init_power(chip);
2486  if (retval != STATUS_SUCCESS)
2487  TRACE_RET(chip, STATUS_FAIL);
2488 
2489  try_sdio = 0;
2490  sd20_mode = 1;
2491  goto Switch_Fail;
2492  }
2493  }
2494 
2495  sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2496 
2497  if (CHK_SD_DDR50(sd_card)) {
2498  retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
2499  if (retval != STATUS_SUCCESS)
2500  read_lba0 = 0;
2501  }
2502 
2503  if (read_lba0) {
2504  retval = sd_read_lba0(chip);
2505  if (retval != STATUS_SUCCESS) {
2506  if (sd20_mode) {
2507  TRACE_RET(chip, STATUS_FAIL);
2508  } else {
2509  retval = sd_init_power(chip);
2510  if (retval != STATUS_SUCCESS)
2511  TRACE_RET(chip, STATUS_FAIL);
2512 
2513  try_sdio = 0;
2514  sd20_mode = 1;
2515  goto Switch_Fail;
2516  }
2517  }
2518  }
2519  }
2520 
2521  retval = sd_check_wp_state(chip);
2522  if (retval != STATUS_SUCCESS)
2523  TRACE_RET(chip, STATUS_FAIL);
2524 
2525  chip->card_bus_width[chip->card2lun[SD_CARD]] = 4;
2526 
2527 #ifdef SUPPORT_SD_LOCK
2528  if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) {
2529  RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_H, 0xFF, 0x02);
2530  RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_L, 0xFF, 0x00);
2531  }
2532 #endif
2533 
2534  return STATUS_SUCCESS;
2535 }
2536 
2537 
2538 static int mmc_test_switch_bus(struct rtsx_chip *chip, u8 width)
2539 {
2540  struct sd_info *sd_card = &(chip->sd_card);
2541  int retval;
2542  u8 buf[8] = {0}, bus_width, *ptr;
2543  u16 byte_cnt;
2544  int len;
2545 
2546  retval = sd_send_cmd_get_rsp(chip, BUSTEST_W, 0, SD_RSP_TYPE_R1, NULL, 0);
2547  if (retval != STATUS_SUCCESS)
2548  TRACE_RET(chip, SWITCH_FAIL);
2549 
2550  if (width == MMC_8BIT_BUS) {
2551  buf[0] = 0x55;
2552  buf[1] = 0xAA;
2553  len = 8;
2554  byte_cnt = 8;
2555  bus_width = SD_BUS_WIDTH_8;
2556  } else {
2557  buf[0] = 0x5A;
2558  len = 4;
2559  byte_cnt = 4;
2560  bus_width = SD_BUS_WIDTH_4;
2561  }
2562 
2563  if (!CHECK_PID(chip, 0x5209)) {
2564  retval = rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0x02);
2565  if (retval != STATUS_SUCCESS)
2566  TRACE_RET(chip, SWITCH_ERR);
2567  }
2568 
2569  retval = sd_write_data(chip, SD_TM_AUTO_WRITE_3,
2570  NULL, 0, byte_cnt, 1, bus_width, buf, len, 100);
2571  if (retval != STATUS_SUCCESS) {
2572  if (CHECK_PID(chip, 0x5209)) {
2573  u8 val1 = 0, val2 = 0;
2574  rtsx_read_register(chip, REG_SD_STAT1, &val1);
2575  rtsx_read_register(chip, REG_SD_STAT2, &val2);
2576  rtsx_clear_sd_error(chip);
2577  if ((val1 & 0xE0) || val2)
2578  TRACE_RET(chip, SWITCH_ERR);
2579  } else {
2580  rtsx_clear_sd_error(chip);
2581  rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0);
2582  TRACE_RET(chip, SWITCH_ERR);
2583  }
2584  }
2585 
2586  if (!CHECK_PID(chip, 0x5209)) {
2587  retval = rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0);
2588  if (retval != STATUS_SUCCESS)
2589  TRACE_RET(chip, SWITCH_ERR);
2590  }
2591 
2592  RTSX_DEBUGP("SD/MMC CMD %d\n", BUSTEST_R);
2593 
2594  rtsx_init_cmd(chip);
2595 
2596  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | BUSTEST_R);
2597 
2598  if (width == MMC_8BIT_BUS)
2599  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x08);
2600  else
2601  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x04);
2602 
2603  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1);
2604  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0);
2605 
2606  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
2607  SD_CALCULATE_CRC7 | SD_NO_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
2608  SD_CHECK_CRC7 | SD_RSP_LEN_6);
2609  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
2610  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, SD_TM_NORMAL_READ | SD_TRANSFER_START);
2611  rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
2612 
2613  rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2, 0, 0);
2614  if (width == MMC_8BIT_BUS)
2615  rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 1, 0, 0);
2616 
2617  retval = rtsx_send_cmd(chip, SD_CARD, 100);
2618  if (retval < 0) {
2619  rtsx_clear_sd_error(chip);
2620  TRACE_RET(chip, SWITCH_ERR);
2621  }
2622 
2623  ptr = rtsx_get_cmd_data(chip) + 1;
2624 
2625  if (width == MMC_8BIT_BUS) {
2626  RTSX_DEBUGP("BUSTEST_R [8bits]: 0x%02x 0x%02x\n", ptr[0], ptr[1]);
2627  if ((ptr[0] == 0xAA) && (ptr[1] == 0x55)) {
2628  u8 rsp[5];
2629  u32 arg;
2630 
2631  if (CHK_MMC_DDR52(sd_card))
2632  arg = 0x03B70600;
2633  else
2634  arg = 0x03B70200;
2635 
2636  retval = sd_send_cmd_get_rsp(chip, SWITCH, arg, SD_RSP_TYPE_R1b, rsp, 5);
2637  if ((retval == STATUS_SUCCESS) && !(rsp[4] & MMC_SWITCH_ERR))
2638  return SWITCH_SUCCESS;
2639  }
2640  } else {
2641  RTSX_DEBUGP("BUSTEST_R [4bits]: 0x%02x\n", ptr[0]);
2642  if (ptr[0] == 0xA5) {
2643  u8 rsp[5];
2644  u32 arg;
2645 
2646  if (CHK_MMC_DDR52(sd_card))
2647  arg = 0x03B70500;
2648  else
2649  arg = 0x03B70100;
2650 
2651  retval = sd_send_cmd_get_rsp(chip, SWITCH, arg, SD_RSP_TYPE_R1b, rsp, 5);
2652  if ((retval == STATUS_SUCCESS) && !(rsp[4] & MMC_SWITCH_ERR))
2653  return SWITCH_SUCCESS;
2654  }
2655  }
2656 
2657  TRACE_RET(chip, SWITCH_FAIL);
2658 }
2659 
2660 
2661 static int mmc_switch_timing_bus(struct rtsx_chip *chip, int switch_ddr)
2662 {
2663  struct sd_info *sd_card = &(chip->sd_card);
2664  int retval;
2665  u8 *ptr, card_type, card_type_mask = 0;
2666 
2667  CLR_MMC_HS(sd_card);
2668 
2669  RTSX_DEBUGP("SD/MMC CMD %d\n", SEND_EXT_CSD);
2670 
2671  rtsx_init_cmd(chip);
2672 
2673  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | SEND_EXT_CSD);
2674  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, 0);
2675  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, 0);
2676  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, 0);
2677  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, 0);
2678 
2679  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0);
2680  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 2);
2681  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1);
2682  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0);
2683 
2684  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
2685  SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
2686  SD_CHECK_CRC7 | SD_RSP_LEN_6);
2687  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
2688  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, SD_TM_NORMAL_READ | SD_TRANSFER_START);
2689  rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
2690 
2691  rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 196, 0xFF, 0);
2692  rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 212, 0xFF, 0);
2693  rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 213, 0xFF, 0);
2694  rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 214, 0xFF, 0);
2695  rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 215, 0xFF, 0);
2696 
2697  retval = rtsx_send_cmd(chip, SD_CARD, 1000);
2698  if (retval < 0) {
2699  if (retval == -ETIMEDOUT) {
2700  rtsx_clear_sd_error(chip);
2701  sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2702  SD_RSP_TYPE_R1, NULL, 0);
2703  }
2704  TRACE_RET(chip, STATUS_FAIL);
2705  }
2706 
2707  ptr = rtsx_get_cmd_data(chip);
2708  if (ptr[0] & SD_TRANSFER_ERR) {
2709  sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
2710  TRACE_RET(chip, STATUS_FAIL);
2711  }
2712 
2713  if (CHK_MMC_SECTOR_MODE(sd_card)) {
2714  sd_card->capacity = ((u32)ptr[5] << 24) | ((u32)ptr[4] << 16) |
2715  ((u32)ptr[3] << 8) | ((u32)ptr[2]);
2716  }
2717 
2718  if (CHECK_PID(chip, 0x5209)) {
2719 #ifdef SUPPORT_SD_LOCK
2720  if (!(sd_card->sd_lock_status & SD_SDR_RST) &&
2721  (chip->sd_ctl & SUPPORT_MMC_DDR_MODE)) {
2722  card_type_mask = 0x07;
2723  } else {
2724  card_type_mask = 0x03;
2725  }
2726 #else
2727  if (chip->sd_ctl & SUPPORT_MMC_DDR_MODE)
2728  card_type_mask = 0x07;
2729  else
2730  card_type_mask = 0x03;
2731 #endif
2732  } else {
2733  card_type_mask = 0x03;
2734  }
2735  card_type = ptr[1] & card_type_mask;
2736  if (card_type) {
2737  u8 rsp[5];
2738 
2739  if (card_type & 0x04) {
2740  if (switch_ddr)
2741  SET_MMC_DDR52(sd_card);
2742  else
2743  SET_MMC_52M(sd_card);
2744  } else if (card_type & 0x02) {
2745  SET_MMC_52M(sd_card);
2746  } else {
2747  SET_MMC_26M(sd_card);
2748  }
2749 
2750  retval = sd_send_cmd_get_rsp(chip, SWITCH,
2751  0x03B90100, SD_RSP_TYPE_R1b, rsp, 5);
2752  if ((retval != STATUS_SUCCESS) || (rsp[4] & MMC_SWITCH_ERR))
2753  CLR_MMC_HS(sd_card);
2754  }
2755 
2756  sd_choose_proper_clock(chip);
2757  retval = switch_clock(chip, sd_card->sd_clock);
2758  if (retval != STATUS_SUCCESS)
2759  TRACE_RET(chip, STATUS_FAIL);
2760 
2761  /* Test Bus Procedure */
2762  retval = mmc_test_switch_bus(chip, MMC_8BIT_BUS);
2763  if (retval == SWITCH_SUCCESS) {
2764  SET_MMC_8BIT(sd_card);
2765  chip->card_bus_width[chip->card2lun[SD_CARD]] = 8;
2766 #ifdef SUPPORT_SD_LOCK
2767  sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2768 #endif
2769  } else if (retval == SWITCH_FAIL) {
2770  retval = mmc_test_switch_bus(chip, MMC_4BIT_BUS);
2771  if (retval == SWITCH_SUCCESS) {
2772  SET_MMC_4BIT(sd_card);
2773  chip->card_bus_width[chip->card2lun[SD_CARD]] = 4;
2774 #ifdef SUPPORT_SD_LOCK
2775  sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2776 #endif
2777  } else if (retval == SWITCH_FAIL) {
2778  CLR_MMC_8BIT(sd_card);
2779  CLR_MMC_4BIT(sd_card);
2780  } else {
2781  TRACE_RET(chip, STATUS_FAIL);
2782  }
2783  } else {
2784  TRACE_RET(chip, STATUS_FAIL);
2785  }
2786 
2787  return STATUS_SUCCESS;
2788 }
2789 
2790 
2791 static int reset_mmc(struct rtsx_chip *chip)
2792 {
2793  struct sd_info *sd_card = &(chip->sd_card);
2794  int retval, i = 0, j = 0, k = 0;
2795  int switch_ddr = 1;
2796  u8 rsp[16];
2797  u8 spec_ver = 0;
2798  u32 temp;
2799 
2800 #ifdef SUPPORT_SD_LOCK
2801  if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON)
2802  goto MMC_UNLOCK_ENTRY;
2803 #endif
2804 
2805 Switch_Fail:
2806  retval = sd_prepare_reset(chip);
2807  if (retval != STATUS_SUCCESS)
2808  TRACE_RET(chip, retval);
2809 
2810  SET_MMC(sd_card);
2811 
2812 RTY_MMC_RST:
2813  retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0, NULL, 0);
2814  if (retval != STATUS_SUCCESS)
2815  TRACE_RET(chip, STATUS_FAIL);
2816 
2817  do {
2818  if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2819  sd_set_err_code(chip, SD_NO_CARD);
2820  TRACE_RET(chip, STATUS_FAIL);
2821  }
2822 
2823  retval = sd_send_cmd_get_rsp(chip, SEND_OP_COND,
2824  (SUPPORT_VOLTAGE|0x40000000), SD_RSP_TYPE_R3, rsp, 5);
2825  if (retval != STATUS_SUCCESS) {
2826  if (sd_check_err_code(chip, SD_BUSY) || sd_check_err_code(chip, SD_TO_ERR)) {
2827  k++;
2828  if (k < 20) {
2829  sd_clr_err_code(chip);
2830  goto RTY_MMC_RST;
2831  } else {
2832  TRACE_RET(chip, STATUS_FAIL);
2833  }
2834  } else {
2835  j++;
2836  if (j < 100) {
2837  sd_clr_err_code(chip);
2838  goto RTY_MMC_RST;
2839  } else {
2840  TRACE_RET(chip, STATUS_FAIL);
2841  }
2842  }
2843  }
2844 
2845  wait_timeout(20);
2846  i++;
2847  } while (!(rsp[1] & 0x80) && (i < 255));
2848 
2849  if (i == 255)
2850  TRACE_RET(chip, STATUS_FAIL);
2851 
2852  if ((rsp[1] & 0x60) == 0x40)
2853  SET_MMC_SECTOR_MODE(sd_card);
2854  else
2855  CLR_MMC_SECTOR_MODE(sd_card);
2856 
2857  retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2, NULL, 0);
2858  if (retval != STATUS_SUCCESS)
2859  TRACE_RET(chip, STATUS_FAIL);
2860 
2861  sd_card->sd_addr = 0x00100000;
2862  retval = sd_send_cmd_get_rsp(chip, SET_RELATIVE_ADDR, sd_card->sd_addr, SD_RSP_TYPE_R6, rsp, 5);
2863  if (retval != STATUS_SUCCESS)
2864  TRACE_RET(chip, STATUS_FAIL);
2865 
2866  retval = sd_check_csd(chip, 1);
2867  if (retval != STATUS_SUCCESS)
2868  TRACE_RET(chip, STATUS_FAIL);
2869 
2870  spec_ver = (sd_card->raw_csd[0] & 0x3C) >> 2;
2871 
2872  retval = sd_select_card(chip, 1);
2873  if (retval != STATUS_SUCCESS)
2874  TRACE_RET(chip, STATUS_FAIL);
2875 
2876  retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1, NULL, 0);
2877  if (retval != STATUS_SUCCESS)
2878  TRACE_RET(chip, STATUS_FAIL);
2879 
2880 #ifdef SUPPORT_SD_LOCK
2881 MMC_UNLOCK_ENTRY:
2882  retval = sd_update_lock_status(chip);
2883  if (retval != STATUS_SUCCESS)
2884  TRACE_RET(chip, STATUS_FAIL);
2885 #endif
2886 
2887  retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
2888  if (retval != STATUS_SUCCESS)
2889  TRACE_RET(chip, STATUS_FAIL);
2890 
2891  chip->card_bus_width[chip->card2lun[SD_CARD]] = 1;
2892 
2893  if (!sd_card->mmc_dont_switch_bus) {
2894  if (spec_ver == 4) {
2895  /* MMC 4.x Cards */
2896  retval = mmc_switch_timing_bus(chip, switch_ddr);
2897  if (retval != STATUS_SUCCESS) {
2898  retval = sd_init_power(chip);
2899  if (retval != STATUS_SUCCESS)
2900  TRACE_RET(chip, STATUS_FAIL);
2901  sd_card->mmc_dont_switch_bus = 1;
2902  TRACE_GOTO(chip, Switch_Fail);
2903  }
2904  }
2905 
2906  if (CHK_MMC_SECTOR_MODE(sd_card) && (sd_card->capacity == 0))
2907  TRACE_RET(chip, STATUS_FAIL);
2908 
2909  if (switch_ddr && CHK_MMC_DDR52(sd_card)) {
2910  retval = sd_set_init_para(chip);
2911  if (retval != STATUS_SUCCESS)
2912  TRACE_RET(chip, STATUS_FAIL);
2913 
2914  retval = mmc_ddr_tuning(chip);
2915  if (retval != STATUS_SUCCESS) {
2916  retval = sd_init_power(chip);
2917  if (retval != STATUS_SUCCESS)
2918  TRACE_RET(chip, STATUS_FAIL);
2919 
2920  switch_ddr = 0;
2921  TRACE_GOTO(chip, Switch_Fail);
2922  }
2923 
2924  retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
2925  if (retval == STATUS_SUCCESS) {
2926  retval = sd_read_lba0(chip);
2927  if (retval != STATUS_SUCCESS) {
2928  retval = sd_init_power(chip);
2929  if (retval != STATUS_SUCCESS)
2930  TRACE_RET(chip, STATUS_FAIL);
2931 
2932  switch_ddr = 0;
2933  TRACE_GOTO(chip, Switch_Fail);
2934  }
2935  }
2936  }
2937  }
2938 
2939 #ifdef SUPPORT_SD_LOCK
2940  if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) {
2941  RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_H, 0xFF, 0x02);
2942  RTSX_WRITE_REG(chip, REG_SD_BLOCK_CNT_L, 0xFF, 0x00);
2943  }
2944 #endif
2945 
2946  temp = rtsx_readl(chip, RTSX_BIPR);
2947  if (temp & SD_WRITE_PROTECT)
2948  chip->card_wp |= SD_CARD;
2949 
2950  return STATUS_SUCCESS;
2951 }
2952 
2953 int reset_sd_card(struct rtsx_chip *chip)
2954 {
2955  struct sd_info *sd_card = &(chip->sd_card);
2956  int retval;
2957 
2958  sd_init_reg_addr(chip);
2959 
2960  memset(sd_card, 0, sizeof(struct sd_info));
2961  chip->capacity[chip->card2lun[SD_CARD]] = 0;
2962 
2963  retval = enable_card_clock(chip, SD_CARD);
2964  if (retval != STATUS_SUCCESS)
2965  TRACE_RET(chip, STATUS_FAIL);
2966 
2967  if (chip->ignore_sd && CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
2968  if (chip->asic_code) {
2969  retval = sd_pull_ctl_enable(chip);
2970  if (retval != STATUS_SUCCESS)
2971  TRACE_RET(chip, STATUS_FAIL);
2972  } else {
2973  retval = rtsx_write_register(chip, FPGA_PULL_CTL,
2974  FPGA_SD_PULL_CTL_BIT | 0x20, 0);
2975  if (retval != STATUS_SUCCESS)
2976  TRACE_RET(chip, STATUS_FAIL);
2977  }
2978  retval = card_share_mode(chip, SD_CARD);
2979  if (retval != STATUS_SUCCESS)
2980  TRACE_RET(chip, STATUS_FAIL);
2981 
2982  chip->sd_io = 1;
2983  TRACE_RET(chip, STATUS_FAIL);
2984  }
2985 
2986  retval = sd_init_power(chip);
2987  if (retval != STATUS_SUCCESS)
2988  TRACE_RET(chip, STATUS_FAIL);
2989 
2990  if (chip->sd_ctl & RESET_MMC_FIRST) {
2991  retval = reset_mmc(chip);
2992  if (retval != STATUS_SUCCESS) {
2993  if (sd_check_err_code(chip, SD_NO_CARD))
2994  TRACE_RET(chip, STATUS_FAIL);
2995 
2996  retval = reset_sd(chip);
2997  if (retval != STATUS_SUCCESS) {
2998  if (CHECK_PID(chip, 0x5209))
2999  sd_change_bank_voltage(chip, SD_IO_3V3);
3000 
3001  TRACE_RET(chip, STATUS_FAIL);
3002  }
3003  }
3004  } else {
3005  retval = reset_sd(chip);
3006  if (retval != STATUS_SUCCESS) {
3007  if (sd_check_err_code(chip, SD_NO_CARD))
3008  TRACE_RET(chip, STATUS_FAIL);
3009 
3010  if (CHECK_PID(chip, 0x5209)) {
3011  retval = sd_change_bank_voltage(chip, SD_IO_3V3);
3012  if (retval != STATUS_SUCCESS)
3013  TRACE_RET(chip, STATUS_FAIL);
3014  }
3015 
3016  if (chip->sd_io) {
3017  TRACE_RET(chip, STATUS_FAIL);
3018  } else {
3019  retval = reset_mmc(chip);
3020  if (retval != STATUS_SUCCESS)
3021  TRACE_RET(chip, STATUS_FAIL);
3022  }
3023  }
3024  }
3025 
3026  retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
3027  if (retval != STATUS_SUCCESS)
3028  TRACE_RET(chip, STATUS_FAIL);
3029 
3030  RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_L, 0xFF, 0);
3031  RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_H, 0xFF, 2);
3032 
3033  chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity;
3034 
3035  retval = sd_set_init_para(chip);
3036  if (retval != STATUS_SUCCESS)
3037  TRACE_RET(chip, STATUS_FAIL);
3038 
3039  RTSX_DEBUGP("sd_card->sd_type = 0x%x\n", sd_card->sd_type);
3040 
3041  return STATUS_SUCCESS;
3042 }
3043 
3044 static int reset_mmc_only(struct rtsx_chip *chip)
3045 {
3046  struct sd_info *sd_card = &(chip->sd_card);
3047  int retval;
3048 
3049  sd_card->sd_type = 0;
3050  sd_card->seq_mode = 0;
3051  sd_card->sd_data_buf_ready = 0;
3052  sd_card->capacity = 0;
3053  sd_card->sd_switch_fail = 0;
3054 
3055 #ifdef SUPPORT_SD_LOCK
3056  sd_card->sd_lock_status = 0;
3057  sd_card->sd_erase_status = 0;
3058 #endif
3059 
3060  chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity = 0;
3061 
3062  retval = enable_card_clock(chip, SD_CARD);
3063  if (retval != STATUS_SUCCESS)
3064  TRACE_RET(chip, STATUS_FAIL);
3065 
3066  retval = sd_init_power(chip);
3067  if (retval != STATUS_SUCCESS)
3068  TRACE_RET(chip, STATUS_FAIL);
3069 
3070  retval = reset_mmc(chip);
3071  if (retval != STATUS_SUCCESS)
3072  TRACE_RET(chip, STATUS_FAIL);
3073 
3074  retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
3075  if (retval != STATUS_SUCCESS)
3076  TRACE_RET(chip, STATUS_FAIL);
3077 
3078  RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_L, 0xFF, 0);
3079  RTSX_WRITE_REG(chip, REG_SD_BYTE_CNT_H, 0xFF, 2);
3080 
3081  chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity;
3082 
3083  retval = sd_set_init_para(chip);
3084  if (retval != STATUS_SUCCESS)
3085  TRACE_RET(chip, STATUS_FAIL);
3086 
3087  RTSX_DEBUGP("In reset_mmc_only, sd_card->sd_type = 0x%x\n", sd_card->sd_type);
3088 
3089  return STATUS_SUCCESS;
3090 }
3091 
3092 #define WAIT_DATA_READY_RTY_CNT 255
3093 
3094 static int wait_data_buf_ready(struct rtsx_chip *chip)
3095 {
3096  struct sd_info *sd_card = &(chip->sd_card);
3097  int i, retval;
3098 
3099  for (i = 0; i < WAIT_DATA_READY_RTY_CNT; i++) {
3100  if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3101  sd_set_err_code(chip, SD_NO_CARD);
3102  TRACE_RET(chip, STATUS_FAIL);
3103  }
3104 
3105  sd_card->sd_data_buf_ready = 0;
3106 
3107  retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
3108  sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
3109  if (retval != STATUS_SUCCESS)
3110  TRACE_RET(chip, STATUS_FAIL);
3111 
3112  if (sd_card->sd_data_buf_ready) {
3113  return sd_send_cmd_get_rsp(chip, SEND_STATUS,
3114  sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
3115  }
3116  }
3117 
3118  sd_set_err_code(chip, SD_TO_ERR);
3119 
3120  TRACE_RET(chip, STATUS_FAIL);
3121 }
3122 
3123 void sd_stop_seq_mode(struct rtsx_chip *chip)
3124 {
3125  struct sd_info *sd_card = &(chip->sd_card);
3126  int retval;
3127 
3128  if (sd_card->seq_mode) {
3129  retval = sd_switch_clock(chip);
3130  if (retval != STATUS_SUCCESS)
3131  return;
3132 
3133  retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
3134  SD_RSP_TYPE_R1b, NULL, 0);
3135  if (retval != STATUS_SUCCESS)
3136  sd_set_err_code(chip, SD_STS_ERR);
3137 
3138  retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
3139  if (retval != STATUS_SUCCESS)
3140  sd_set_err_code(chip, SD_STS_ERR);
3141 
3142  sd_card->seq_mode = 0;
3143 
3144  rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
3145  }
3146 }
3147 
3148 static inline int sd_auto_tune_clock(struct rtsx_chip *chip)
3149 {
3150  struct sd_info *sd_card = &(chip->sd_card);
3151  int retval;
3152 
3153  if (chip->asic_code) {
3154  if (sd_card->sd_clock > 30)
3155  sd_card->sd_clock -= 20;
3156  } else {
3157  switch (sd_card->sd_clock) {
3158  case CLK_200:
3159  sd_card->sd_clock = CLK_150;
3160  break;
3161 
3162  case CLK_150:
3163  sd_card->sd_clock = CLK_120;
3164  break;
3165 
3166  case CLK_120:
3167  sd_card->sd_clock = CLK_100;
3168  break;
3169 
3170  case CLK_100:
3171  sd_card->sd_clock = CLK_80;
3172  break;
3173 
3174  case CLK_80:
3175  sd_card->sd_clock = CLK_60;
3176  break;
3177 
3178  case CLK_60:
3179  sd_card->sd_clock = CLK_50;
3180  break;
3181 
3182  default:
3183  break;
3184  }
3185  }
3186 
3187  retval = sd_switch_clock(chip);
3188  if (retval != STATUS_SUCCESS)
3189  TRACE_RET(chip, STATUS_FAIL);
3190 
3191  return STATUS_SUCCESS;
3192 }
3193 
3194 int sd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector, u16 sector_cnt)
3195 {
3196  struct sd_info *sd_card = &(chip->sd_card);
3197  u32 data_addr;
3198  u8 cfg2;
3199  int retval;
3200 
3201  if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3202  RTSX_DEBUGP("sd_rw: Read %d %s from 0x%x\n", sector_cnt,
3203  (sector_cnt > 1) ? "sectors" : "sector", start_sector);
3204  } else {
3205  RTSX_DEBUGP("sd_rw: Write %d %s to 0x%x\n", sector_cnt,
3206  (sector_cnt > 1) ? "sectors" : "sector", start_sector);
3207  }
3208 
3209  sd_card->cleanup_counter = 0;
3210 
3211  if (!(chip->card_ready & SD_CARD)) {
3212  sd_card->seq_mode = 0;
3213 
3214  retval = reset_sd_card(chip);
3215  if (retval == STATUS_SUCCESS) {
3216  chip->card_ready |= SD_CARD;
3217  chip->card_fail &= ~SD_CARD;
3218  } else {
3219  chip->card_ready &= ~SD_CARD;
3220  chip->card_fail |= SD_CARD;
3221  chip->capacity[chip->card2lun[SD_CARD]] = 0;
3222  chip->rw_need_retry = 1;
3223  TRACE_RET(chip, STATUS_FAIL);
3224  }
3225  }
3226 
3227  if (!CHK_SD_HCXC(sd_card) && !CHK_MMC_SECTOR_MODE(sd_card))
3228  data_addr = start_sector << 9;
3229  else
3230  data_addr = start_sector;
3231 
3232  sd_clr_err_code(chip);
3233 
3234  retval = sd_switch_clock(chip);
3235  if (retval != STATUS_SUCCESS) {
3236  sd_set_err_code(chip, SD_IO_ERR);
3237  TRACE_GOTO(chip, RW_FAIL);
3238  }
3239 
3240  if (sd_card->seq_mode && ((sd_card->pre_dir != srb->sc_data_direction)
3241  || ((sd_card->pre_sec_addr + sd_card->pre_sec_cnt) != start_sector))) {
3242  if ((sd_card->pre_sec_cnt < 0x80)
3243  && (sd_card->pre_dir == DMA_FROM_DEVICE)
3244  && !CHK_SD30_SPEED(sd_card)
3245  && !CHK_SD_HS(sd_card)
3246  && !CHK_MMC_HS(sd_card)) {
3247  sd_send_cmd_get_rsp(chip, SEND_STATUS,
3248  sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
3249  }
3250 
3251  retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION,
3252  0, SD_RSP_TYPE_R1b, NULL, 0);
3253  if (retval != STATUS_SUCCESS) {
3254  chip->rw_need_retry = 1;
3255  sd_set_err_code(chip, SD_STS_ERR);
3256  TRACE_GOTO(chip, RW_FAIL);
3257  }
3258 
3259  sd_card->seq_mode = 0;
3260 
3261  retval = rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
3262  if (retval != STATUS_SUCCESS) {
3263  sd_set_err_code(chip, SD_IO_ERR);
3264  TRACE_GOTO(chip, RW_FAIL);
3265  }
3266 
3267  if ((sd_card->pre_sec_cnt < 0x80)
3268  && !CHK_SD30_SPEED(sd_card)
3269  && !CHK_SD_HS(sd_card)
3270  && !CHK_MMC_HS(sd_card)) {
3271  sd_send_cmd_get_rsp(chip, SEND_STATUS,
3272  sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
3273  }
3274  }
3275 
3276  rtsx_init_cmd(chip);
3277 
3278  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x00);
3279  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 0x02);
3280  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, (u8)sector_cnt);
3281  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, (u8)(sector_cnt >> 8));
3282 
3283  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
3284 
3285  if (CHK_MMC_8BIT(sd_card))
3286  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_8);
3287  else if (CHK_MMC_4BIT(sd_card) || CHK_SD(sd_card))
3288  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
3289  else
3290  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_1);
3291 
3292  if (sd_card->seq_mode) {
3293  cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
3294  SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
3295  if (CHECK_PID(chip, 0x5209)) {
3296  if (!CHK_SD30_SPEED(sd_card))
3297  cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
3298  }
3299  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, cfg2);
3300 
3301  trans_dma_enable(srb->sc_data_direction, chip, sector_cnt * 512, DMA_512);
3302 
3303  if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3304  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3305  SD_TM_AUTO_READ_3 | SD_TRANSFER_START);
3306  } else {
3307  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3308  SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
3309  }
3310 
3311  rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
3312 
3313  rtsx_send_cmd_no_wait(chip);
3314  } else {
3315  if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3316  RTSX_DEBUGP("SD/MMC CMD %d\n", READ_MULTIPLE_BLOCK);
3317  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF,
3318  0x40 | READ_MULTIPLE_BLOCK);
3319  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(data_addr >> 24));
3320  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(data_addr >> 16));
3321  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(data_addr >> 8));
3322  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)data_addr);
3323 
3324  cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
3325  SD_CHECK_CRC7 | SD_RSP_LEN_6;
3326  if (CHECK_PID(chip, 0x5209)) {
3327  if (!CHK_SD30_SPEED(sd_card))
3328  cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
3329  }
3330  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, cfg2);
3331 
3332  trans_dma_enable(srb->sc_data_direction, chip, sector_cnt * 512, DMA_512);
3333 
3334  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3335  SD_TM_AUTO_READ_2 | SD_TRANSFER_START);
3336  rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3337  SD_TRANSFER_END, SD_TRANSFER_END);
3338 
3339  rtsx_send_cmd_no_wait(chip);
3340  } else {
3341  retval = rtsx_send_cmd(chip, SD_CARD, 50);
3342  if (retval < 0) {
3343  rtsx_clear_sd_error(chip);
3344 
3345  chip->rw_need_retry = 1;
3346  sd_set_err_code(chip, SD_TO_ERR);
3347  TRACE_GOTO(chip, RW_FAIL);
3348  }
3349 
3350  retval = wait_data_buf_ready(chip);
3351  if (retval != STATUS_SUCCESS) {
3352  chip->rw_need_retry = 1;
3353  sd_set_err_code(chip, SD_TO_ERR);
3354  TRACE_GOTO(chip, RW_FAIL);
3355  }
3356 
3357  retval = sd_send_cmd_get_rsp(chip, WRITE_MULTIPLE_BLOCK,
3358  data_addr, SD_RSP_TYPE_R1, NULL, 0);
3359  if (retval != STATUS_SUCCESS) {
3360  chip->rw_need_retry = 1;
3361  TRACE_GOTO(chip, RW_FAIL);
3362  }
3363 
3364  rtsx_init_cmd(chip);
3365 
3366  cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
3367  SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
3368  if (CHECK_PID(chip, 0x5209)) {
3369  if (!CHK_SD30_SPEED(sd_card))
3370  cfg2 |= SD_NO_CHECK_WAIT_CRC_TO;
3371  }
3372  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, cfg2);
3373 
3374  trans_dma_enable(srb->sc_data_direction, chip, sector_cnt * 512, DMA_512);
3375 
3376  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3377  SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
3378  rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3379  SD_TRANSFER_END, SD_TRANSFER_END);
3380 
3381  rtsx_send_cmd_no_wait(chip);
3382  }
3383 
3384  sd_card->seq_mode = 1;
3385  }
3386 
3387  retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb), scsi_bufflen(srb),
3388  scsi_sg_count(srb), srb->sc_data_direction, chip->sd_timeout);
3389  if (retval < 0) {
3390  u8 stat = 0;
3391  int err;
3392 
3393  sd_card->seq_mode = 0;
3394 
3395  if (retval == -ETIMEDOUT)
3396  err = STATUS_TIMEDOUT;
3397  else
3398  err = STATUS_FAIL;
3399 
3400  rtsx_read_register(chip, REG_SD_STAT1, &stat);
3401  rtsx_clear_sd_error(chip);
3402  if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3403  chip->rw_need_retry = 0;
3404  RTSX_DEBUGP("No card exist, exit sd_rw\n");
3405  TRACE_RET(chip, STATUS_FAIL);
3406  }
3407 
3408  chip->rw_need_retry = 1;
3409 
3410  retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0, SD_RSP_TYPE_R1b, NULL, 0);
3411  if (retval != STATUS_SUCCESS) {
3412  sd_set_err_code(chip, SD_STS_ERR);
3413  TRACE_GOTO(chip, RW_FAIL);
3414  }
3415 
3416  if (stat & (SD_CRC7_ERR | SD_CRC16_ERR | SD_CRC_WRITE_ERR)) {
3417  RTSX_DEBUGP("SD CRC error, tune clock!\n");
3418  sd_set_err_code(chip, SD_CRC_ERR);
3419  TRACE_GOTO(chip, RW_FAIL);
3420  }
3421 
3422  if (err == STATUS_TIMEDOUT) {
3423  sd_set_err_code(chip, SD_TO_ERR);
3424  TRACE_GOTO(chip, RW_FAIL);
3425  }
3426 
3427  TRACE_RET(chip, err);
3428  }
3429 
3430  sd_card->pre_sec_addr = start_sector;
3431  sd_card->pre_sec_cnt = sector_cnt;
3432  sd_card->pre_dir = srb->sc_data_direction;
3433 
3434  return STATUS_SUCCESS;
3435 
3436 RW_FAIL:
3437  sd_card->seq_mode = 0;
3438 
3439  if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3440  chip->rw_need_retry = 0;
3441  RTSX_DEBUGP("No card exist, exit sd_rw\n");
3442  TRACE_RET(chip, STATUS_FAIL);
3443  }
3444 
3445  if (sd_check_err_code(chip, SD_CRC_ERR)) {
3446  if (CHK_MMC_4BIT(sd_card) || CHK_MMC_8BIT(sd_card)) {
3447  sd_card->mmc_dont_switch_bus = 1;
3448  reset_mmc_only(chip);
3449  sd_card->mmc_dont_switch_bus = 0;
3450  } else {
3451  sd_card->need_retune = 1;
3452  sd_auto_tune_clock(chip);
3453  }
3454  } else if (sd_check_err_code(chip, SD_TO_ERR | SD_STS_ERR)) {
3455  retval = reset_sd_card(chip);
3456  if (retval != STATUS_SUCCESS) {
3457  chip->card_ready &= ~SD_CARD;
3458  chip->card_fail |= SD_CARD;
3459  chip->capacity[chip->card2lun[SD_CARD]] = 0;
3460  }
3461  }
3462 
3463  TRACE_RET(chip, STATUS_FAIL);
3464 }
3465 
3466 #ifdef SUPPORT_CPRM
3467 int soft_reset_sd_card(struct rtsx_chip *chip)
3468 {
3469  return reset_sd(chip);
3470 }
3471 
3472 int ext_sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx,
3473  u32 arg, u8 rsp_type, u8 *rsp, int rsp_len, int special_check)
3474 {
3475  int retval;
3476  int timeout = 100;
3477  u16 reg_addr;
3478  u8 *ptr;
3479  int stat_idx = 0;
3480  int rty_cnt = 0;
3481 
3482  RTSX_DEBUGP("EXT SD/MMC CMD %d\n", cmd_idx);
3483 
3484  if (rsp_type == SD_RSP_TYPE_R1b)
3485  timeout = 3000;
3486 
3487 RTY_SEND_CMD:
3488 
3489  rtsx_init_cmd(chip);
3490 
3491  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
3492  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24));
3493  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16));
3494  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8));
3495  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg);
3496 
3497  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
3498  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
3499  0x01, PINGPONG_BUFFER);
3500  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
3501  0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
3502  rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
3503 
3504  if (rsp_type == SD_RSP_TYPE_R2) {
3505  for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; reg_addr++)
3506  rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
3507 
3508  stat_idx = 17;
3509  } else if (rsp_type != SD_RSP_TYPE_R0) {
3510  for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4; reg_addr++)
3511  rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
3512 
3513  stat_idx = 6;
3514  }
3515  rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0, 0);
3516 
3517  rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0);
3518 
3519  retval = rtsx_send_cmd(chip, SD_CARD, timeout);
3520  if (retval < 0) {
3521  if (retval == -ETIMEDOUT) {
3522  rtsx_clear_sd_error(chip);
3523 
3524  if (rsp_type & SD_WAIT_BUSY_END) {
3525  retval = sd_check_data0_status(chip);
3526  if (retval != STATUS_SUCCESS)
3527  TRACE_RET(chip, retval);
3528  } else {
3529  sd_set_err_code(chip, SD_TO_ERR);
3530  }
3531  }
3532  TRACE_RET(chip, STATUS_FAIL);
3533  }
3534 
3535  if (rsp_type == SD_RSP_TYPE_R0)
3536  return STATUS_SUCCESS;
3537 
3538  ptr = rtsx_get_cmd_data(chip) + 1;
3539 
3540  if ((ptr[0] & 0xC0) != 0) {
3541  sd_set_err_code(chip, SD_STS_ERR);
3542  TRACE_RET(chip, STATUS_FAIL);
3543  }
3544 
3545  if (!(rsp_type & SD_NO_CHECK_CRC7)) {
3546  if (ptr[stat_idx] & SD_CRC7_ERR) {
3547  if (cmd_idx == WRITE_MULTIPLE_BLOCK) {
3548  sd_set_err_code(chip, SD_CRC_ERR);
3549  TRACE_RET(chip, STATUS_FAIL);
3550  }
3551  if (rty_cnt < SD_MAX_RETRY_COUNT) {
3552  wait_timeout(20);
3553  rty_cnt++;
3554  goto RTY_SEND_CMD;
3555  } else {
3556  sd_set_err_code(chip, SD_CRC_ERR);
3557  TRACE_RET(chip, STATUS_FAIL);
3558  }
3559  }
3560  }
3561 
3562  if ((cmd_idx == SELECT_CARD) || (cmd_idx == APP_CMD) ||
3563  (cmd_idx == SEND_STATUS) || (cmd_idx == STOP_TRANSMISSION)) {
3564  if ((cmd_idx != STOP_TRANSMISSION) && (special_check == 0)) {
3565  if (ptr[1] & 0x80)
3566  TRACE_RET(chip, STATUS_FAIL);
3567  }
3568 #ifdef SUPPORT_SD_LOCK
3569  if (ptr[1] & 0x7D)
3570 #else
3571  if (ptr[1] & 0x7F)
3572 #endif
3573  {
3574  TRACE_RET(chip, STATUS_FAIL);
3575  }
3576  if (ptr[2] & 0xF8)
3577  TRACE_RET(chip, STATUS_FAIL);
3578 
3579  if (cmd_idx == SELECT_CARD) {
3580  if (rsp_type == SD_RSP_TYPE_R2) {
3581  if ((ptr[3] & 0x1E) != 0x04)
3582  TRACE_RET(chip, STATUS_FAIL);
3583 
3584  } else if (rsp_type == SD_RSP_TYPE_R0) {
3585  if ((ptr[3] & 0x1E) != 0x03)
3586  TRACE_RET(chip, STATUS_FAIL);
3587  }
3588  }
3589  }
3590 
3591  if (rsp && rsp_len)
3592  memcpy(rsp, ptr, rsp_len);
3593 
3594  return STATUS_SUCCESS;
3595 }
3596 
3597 int ext_sd_get_rsp(struct rtsx_chip *chip, int len, u8 *rsp, u8 rsp_type)
3598 {
3599  int retval, rsp_len;
3600  u16 reg_addr;
3601 
3602  if (rsp_type == SD_RSP_TYPE_R0)
3603  return STATUS_SUCCESS;
3604 
3605  rtsx_init_cmd(chip);
3606 
3607  if (rsp_type == SD_RSP_TYPE_R2) {
3608  for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; reg_addr++)
3609  rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0);
3610 
3611  rsp_len = 17;
3612  } else if (rsp_type != SD_RSP_TYPE_R0) {
3613  for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4; reg_addr++)
3614  rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0);
3615 
3616  rsp_len = 6;
3617  }
3618  rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0xFF, 0);
3619 
3620  retval = rtsx_send_cmd(chip, SD_CARD, 100);
3621  if (retval != STATUS_SUCCESS)
3622  TRACE_RET(chip, STATUS_FAIL);
3623 
3624  if (rsp) {
3625  int min_len = (rsp_len < len) ? rsp_len : len;
3626 
3627  memcpy(rsp, rtsx_get_cmd_data(chip), min_len);
3628 
3629  RTSX_DEBUGP("min_len = %d\n", min_len);
3630  RTSX_DEBUGP("Response in cmd buf: 0x%x 0x%x 0x%x 0x%x\n",
3631  rsp[0], rsp[1], rsp[2], rsp[3]);
3632  }
3633 
3634  return STATUS_SUCCESS;
3635 }
3636 
3637 int sd_pass_thru_mode(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3638 {
3639  struct sd_info *sd_card = &(chip->sd_card);
3640  unsigned int lun = SCSI_LUN(srb);
3641  int len;
3642  u8 buf[18] = {
3643  0x00,
3644  0x00,
3645  0x00,
3646  0x0E,
3647  0x00,
3648  0x00,
3649  0x00,
3650  0x00,
3651  0x53,
3652  0x44,
3653  0x20,
3654  0x43,
3655  0x61,
3656  0x72,
3657  0x64,
3658  0x00,
3659  0x00,
3660  0x00,
3661  };
3662 
3663  sd_card->pre_cmd_err = 0;
3664 
3665  if (!(CHK_BIT(chip->lun_mc, lun))) {
3666  SET_BIT(chip->lun_mc, lun);
3667  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
3668  TRACE_RET(chip, TRANSPORT_FAILED);
3669  }
3670 
3671  if ((0x53 != srb->cmnd[2]) || (0x44 != srb->cmnd[3]) || (0x20 != srb->cmnd[4]) ||
3672  (0x43 != srb->cmnd[5]) || (0x61 != srb->cmnd[6]) ||
3673  (0x72 != srb->cmnd[7]) || (0x64 != srb->cmnd[8])) {
3674  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3675  TRACE_RET(chip, TRANSPORT_FAILED);
3676  }
3677 
3678  switch (srb->cmnd[1] & 0x0F) {
3679  case 0:
3680  sd_card->sd_pass_thru_en = 0;
3681  break;
3682 
3683  case 1:
3684  sd_card->sd_pass_thru_en = 1;
3685  break;
3686 
3687  default:
3688  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3689  TRACE_RET(chip, TRANSPORT_FAILED);
3690  }
3691 
3692  buf[5] = (1 == CHK_SD(sd_card)) ? 0x01 : 0x02;
3693  if (chip->card_wp & SD_CARD)
3694  buf[5] |= 0x80;
3695 
3696  buf[6] = (u8)(sd_card->sd_addr >> 16);
3697  buf[7] = (u8)(sd_card->sd_addr >> 24);
3698 
3699  buf[15] = chip->max_lun;
3700 
3701  len = min(18, (int)scsi_bufflen(srb));
3702  rtsx_stor_set_xfer_buf(buf, len, srb);
3703 
3704  return TRANSPORT_GOOD;
3705 }
3706 
3707 static inline int get_rsp_type(struct scsi_cmnd *srb, u8 *rsp_type, int *rsp_len)
3708 {
3709  if (!rsp_type || !rsp_len)
3710  return STATUS_FAIL;
3711 
3712  switch (srb->cmnd[10]) {
3713  case 0x03:
3714  *rsp_type = SD_RSP_TYPE_R0;
3715  *rsp_len = 0;
3716  break;
3717 
3718  case 0x04:
3719  *rsp_type = SD_RSP_TYPE_R1;
3720  *rsp_len = 6;
3721  break;
3722 
3723  case 0x05:
3724  *rsp_type = SD_RSP_TYPE_R1b;
3725  *rsp_len = 6;
3726  break;
3727 
3728  case 0x06:
3729  *rsp_type = SD_RSP_TYPE_R2;
3730  *rsp_len = 17;
3731  break;
3732 
3733  case 0x07:
3734  *rsp_type = SD_RSP_TYPE_R3;
3735  *rsp_len = 6;
3736  break;
3737 
3738  default:
3739  return STATUS_FAIL;
3740  }
3741 
3742  return STATUS_SUCCESS;
3743 }
3744 
3745 int sd_execute_no_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3746 {
3747  struct sd_info *sd_card = &(chip->sd_card);
3748  unsigned int lun = SCSI_LUN(srb);
3749  int retval, rsp_len;
3750  u8 cmd_idx, rsp_type;
3751  u8 standby = 0, acmd = 0;
3752  u32 arg;
3753 
3754  if (!sd_card->sd_pass_thru_en) {
3755  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3756  TRACE_RET(chip, TRANSPORT_FAILED);
3757  }
3758 
3759  retval = sd_switch_clock(chip);
3760  if (retval != STATUS_SUCCESS)
3761  TRACE_RET(chip, TRANSPORT_FAILED);
3762 
3763  if (sd_card->pre_cmd_err) {
3764  sd_card->pre_cmd_err = 0;
3765  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
3766  TRACE_RET(chip, TRANSPORT_FAILED);
3767  }
3768 
3769  cmd_idx = srb->cmnd[2] & 0x3F;
3770  if (srb->cmnd[1] & 0x02)
3771  standby = 1;
3772 
3773  if (srb->cmnd[1] & 0x01)
3774  acmd = 1;
3775 
3776  arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) |
3777  ((u32)srb->cmnd[5] << 8) | srb->cmnd[6];
3778 
3779  retval = get_rsp_type(srb, &rsp_type, &rsp_len);
3780  if (retval != STATUS_SUCCESS) {
3781  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3782  TRACE_RET(chip, TRANSPORT_FAILED);
3783  }
3784  sd_card->last_rsp_type = rsp_type;
3785 
3786  retval = sd_switch_clock(chip);
3787  if (retval != STATUS_SUCCESS)
3788  TRACE_RET(chip, TRANSPORT_FAILED);
3789 
3790 #ifdef SUPPORT_SD_LOCK
3791  if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
3792  if (CHK_MMC_8BIT(sd_card)) {
3793  retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_8);
3794  if (retval != STATUS_SUCCESS)
3795  TRACE_RET(chip, TRANSPORT_FAILED);
3796 
3797  } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) {
3798  retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
3799  if (retval != STATUS_SUCCESS)
3800  TRACE_RET(chip, TRANSPORT_FAILED);
3801  }
3802  }
3803 #else
3804  retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
3805  if (retval != STATUS_SUCCESS)
3806  TRACE_RET(chip, TRANSPORT_FAILED);
3807 #endif
3808 
3809  if (standby) {
3810  retval = sd_select_card(chip, 0);
3811  if (retval != STATUS_SUCCESS)
3812  TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3813  }
3814 
3815  if (acmd) {
3816  retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
3817  SD_RSP_TYPE_R1, NULL, 0, 0);
3818  if (retval != STATUS_SUCCESS)
3819  TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3820  }
3821 
3822  retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type,
3823  sd_card->rsp, rsp_len, 0);
3824  if (retval != STATUS_SUCCESS)
3825  TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3826 
3827  if (standby) {
3828  retval = sd_select_card(chip, 1);
3829  if (retval != STATUS_SUCCESS)
3830  TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3831  }
3832 
3833 #ifdef SUPPORT_SD_LOCK
3834  retval = sd_update_lock_status(chip);
3835  if (retval != STATUS_SUCCESS)
3836  TRACE_GOTO(chip, SD_Execute_Cmd_Failed);
3837 #endif
3838 
3839  scsi_set_resid(srb, 0);
3840  return TRANSPORT_GOOD;
3841 
3842 SD_Execute_Cmd_Failed:
3843  sd_card->pre_cmd_err = 1;
3844  set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
3845  release_sd_card(chip);
3846  do_reset_sd_card(chip);
3847  if (!(chip->card_ready & SD_CARD))
3848  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
3849 
3850  TRACE_RET(chip, TRANSPORT_FAILED);
3851 }
3852 
3853 int sd_execute_read_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3854 {
3855  struct sd_info *sd_card = &(chip->sd_card);
3856  unsigned int lun = SCSI_LUN(srb);
3857  int retval, rsp_len, i;
3858  int cmd13_checkbit = 0, read_err = 0;
3859  u8 cmd_idx, rsp_type, bus_width;
3860  u8 send_cmd12 = 0, standby = 0, acmd = 0;
3861  u32 data_len;
3862 
3863  if (!sd_card->sd_pass_thru_en) {
3864  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3865  TRACE_RET(chip, TRANSPORT_FAILED);
3866  }
3867 
3868  if (sd_card->pre_cmd_err) {
3869  sd_card->pre_cmd_err = 0;
3870  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
3871  TRACE_RET(chip, TRANSPORT_FAILED);
3872  }
3873 
3874  retval = sd_switch_clock(chip);
3875  if (retval != STATUS_SUCCESS)
3876  TRACE_RET(chip, TRANSPORT_FAILED);
3877 
3878  cmd_idx = srb->cmnd[2] & 0x3F;
3879  if (srb->cmnd[1] & 0x04)
3880  send_cmd12 = 1;
3881 
3882  if (srb->cmnd[1] & 0x02)
3883  standby = 1;
3884 
3885  if (srb->cmnd[1] & 0x01)
3886  acmd = 1;
3887 
3888  data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8] << 8) | srb->cmnd[9];
3889 
3890  retval = get_rsp_type(srb, &rsp_type, &rsp_len);
3891  if (retval != STATUS_SUCCESS) {
3892  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3893  TRACE_RET(chip, TRANSPORT_FAILED);
3894  }
3895  sd_card->last_rsp_type = rsp_type;
3896 
3897  retval = sd_switch_clock(chip);
3898  if (retval != STATUS_SUCCESS)
3899  TRACE_RET(chip, TRANSPORT_FAILED);
3900 
3901 #ifdef SUPPORT_SD_LOCK
3902  if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
3903  if (CHK_MMC_8BIT(sd_card))
3904  bus_width = SD_BUS_WIDTH_8;
3905  else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card))
3906  bus_width = SD_BUS_WIDTH_4;
3907  else
3908  bus_width = SD_BUS_WIDTH_1;
3909  } else {
3910  bus_width = SD_BUS_WIDTH_4;
3911  }
3912  RTSX_DEBUGP("bus_width = %d\n", bus_width);
3913 #else
3914  bus_width = SD_BUS_WIDTH_4;
3915 #endif
3916 
3917  if (data_len < 512) {
3918  retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len,
3919  SD_RSP_TYPE_R1, NULL, 0, 0);
3920  if (retval != STATUS_SUCCESS)
3921  TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
3922  }
3923 
3924  if (standby) {
3925  retval = sd_select_card(chip, 0);
3926  if (retval != STATUS_SUCCESS)
3927  TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
3928  }
3929 
3930  if (acmd) {
3931  retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
3932  SD_RSP_TYPE_R1, NULL, 0, 0);
3933  if (retval != STATUS_SUCCESS)
3934  TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
3935  }
3936 
3937  if (data_len <= 512) {
3938  int min_len;
3939  u8 *buf;
3940  u16 byte_cnt, blk_cnt;
3941  u8 cmd[5];
3942 
3943  byte_cnt = ((u16)(srb->cmnd[8] & 0x03) << 8) | srb->cmnd[9];
3944  blk_cnt = 1;
3945 
3946  cmd[0] = 0x40 | cmd_idx;
3947  cmd[1] = srb->cmnd[3];
3948  cmd[2] = srb->cmnd[4];
3949  cmd[3] = srb->cmnd[5];
3950  cmd[4] = srb->cmnd[6];
3951 
3952  buf = kmalloc(data_len, GFP_KERNEL);
3953  if (buf == NULL)
3954  TRACE_RET(chip, TRANSPORT_ERROR);
3955 
3956  retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, byte_cnt,
3957  blk_cnt, bus_width, buf, data_len, 2000);
3958  if (retval != STATUS_SUCCESS) {
3959  read_err = 1;
3960  kfree(buf);
3961  rtsx_clear_sd_error(chip);
3962  TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
3963  }
3964 
3965  min_len = min(data_len, scsi_bufflen(srb));
3966  rtsx_stor_set_xfer_buf(buf, min_len, srb);
3967 
3968  kfree(buf);
3969  } else if (!(data_len & 0x1FF)) {
3970  rtsx_init_cmd(chip);
3971 
3972  trans_dma_enable(DMA_FROM_DEVICE, chip, data_len, DMA_512);
3973 
3974  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 0x02);
3975  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x00);
3976  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H,
3977  0xFF, (srb->cmnd[7] & 0xFE) >> 1);
3978  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L,
3979  0xFF, (u8)((data_len & 0x0001FE00) >> 9));
3980 
3981  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
3982  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, srb->cmnd[3]);
3983  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, srb->cmnd[4]);
3984  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, srb->cmnd[5]);
3985  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, srb->cmnd[6]);
3986 
3987  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
3988  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
3989 
3990  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
3991  0xFF, SD_TM_AUTO_READ_2 | SD_TRANSFER_START);
3992  rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
3993 
3994  rtsx_send_cmd_no_wait(chip);
3995 
3996  retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb), scsi_bufflen(srb),
3997  scsi_sg_count(srb), DMA_FROM_DEVICE, 10000);
3998  if (retval < 0) {
3999  read_err = 1;
4000  rtsx_clear_sd_error(chip);
4001  TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4002  }
4003 
4004  } else {
4005  TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4006  }
4007 
4008  retval = ext_sd_get_rsp(chip, rsp_len, sd_card->rsp, rsp_type);
4009  if (retval != STATUS_SUCCESS)
4010  TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4011 
4012  if (standby) {
4013  retval = sd_select_card(chip, 1);
4014  if (retval != STATUS_SUCCESS)
4015  TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4016  }
4017 
4018  if (send_cmd12) {
4019  retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION,
4020  0, SD_RSP_TYPE_R1b, NULL, 0, 0);
4021  if (retval != STATUS_SUCCESS)
4022  TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4023  }
4024 
4025  if (data_len < 512) {
4026  retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200,
4027  SD_RSP_TYPE_R1, NULL, 0, 0);
4028  if (retval != STATUS_SUCCESS)
4029  TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4030 
4031  retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02);
4032  if (retval != STATUS_SUCCESS)
4033  TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4034 
4035  retval = rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00);
4036  if (retval != STATUS_SUCCESS)
4037  TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4038  }
4039 
4040  if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04))
4041  cmd13_checkbit = 1;
4042 
4043  for (i = 0; i < 3; i++) {
4044  retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
4045  SD_RSP_TYPE_R1, NULL, 0, cmd13_checkbit);
4046  if (retval == STATUS_SUCCESS)
4047  break;
4048  }
4049  if (retval != STATUS_SUCCESS)
4050  TRACE_GOTO(chip, SD_Execute_Read_Cmd_Failed);
4051 
4052  scsi_set_resid(srb, 0);
4053  return TRANSPORT_GOOD;
4054 
4055 SD_Execute_Read_Cmd_Failed:
4056  sd_card->pre_cmd_err = 1;
4057  set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4058  if (read_err)
4059  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
4060 
4061  release_sd_card(chip);
4062  do_reset_sd_card(chip);
4063  if (!(chip->card_ready & SD_CARD))
4064  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4065 
4066  TRACE_RET(chip, TRANSPORT_FAILED);
4067 }
4068 
4069 int sd_execute_write_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4070 {
4071  struct sd_info *sd_card = &(chip->sd_card);
4072  unsigned int lun = SCSI_LUN(srb);
4073  int retval, rsp_len, i;
4074  int cmd13_checkbit = 0, write_err = 0;
4075  u8 cmd_idx, rsp_type;
4076  u8 send_cmd12 = 0, standby = 0, acmd = 0;
4077  u32 data_len, arg;
4078 #ifdef SUPPORT_SD_LOCK
4079  int lock_cmd_fail = 0;
4080  u8 sd_lock_state = 0;
4081  u8 lock_cmd_type = 0;
4082 #endif
4083 
4084  if (!sd_card->sd_pass_thru_en) {
4085  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4086  TRACE_RET(chip, TRANSPORT_FAILED);
4087  }
4088 
4089  if (sd_card->pre_cmd_err) {
4090  sd_card->pre_cmd_err = 0;
4091  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4092  TRACE_RET(chip, TRANSPORT_FAILED);
4093  }
4094 
4095  retval = sd_switch_clock(chip);
4096  if (retval != STATUS_SUCCESS)
4097  TRACE_RET(chip, TRANSPORT_FAILED);
4098 
4099  cmd_idx = srb->cmnd[2] & 0x3F;
4100  if (srb->cmnd[1] & 0x04)
4101  send_cmd12 = 1;
4102 
4103  if (srb->cmnd[1] & 0x02)
4104  standby = 1;
4105 
4106  if (srb->cmnd[1] & 0x01)
4107  acmd = 1;
4108 
4109  data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8] << 8) | srb->cmnd[9];
4110  arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) |
4111  ((u32)srb->cmnd[5] << 8) | srb->cmnd[6];
4112 
4113 #ifdef SUPPORT_SD_LOCK
4114  if (cmd_idx == LOCK_UNLOCK) {
4115  sd_lock_state = sd_card->sd_lock_status;
4116  sd_lock_state &= SD_LOCKED;
4117  }
4118 #endif
4119 
4120  retval = get_rsp_type(srb, &rsp_type, &rsp_len);
4121  if (retval != STATUS_SUCCESS) {
4122  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4123  TRACE_RET(chip, TRANSPORT_FAILED);
4124  }
4125  sd_card->last_rsp_type = rsp_type;
4126 
4127  retval = sd_switch_clock(chip);
4128  if (retval != STATUS_SUCCESS)
4129  TRACE_RET(chip, TRANSPORT_FAILED);
4130 
4131 #ifdef SUPPORT_SD_LOCK
4132  if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
4133  if (CHK_MMC_8BIT(sd_card)) {
4134  retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_8);
4135  if (retval != STATUS_SUCCESS)
4136  TRACE_RET(chip, TRANSPORT_FAILED);
4137 
4138  } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) {
4139  retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
4140  if (retval != STATUS_SUCCESS)
4141  TRACE_RET(chip, TRANSPORT_FAILED);
4142  }
4143  }
4144 #else
4145  retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
4146  if (retval != STATUS_SUCCESS)
4147  TRACE_RET(chip, TRANSPORT_FAILED);
4148 #endif
4149 
4150  if (data_len < 512) {
4151  retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len,
4152  SD_RSP_TYPE_R1, NULL, 0, 0);
4153  if (retval != STATUS_SUCCESS)
4154  TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4155  }
4156 
4157  if (standby) {
4158  retval = sd_select_card(chip, 0);
4159  if (retval != STATUS_SUCCESS)
4160  TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4161  }
4162 
4163  if (acmd) {
4164  retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
4165  SD_RSP_TYPE_R1, NULL, 0, 0);
4166  if (retval != STATUS_SUCCESS)
4167  TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4168  }
4169 
4170  retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type,
4171  sd_card->rsp, rsp_len, 0);
4172  if (retval != STATUS_SUCCESS)
4173  TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4174 
4175  if (data_len <= 512) {
4176  u16 i;
4177  u8 *buf;
4178 
4179  buf = kmalloc(data_len, GFP_KERNEL);
4180  if (buf == NULL)
4181  TRACE_RET(chip, TRANSPORT_ERROR);
4182 
4183  rtsx_stor_get_xfer_buf(buf, data_len, srb);
4184 
4185 #ifdef SUPPORT_SD_LOCK
4186  if (cmd_idx == LOCK_UNLOCK)
4187  lock_cmd_type = buf[0] & 0x0F;
4188 #endif
4189 
4190  if (data_len > 256) {
4191  rtsx_init_cmd(chip);
4192  for (i = 0; i < 256; i++) {
4193  rtsx_add_cmd(chip, WRITE_REG_CMD,
4194  PPBUF_BASE2 + i, 0xFF, buf[i]);
4195  }
4196  retval = rtsx_send_cmd(chip, 0, 250);
4197  if (retval != STATUS_SUCCESS) {
4198  kfree(buf);
4199  TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4200  }
4201 
4202  rtsx_init_cmd(chip);
4203  for (i = 256; i < data_len; i++) {
4204  rtsx_add_cmd(chip, WRITE_REG_CMD,
4205  PPBUF_BASE2 + i, 0xFF, buf[i]);
4206  }
4207  retval = rtsx_send_cmd(chip, 0, 250);
4208  if (retval != STATUS_SUCCESS) {
4209  kfree(buf);
4210  TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4211  }
4212  } else {
4213  rtsx_init_cmd(chip);
4214  for (i = 0; i < data_len; i++) {
4215  rtsx_add_cmd(chip, WRITE_REG_CMD,
4216  PPBUF_BASE2 + i, 0xFF, buf[i]);
4217  }
4218  retval = rtsx_send_cmd(chip, 0, 250);
4219  if (retval != STATUS_SUCCESS) {
4220  kfree(buf);
4221  TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4222  }
4223  }
4224 
4225  kfree(buf);
4226 
4227  rtsx_init_cmd(chip);
4228 
4229  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, srb->cmnd[8] & 0x03);
4230  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, srb->cmnd[9]);
4231  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0x00);
4232  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 0x01);
4233  rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
4234 
4235  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
4236  SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
4237  rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
4238 
4239  retval = rtsx_send_cmd(chip, SD_CARD, 250);
4240  } else if (!(data_len & 0x1FF)) {
4241  rtsx_init_cmd(chip);
4242 
4243  trans_dma_enable(DMA_TO_DEVICE, chip, data_len, DMA_512);
4244 
4245  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 0x02);
4246  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x00);
4247  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H,
4248  0xFF, (srb->cmnd[7] & 0xFE) >> 1);
4249  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L,
4250  0xFF, (u8)((data_len & 0x0001FE00) >> 9));
4251 
4252  rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
4253  rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
4254 
4255  rtsx_send_cmd_no_wait(chip);
4256 
4257  retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb), scsi_bufflen(srb),
4258  scsi_sg_count(srb), DMA_TO_DEVICE, 10000);
4259 
4260  } else {
4261  TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4262  }
4263 
4264  if (retval < 0) {
4265  write_err = 1;
4266  rtsx_clear_sd_error(chip);
4267  TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4268  }
4269 
4270 #ifdef SUPPORT_SD_LOCK
4271  if (cmd_idx == LOCK_UNLOCK) {
4272  if (lock_cmd_type == SD_ERASE) {
4273  sd_card->sd_erase_status = SD_UNDER_ERASING;
4274  scsi_set_resid(srb, 0);
4275  return TRANSPORT_GOOD;
4276  }
4277 
4278  rtsx_init_cmd(chip);
4279  if (CHECK_PID(chip, 0x5209))
4280  rtsx_add_cmd(chip, CHECK_REG_CMD, SD_BUS_STAT, SD_DAT0_STATUS, SD_DAT0_STATUS);
4281  else
4282  rtsx_add_cmd(chip, CHECK_REG_CMD, 0xFD30, 0x02, 0x02);
4283 
4284  rtsx_send_cmd(chip, SD_CARD, 250);
4285 
4286  retval = sd_update_lock_status(chip);
4287  if (retval != STATUS_SUCCESS) {
4288  RTSX_DEBUGP("Lock command fail!\n");
4289  lock_cmd_fail = 1;
4290  }
4291  }
4292 #endif /* SUPPORT_SD_LOCK */
4293 
4294  if (standby) {
4295  retval = sd_select_card(chip, 1);
4296  if (retval != STATUS_SUCCESS)
4297  TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4298  }
4299 
4300  if (send_cmd12) {
4301  retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION,
4302  0, SD_RSP_TYPE_R1b, NULL, 0, 0);
4303  if (retval != STATUS_SUCCESS)
4304  TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4305  }
4306 
4307  if (data_len < 512) {
4308  retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200,
4309  SD_RSP_TYPE_R1, NULL, 0, 0);
4310  if (retval != STATUS_SUCCESS)
4311  TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4312 
4313  retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02);
4314  if (retval != STATUS_SUCCESS)
4315  TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4316 
4317  rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00);
4318  if (retval != STATUS_SUCCESS)
4319  TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4320  }
4321 
4322  if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04))
4323  cmd13_checkbit = 1;
4324 
4325  for (i = 0; i < 3; i++) {
4326  retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
4327  SD_RSP_TYPE_R1, NULL, 0, cmd13_checkbit);
4328  if (retval == STATUS_SUCCESS)
4329  break;
4330  }
4331  if (retval != STATUS_SUCCESS)
4332  TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4333 
4334 #ifdef SUPPORT_SD_LOCK
4335  if (cmd_idx == LOCK_UNLOCK) {
4336  if (!lock_cmd_fail) {
4337  RTSX_DEBUGP("lock_cmd_type = 0x%x\n", lock_cmd_type);
4338  if (lock_cmd_type & SD_CLR_PWD)
4339  sd_card->sd_lock_status &= ~SD_PWD_EXIST;
4340 
4341  if (lock_cmd_type & SD_SET_PWD)
4342  sd_card->sd_lock_status |= SD_PWD_EXIST;
4343  }
4344 
4345  RTSX_DEBUGP("sd_lock_state = 0x%x, sd_card->sd_lock_status = 0x%x\n",
4346  sd_lock_state, sd_card->sd_lock_status);
4347  if (sd_lock_state ^ (sd_card->sd_lock_status & SD_LOCKED)) {
4348  sd_card->sd_lock_notify = 1;
4349  if (sd_lock_state) {
4350  if (sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) {
4351  sd_card->sd_lock_status |= (SD_UNLOCK_POW_ON | SD_SDR_RST);
4352  if (CHK_SD(sd_card)) {
4353  retval = reset_sd(chip);
4354  if (retval != STATUS_SUCCESS) {
4355  sd_card->sd_lock_status &= ~(SD_UNLOCK_POW_ON | SD_SDR_RST);
4356  TRACE_GOTO(chip, SD_Execute_Write_Cmd_Failed);
4357  }
4358  }
4359 
4360  sd_card->sd_lock_status &= ~(SD_UNLOCK_POW_ON | SD_SDR_RST);
4361  }
4362  }
4363  }
4364  }
4365 
4366  if (lock_cmd_fail) {
4367  scsi_set_resid(srb, 0);
4368  set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4369  TRACE_RET(chip, TRANSPORT_FAILED);
4370  }
4371 #endif /* SUPPORT_SD_LOCK */
4372 
4373  scsi_set_resid(srb, 0);
4374  return TRANSPORT_GOOD;
4375 
4376 SD_Execute_Write_Cmd_Failed:
4377  sd_card->pre_cmd_err = 1;
4378  set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4379  if (write_err)
4380  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
4381 
4382  release_sd_card(chip);
4383  do_reset_sd_card(chip);
4384  if (!(chip->card_ready & SD_CARD))
4385  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4386 
4387  TRACE_RET(chip, TRANSPORT_FAILED);
4388 }
4389 
4390 int sd_get_cmd_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4391 {
4392  struct sd_info *sd_card = &(chip->sd_card);
4393  unsigned int lun = SCSI_LUN(srb);
4394  int count;
4395  u16 data_len;
4396 
4397  if (!sd_card->sd_pass_thru_en) {
4398  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4399  TRACE_RET(chip, TRANSPORT_FAILED);
4400  }
4401 
4402  if (sd_card->pre_cmd_err) {
4403  sd_card->pre_cmd_err = 0;
4404  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4405  TRACE_RET(chip, TRANSPORT_FAILED);
4406  }
4407 
4408  data_len = ((u16)srb->cmnd[7] << 8) | srb->cmnd[8];
4409 
4410  if (sd_card->last_rsp_type == SD_RSP_TYPE_R0) {
4411  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4412  TRACE_RET(chip, TRANSPORT_FAILED);
4413  } else if (sd_card->last_rsp_type == SD_RSP_TYPE_R2) {
4414  count = (data_len < 17) ? data_len : 17;
4415  } else {
4416  count = (data_len < 6) ? data_len : 6;
4417  }
4418  rtsx_stor_set_xfer_buf(sd_card->rsp, count, srb);
4419 
4420  RTSX_DEBUGP("Response length: %d\n", data_len);
4421  RTSX_DEBUGP("Response: 0x%x 0x%x 0x%x 0x%x\n",
4422  sd_card->rsp[0], sd_card->rsp[1], sd_card->rsp[2], sd_card->rsp[3]);
4423 
4424  scsi_set_resid(srb, 0);
4425  return TRANSPORT_GOOD;
4426 }
4427 
4428 int sd_hw_rst(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4429 {
4430  struct sd_info *sd_card = &(chip->sd_card);
4431  unsigned int lun = SCSI_LUN(srb);
4432  int retval;
4433 
4434  if (!sd_card->sd_pass_thru_en) {
4435  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4436  TRACE_RET(chip, TRANSPORT_FAILED);
4437  }
4438 
4439  if (sd_card->pre_cmd_err) {
4440  sd_card->pre_cmd_err = 0;
4441  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4442  TRACE_RET(chip, TRANSPORT_FAILED);
4443  }
4444 
4445  if ((0x53 != srb->cmnd[2]) || (0x44 != srb->cmnd[3]) || (0x20 != srb->cmnd[4]) ||
4446  (0x43 != srb->cmnd[5]) || (0x61 != srb->cmnd[6]) ||
4447  (0x72 != srb->cmnd[7]) || (0x64 != srb->cmnd[8])) {
4448  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4449  TRACE_RET(chip, TRANSPORT_FAILED);
4450  }
4451 
4452  switch (srb->cmnd[1] & 0x0F) {
4453  case 0:
4454 #ifdef SUPPORT_SD_LOCK
4455  if (0x64 == srb->cmnd[9])
4456  sd_card->sd_lock_status |= SD_SDR_RST;
4457 #endif
4458  retval = reset_sd_card(chip);
4459  if (retval != STATUS_SUCCESS) {
4460 #ifdef SUPPORT_SD_LOCK
4461  sd_card->sd_lock_status &= ~SD_SDR_RST;
4462 #endif
4463  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4464  sd_card->pre_cmd_err = 1;
4465  TRACE_RET(chip, TRANSPORT_FAILED);
4466  }
4467 #ifdef SUPPORT_SD_LOCK
4468  sd_card->sd_lock_status &= ~SD_SDR_RST;
4469 #endif
4470  break;
4471 
4472  case 1:
4473  retval = soft_reset_sd_card(chip);
4474  if (retval != STATUS_SUCCESS) {
4475  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4476  sd_card->pre_cmd_err = 1;
4477  TRACE_RET(chip, TRANSPORT_FAILED);
4478  }
4479  break;
4480 
4481  default:
4482  set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4483  TRACE_RET(chip, TRANSPORT_FAILED);
4484  }
4485 
4486  scsi_set_resid(srb, 0);
4487  return TRANSPORT_GOOD;
4488 }
4489 #endif
4490 
4491 void sd_cleanup_work(struct rtsx_chip *chip)
4492 {
4493  struct sd_info *sd_card = &(chip->sd_card);
4494 
4495  if (sd_card->seq_mode) {
4496  RTSX_DEBUGP("SD: stop transmission\n");
4497  sd_stop_seq_mode(chip);
4498  sd_card->cleanup_counter = 0;
4499  }
4500 }
4501 
4502 int sd_power_off_card3v3(struct rtsx_chip *chip)
4503 {
4504  int retval;
4505 
4506  retval = disable_card_clock(chip, SD_CARD);
4507  if (retval != STATUS_SUCCESS)
4508  TRACE_RET(chip, STATUS_FAIL);
4509 
4510  RTSX_WRITE_REG(chip, CARD_OE, SD_OUTPUT_EN, 0);
4511 
4512  if (!chip->ft2_fast_mode) {
4513  retval = card_power_off(chip, SD_CARD);
4514  if (retval != STATUS_SUCCESS)
4515  TRACE_RET(chip, STATUS_FAIL);
4516 
4517  wait_timeout(50);
4518  }
4519 
4520  if (chip->asic_code) {
4521  retval = sd_pull_ctl_disable(chip);
4522  if (retval != STATUS_SUCCESS)
4523  TRACE_RET(chip, STATUS_FAIL);
4524  } else {
4525  RTSX_WRITE_REG(chip, FPGA_PULL_CTL,
4526  FPGA_SD_PULL_CTL_BIT | 0x20, FPGA_SD_PULL_CTL_BIT);
4527  }
4528 
4529  return STATUS_SUCCESS;
4530 }
4531 
4532 int release_sd_card(struct rtsx_chip *chip)
4533 {
4534  struct sd_info *sd_card = &(chip->sd_card);
4535  int retval;
4536 
4537  RTSX_DEBUGP("release_sd_card\n");
4538 
4539  chip->card_ready &= ~SD_CARD;
4540  chip->card_fail &= ~SD_CARD;
4541  chip->card_wp &= ~SD_CARD;
4542 
4543  chip->sd_io = 0;
4544  chip->sd_int = 0;
4545 
4546 #ifdef SUPPORT_SD_LOCK
4547  sd_card->sd_lock_status = 0;
4548  sd_card->sd_erase_status = 0;
4549 #endif
4550 
4551  memset(sd_card->raw_csd, 0, 16);
4552  memset(sd_card->raw_scr, 0, 8);
4553 
4554  retval = sd_power_off_card3v3(chip);
4555  if (retval != STATUS_SUCCESS)
4556  TRACE_RET(chip, STATUS_FAIL);
4557 
4558  if (CHECK_PID(chip, 0x5209)) {
4559  retval = sd_change_bank_voltage(chip, SD_IO_3V3);
4560  if (retval != STATUS_SUCCESS)
4561  TRACE_RET(chip, STATUS_FAIL);
4562 
4563  if (CHK_SD30_SPEED(sd_card))
4564  RTSX_WRITE_REG(chip, SD30_DRIVE_SEL, 0x07, chip->sd30_drive_sel_3v3);
4565 
4566  RTSX_WRITE_REG(chip, OCPPARA2, SD_OCP_THD_MASK, chip->sd_400mA_ocp_thd);
4567  }
4568 
4569  return STATUS_SUCCESS;
4570 }
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