Linux Kernel
3.7.1
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#include <i915_drv.h>
Definition at line 920 of file i915_drv.h.
unsigned int active |
This is set if the object is on the active lists (has pending rendering and so a non-zero seqno), and is not set if it i s on inactive (ready to be unbound) list.
Definition at line 940 of file i915_drv.h.
struct drm_gem_object base |
Definition at line 921 of file i915_drv.h.
unsigned long* bit_17 |
Record of address bit 17 of each page at last unbind.
Definition at line 1044 of file i915_drv.h.
unsigned int cache_level |
Definition at line 1005 of file i915_drv.h.
unsigned int dirty |
This is set if the object has been written to since last bound to the GTT
Definition at line 946 of file i915_drv.h.
void* dma_buf_vmapping |
Definition at line 1015 of file i915_drv.h.
struct drm_i915_gem_exec_object2* exec_entry |
Definition at line 1023 of file i915_drv.h.
unsigned long exec_handle |
Definition at line 1022 of file i915_drv.h.
This object's place in the batchbuffer or on the eviction list
Definition at line 933 of file i915_drv.h.
struct hlist_node exec_node |
Used for performing relocations during execbuffer insertion.
Definition at line 1021 of file i915_drv.h.
unsigned int fault_mappable |
Whether the current gtt mapping needs to be mappable (and isn't just mappable by accident). Track pin and fault separate for a more accurate mappable working set.
Definition at line 996 of file i915_drv.h.
unsigned int fence_dirty |
Whether the tiling parameters for the currently associated fence register have changed. Note that for the purposes of tracking tiling changes we also treat the unfenced register, the register slot that the object occupies whilst it executes a fenced command (such as BLT on gen2/3), as a "fence".
Definition at line 971 of file i915_drv.h.
signed int fence_reg |
Fence register bits (if any) for this object. Will be set as needed when mapped into the GTT. Protected by dev->struct_mutex.
Definition at line 953 of file i915_drv.h.
unsigned int fenced_gpu_access |
Definition at line 1003 of file i915_drv.h.
Definition at line 927 of file i915_drv.h.
uint32_t gtt_offset |
Current offset of the object in GTT space.
This is the same as gtt_space->start
Definition at line 1030 of file i915_drv.h.
struct drm_mm_node* gtt_space |
Current space allocated to this object in the GTT, if any.
Definition at line 926 of file i915_drv.h.
unsigned int has_aliasing_ppgtt_mapping |
Definition at line 1007 of file i915_drv.h.
unsigned int has_dma_mapping |
Definition at line 1009 of file i915_drv.h.
unsigned int has_global_gtt_mapping |
Definition at line 1008 of file i915_drv.h.
uint32_t last_fenced_seqno |
Breadcrumb of last fenced GPU access to the buffer.
Definition at line 1038 of file i915_drv.h.
uint32_t last_read_seqno |
Breadcrumb of last rendering to the buffer.
Definition at line 1035 of file i915_drv.h.
uint32_t last_write_seqno |
Definition at line 1036 of file i915_drv.h.
unsigned int madv |
Advice: are the backing pages purgeable?
Definition at line 958 of file i915_drv.h.
unsigned int map_and_fenceable |
Is the object at the current location in the gtt mappable and fenceable? Used to avoid costly recalculations.
Definition at line 989 of file i915_drv.h.
Definition at line 931 of file i915_drv.h.
Definition at line 923 of file i915_drv.h.
Definition at line 1011 of file i915_drv.h.
int pages_pin_count |
Definition at line 1012 of file i915_drv.h.
unsigned int pending_fenced_gpu_access |
Definition at line 1002 of file i915_drv.h.
atomic_t pending_flip |
Number of crtcs where this object is currently the fb, but will be page flipped away on the next vblank. When it reaches 0, dev_priv->pending_flip_queue will be woken up.
Definition at line 1058 of file i915_drv.h.
struct drm_i915_gem_phys_object* phys_obj |
for phy allocated objects
Definition at line 1051 of file i915_drv.h.
unsigned int pin_count |
How many users have pinned this object in GTT space. The following users can each hold at most one reference: pwrite/pread, pin_ioctl (via user_pin_count), execbuffer (objects are not allowed multiple times for the same batchbuffer), and the framebuffer code. When switching/pageflipping, the framebuffer code has at most two buffers pinned per crtc.
In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 bits with absolutely no headroom. So use 4 bits.
Definition at line 982 of file i915_drv.h.
struct drm_file* pin_filp |
Definition at line 1048 of file i915_drv.h.
unsigned int pin_mappable |
Definition at line 997 of file i915_drv.h.
Definition at line 1032 of file i915_drv.h.
This object's place on the active/inactive lists
Definition at line 930 of file i915_drv.h.
uint32_t stride |
Current tiling stride for the object, if it's tiled.
Definition at line 1041 of file i915_drv.h.
unsigned int tiling_mode |
Current tiling mode for the object.
Definition at line 963 of file i915_drv.h.
uint32_t user_pin_count |
User space pin count and filp owning the pin
Definition at line 1047 of file i915_drv.h.
int vmapping_count |
Definition at line 1016 of file i915_drv.h.