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nvc0.c
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1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24 
25 #include <core/gpuobj.h>
26 
27 #include <subdev/timer.h>
28 #include <subdev/bar.h>
29 #include <subdev/fb.h>
30 #include <subdev/vm.h>
31 
32 struct nvc0_bar_priv {
33  struct nouveau_bar base;
35  struct {
38  struct nouveau_vm *vm;
39  } bar[2];
40 };
41 
42 static int
43 nvc0_bar_kmap(struct nouveau_bar *bar, struct nouveau_mem *mem,
44  u32 flags, struct nouveau_vma *vma)
45 {
46  struct nvc0_bar_priv *priv = (void *)bar;
47  int ret;
48 
49  ret = nouveau_vm_get(priv->bar[0].vm, mem->size << 12, 12, flags, vma);
50  if (ret)
51  return ret;
52 
53  nouveau_vm_map(vma, mem);
54  nvc0_vm_flush_engine(nv_subdev(bar), priv->bar[0].pgd->addr, 5);
55  return 0;
56 }
57 
58 static int
59 nvc0_bar_umap(struct nouveau_bar *bar, struct nouveau_mem *mem,
60  u32 flags, struct nouveau_vma *vma)
61 {
62  struct nvc0_bar_priv *priv = (void *)bar;
63  int ret;
64 
65  ret = nouveau_vm_get(priv->bar[1].vm, mem->size << 12,
66  mem->page_shift, flags, vma);
67  if (ret)
68  return ret;
69 
70  nouveau_vm_map(vma, mem);
71  nvc0_vm_flush_engine(nv_subdev(bar), priv->bar[1].pgd->addr, 5);
72  return 0;
73 }
74 
75 static void
76 nvc0_bar_unmap(struct nouveau_bar *bar, struct nouveau_vma *vma)
77 {
78  struct nvc0_bar_priv *priv = (void *)bar;
79  int i = !(vma->vm == priv->bar[0].vm);
80 
81  nouveau_vm_unmap(vma);
82  nvc0_vm_flush_engine(nv_subdev(bar), priv->bar[i].pgd->addr, 5);
83  nouveau_vm_put(vma);
84 }
85 
86 static int
87 nvc0_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
88  struct nouveau_oclass *oclass, void *data, u32 size,
89  struct nouveau_object **pobject)
90 {
91  struct nouveau_device *device = nv_device(parent);
92  struct pci_dev *pdev = device->pdev;
93  struct nvc0_bar_priv *priv;
94  struct nouveau_gpuobj *mem;
95  struct nouveau_vm *vm;
96  int ret;
97 
98  ret = nouveau_bar_create(parent, engine, oclass, &priv);
99  *pobject = nv_object(priv);
100  if (ret)
101  return ret;
102 
103  /* BAR3 */
104  ret = nouveau_gpuobj_new(parent, NULL, 0x1000, 0, 0, &priv->bar[0].mem);
105  mem = priv->bar[0].mem;
106  if (ret)
107  return ret;
108 
109  ret = nouveau_gpuobj_new(parent, NULL, 0x8000, 0, 0, &priv->bar[0].pgd);
110  if (ret)
111  return ret;
112 
113  ret = nouveau_vm_new(device, 0, pci_resource_len(pdev, 3), 0, &vm);
114  if (ret)
115  return ret;
116 
117  ret = nouveau_gpuobj_new(parent, NULL,
118  (pci_resource_len(pdev, 3) >> 12) * 8,
119  0x1000, NVOBJ_FLAG_ZERO_ALLOC,
120  &vm->pgt[0].obj[0]);
121  vm->pgt[0].refcount[0] = 1;
122  if (ret)
123  return ret;
124 
125  ret = nouveau_vm_ref(vm, &priv->bar[0].vm, priv->bar[0].pgd);
126  nouveau_vm_ref(NULL, &vm, NULL);
127  if (ret)
128  return ret;
129 
130  nv_wo32(mem, 0x0200, lower_32_bits(priv->bar[0].pgd->addr));
131  nv_wo32(mem, 0x0204, upper_32_bits(priv->bar[0].pgd->addr));
132  nv_wo32(mem, 0x0208, lower_32_bits(pci_resource_len(pdev, 3) - 1));
133  nv_wo32(mem, 0x020c, upper_32_bits(pci_resource_len(pdev, 3) - 1));
134 
135  /* BAR1 */
136  ret = nouveau_gpuobj_new(parent, NULL, 0x1000, 0, 0, &priv->bar[1].mem);
137  mem = priv->bar[1].mem;
138  if (ret)
139  return ret;
140 
141  ret = nouveau_gpuobj_new(parent, NULL, 0x8000, 0, 0, &priv->bar[1].pgd);
142  if (ret)
143  return ret;
144 
145  ret = nouveau_vm_new(device, 0, pci_resource_len(pdev, 1), 0, &vm);
146  if (ret)
147  return ret;
148 
149  ret = nouveau_vm_ref(vm, &priv->bar[1].vm, priv->bar[1].pgd);
150  nouveau_vm_ref(NULL, &vm, NULL);
151  if (ret)
152  return ret;
153 
154  nv_wo32(mem, 0x0200, lower_32_bits(priv->bar[1].pgd->addr));
155  nv_wo32(mem, 0x0204, upper_32_bits(priv->bar[1].pgd->addr));
156  nv_wo32(mem, 0x0208, lower_32_bits(pci_resource_len(pdev, 1) - 1));
157  nv_wo32(mem, 0x020c, upper_32_bits(pci_resource_len(pdev, 1) - 1));
158 
159  priv->base.alloc = nouveau_bar_alloc;
160  priv->base.kmap = nvc0_bar_kmap;
161  priv->base.umap = nvc0_bar_umap;
162  priv->base.unmap = nvc0_bar_unmap;
163  priv->base.flush = nv84_bar_flush;
164  spin_lock_init(&priv->lock);
165  return 0;
166 }
167 
168 static void
169 nvc0_bar_dtor(struct nouveau_object *object)
170 {
171  struct nvc0_bar_priv *priv = (void *)object;
172 
173  nouveau_vm_ref(NULL, &priv->bar[1].vm, priv->bar[1].pgd);
174  nouveau_gpuobj_ref(NULL, &priv->bar[1].pgd);
175  nouveau_gpuobj_ref(NULL, &priv->bar[1].mem);
176 
177  if (priv->bar[0].vm) {
178  nouveau_gpuobj_ref(NULL, &priv->bar[0].vm->pgt[0].obj[0]);
179  nouveau_vm_ref(NULL, &priv->bar[0].vm, priv->bar[0].pgd);
180  }
181  nouveau_gpuobj_ref(NULL, &priv->bar[0].pgd);
182  nouveau_gpuobj_ref(NULL, &priv->bar[0].mem);
183 
184  nouveau_bar_destroy(&priv->base);
185 }
186 
187 static int
188 nvc0_bar_init(struct nouveau_object *object)
189 {
190  struct nvc0_bar_priv *priv = (void *)object;
191  int ret;
192 
193  ret = nouveau_bar_init(&priv->base);
194  if (ret)
195  return ret;
196 
197  nv_mask(priv, 0x000200, 0x00000100, 0x00000000);
198  nv_mask(priv, 0x000200, 0x00000100, 0x00000100);
199  nv_mask(priv, 0x100c80, 0x00000001, 0x00000000);
200 
201  nv_wr32(priv, 0x001704, 0x80000000 | priv->bar[1].mem->addr >> 12);
202  nv_wr32(priv, 0x001714, 0xc0000000 | priv->bar[0].mem->addr >> 12);
203  return 0;
204 }
205 
206 struct nouveau_oclass
208  .handle = NV_SUBDEV(BAR, 0xc0),
209  .ofuncs = &(struct nouveau_ofuncs) {
210  .ctor = nvc0_bar_ctor,
211  .dtor = nvc0_bar_dtor,
212  .init = nvc0_bar_init,
213  .fini = _nouveau_bar_fini,
214  },
215 };