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Linux Kernel
3.7.1
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All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
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Linux Kernel
3.7.1
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#include <linux/module.h>#include <linux/kernel.h>#include <linux/types.h>#include <linux/fcntl.h>#include <linux/interrupt.h>#include <linux/ioport.h>#include <linux/in.h>#include <linux/if_vlan.h>#include <linux/slab.h>#include <linux/string.h>#include <linux/spinlock.h>#include <linux/errno.h>#include <linux/init.h>#include <linux/netdevice.h>#include <linux/etherdevice.h>#include <linux/skbuff.h>#include <linux/delay.h>#include <linux/pci.h>#include <linux/phy.h>#include <linux/workqueue.h>#include <linux/platform_device.h>#include <linux/prefetch.h>#include <asm/io.h>#include <asm/byteorder.h>Go to the source code of this file.
Data Structures | |
| struct | tc35815_options |
| struct | tc35815_regs |
| struct | FDesc |
| struct | BDesc |
| struct | TxFD |
| struct | RxFD |
| struct | FrFD |
| struct | tc35815_local |
Macros | |
| #define | DRV_VERSION "1.39" |
| #define | MODNAME "tc35815" |
| #define | DMA_RxAlign 0x00c00000 /* 1:Reception Alignment */ |
| #define | DMA_RxAlign_1 0x00400000 |
| #define | DMA_RxAlign_2 0x00800000 |
| #define | DMA_RxAlign_3 0x00c00000 |
| #define | DMA_M66EnStat 0x00080000 /* 1:66MHz Enable State */ |
| #define | DMA_IntMask 0x00040000 /* 1:Interrupt mask */ |
| #define | DMA_SWIntReq 0x00020000 /* 1:Software Interrupt request */ |
| #define | DMA_TxWakeUp 0x00010000 /* 1:Transmit Wake Up */ |
| #define | DMA_RxBigE 0x00008000 /* 1:Receive Big Endian */ |
| #define | DMA_TxBigE 0x00004000 /* 1:Transmit Big Endian */ |
| #define | DMA_TestMode 0x00002000 /* 1:Test Mode */ |
| #define | DMA_PowrMgmnt 0x00001000 /* 1:Power Management */ |
| #define | DMA_DmBurst_Mask 0x000001fc /* DMA Burst size */ |
| #define | RxFrag_EnPack 0x00008000 /* 1:Enable Packing */ |
| #define | RxFrag_MinFragMask 0x00000ffc /* Minimum Fragment */ |
| #define | MAC_Link10 0x00008000 /* 1:Link Status 10Mbits */ |
| #define | MAC_EnMissRoll 0x00002000 /* 1:Enable Missed Roll */ |
| #define | MAC_MissRoll 0x00000400 /* 1:Missed Roll */ |
| #define | MAC_Loop10 0x00000080 /* 1:Loop 10 Mbps */ |
| #define | MAC_Conn_Auto 0x00000000 /*00:Connection mode (Automatic) */ |
| #define | MAC_Conn_10M 0x00000020 /*01: (10Mbps endec)*/ |
| #define | MAC_Conn_Mll 0x00000040 /*10: (Mll clock) */ |
| #define | MAC_MacLoop 0x00000010 /* 1:MAC Loopback */ |
| #define | MAC_FullDup 0x00000008 /* 1:Full Duplex 0:Half Duplex */ |
| #define | MAC_Reset 0x00000004 /* 1:Software Reset */ |
| #define | MAC_HaltImm 0x00000002 /* 1:Halt Immediate */ |
| #define | MAC_HaltReq 0x00000001 /* 1:Halt request */ |
| #define | PROM_Busy 0x00008000 /* 1:Busy (Start Operation) */ |
| #define | PROM_Read 0x00004000 /*10:Read operation */ |
| #define | PROM_Write 0x00002000 /*01:Write operation */ |
| #define | PROM_Erase 0x00006000 /*11:Erase operation */ |
| #define | PROM_Addr_Ena 0x00000030 /*11xxxx:PROM Write enable */ |
| #define | CAM_CompEn 0x00000010 /* 1:CAM Compare Enable */ |
| #define | CAM_NegCAM 0x00000008 /* 1:Reject packets CAM recognizes,*/ |
| #define | CAM_BroadAcc 0x00000004 /* 1:Broadcast assept */ |
| #define | CAM_GroupAcc 0x00000002 /* 1:Multicast assept */ |
| #define | CAM_StationAcc 0x00000001 /* 1:unicast accept */ |
| #define | CAM_ENTRY_MAX 21 /* CAM Data entry max count */ |
| #define | CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits) */ |
| #define | CAM_Ena_Bit(index) (1 << (index)) |
| #define | CAM_ENTRY_DESTINATION 0 |
| #define | CAM_ENTRY_SOURCE 1 |
| #define | CAM_ENTRY_MACCTL 20 |
| #define | Tx_En 0x00000001 /* 1:Transmit enable */ |
| #define | Tx_TxHalt 0x00000002 /* 1:Transmit Halt Request */ |
| #define | Tx_NoPad 0x00000004 /* 1:Suppress Padding */ |
| #define | Tx_NoCRC 0x00000008 /* 1:Suppress Padding */ |
| #define | Tx_FBack 0x00000010 /* 1:Fast Back-off */ |
| #define | Tx_EnUnder 0x00000100 /* 1:Enable Underrun */ |
| #define | Tx_EnExDefer 0x00000200 /* 1:Enable Excessive Deferral */ |
| #define | Tx_EnLCarr 0x00000400 /* 1:Enable Lost Carrier */ |
| #define | Tx_EnExColl 0x00000800 /* 1:Enable Excessive Collision */ |
| #define | Tx_EnLateColl 0x00001000 /* 1:Enable Late Collision */ |
| #define | Tx_EnTxPar 0x00002000 /* 1:Enable Transmit Parity */ |
| #define | Tx_EnComp 0x00004000 /* 1:Enable Completion */ |
| #define | Tx_TxColl_MASK 0x0000000F /* Tx Collision Count */ |
| #define | Tx_ExColl 0x00000010 /* Excessive Collision */ |
| #define | Tx_TXDefer 0x00000020 /* Transmit Defered */ |
| #define | Tx_Paused 0x00000040 /* Transmit Paused */ |
| #define | Tx_IntTx 0x00000080 /* Interrupt on Tx */ |
| #define | Tx_Under 0x00000100 /* Underrun */ |
| #define | Tx_Defer 0x00000200 /* Deferral */ |
| #define | Tx_NCarr 0x00000400 /* No Carrier */ |
| #define | Tx_10Stat 0x00000800 /* 10Mbps Status */ |
| #define | Tx_LateColl 0x00001000 /* Late Collision */ |
| #define | Tx_TxPar 0x00002000 /* Tx Parity Error */ |
| #define | Tx_Comp 0x00004000 /* Completion */ |
| #define | Tx_Halted 0x00008000 /* Tx Halted */ |
| #define | Tx_SQErr 0x00010000 /* Signal Quality Error(SQE) */ |
| #define | Rx_EnGood 0x00004000 /* 1:Enable Good */ |
| #define | Rx_EnRxPar 0x00002000 /* 1:Enable Receive Parity */ |
| #define | Rx_EnLongErr 0x00000800 /* 1:Enable Long Error */ |
| #define | Rx_EnOver 0x00000400 /* 1:Enable OverFlow */ |
| #define | Rx_EnCRCErr 0x00000200 /* 1:Enable CRC Error */ |
| #define | Rx_EnAlign 0x00000100 /* 1:Enable Alignment */ |
| #define | Rx_IgnoreCRC 0x00000040 /* 1:Ignore CRC Value */ |
| #define | Rx_StripCRC 0x00000010 /* 1:Strip CRC Value */ |
| #define | Rx_ShortEn 0x00000008 /* 1:Short Enable */ |
| #define | Rx_LongEn 0x00000004 /* 1:Long Enable */ |
| #define | Rx_RxHalt 0x00000002 /* 1:Receive Halt Request */ |
| #define | Rx_RxEn 0x00000001 /* 1:Receive Intrrupt Enable */ |
| #define | Rx_Halted 0x00008000 /* Rx Halted */ |
| #define | Rx_Good 0x00004000 /* Rx Good */ |
| #define | Rx_RxPar 0x00002000 /* Rx Parity Error */ |
| #define | Rx_TypePkt 0x00001000 /* Rx Type Packet */ |
| #define | Rx_LongErr 0x00000800 /* Rx Long Error */ |
| #define | Rx_Over 0x00000400 /* Rx Overflow */ |
| #define | Rx_CRCErr 0x00000200 /* Rx CRC Error */ |
| #define | Rx_Align 0x00000100 /* Rx Alignment Error */ |
| #define | Rx_10Stat 0x00000080 /* Rx 10Mbps Status */ |
| #define | Rx_IntRx 0x00000040 /* Rx Interrupt */ |
| #define | Rx_CtlRecd 0x00000020 /* Rx Control Receive */ |
| #define | Rx_InLenErr 0x00000010 /* Rx In Range Frame Length Error */ |
| #define | Rx_Stat_Mask 0x0000FFF0 /* Rx All Status Mask */ |
| #define | Int_NRAbtEn 0x00000800 /* 1:Non-recoverable Abort Enable */ |
| #define | Int_TxCtlCmpEn 0x00000400 /* 1:Transmit Ctl Complete Enable */ |
| #define | Int_DmParErrEn 0x00000200 /* 1:DMA Parity Error Enable */ |
| #define | Int_DParDEn 0x00000100 /* 1:Data Parity Error Enable */ |
| #define | Int_EarNotEn 0x00000080 /* 1:Early Notify Enable */ |
| #define | Int_DParErrEn 0x00000040 /* 1:Detected Parity Error Enable */ |
| #define | Int_SSysErrEn 0x00000020 /* 1:Signalled System Error Enable */ |
| #define | Int_RMasAbtEn 0x00000010 /* 1:Received Master Abort Enable */ |
| #define | Int_RTargAbtEn 0x00000008 /* 1:Received Target Abort Enable */ |
| #define | Int_STargAbtEn 0x00000004 /* 1:Signalled Target Abort Enable */ |
| #define | Int_BLExEn 0x00000002 /* 1:Buffer List Exhausted Enable */ |
| #define | Int_FDAExEn 0x00000001 /* 1:Free Descriptor Area */ |
| #define | Int_NRabt 0x00004000 /* 1:Non Recoverable error */ |
| #define | Int_DmParErrStat 0x00002000 /* 1:DMA Parity Error & Clear */ |
| #define | Int_BLEx 0x00001000 /* 1:Buffer List Empty & Clear */ |
| #define | Int_FDAEx 0x00000800 /* 1:FDA Empty & Clear */ |
| #define | Int_IntNRAbt 0x00000400 /* 1:Non Recoverable Abort */ |
| #define | Int_IntCmp 0x00000200 /* 1:MAC control packet complete */ |
| #define | Int_IntExBD 0x00000100 /* 1:Interrupt Extra BD & Clear */ |
| #define | Int_DmParErr 0x00000080 /* 1:DMA Parity Error & Clear */ |
| #define | Int_IntEarNot 0x00000040 /* 1:Receive Data write & Clear */ |
| #define | Int_SWInt 0x00000020 /* 1:Software request & Clear */ |
| #define | Int_IntBLEx 0x00000010 /* 1:Buffer List Empty & Clear */ |
| #define | Int_IntFDAEx 0x00000008 /* 1:FDA Empty & Clear */ |
| #define | Int_IntPCI 0x00000004 /* 1:PCI controller & Clear */ |
| #define | Int_IntMacRx 0x00000002 /* 1:Rx controller & Clear */ |
| #define | Int_IntMacTx 0x00000001 /* 1:Tx controller & Clear */ |
| #define | MD_CA_PreSup 0x00001000 /* 1:Preamble Suppress */ |
| #define | MD_CA_Busy 0x00000800 /* 1:Busy (Start Operation) */ |
| #define | MD_CA_Wr 0x00000400 /* 1:Write 0:Read */ |
| #define | FD_ALIGN 16 |
| #define | FD_FDLength_MASK 0x0000FFFF /* Length MASK */ |
| #define | FD_BDCnt_MASK 0x001F0000 /* BD count MASK in FD */ |
| #define | FD_FrmOpt_MASK 0x7C000000 /* Frame option MASK */ |
| #define | FD_FrmOpt_BigEndian 0x40000000 /* Tx/Rx */ |
| #define | FD_FrmOpt_IntTx 0x20000000 /* Tx only */ |
| #define | FD_FrmOpt_NoCRC 0x10000000 /* Tx only */ |
| #define | FD_FrmOpt_NoPadding 0x08000000 /* Tx only */ |
| #define | FD_FrmOpt_Packing 0x04000000 /* Rx only */ |
| #define | FD_CownsFD 0x80000000 /* FD Controller owner bit */ |
| #define | FD_Next_EOL 0x00000001 /* FD EOL indicator */ |
| #define | FD_BDCnt_SHIFT 16 |
| #define | BD_BuffLength_MASK 0x0000FFFF /* Receive Data Size */ |
| #define | BD_RxBDID_MASK 0x00FF0000 /* BD ID Number MASK */ |
| #define | BD_RxBDSeqN_MASK 0x7F000000 /* Rx BD Sequence Number */ |
| #define | BD_CownsBD 0x80000000 /* BD Controller owner bit */ |
| #define | BD_RxBDID_SHIFT 16 |
| #define | BD_RxBDSeqN_SHIFT 24 |
| #define | TX_CTL_CMD |
| #define | RX_CTL_CMD |
| #define | INT_EN_CMD |
| #define | DMA_CTL_CMD DMA_BURST_SIZE |
| #define | HAVE_DMA_RXALIGN(lp) likely((lp)->chiptype != TC35815CF) |
| #define | DMA_BURST_SIZE 32 |
| #define | TX_THRESHOLD 1024 |
| #define | TX_THRESHOLD_MAX 1536 |
| #define | TX_THRESHOLD_KEEP_LIMIT 10 |
| #define | FD_PAGE_NUM 4 |
| #define | RX_BUF_NUM 128 /* < 256 */ |
| #define | RX_FD_NUM 256 /* >= 32 */ |
| #define | TX_FD_NUM 128 |
| #define | RX_BUF_SIZE L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN + NET_IP_ALIGN) |
| #define | RX_FD_RESERVE (2 / 2) /* max 2 BD per RxFD */ |
| #define | NAPI_WEIGHT 16 |
| #define | tc_readl(addr) ioread32(addr) |
| #define | tc_writel(d, addr) iowrite32(d, addr) |
| #define | TC35815_TX_TIMEOUT msecs_to_jiffies(400) |
| #define | FATAL_ERROR_INT (Int_IntPCI | Int_DmParErr | Int_IntNRAbt) |
| #define | TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_NCarr|Tx_LateColl|Tx_TxPar|Tx_SQErr) |
Enumerations | |
| enum | tc35815_chiptype { TC35815CF = 0, TC35815_NWU, TC35815_TX4939 } |
Functions | |
| MODULE_DEVICE_TABLE (pci, tc35815_pci_tbl) | |
| module_param_named (speed, options.speed, int, 0) | |
| MODULE_PARM_DESC (speed,"0:auto, 10:10Mbps, 100:100Mbps") | |
| module_param_named (duplex, options.duplex, int, 0) | |
| MODULE_PARM_DESC (duplex,"0:auto, 1:half, 2:full") | |
| module_init (tc35815_init_module) | |
| module_exit (tc35815_cleanup_module) | |
| MODULE_DESCRIPTION ("TOSHIBA TC35815 PCI 10M/100M Ethernet driver") | |
| MODULE_LICENSE ("GPL") | |
| #define BD_BuffLength_MASK 0x0000FFFF /* Receive Data Size */ |
| #define BD_CownsBD 0x80000000 /* BD Controller owner bit */ |
| #define BD_RxBDSeqN_MASK 0x7F000000 /* Rx BD Sequence Number */ |
| #define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits) */ |
| #define CAM_NegCAM 0x00000008 /* 1:Reject packets CAM recognizes,*/ |
| #define DMA_CTL_CMD DMA_BURST_SIZE |
| #define DMA_M66EnStat 0x00080000 /* 1:66MHz Enable State */ |
| #define DMA_RxAlign 0x00c00000 /* 1:Reception Alignment */ |
| #define DMA_SWIntReq 0x00020000 /* 1:Software Interrupt request */ |
| #define FATAL_ERROR_INT (Int_IntPCI | Int_DmParErr | Int_IntNRAbt) |
| #define FD_BDCnt_MASK 0x001F0000 /* BD count MASK in FD */ |
| #define FD_CownsFD 0x80000000 /* FD Controller owner bit */ |
| #define Int_BLEx 0x00001000 /* 1:Buffer List Empty & Clear */ |
| #define Int_BLExEn 0x00000002 /* 1:Buffer List Exhausted Enable */ |
| #define Int_DmParErr 0x00000080 /* 1:DMA Parity Error & Clear */ |
| #define Int_DmParErrEn 0x00000200 /* 1:DMA Parity Error Enable */ |
| #define Int_DmParErrStat 0x00002000 /* 1:DMA Parity Error & Clear */ |
| #define Int_DParDEn 0x00000100 /* 1:Data Parity Error Enable */ |
| #define Int_DParErrEn 0x00000040 /* 1:Detected Parity Error Enable */ |
| #define Int_EarNotEn 0x00000080 /* 1:Early Notify Enable */ |
| #define INT_EN_CMD |
| #define Int_FDAExEn 0x00000001 /* 1:Free Descriptor Area */ |
| #define Int_IntBLEx 0x00000010 /* 1:Buffer List Empty & Clear */ |
| #define Int_IntCmp 0x00000200 /* 1:MAC control packet complete */ |
| #define Int_IntEarNot 0x00000040 /* 1:Receive Data write & Clear */ |
| #define Int_IntExBD 0x00000100 /* 1:Interrupt Extra BD & Clear */ |
| #define Int_IntMacRx 0x00000002 /* 1:Rx controller & Clear */ |
| #define Int_IntMacTx 0x00000001 /* 1:Tx controller & Clear */ |
| #define Int_IntNRAbt 0x00000400 /* 1:Non Recoverable Abort */ |
| #define Int_IntPCI 0x00000004 /* 1:PCI controller & Clear */ |
| #define Int_NRabt 0x00004000 /* 1:Non Recoverable error */ |
| #define Int_NRAbtEn 0x00000800 /* 1:Non-recoverable Abort Enable */ |
| #define Int_RMasAbtEn 0x00000010 /* 1:Received Master Abort Enable */ |
| #define Int_RTargAbtEn 0x00000008 /* 1:Received Target Abort Enable */ |
| #define Int_SSysErrEn 0x00000020 /* 1:Signalled System Error Enable */ |
| #define Int_STargAbtEn 0x00000004 /* 1:Signalled Target Abort Enable */ |
| #define Int_SWInt 0x00000020 /* 1:Software request & Clear */ |
| #define Int_TxCtlCmpEn 0x00000400 /* 1:Transmit Ctl Complete Enable */ |
| #define MAC_Conn_Auto 0x00000000 /*00:Connection mode (Automatic) */ |
| #define MAC_EnMissRoll 0x00002000 /* 1:Enable Missed Roll */ |
| #define MAC_FullDup 0x00000008 /* 1:Full Duplex 0:Half Duplex */ |
| #define MD_CA_Busy 0x00000800 /* 1:Busy (Start Operation) */ |
| #define PROM_Addr_Ena 0x00000030 /*11xxxx:PROM Write enable */ |
| #define PROM_Busy 0x00008000 /* 1:Busy (Start Operation) */ |
| #define RX_BUF_SIZE L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN + NET_IP_ALIGN) |
| #define RX_CTL_CMD |
| #define Rx_EnRxPar 0x00002000 /* 1:Enable Receive Parity */ |
| #define Rx_InLenErr 0x00000010 /* Rx In Range Frame Length Error */ |
| #define Rx_RxEn 0x00000001 /* 1:Receive Intrrupt Enable */ |
| #define RxFrag_MinFragMask 0x00000ffc /* Minimum Fragment */ |
| #define TC35815_TX_TIMEOUT msecs_to_jiffies(400) |
| #define TX_CTL_CMD |
| #define Tx_EnExColl 0x00000800 /* 1:Enable Excessive Collision */ |
| #define Tx_EnExDefer 0x00000200 /* 1:Enable Excessive Deferral */ |
| #define Tx_EnLateColl 0x00001000 /* 1:Enable Late Collision */ |
| #define Tx_EnTxPar 0x00002000 /* 1:Enable Transmit Parity */ |
| #define Tx_SQErr 0x00010000 /* Signal Quality Error(SQE) */ |
| #define Tx_TxColl_MASK 0x0000000F /* Tx Collision Count */ |
| #define Tx_TxHalt 0x00000002 /* 1:Transmit Halt Request */ |
| enum tc35815_chiptype |
| MODULE_DESCRIPTION | ( | "TOSHIBA TC35815 PCI 10M/100M Ethernet driver" | ) |
| MODULE_DEVICE_TABLE | ( | pci | , |
| tc35815_pci_tbl | |||
| ) |
| module_exit | ( | tc35815_cleanup_module | ) |
| module_init | ( | tc35815_init_module | ) |
| MODULE_LICENSE | ( | "GPL" | ) |
| MODULE_PARM_DESC | ( | speed | , |
| "0:auto | , | ||
| 10:10Mbps | , | ||
| 100:100Mbps" | |||
| ) |
| const char str[ETH_GSTRING_LEN] |
1.8.2