#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/list.h>
#include <linux/spinlock.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/cpufreq.h>
#include <linux/syscore_ops.h>
#include <asm/clkdev.h>
#include <mach/iomap.h>
#include "clock.h"
#include "fuse.h"
#include "tegra_cpu_car.h"

Data Structures
struct	utmi_clk_param

Macros
#define	USE_PLL_LOCK_BITS 0

#define	RST_DEVICES_L 0x004

#define	RST_DEVICES_H 0x008

#define	RST_DEVICES_U 0x00C

#define	RST_DEVICES_V 0x358

#define	RST_DEVICES_W 0x35C

#define	RST_DEVICES_SET_L 0x300

#define	RST_DEVICES_CLR_L 0x304

#define	RST_DEVICES_SET_V 0x430

#define	RST_DEVICES_CLR_V 0x434

#define	RST_DEVICES_NUM 5

#define	CLK_OUT_ENB_L 0x010

#define	CLK_OUT_ENB_H 0x014

#define	CLK_OUT_ENB_U 0x018

#define	CLK_OUT_ENB_V 0x360

#define	CLK_OUT_ENB_W 0x364

#define	CLK_OUT_ENB_SET_L 0x320

#define	CLK_OUT_ENB_CLR_L 0x324

#define	CLK_OUT_ENB_SET_V 0x440

#define	CLK_OUT_ENB_CLR_V 0x444

#define	CLK_OUT_ENB_NUM 5

#define	RST_DEVICES_V_SWR_CPULP_RST_DIS (0x1 << 1)

#define	CLK_OUT_ENB_V_CLK_ENB_CPULP_EN (0x1 << 1)

#define	PERIPH_CLK_TO_BIT(c) (1 << (c->u.periph.clk_num % 32))

#define	PERIPH_CLK_TO_RST_REG(c) periph_clk_to_reg((c), RST_DEVICES_L, RST_DEVICES_V, 4)

#define	PERIPH_CLK_TO_RST_SET_REG(c) periph_clk_to_reg((c), RST_DEVICES_SET_L, RST_DEVICES_SET_V, 8)

#define	PERIPH_CLK_TO_RST_CLR_REG(c) periph_clk_to_reg((c), RST_DEVICES_CLR_L, RST_DEVICES_CLR_V, 8)

#define	PERIPH_CLK_TO_ENB_REG(c) periph_clk_to_reg((c), CLK_OUT_ENB_L, CLK_OUT_ENB_V, 4)

#define	PERIPH_CLK_TO_ENB_SET_REG(c) periph_clk_to_reg((c), CLK_OUT_ENB_SET_L, CLK_OUT_ENB_SET_V, 8)

#define	PERIPH_CLK_TO_ENB_CLR_REG(c) periph_clk_to_reg((c), CLK_OUT_ENB_CLR_L, CLK_OUT_ENB_CLR_V, 8)

#define	CLK_MASK_ARM 0x44

#define	MISC_CLK_ENB 0x48

#define	OSC_CTRL 0x50

#define	OSC_CTRL_OSC_FREQ_MASK (0xF<<28)

#define	OSC_CTRL_OSC_FREQ_13MHZ (0x0<<28)

#define	OSC_CTRL_OSC_FREQ_19_2MHZ (0x4<<28)

#define	OSC_CTRL_OSC_FREQ_12MHZ (0x8<<28)

#define	OSC_CTRL_OSC_FREQ_26MHZ (0xC<<28)

#define	OSC_CTRL_OSC_FREQ_16_8MHZ (0x1<<28)

#define	OSC_CTRL_OSC_FREQ_38_4MHZ (0x5<<28)

#define	OSC_CTRL_OSC_FREQ_48MHZ (0x9<<28)

#define	OSC_CTRL_MASK (0x3f2 \| OSC_CTRL_OSC_FREQ_MASK)

#define	OSC_CTRL_PLL_REF_DIV_MASK (3<<26)

#define	OSC_CTRL_PLL_REF_DIV_1 (0<<26)

#define	OSC_CTRL_PLL_REF_DIV_2 (1<<26)

#define	OSC_CTRL_PLL_REF_DIV_4 (2<<26)

#define	OSC_FREQ_DET 0x58

#define	OSC_FREQ_DET_TRIG (1<<31)

#define	OSC_FREQ_DET_STATUS 0x5C

#define	OSC_FREQ_DET_BUSY (1<<31)

#define	OSC_FREQ_DET_CNT_MASK 0xFFFF

#define	PERIPH_CLK_SOURCE_I2S1 0x100

#define	PERIPH_CLK_SOURCE_EMC 0x19c

#define	PERIPH_CLK_SOURCE_OSC 0x1fc

#define	PERIPH_CLK_SOURCE_NUM1 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)

#define	PERIPH_CLK_SOURCE_G3D2 0x3b0

#define	PERIPH_CLK_SOURCE_SE 0x42c

#define	PERIPH_CLK_SOURCE_NUM2 ((PERIPH_CLK_SOURCE_SE - PERIPH_CLK_SOURCE_G3D2) / 4 + 1)

#define	AUDIO_DLY_CLK 0x49c

#define	AUDIO_SYNC_CLK_SPDIF 0x4b4

#define	PERIPH_CLK_SOURCE_NUM3 ((AUDIO_SYNC_CLK_SPDIF - AUDIO_DLY_CLK) / 4 + 1)

#define	PERIPH_CLK_SOURCE_NUM

#define	CPU_SOFTRST_CTRL 0x380

#define	PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF

#define	PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF

#define	PERIPH_CLK_SOURCE_DIV_SHIFT 0

#define	PERIPH_CLK_SOURCE_DIVIDLE_SHIFT 8

#define	PERIPH_CLK_SOURCE_DIVIDLE_VAL 50

#define	PERIPH_CLK_UART_DIV_ENB (1<<24)

#define	PERIPH_CLK_VI_SEL_EX_SHIFT 24

#define	PERIPH_CLK_VI_SEL_EX_MASK (0x3<<PERIPH_CLK_VI_SEL_EX_SHIFT)

#define	PERIPH_CLK_NAND_DIV_EX_ENB (1<<8)

#define	PERIPH_CLK_DTV_POLARITY_INV (1<<25)

#define	AUDIO_SYNC_SOURCE_MASK 0x0F

#define	AUDIO_SYNC_DISABLE_BIT 0x10

#define	AUDIO_SYNC_TAP_NIBBLE_SHIFT(c) ((c->reg_shift - 24) * 4)

#define	PLL_BASE 0x0

#define	PLL_BASE_BYPASS (1<<31)

#define	PLL_BASE_ENABLE (1<<30)

#define	PLL_BASE_REF_ENABLE (1<<29)

#define	PLL_BASE_OVERRIDE (1<<28)

#define	PLL_BASE_LOCK (1<<27)

#define	PLL_BASE_DIVP_MASK (0x7<<20)

#define	PLL_BASE_DIVP_SHIFT 20

#define	PLL_BASE_DIVN_MASK (0x3FF<<8)

#define	PLL_BASE_DIVN_SHIFT 8

#define	PLL_BASE_DIVM_MASK (0x1F)

#define	PLL_BASE_DIVM_SHIFT 0

#define	PLL_OUT_RATIO_MASK (0xFF<<8)

#define	PLL_OUT_RATIO_SHIFT 8

#define	PLL_OUT_OVERRIDE (1<<2)

#define	PLL_OUT_CLKEN (1<<1)

#define	PLL_OUT_RESET_DISABLE (1<<0)

#define	PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)

#define	PLL_MISC_LOCK_ENABLE(c) (((c)->flags & (PLLU \| PLLD)) ? (1<<22) : (1<<18))

#define	PLL_MISC_DCCON_SHIFT 20

#define	PLL_MISC_CPCON_SHIFT 8

#define	PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)

#define	PLL_MISC_LFCON_SHIFT 4

#define	PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)

#define	PLL_MISC_VCOCON_SHIFT 0

#define	PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)

#define	PLLD_MISC_CLKENABLE (1<<30)

#define	PLLU_BASE_POST_DIV (1<<20)

#define	PLLD_BASE_DSIB_MUX_SHIFT 25

#define	PLLD_BASE_DSIB_MUX_MASK (1<<PLLD_BASE_DSIB_MUX_SHIFT)

#define	PLLD_BASE_CSI_CLKENABLE (1<<26)

#define	PLLD_MISC_DSI_CLKENABLE (1<<30)

#define	PLLD_MISC_DIV_RST (1<<23)

#define	PLLD_MISC_DCCON_SHIFT 12

#define	PLLDU_LFCON_SET_DIVN 600

#define	OUT_OF_TABLE_CPCON 0x8

#define	SUPER_CLK_MUX 0x00

#define	SUPER_STATE_SHIFT 28

#define	SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)

#define	SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)

#define	SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)

#define	SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)

#define	SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)

#define	SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)

#define	SUPER_LP_DIV2_BYPASS (0x1 << 16)

#define	SUPER_SOURCE_MASK 0xF

#define	SUPER_FIQ_SOURCE_SHIFT 12

#define	SUPER_IRQ_SOURCE_SHIFT 8

#define	SUPER_RUN_SOURCE_SHIFT 4

#define	SUPER_IDLE_SOURCE_SHIFT 0

#define	SUPER_CLK_DIVIDER 0x04

#define	SUPER_CLOCK_DIV_U71_SHIFT 16

#define	SUPER_CLOCK_DIV_U71_MASK (0xff << SUPER_CLOCK_DIV_U71_SHIFT)

#define	SUPER_CLOCK_DIV_U71_MIN 0x2

#define	BUS_CLK_DISABLE (1<<3)

#define	BUS_CLK_DIV_MASK 0x3

#define	PMC_CTRL 0x0

#define	PMC_CTRL_BLINK_ENB (1 << 7)

#define	PMC_DPD_PADS_ORIDE 0x1c

#define	PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)

#define	PMC_BLINK_TIMER_DATA_ON_SHIFT 0

#define	PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff

#define	PMC_BLINK_TIMER_ENB (1 << 15)

#define	PMC_BLINK_TIMER_DATA_OFF_SHIFT 16

#define	PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff

#define	PMC_PLLP_WB0_OVERRIDE 0xf8

#define	PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE (1 << 12)

#define	UTMIP_PLL_CFG2 0x488

#define	UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xfff) << 6)

#define	UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)

#define	UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)

#define	UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)

#define	UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)

#define	UTMIP_PLL_CFG1 0x484

#define	UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)

#define	UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)

#define	UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN (1 << 14)

#define	UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN (1 << 12)

#define	UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN (1 << 16)

#define	PLLE_BASE_CML_ENABLE (1<<31)

#define	PLLE_BASE_ENABLE (1<<30)

#define	PLLE_BASE_DIVCML_SHIFT 24

#define	PLLE_BASE_DIVCML_MASK (0xf<<PLLE_BASE_DIVCML_SHIFT)

#define	PLLE_BASE_DIVP_SHIFT 16

#define	PLLE_BASE_DIVP_MASK (0x3f<<PLLE_BASE_DIVP_SHIFT)

#define	PLLE_BASE_DIVN_SHIFT 8

#define	PLLE_BASE_DIVN_MASK (0xFF<<PLLE_BASE_DIVN_SHIFT)

#define	PLLE_BASE_DIVM_SHIFT 0

#define	PLLE_BASE_DIVM_MASK (0xFF<<PLLE_BASE_DIVM_SHIFT)

#define	PLLE_BASE_DIV_MASK

#define	PLLE_BASE_DIV(m, n, p, cml)

#define	PLLE_MISC_SETUP_BASE_SHIFT 16

#define	PLLE_MISC_SETUP_BASE_MASK (0xFFFF<<PLLE_MISC_SETUP_BASE_SHIFT)

#define	PLLE_MISC_READY (1<<15)

#define	PLLE_MISC_LOCK (1<<11)

#define	PLLE_MISC_LOCK_ENABLE (1<<9)

#define	PLLE_MISC_SETUP_EX_SHIFT 2

#define	PLLE_MISC_SETUP_EX_MASK (0x3<<PLLE_MISC_SETUP_EX_SHIFT)

#define	PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK \| PLLE_MISC_SETUP_EX_MASK)

#define	PLLE_MISC_SETUP_VALUE ((0x7<<PLLE_MISC_SETUP_BASE_SHIFT) \| (0x0<<PLLE_MISC_SETUP_EX_SHIFT))

#define	PLLE_SS_CTRL 0x68

#define	PLLE_SS_INCINTRV_SHIFT 24

#define	PLLE_SS_INCINTRV_MASK (0x3f<<PLLE_SS_INCINTRV_SHIFT)

#define	PLLE_SS_INC_SHIFT 16

#define	PLLE_SS_INC_MASK (0xff<<PLLE_SS_INC_SHIFT)

#define	PLLE_SS_MAX_SHIFT 0

#define	PLLE_SS_MAX_MASK (0x1ff<<PLLE_SS_MAX_SHIFT)

#define	PLLE_SS_COEFFICIENTS_MASK (PLLE_SS_INCINTRV_MASK \| PLLE_SS_INC_MASK \| PLLE_SS_MAX_MASK)

#define	PLLE_SS_COEFFICIENTS_12MHZ

#define	PLLE_SS_DISABLE ((1<<12) \| (1<<11) \| (1<<10))

#define	PLLE_AUX 0x48c

#define	PLLE_AUX_PLLP_SEL (1<<2)

#define	PLLE_AUX_CML_SATA_ENABLE (1<<1)

#define	PLLE_AUX_CML_PCIE_ENABLE (1<<0)

#define	PMC_SATA_PWRGT 0x1ac

#define	PMC_SATA_PWRGT_PLLE_IDDQ_VALUE (1<<5)

#define	PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1<<4)

#define	ROUND_DIVIDER_UP 0

#define	ROUND_DIVIDER_DOWN 1

#define	PLL_POST_LOCK_DELAY 100

#define	TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c

#define	TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340

#define	TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344

#define	TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c

#define	TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470

#define	CPU_CLOCK(cpu) (0x1 << (8 + cpu))

#define	CPU_RESET(cpu) (0x1111ul << (cpu))

#define	MISC_GP_HIDREV 0x804

#define	clk_writel(value, reg) __raw_writel(value, reg_clk_base + (reg))

#define	clk_readl(reg) __raw_readl(reg_clk_base + (reg))

#define	pmc_writel(value, reg) __raw_writel(value, reg_pmc_base + (reg))

#define	pmc_readl(reg) __raw_readl(reg_pmc_base + (reg))

#define	chipid_readl() __raw_readl(misc_gp_hidrev_base + MISC_GP_HIDREV)

#define	clk_writel_delay(value, reg)

Functions
int	tegra30_plld_clk_cfg_ex (struct clk_hw *hw, enum tegra_clk_ex_param p, u32 setting)

void	tegra30_periph_clk_reset (struct clk_hw *hw, bool assert)

int	tegra30_vi_clk_cfg_ex (struct clk_hw *hw, enum tegra_clk_ex_param p, u32 setting)

int	tegra30_nand_clk_cfg_ex (struct clk_hw *hw, enum tegra_clk_ex_param p, u32 setting)

int	tegra30_dtv_clk_cfg_ex (struct clk_hw *hw, enum tegra_clk_ex_param p, u32 setting)

void __init	tegra30_cpu_car_ops_init (void)

Macro Definition Documentation

#define AUDIO_DLY_CLK 0x49c

Definition at line 119 of file tegra30_clocks.c.

#define AUDIO_SYNC_CLK_SPDIF 0x4b4

Definition at line 120 of file tegra30_clocks.c.

#define AUDIO_SYNC_DISABLE_BIT 0x10

Definition at line 142 of file tegra30_clocks.c.

#define AUDIO_SYNC_SOURCE_MASK 0x0F

Definition at line 141 of file tegra30_clocks.c.

#define AUDIO_SYNC_TAP_NIBBLE_SHIFT ( c ) ((c->reg_shift - 24) * 4)

Definition at line 143 of file tegra30_clocks.c.

#define BUS_CLK_DISABLE (1<<3)

Definition at line 213 of file tegra30_clocks.c.

#define BUS_CLK_DIV_MASK 0x3

Definition at line 214 of file tegra30_clocks.c.

#define chipid_readl ( ) __raw_readl(misc_gp_hidrev_base + MISC_GP_HIDREV)

Definition at line 386 of file tegra30_clocks.c.

#define CLK_MASK_ARM 0x44

Definition at line 82 of file tegra30_clocks.c.

#define CLK_OUT_ENB_CLR_L 0x324

Definition at line 59 of file tegra30_clocks.c.

#define CLK_OUT_ENB_CLR_V 0x444

Definition at line 61 of file tegra30_clocks.c.

#define CLK_OUT_ENB_H 0x014

Definition at line 54 of file tegra30_clocks.c.

#define CLK_OUT_ENB_L 0x010

Definition at line 53 of file tegra30_clocks.c.

#define CLK_OUT_ENB_NUM 5

Definition at line 62 of file tegra30_clocks.c.

#define CLK_OUT_ENB_SET_L 0x320

Definition at line 58 of file tegra30_clocks.c.

#define CLK_OUT_ENB_SET_V 0x440

Definition at line 60 of file tegra30_clocks.c.

#define CLK_OUT_ENB_U 0x018

Definition at line 55 of file tegra30_clocks.c.

#define CLK_OUT_ENB_V 0x360

Definition at line 56 of file tegra30_clocks.c.

#define CLK_OUT_ENB_V_CLK_ENB_CPULP_EN (0x1 << 1)

Definition at line 65 of file tegra30_clocks.c.

#define CLK_OUT_ENB_W 0x364

Definition at line 57 of file tegra30_clocks.c.

#define clk_readl ( reg ) __raw_readl(reg_clk_base + (reg))

Definition at line 380 of file tegra30_clocks.c.

#define clk_writel	(	value,
		reg
	)	__raw_writel(value, reg_clk_base + (reg))

Definition at line 378 of file tegra30_clocks.c.

#define clk_writel_delay	(	value,
		reg
	)

Value:

do {                                \
        __raw_writel((value), reg_clk_base + (reg));    \
        udelay(2);                      \
    } while (0)

Definition at line 389 of file tegra30_clocks.c.

#define CPU_CLOCK ( cpu ) (0x1 << (8 + cpu))

Definition at line 310 of file tegra30_clocks.c.

#define CPU_RESET ( cpu ) (0x1111ul << (cpu))

Definition at line 311 of file tegra30_clocks.c.

#define CPU_SOFTRST_CTRL 0x380

Definition at line 128 of file tegra30_clocks.c.

#define MISC_CLK_ENB 0x48

Definition at line 83 of file tegra30_clocks.c.

#define MISC_GP_HIDREV 0x804

Definition at line 370 of file tegra30_clocks.c.

#define OSC_CTRL 0x50

Definition at line 85 of file tegra30_clocks.c.

#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)

Definition at line 94 of file tegra30_clocks.c.

#define OSC_CTRL_OSC_FREQ_12MHZ (0x8<<28)

Definition at line 89 of file tegra30_clocks.c.

#define OSC_CTRL_OSC_FREQ_13MHZ (0x0<<28)

Definition at line 87 of file tegra30_clocks.c.

#define OSC_CTRL_OSC_FREQ_16_8MHZ (0x1<<28)

Definition at line 91 of file tegra30_clocks.c.

#define OSC_CTRL_OSC_FREQ_19_2MHZ (0x4<<28)

Definition at line 88 of file tegra30_clocks.c.

#define OSC_CTRL_OSC_FREQ_26MHZ (0xC<<28)

Definition at line 90 of file tegra30_clocks.c.

#define OSC_CTRL_OSC_FREQ_38_4MHZ (0x5<<28)

Definition at line 92 of file tegra30_clocks.c.

#define OSC_CTRL_OSC_FREQ_48MHZ (0x9<<28)

Definition at line 93 of file tegra30_clocks.c.

#define OSC_CTRL_OSC_FREQ_MASK (0xF<<28)

Definition at line 86 of file tegra30_clocks.c.

#define OSC_CTRL_PLL_REF_DIV_1 (0<<26)

Definition at line 97 of file tegra30_clocks.c.

#define OSC_CTRL_PLL_REF_DIV_2 (1<<26)

Definition at line 98 of file tegra30_clocks.c.

#define OSC_CTRL_PLL_REF_DIV_4 (2<<26)

Definition at line 99 of file tegra30_clocks.c.

#define OSC_CTRL_PLL_REF_DIV_MASK (3<<26)

Definition at line 96 of file tegra30_clocks.c.

#define OSC_FREQ_DET 0x58

Definition at line 101 of file tegra30_clocks.c.

#define OSC_FREQ_DET_BUSY (1<<31)

Definition at line 105 of file tegra30_clocks.c.

#define OSC_FREQ_DET_CNT_MASK 0xFFFF

Definition at line 106 of file tegra30_clocks.c.

#define OSC_FREQ_DET_STATUS 0x5C

Definition at line 104 of file tegra30_clocks.c.

#define OSC_FREQ_DET_TRIG (1<<31)

Definition at line 102 of file tegra30_clocks.c.

#define OUT_OF_TABLE_CPCON 0x8

Definition at line 190 of file tegra30_clocks.c.

#define PERIPH_CLK_DTV_POLARITY_INV (1<<25)

Definition at line 139 of file tegra30_clocks.c.

#define PERIPH_CLK_NAND_DIV_EX_ENB (1<<8)

Definition at line 138 of file tegra30_clocks.c.

#define PERIPH_CLK_SOURCE_DIV_SHIFT 0

Definition at line 132 of file tegra30_clocks.c.

#define PERIPH_CLK_SOURCE_DIVIDLE_SHIFT 8

Definition at line 133 of file tegra30_clocks.c.

#define PERIPH_CLK_SOURCE_DIVIDLE_VAL 50

Definition at line 134 of file tegra30_clocks.c.

#define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF

Definition at line 131 of file tegra30_clocks.c.

#define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF

Definition at line 130 of file tegra30_clocks.c.

#define PERIPH_CLK_SOURCE_EMC 0x19c

Definition at line 109 of file tegra30_clocks.c.

#define PERIPH_CLK_SOURCE_G3D2 0x3b0

Definition at line 114 of file tegra30_clocks.c.

#define PERIPH_CLK_SOURCE_I2S1 0x100

Definition at line 108 of file tegra30_clocks.c.

#define PERIPH_CLK_SOURCE_NUM

Value:

(PERIPH_CLK_SOURCE_NUM1 + \
                     PERIPH_CLK_SOURCE_NUM2 + \
                     PERIPH_CLK_SOURCE_NUM3)

Definition at line 124 of file tegra30_clocks.c.

#define PERIPH_CLK_SOURCE_NUM1 ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)

Definition at line 111 of file tegra30_clocks.c.

#define PERIPH_CLK_SOURCE_NUM2 ((PERIPH_CLK_SOURCE_SE - PERIPH_CLK_SOURCE_G3D2) / 4 + 1)

Definition at line 116 of file tegra30_clocks.c.

#define PERIPH_CLK_SOURCE_NUM3 ((AUDIO_SYNC_CLK_SPDIF - AUDIO_DLY_CLK) / 4 + 1)

Definition at line 121 of file tegra30_clocks.c.

#define PERIPH_CLK_SOURCE_OSC 0x1fc

Definition at line 110 of file tegra30_clocks.c.

#define PERIPH_CLK_SOURCE_SE 0x42c

Definition at line 115 of file tegra30_clocks.c.

#define PERIPH_CLK_TO_BIT ( c ) (1 << (c->u.periph.clk_num % 32))

Definition at line 67 of file tegra30_clocks.c.

#define PERIPH_CLK_TO_ENB_CLR_REG ( c ) periph_clk_to_reg((c), CLK_OUT_ENB_CLR_L, CLK_OUT_ENB_CLR_V, 8)

Definition at line 79 of file tegra30_clocks.c.

#define PERIPH_CLK_TO_ENB_REG ( c ) periph_clk_to_reg((c), CLK_OUT_ENB_L, CLK_OUT_ENB_V, 4)

Definition at line 75 of file tegra30_clocks.c.

#define PERIPH_CLK_TO_ENB_SET_REG ( c ) periph_clk_to_reg((c), CLK_OUT_ENB_SET_L, CLK_OUT_ENB_SET_V, 8)

Definition at line 77 of file tegra30_clocks.c.

#define PERIPH_CLK_TO_RST_CLR_REG ( c ) periph_clk_to_reg((c), RST_DEVICES_CLR_L, RST_DEVICES_CLR_V, 8)

Definition at line 72 of file tegra30_clocks.c.

#define PERIPH_CLK_TO_RST_REG ( c ) periph_clk_to_reg((c), RST_DEVICES_L, RST_DEVICES_V, 4)

Definition at line 68 of file tegra30_clocks.c.

#define PERIPH_CLK_TO_RST_SET_REG ( c ) periph_clk_to_reg((c), RST_DEVICES_SET_L, RST_DEVICES_SET_V, 8)

Definition at line 70 of file tegra30_clocks.c.

#define PERIPH_CLK_UART_DIV_ENB (1<<24)

Definition at line 135 of file tegra30_clocks.c.

#define PERIPH_CLK_VI_SEL_EX_MASK (0x3<<PERIPH_CLK_VI_SEL_EX_SHIFT)

Definition at line 137 of file tegra30_clocks.c.

#define PERIPH_CLK_VI_SEL_EX_SHIFT 24

Definition at line 136 of file tegra30_clocks.c.

#define PLL_BASE 0x0

Definition at line 145 of file tegra30_clocks.c.

#define PLL_BASE_BYPASS (1<<31)

Definition at line 146 of file tegra30_clocks.c.

#define PLL_BASE_DIVM_MASK (0x1F)

Definition at line 155 of file tegra30_clocks.c.

#define PLL_BASE_DIVM_SHIFT 0

Definition at line 156 of file tegra30_clocks.c.

#define PLL_BASE_DIVN_MASK (0x3FF<<8)

Definition at line 153 of file tegra30_clocks.c.

#define PLL_BASE_DIVN_SHIFT 8

Definition at line 154 of file tegra30_clocks.c.

#define PLL_BASE_DIVP_MASK (0x7<<20)

Definition at line 151 of file tegra30_clocks.c.

#define PLL_BASE_DIVP_SHIFT 20

Definition at line 152 of file tegra30_clocks.c.

#define PLL_BASE_ENABLE (1<<30)

Definition at line 147 of file tegra30_clocks.c.

#define PLL_BASE_LOCK (1<<27)

Definition at line 150 of file tegra30_clocks.c.

#define PLL_BASE_OVERRIDE (1<<28)

Definition at line 149 of file tegra30_clocks.c.

#define PLL_BASE_REF_ENABLE (1<<29)

Definition at line 148 of file tegra30_clocks.c.

#define PLL_MISC ( c ) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)

Definition at line 164 of file tegra30_clocks.c.

#define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)

Definition at line 171 of file tegra30_clocks.c.

#define PLL_MISC_CPCON_SHIFT 8

Definition at line 170 of file tegra30_clocks.c.

#define PLL_MISC_DCCON_SHIFT 20

Definition at line 169 of file tegra30_clocks.c.

#define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)

Definition at line 173 of file tegra30_clocks.c.

#define PLL_MISC_LFCON_SHIFT 4

Definition at line 172 of file tegra30_clocks.c.

#define PLL_MISC_LOCK_ENABLE ( c ) (((c)->flags & (PLLU | PLLD)) ? (1<<22) : (1<<18))

Definition at line 166 of file tegra30_clocks.c.

#define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)

Definition at line 175 of file tegra30_clocks.c.

#define PLL_MISC_VCOCON_SHIFT 0

Definition at line 174 of file tegra30_clocks.c.

#define PLL_OUT_CLKEN (1<<1)

Definition at line 161 of file tegra30_clocks.c.

#define PLL_OUT_OVERRIDE (1<<2)

Definition at line 160 of file tegra30_clocks.c.

#define PLL_OUT_RATIO_MASK (0xFF<<8)

Definition at line 158 of file tegra30_clocks.c.

#define PLL_OUT_RATIO_SHIFT 8

Definition at line 159 of file tegra30_clocks.c.

#define PLL_OUT_RESET_DISABLE (1<<0)

Definition at line 162 of file tegra30_clocks.c.

#define PLL_POST_LOCK_DELAY 100

Definition at line 301 of file tegra30_clocks.c.

#define PLLD_BASE_CSI_CLKENABLE (1<<26)

Definition at line 182 of file tegra30_clocks.c.

#define PLLD_BASE_DSIB_MUX_MASK (1<<PLLD_BASE_DSIB_MUX_SHIFT)

Definition at line 181 of file tegra30_clocks.c.

#define PLLD_BASE_DSIB_MUX_SHIFT 25

Definition at line 180 of file tegra30_clocks.c.

#define PLLD_MISC_CLKENABLE (1<<30)

Definition at line 176 of file tegra30_clocks.c.

#define PLLD_MISC_DCCON_SHIFT 12

Definition at line 185 of file tegra30_clocks.c.

#define PLLD_MISC_DIV_RST (1<<23)

Definition at line 184 of file tegra30_clocks.c.

#define PLLD_MISC_DSI_CLKENABLE (1<<30)

Definition at line 183 of file tegra30_clocks.c.

#define PLLDU_LFCON_SET_DIVN 600

Definition at line 187 of file tegra30_clocks.c.

#define PLLE_AUX 0x48c

Definition at line 288 of file tegra30_clocks.c.

#define PLLE_AUX_CML_PCIE_ENABLE (1<<0)

Definition at line 291 of file tegra30_clocks.c.

#define PLLE_AUX_CML_SATA_ENABLE (1<<1)

Definition at line 290 of file tegra30_clocks.c.

#define PLLE_AUX_PLLP_SEL (1<<2)

Definition at line 289 of file tegra30_clocks.c.

#define PLLE_BASE_CML_ENABLE (1<<31)

Definition at line 245 of file tegra30_clocks.c.

#define PLLE_BASE_DIV	(	m,
		n,
		p,
		cml
	)

Value:

(((cml)<<PLLE_BASE_DIVCML_SHIFT) | ((p)<<PLLE_BASE_DIVP_SHIFT) | \

((n)<<PLLE_BASE_DIVN_SHIFT) | ((m)<<PLLE_BASE_DIVM_SHIFT))

Definition at line 258 of file tegra30_clocks.c.

#define PLLE_BASE_DIV_MASK

Value:

(PLLE_BASE_DIVCML_MASK | PLLE_BASE_DIVP_MASK | \

PLLE_BASE_DIVN_MASK | PLLE_BASE_DIVM_MASK)

Definition at line 255 of file tegra30_clocks.c.

#define PLLE_BASE_DIVCML_MASK (0xf<<PLLE_BASE_DIVCML_SHIFT)

Definition at line 248 of file tegra30_clocks.c.

#define PLLE_BASE_DIVCML_SHIFT 24

Definition at line 247 of file tegra30_clocks.c.

#define PLLE_BASE_DIVM_MASK (0xFF<<PLLE_BASE_DIVM_SHIFT)

Definition at line 254 of file tegra30_clocks.c.

#define PLLE_BASE_DIVM_SHIFT 0

Definition at line 253 of file tegra30_clocks.c.

#define PLLE_BASE_DIVN_MASK (0xFF<<PLLE_BASE_DIVN_SHIFT)

Definition at line 252 of file tegra30_clocks.c.

#define PLLE_BASE_DIVN_SHIFT 8

Definition at line 251 of file tegra30_clocks.c.

#define PLLE_BASE_DIVP_MASK (0x3f<<PLLE_BASE_DIVP_SHIFT)

Definition at line 250 of file tegra30_clocks.c.

#define PLLE_BASE_DIVP_SHIFT 16

Definition at line 249 of file tegra30_clocks.c.

#define PLLE_BASE_ENABLE (1<<30)

Definition at line 246 of file tegra30_clocks.c.

#define PLLE_MISC_LOCK (1<<11)

Definition at line 265 of file tegra30_clocks.c.

#define PLLE_MISC_LOCK_ENABLE (1<<9)

Definition at line 266 of file tegra30_clocks.c.

#define PLLE_MISC_READY (1<<15)

Definition at line 264 of file tegra30_clocks.c.

#define PLLE_MISC_SETUP_BASE_MASK (0xFFFF<<PLLE_MISC_SETUP_BASE_SHIFT)

Definition at line 263 of file tegra30_clocks.c.

#define PLLE_MISC_SETUP_BASE_SHIFT 16

Definition at line 262 of file tegra30_clocks.c.

#define PLLE_MISC_SETUP_EX_MASK (0x3<<PLLE_MISC_SETUP_EX_SHIFT)

Definition at line 268 of file tegra30_clocks.c.

#define PLLE_MISC_SETUP_EX_SHIFT 2

Definition at line 267 of file tegra30_clocks.c.

#define PLLE_MISC_SETUP_MASK (PLLE_MISC_SETUP_BASE_MASK | PLLE_MISC_SETUP_EX_MASK)

Definition at line 269 of file tegra30_clocks.c.

#define PLLE_MISC_SETUP_VALUE ((0x7<<PLLE_MISC_SETUP_BASE_SHIFT) | (0x0<<PLLE_MISC_SETUP_EX_SHIFT))

Definition at line 271 of file tegra30_clocks.c.

#define PLLE_SS_COEFFICIENTS_12MHZ

Value:

((0x18<<PLLE_SS_INCINTRV_SHIFT) | (0x1<<PLLE_SS_INC_SHIFT) | \

(0x24<<PLLE_SS_MAX_SHIFT))

Definition at line 283 of file tegra30_clocks.c.

#define PLLE_SS_COEFFICIENTS_MASK (PLLE_SS_INCINTRV_MASK | PLLE_SS_INC_MASK | PLLE_SS_MAX_MASK)

Definition at line 281 of file tegra30_clocks.c.

#define PLLE_SS_CTRL 0x68

Definition at line 274 of file tegra30_clocks.c.

#define PLLE_SS_DISABLE ((1<<12) | (1<<11) | (1<<10))

Definition at line 286 of file tegra30_clocks.c.

#define PLLE_SS_INC_MASK (0xff<<PLLE_SS_INC_SHIFT)

Definition at line 278 of file tegra30_clocks.c.

#define PLLE_SS_INC_SHIFT 16

Definition at line 277 of file tegra30_clocks.c.

#define PLLE_SS_INCINTRV_MASK (0x3f<<PLLE_SS_INCINTRV_SHIFT)

Definition at line 276 of file tegra30_clocks.c.

#define PLLE_SS_INCINTRV_SHIFT 24

Definition at line 275 of file tegra30_clocks.c.

#define PLLE_SS_MAX_MASK (0x1ff<<PLLE_SS_MAX_SHIFT)

Definition at line 280 of file tegra30_clocks.c.

#define PLLE_SS_MAX_SHIFT 0

Definition at line 279 of file tegra30_clocks.c.

#define PLLU_BASE_POST_DIV (1<<20)

Definition at line 178 of file tegra30_clocks.c.

#define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff

Definition at line 226 of file tegra30_clocks.c.

#define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16

Definition at line 225 of file tegra30_clocks.c.

#define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff

Definition at line 223 of file tegra30_clocks.c.

#define PMC_BLINK_TIMER_DATA_ON_SHIFT 0

Definition at line 222 of file tegra30_clocks.c.

#define PMC_BLINK_TIMER_ENB (1 << 15)

Definition at line 224 of file tegra30_clocks.c.

#define PMC_CTRL 0x0

Definition at line 216 of file tegra30_clocks.c.

#define PMC_CTRL_BLINK_ENB (1 << 7)

Definition at line 217 of file tegra30_clocks.c.

#define PMC_DPD_PADS_ORIDE 0x1c

Definition at line 219 of file tegra30_clocks.c.

#define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)

Definition at line 220 of file tegra30_clocks.c.

#define PMC_PLLP_WB0_OVERRIDE 0xf8

Definition at line 228 of file tegra30_clocks.c.

#define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE (1 << 12)

Definition at line 229 of file tegra30_clocks.c.

#define pmc_readl ( reg ) __raw_readl(reg_pmc_base + (reg))

Definition at line 384 of file tegra30_clocks.c.

#define PMC_SATA_PWRGT 0x1ac

Definition at line 293 of file tegra30_clocks.c.

#define PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL (1<<4)

Definition at line 295 of file tegra30_clocks.c.

#define PMC_SATA_PWRGT_PLLE_IDDQ_VALUE (1<<5)

Definition at line 294 of file tegra30_clocks.c.

#define pmc_writel	(	value,
		reg
	)	__raw_writel(value, reg_pmc_base + (reg))

Definition at line 382 of file tegra30_clocks.c.

#define ROUND_DIVIDER_DOWN 1

Definition at line 298 of file tegra30_clocks.c.

#define ROUND_DIVIDER_UP 0

Definition at line 297 of file tegra30_clocks.c.

#define RST_DEVICES_CLR_L 0x304

Definition at line 48 of file tegra30_clocks.c.

#define RST_DEVICES_CLR_V 0x434

Definition at line 50 of file tegra30_clocks.c.

#define RST_DEVICES_H 0x008

Definition at line 43 of file tegra30_clocks.c.

#define RST_DEVICES_L 0x004

Definition at line 42 of file tegra30_clocks.c.

#define RST_DEVICES_NUM 5

Definition at line 51 of file tegra30_clocks.c.

#define RST_DEVICES_SET_L 0x300

Definition at line 47 of file tegra30_clocks.c.

#define RST_DEVICES_SET_V 0x430

Definition at line 49 of file tegra30_clocks.c.

#define RST_DEVICES_U 0x00C

Definition at line 44 of file tegra30_clocks.c.

#define RST_DEVICES_V 0x358

Definition at line 45 of file tegra30_clocks.c.

#define RST_DEVICES_V_SWR_CPULP_RST_DIS (0x1 << 1)

Definition at line 64 of file tegra30_clocks.c.

#define RST_DEVICES_W 0x35C

Definition at line 46 of file tegra30_clocks.c.

#define SUPER_CLK_DIVIDER 0x04

Definition at line 207 of file tegra30_clocks.c.

#define SUPER_CLK_MUX 0x00

Definition at line 192 of file tegra30_clocks.c.

#define SUPER_CLOCK_DIV_U71_MASK (0xff << SUPER_CLOCK_DIV_U71_SHIFT)

Definition at line 209 of file tegra30_clocks.c.

#define SUPER_CLOCK_DIV_U71_MIN 0x2

Definition at line 211 of file tegra30_clocks.c.

#define SUPER_CLOCK_DIV_U71_SHIFT 16

Definition at line 208 of file tegra30_clocks.c.

#define SUPER_FIQ_SOURCE_SHIFT 12

Definition at line 202 of file tegra30_clocks.c.

#define SUPER_IDLE_SOURCE_SHIFT 0

Definition at line 205 of file tegra30_clocks.c.

#define SUPER_IRQ_SOURCE_SHIFT 8

Definition at line 203 of file tegra30_clocks.c.

#define SUPER_LP_DIV2_BYPASS (0x1 << 16)

Definition at line 200 of file tegra30_clocks.c.

#define SUPER_RUN_SOURCE_SHIFT 4

Definition at line 204 of file tegra30_clocks.c.

#define SUPER_SOURCE_MASK 0xF

Definition at line 201 of file tegra30_clocks.c.

#define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)

Definition at line 199 of file tegra30_clocks.c.

#define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)

Definition at line 196 of file tegra30_clocks.c.

#define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)

Definition at line 198 of file tegra30_clocks.c.

#define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)

Definition at line 194 of file tegra30_clocks.c.

#define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)

Definition at line 197 of file tegra30_clocks.c.

#define SUPER_STATE_SHIFT 28

Definition at line 193 of file tegra30_clocks.c.

#define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)

Definition at line 195 of file tegra30_clocks.c.

#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c

Definition at line 307 of file tegra30_clocks.c.

#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470

Definition at line 308 of file tegra30_clocks.c.

#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c

Definition at line 304 of file tegra30_clocks.c.

#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344

Definition at line 306 of file tegra30_clocks.c.

#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340

Definition at line 305 of file tegra30_clocks.c.

#define USE_PLL_LOCK_BITS 0

Definition at line 40 of file tegra30_clocks.c.

#define UTMIP_PLL_CFG1 0x484

Definition at line 238 of file tegra30_clocks.c.

#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT ( x ) (((x) & 0x1f) << 27)

Definition at line 239 of file tegra30_clocks.c.

#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN (1 << 12)

Definition at line 242 of file tegra30_clocks.c.

#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN (1 << 14)

Definition at line 241 of file tegra30_clocks.c.

#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN (1 << 16)

Definition at line 243 of file tegra30_clocks.c.

#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT ( x ) (((x) & 0xfff) << 0)

Definition at line 240 of file tegra30_clocks.c.

#define UTMIP_PLL_CFG2 0x488

Definition at line 231 of file tegra30_clocks.c.

#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT ( x ) (((x) & 0x3f) << 18)

Definition at line 233 of file tegra30_clocks.c.

#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)

Definition at line 234 of file tegra30_clocks.c.

#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)

Definition at line 235 of file tegra30_clocks.c.

#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)

Definition at line 236 of file tegra30_clocks.c.

#define UTMIP_PLL_CFG2_STABLE_COUNT ( x ) (((x) & 0xfff) << 6)

Definition at line 232 of file tegra30_clocks.c.

Function Documentation

void __init tegra30_cpu_car_ops_init ( void )

Definition at line 2292 of file tegra30_clocks.c.

int tegra30_dtv_clk_cfg_ex	(	struct clk_hw *	hw,
		enum tegra_clk_ex_param	p,
		u32	setting
	)

Definition at line 1970 of file tegra30_clocks.c.

int tegra30_nand_clk_cfg_ex	(	struct clk_hw *	hw,
		enum tegra_clk_ex_param	p,
		u32	setting
	)

Definition at line 1953 of file tegra30_clocks.c.

void tegra30_periph_clk_reset	(	struct clk_hw *	hw,
		bool	assert
	)

Definition at line 1743 of file tegra30_clocks.c.

int tegra30_plld_clk_cfg_ex	(	struct clk_hw *	hw,
		enum tegra_clk_ex_param	p,
		u32	setting
	)

Definition at line 1329 of file tegra30_clocks.c.

int tegra30_vi_clk_cfg_ex	(	struct clk_hw *	hw,
		enum tegra_clk_ex_param	p,
		u32	setting
	)

Definition at line 1937 of file tegra30_clocks.c.

Variable Documentation

struct clk_ops tegra30_audio_sync_clk_ops

Initial value:

= {
    .is_enabled = tegra30_audio_sync_clk_is_enabled,
    .enable = tegra30_audio_sync_clk_enable,
    .disable = tegra30_audio_sync_clk_disable,
    .set_parent = tegra30_audio_sync_clk_set_parent,
    .get_parent = tegra30_audio_sync_clk_get_parent,
    .recalc_rate = tegra30_clk_fixed_recalc_rate,
}

Definition at line 2187 of file tegra30_clocks.c.

struct clk_ops tegra30_blink_clk_ops

Initial value:

= {
    .is_enabled = tegra30_blink_clk_is_enabled,
    .enable = tegra30_blink_clk_enable,
    .disable = tegra30_blink_clk_disable,
    .recalc_rate = tegra30_blink_clk_recalc_rate,
    .round_rate = tegra30_blink_clk_round_rate,
    .set_rate = tegra30_blink_clk_set_rate,
}

Definition at line 913 of file tegra30_clocks.c.

struct clk_ops tegra30_clk_32k_ops

Initial value:

= {
    .recalc_rate = tegra30_clk_fixed_recalc_rate,
}

Definition at line 492 of file tegra30_clocks.c.

struct clk_ops tegra30_clk_double_ops

Initial value:

= {
    .is_enabled = tegra30_clk_double_is_enabled,
    .enable = tegra30_periph_clk_enable,
    .disable = tegra30_periph_clk_disable,
    .recalc_rate = tegra30_clk_double_recalc_rate,
    .round_rate = tegra30_clk_double_round_rate,
    .set_rate = tegra30_clk_double_set_rate,
}

Definition at line 2127 of file tegra30_clocks.c.

struct clk_ops tegra30_clk_m_ops

Initial value:

= {
    .init = tegra30_clk_m_init,
    .recalc_rate = tegra30_clk_m_recalc_rate,
}

Definition at line 548 of file tegra30_clocks.c.

struct clk_ops tegra30_dsib_clk_ops

Initial value:

= {
    .is_enabled = tegra30_periph_clk_is_enabled,
    .enable         = &tegra30_periph_clk_enable,
    .disable        = &tegra30_periph_clk_disable,
    .set_parent     = &tegra30_dsib_clk_set_parent,
    .get_parent     = &tegra30_periph_clk_get_parent,
    .set_rate       = &tegra30_periph_clk_set_rate,
    .round_rate     = &tegra30_periph_clk_round_rate,
    .recalc_rate        = &tegra30_periph_clk_recalc_rate,
}

Definition at line 1925 of file tegra30_clocks.c.

struct clk_ops tegra30_periph_clk_ops

Initial value:

= {
    .is_enabled = tegra30_periph_clk_is_enabled,
    .enable = tegra30_periph_clk_enable,
    .disable = tegra30_periph_clk_disable,
    .set_parent = tegra30_periph_clk_set_parent,
    .get_parent = tegra30_periph_clk_get_parent,
    .set_rate = tegra30_periph_clk_set_rate,
    .round_rate = tegra30_periph_clk_round_rate,
    .recalc_rate = tegra30_periph_clk_recalc_rate,
}

Definition at line 1902 of file tegra30_clocks.c.

struct clk_ops tegra30_pll_div_ops

Initial value:

= {
    .is_enabled = tegra30_pll_div_clk_is_enabled,
    .enable = tegra30_pll_div_clk_enable,
    .disable = tegra30_pll_div_clk_disable,
    .set_rate = tegra30_pll_div_clk_set_rate,
    .recalc_rate = tegra30_pll_div_clk_recalc_rate,
    .round_rate = tegra30_pll_div_clk_round_rate,
}

Definition at line 1652 of file tegra30_clocks.c.

struct clk_ops tegra30_pll_ops

Initial value:

= {
    .is_enabled = tegra30_pll_clk_is_enabled,
    .init = tegra30_pll_clk_init,
    .enable = tegra30_pll_clk_enable,
    .disable = tegra30_pll_clk_disable,
    .recalc_rate = tegra30_pll_recalc_rate,
    .round_rate = tegra30_pll_round_rate,
    .set_rate = tegra30_pll_clk_set_rate,
}

Definition at line 1319 of file tegra30_clocks.c.

struct clk_ops tegra30_plle_ops

Initial value:

= {
    .is_enabled = tegra30_plle_clk_is_enabled,
    .enable = tegra30_plle_clk_enable,
    .disable = tegra30_plle_clk_disable,
    .recalc_rate = tegra30_plle_clk_recalc_rate,
}

Definition at line 1491 of file tegra30_clocks.c.

struct clk_ops tegra30_super_ops

Initial value:

= {
    .init = tegra30_super_clk_init,
    .set_parent = tegra30_super_clk_set_parent,
    .get_parent = tegra30_super_clk_get_parent,
    .recalc_rate = tegra30_super_clk_recalc_rate,
    .round_rate = tegra30_super_clk_round_rate,
    .set_rate = tegra30_super_clk_set_rate,
}

Definition at line 767 of file tegra30_clocks.c.

struct clk_ops tegra30_twd_ops

Initial value:

= {
    .recalc_rate = tegra30_twd_clk_recalc_rate,
}

Definition at line 791 of file tegra30_clocks.c.

struct clk_ops tegra_clk_m_div_ops

Initial value:

= {
    .recalc_rate = tegra30_clk_m_div_recalc_rate,
}

Definition at line 568 of file tegra30_clocks.c.

struct clk_ops tegra_clk_out_ops

Initial value:

= {
    .is_enabled = tegra30_clk_out_is_enabled,
    .enable = tegra30_clk_out_enable,
    .disable = tegra30_clk_out_disable,
    .set_parent = tegra30_clk_out_set_parent,
    .get_parent = tegra30_clk_out_get_parent,
    .recalc_rate = tegra30_clk_fixed_recalc_rate,
}

Definition at line 2057 of file tegra30_clocks.c.

struct clk_ops tegra_cml_clk_ops

Initial value:

= {
    .is_enabled = tegra30_cml_clk_is_enabled,
    .enable = tegra30_cml_clk_enable,
    .disable = tegra30_cml_clk_disable,
    .recalc_rate = tegra30_clk_fixed_recalc_rate,
}

Definition at line 2225 of file tegra30_clocks.c.

struct clk_ops tegra_pciex_clk_ops

Initial value:

= {
    .recalc_rate = tegra30_clk_fixed_recalc_rate,
}

Definition at line 2232 of file tegra30_clocks.c.

struct clk_ops tegra_pll_ref_ops

Initial value:

= {
    .recalc_rate = tegra30_pll_ref_recalc_rate,
}

Definition at line 605 of file tegra30_clocks.c.

struct clk_ops tegra_sync_source_ops

Initial value:

= {
    .recalc_rate = tegra30_clk_fixed_recalc_rate,
}

Definition at line 2137 of file tegra30_clocks.c.

Variables
struct clk_ops	tegra30_clk_32k_ops

struct clk_ops	tegra30_clk_m_ops

struct clk_ops	tegra_clk_m_div_ops

struct clk_ops	tegra_pll_ref_ops

struct clk_ops	tegra30_super_ops

struct clk_ops	tegra30_twd_ops

struct clk_ops	tegra30_blink_clk_ops

struct clk_ops	tegra30_pll_ops

struct clk_ops	tegra30_plle_ops

struct clk_ops	tegra30_pll_div_ops

struct clk_ops	tegra30_periph_clk_ops

struct clk_ops	tegra30_dsib_clk_ops

struct clk_ops	tegra_clk_out_ops

struct clk_ops	tegra30_clk_double_ops

struct clk_ops	tegra_sync_source_ops

struct clk_ops	tegra30_audio_sync_clk_ops

struct clk_ops	tegra_cml_clk_ops

struct clk_ops	tegra_pciex_clk_ops

Data Structures

Macros

Functions

Variables

Macro Definition Documentation

Function Documentation

Variable Documentation