|
| #define | BAR_0 0 |
| |
| #define | BAR_2 2 |
| |
| #define | tg3_flag(tp, flag) _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags) |
| |
| #define | tg3_flag_set(tp, flag) _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags) |
| |
| #define | tg3_flag_clear(tp, flag) _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags) |
| |
| #define | DRV_MODULE_NAME "tg3" |
| |
| #define | TG3_MAJ_NUM 3 |
| |
| #define | TG3_MIN_NUM 125 |
| |
| #define | DRV_MODULE_VERSION __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM) |
| |
| #define | DRV_MODULE_RELDATE "September 26, 2012" |
| |
| #define | RESET_KIND_SHUTDOWN 0 |
| |
| #define | RESET_KIND_INIT 1 |
| |
| #define | RESET_KIND_SUSPEND 2 |
| |
| #define | TG3_DEF_RX_MODE 0 |
| |
| #define | TG3_DEF_TX_MODE 0 |
| |
| #define | TG3_DEF_MSG_ENABLE |
| |
| #define | TG3_GRC_LCLCTL_PWRSW_DELAY 100 |
| |
| #define | TG3_TX_TIMEOUT (5 * HZ) |
| |
| #define | TG3_MIN_MTU 60 |
| |
| #define | TG3_MAX_MTU(tp) (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500) |
| |
| #define | TG3_RX_STD_RING_SIZE(tp) |
| |
| #define | TG3_DEF_RX_RING_PENDING 200 |
| |
| #define | TG3_RX_JMB_RING_SIZE(tp) |
| |
| #define | TG3_DEF_RX_JUMBO_RING_PENDING 100 |
| |
| #define | TG3_TX_RING_SIZE 512 |
| |
| #define | TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1) |
| |
| #define | TG3_RX_STD_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp)) |
| |
| #define | TG3_RX_JMB_RING_BYTES(tp) (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp)) |
| |
| #define | TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1)) |
| |
| #define | TG3_TX_RING_BYTES |
| |
| #define | NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1)) |
| |
| #define | TG3_DMA_BYTE_ENAB 64 |
| |
| #define | TG3_RX_STD_DMA_SZ 1536 |
| |
| #define | TG3_RX_JMB_DMA_SZ 9046 |
| |
| #define | TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB) |
| |
| #define | TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ) |
| |
| #define | TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ) |
| |
| #define | TG3_RX_STD_BUFF_RING_SIZE(tp) (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp)) |
| |
| #define | TG3_RX_JMB_BUFF_RING_SIZE(tp) (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp)) |
| |
| #define | TG3_RX_COPY_THRESHOLD 256 |
| |
| #define | TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD |
| |
| #define | TG3_RX_OFFSET(tp) (NET_SKB_PAD) |
| |
| #define | TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4) |
| |
| #define | TG3_TX_BD_DMA_MAX_2K 2048 |
| |
| #define | TG3_TX_BD_DMA_MAX_4K 4096 |
| |
| #define | TG3_RAW_IP_ALIGN 2 |
| |
| #define | TG3_FW_UPDATE_TIMEOUT_SEC 5 |
| |
| #define | TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2) |
| |
| #define | FIRMWARE_TG3 "tigon/tg3.bin" |
| |
| #define | FIRMWARE_TG3TSO "tigon/tg3_tso.bin" |
| |
| #define | FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin" |
| |
| #define | TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys) |
| |
| #define | TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys) |
| |
| #define | tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val) |
| |
| #define | tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val)) |
| |
| #define | tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val) |
| |
| #define | tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val) |
| |
| #define | tr32_mailbox(reg) tp->read32_mbox(tp, reg) |
| |
| #define | tw32(reg, val) tp->write32(tp, reg, val) |
| |
| #define | tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0) |
| |
| #define | tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us)) |
| |
| #define | tr32(reg) tp->read32(tp, reg) |
| |
| #define | PHY_BUSY_LOOPS 5000 |
| |
| #define | TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) |
| |
| #define | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) |
| |
| #define | TG3_FW_EVENT_TIMEOUT_USEC 2500 |
| |
| #define | TG3_GPIO_MSG_DRVR_PRES 0x00000001 |
| |
| #define | TG3_GPIO_MSG_NEED_VAUX 0x00000002 |
| |
| #define | TG3_GPIO_MSG_MASK |
| |
| #define | TG3_GPIO_MSG_ALL_DRVR_PRES_MASK |
| |
| #define | TG3_GPIO_MSG_ALL_NEED_VAUX_MASK |
| |
| #define | NVRAM_CMD_TIMEOUT 10000 |
| |
| #define | RX_CPU_SCRATCH_BASE 0x30000 |
| |
| #define | RX_CPU_SCRATCH_SIZE 0x04000 |
| |
| #define | TX_CPU_SCRATCH_BASE 0x34000 |
| |
| #define | TX_CPU_SCRATCH_SIZE 0x04000 |
| |
| #define | ANEG_STATE_UNKNOWN 0 |
| |
| #define | ANEG_STATE_AN_ENABLE 1 |
| |
| #define | ANEG_STATE_RESTART_INIT 2 |
| |
| #define | ANEG_STATE_RESTART 3 |
| |
| #define | ANEG_STATE_DISABLE_LINK_OK 4 |
| |
| #define | ANEG_STATE_ABILITY_DETECT_INIT 5 |
| |
| #define | ANEG_STATE_ABILITY_DETECT 6 |
| |
| #define | ANEG_STATE_ACK_DETECT_INIT 7 |
| |
| #define | ANEG_STATE_ACK_DETECT 8 |
| |
| #define | ANEG_STATE_COMPLETE_ACK_INIT 9 |
| |
| #define | ANEG_STATE_COMPLETE_ACK 10 |
| |
| #define | ANEG_STATE_IDLE_DETECT_INIT 11 |
| |
| #define | ANEG_STATE_IDLE_DETECT 12 |
| |
| #define | ANEG_STATE_LINK_OK 13 |
| |
| #define | ANEG_STATE_NEXT_PAGE_WAIT_INIT 14 |
| |
| #define | ANEG_STATE_NEXT_PAGE_WAIT 15 |
| |
| #define | MR_AN_ENABLE 0x00000001 |
| |
| #define | MR_RESTART_AN 0x00000002 |
| |
| #define | MR_AN_COMPLETE 0x00000004 |
| |
| #define | MR_PAGE_RX 0x00000008 |
| |
| #define | MR_NP_LOADED 0x00000010 |
| |
| #define | MR_TOGGLE_TX 0x00000020 |
| |
| #define | MR_LP_ADV_FULL_DUPLEX 0x00000040 |
| |
| #define | MR_LP_ADV_HALF_DUPLEX 0x00000080 |
| |
| #define | MR_LP_ADV_SYM_PAUSE 0x00000100 |
| |
| #define | MR_LP_ADV_ASYM_PAUSE 0x00000200 |
| |
| #define | MR_LP_ADV_REMOTE_FAULT1 0x00000400 |
| |
| #define | MR_LP_ADV_REMOTE_FAULT2 0x00000800 |
| |
| #define | MR_LP_ADV_NEXT_PAGE 0x00001000 |
| |
| #define | MR_TOGGLE_RX 0x00002000 |
| |
| #define | MR_NP_RX 0x00004000 |
| |
| #define | MR_LINK_OK 0x80000000 |
| |
| #define | ANEG_CFG_NP 0x00000080 |
| |
| #define | ANEG_CFG_ACK 0x00000040 |
| |
| #define | ANEG_CFG_RF2 0x00000020 |
| |
| #define | ANEG_CFG_RF1 0x00000010 |
| |
| #define | ANEG_CFG_PS2 0x00000001 |
| |
| #define | ANEG_CFG_PS1 0x00008000 |
| |
| #define | ANEG_CFG_HD 0x00004000 |
| |
| #define | ANEG_CFG_FD 0x00002000 |
| |
| #define | ANEG_CFG_INVAL 0x00001f06 |
| |
| #define | ANEG_OK 0 |
| |
| #define | ANEG_DONE 1 |
| |
| #define | ANEG_TIMER_ENAB 2 |
| |
| #define | ANEG_FAILED -1 |
| |
| #define | ANEG_STATE_SETTLE_TIME 10000 |
| |
| #define | MAX_WAIT_CNT 1000 |
| |
| #define | TG3_STAT_ADD32(PSTAT, REG) |
| |
| #define | ESTAT_ADD(member) |
| |
| #define | NVRAM_TEST_SIZE 0x100 |
| |
| #define | NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14 |
| |
| #define | NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18 |
| |
| #define | NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c |
| |
| #define | NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20 |
| |
| #define | NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24 |
| |
| #define | NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50 |
| |
| #define | NVRAM_SELFBOOT_HW_SIZE 0x20 |
| |
| #define | NVRAM_SELFBOOT_DATA_SIZE 0x1c |
| |
| #define | TG3_SERDES_TIMEOUT_SEC 2 |
| |
| #define | TG3_COPPER_TIMEOUT_SEC 6 |
| |
| #define | TG3_FL_5705 0x1 |
| |
| #define | TG3_FL_NOT_5705 0x2 |
| |
| #define | TG3_FL_NOT_5788 0x4 |
| |
| #define | TG3_FL_NOT_5750 0x8 |
| |
| #define | TG3_TSO_MSS 500 |
| |
| #define | TG3_TSO_IP_HDR_LEN 20 |
| |
| #define | TG3_TSO_TCP_HDR_LEN 20 |
| |
| #define | TG3_TSO_TCP_OPT_LEN 12 |
| |
| #define | TG3_STD_LOOPBACK_FAILED 1 |
| |
| #define | TG3_JMB_LOOPBACK_FAILED 2 |
| |
| #define | TG3_TSO_LOOPBACK_FAILED 4 |
| |
| #define | TG3_LOOPBACK_FAILED |
| |
| #define | BOUNDARY_SINGLE_CACHELINE 1 |
| |
| #define | BOUNDARY_MULTI_CACHELINE 2 |
| |
| #define | TEST_BUFFER_SIZE 0x2000 |
| |
| #define | TG3_PM_OPS NULL |
| |
1.8.2