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tg3.c
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1 /*
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller ([email protected])
5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik ([email protected])
6  * Copyright (C) 2004 Sun Microsystems Inc.
7  * Copyright (C) 2005-2012 Broadcom Corporation.
8  *
9  * Firmware is:
10  * Derived from proprietary unpublished source code,
11  * Copyright (C) 2000-2003 Broadcom Corporation.
12  *
13  * Permission is hereby granted for the distribution of this firmware
14  * data in hexadecimal or equivalent format, provided this copyright
15  * notice is accompanying it.
16  */
17 
18 
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/in.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/skbuff.h>
35 #include <linux/ethtool.h>
36 #include <linux/mdio.h>
37 #include <linux/mii.h>
38 #include <linux/phy.h>
39 #include <linux/brcmphy.h>
40 #include <linux/if_vlan.h>
41 #include <linux/ip.h>
42 #include <linux/tcp.h>
43 #include <linux/workqueue.h>
44 #include <linux/prefetch.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/firmware.h>
47 #include <linux/hwmon.h>
48 #include <linux/hwmon-sysfs.h>
49 
50 #include <net/checksum.h>
51 #include <net/ip.h>
52 
53 #include <linux/io.h>
54 #include <asm/byteorder.h>
55 #include <linux/uaccess.h>
56 
57 #ifdef CONFIG_SPARC
58 #include <asm/idprom.h>
59 #include <asm/prom.h>
60 #endif
61 
62 #define BAR_0 0
63 #define BAR_2 2
64 
65 #include "tg3.h"
66 
67 /* Functions & macros to verify TG3_FLAGS types */
68 
69 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
70 {
71  return test_bit(flag, bits);
72 }
73 
74 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
75 {
76  set_bit(flag, bits);
77 }
78 
79 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
80 {
81  clear_bit(flag, bits);
82 }
83 
84 #define tg3_flag(tp, flag) \
85  _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
86 #define tg3_flag_set(tp, flag) \
87  _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
88 #define tg3_flag_clear(tp, flag) \
89  _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
90 
91 #define DRV_MODULE_NAME "tg3"
92 #define TG3_MAJ_NUM 3
93 #define TG3_MIN_NUM 125
94 #define DRV_MODULE_VERSION \
95  __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
96 #define DRV_MODULE_RELDATE "September 26, 2012"
97 
98 #define RESET_KIND_SHUTDOWN 0
99 #define RESET_KIND_INIT 1
100 #define RESET_KIND_SUSPEND 2
101 
102 #define TG3_DEF_RX_MODE 0
103 #define TG3_DEF_TX_MODE 0
104 #define TG3_DEF_MSG_ENABLE \
105  (NETIF_MSG_DRV | \
106  NETIF_MSG_PROBE | \
107  NETIF_MSG_LINK | \
108  NETIF_MSG_TIMER | \
109  NETIF_MSG_IFDOWN | \
110  NETIF_MSG_IFUP | \
111  NETIF_MSG_RX_ERR | \
112  NETIF_MSG_TX_ERR)
113 
114 #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
115 
116 /* length of time before we decide the hardware is borked,
117  * and dev->tx_timeout() should be called to fix the problem
118  */
119 
120 #define TG3_TX_TIMEOUT (5 * HZ)
121 
122 /* hardware minimum and maximum for a single frame's data payload */
123 #define TG3_MIN_MTU 60
124 #define TG3_MAX_MTU(tp) \
125  (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
126 
127 /* These numbers seem to be hard coded in the NIC firmware somehow.
128  * You can't change the ring sizes, but you can change where you place
129  * them in the NIC onboard memory.
130  */
131 #define TG3_RX_STD_RING_SIZE(tp) \
132  (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
133  TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
134 #define TG3_DEF_RX_RING_PENDING 200
135 #define TG3_RX_JMB_RING_SIZE(tp) \
136  (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
137  TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
138 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
139 
140 /* Do not place this n-ring entries value into the tp struct itself,
141  * we really want to expose these constants to GCC so that modulo et
142  * al. operations are done with shifts and masks instead of with
143  * hw multiply/modulo instructions. Another solution would be to
144  * replace things like '% foo' with '& (foo - 1)'.
145  */
146 
147 #define TG3_TX_RING_SIZE 512
148 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
149 
150 #define TG3_RX_STD_RING_BYTES(tp) \
151  (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
152 #define TG3_RX_JMB_RING_BYTES(tp) \
153  (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
154 #define TG3_RX_RCB_RING_BYTES(tp) \
155  (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
156 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
157  TG3_TX_RING_SIZE)
158 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
159 
160 #define TG3_DMA_BYTE_ENAB 64
161 
162 #define TG3_RX_STD_DMA_SZ 1536
163 #define TG3_RX_JMB_DMA_SZ 9046
164 
165 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
166 
167 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
168 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
169 
170 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
171  (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
172 
173 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
174  (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
175 
176 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
177  * that are at least dword aligned when used in PCIX mode. The driver
178  * works around this bug by double copying the packet. This workaround
179  * is built into the normal double copy length check for efficiency.
180  *
181  * However, the double copy is only necessary on those architectures
182  * where unaligned memory accesses are inefficient. For those architectures
183  * where unaligned memory accesses incur little penalty, we can reintegrate
184  * the 5701 in the normal rx path. Doing so saves a device structure
185  * dereference by hardcoding the double copy threshold in place.
186  */
187 #define TG3_RX_COPY_THRESHOLD 256
188 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
189  #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
190 #else
191  #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
192 #endif
193 
194 #if (NET_IP_ALIGN != 0)
195 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
196 #else
197 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
198 #endif
199 
200 /* minimum number of free TX descriptors required to wake up TX process */
201 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
202 #define TG3_TX_BD_DMA_MAX_2K 2048
203 #define TG3_TX_BD_DMA_MAX_4K 4096
204 
205 #define TG3_RAW_IP_ALIGN 2
206 
207 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
208 #define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
209 
210 #define FIRMWARE_TG3 "tigon/tg3.bin"
211 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
212 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
213 
214 static char version[] __devinitdata =
216 
217 MODULE_AUTHOR("David S. Miller ([email protected]) and Jeff Garzik ([email protected])");
218 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
219 MODULE_LICENSE("GPL");
224 
225 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
226 module_param(tg3_debug, int, 0);
227 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
228 
229 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
311  {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
312  {}
313 };
314 
315 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
316 
317 static const struct {
318  const char string[ETH_GSTRING_LEN];
319 } ethtool_stats_keys[] = {
320  { "rx_octets" },
321  { "rx_fragments" },
322  { "rx_ucast_packets" },
323  { "rx_mcast_packets" },
324  { "rx_bcast_packets" },
325  { "rx_fcs_errors" },
326  { "rx_align_errors" },
327  { "rx_xon_pause_rcvd" },
328  { "rx_xoff_pause_rcvd" },
329  { "rx_mac_ctrl_rcvd" },
330  { "rx_xoff_entered" },
331  { "rx_frame_too_long_errors" },
332  { "rx_jabbers" },
333  { "rx_undersize_packets" },
334  { "rx_in_length_errors" },
335  { "rx_out_length_errors" },
336  { "rx_64_or_less_octet_packets" },
337  { "rx_65_to_127_octet_packets" },
338  { "rx_128_to_255_octet_packets" },
339  { "rx_256_to_511_octet_packets" },
340  { "rx_512_to_1023_octet_packets" },
341  { "rx_1024_to_1522_octet_packets" },
342  { "rx_1523_to_2047_octet_packets" },
343  { "rx_2048_to_4095_octet_packets" },
344  { "rx_4096_to_8191_octet_packets" },
345  { "rx_8192_to_9022_octet_packets" },
346 
347  { "tx_octets" },
348  { "tx_collisions" },
349 
350  { "tx_xon_sent" },
351  { "tx_xoff_sent" },
352  { "tx_flow_control" },
353  { "tx_mac_errors" },
354  { "tx_single_collisions" },
355  { "tx_mult_collisions" },
356  { "tx_deferred" },
357  { "tx_excessive_collisions" },
358  { "tx_late_collisions" },
359  { "tx_collide_2times" },
360  { "tx_collide_3times" },
361  { "tx_collide_4times" },
362  { "tx_collide_5times" },
363  { "tx_collide_6times" },
364  { "tx_collide_7times" },
365  { "tx_collide_8times" },
366  { "tx_collide_9times" },
367  { "tx_collide_10times" },
368  { "tx_collide_11times" },
369  { "tx_collide_12times" },
370  { "tx_collide_13times" },
371  { "tx_collide_14times" },
372  { "tx_collide_15times" },
373  { "tx_ucast_packets" },
374  { "tx_mcast_packets" },
375  { "tx_bcast_packets" },
376  { "tx_carrier_sense_errors" },
377  { "tx_discards" },
378  { "tx_errors" },
379 
380  { "dma_writeq_full" },
381  { "dma_write_prioq_full" },
382  { "rxbds_empty" },
383  { "rx_discards" },
384  { "rx_errors" },
385  { "rx_threshold_hit" },
386 
387  { "dma_readq_full" },
388  { "dma_read_prioq_full" },
389  { "tx_comp_queue_full" },
390 
391  { "ring_set_send_prod_index" },
392  { "ring_status_update" },
393  { "nic_irqs" },
394  { "nic_avoided_irqs" },
395  { "nic_tx_threshold_hit" },
396 
397  { "mbuf_lwm_thresh_hit" },
398 };
399 
400 #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
401 
402 
403 static const struct {
404  const char string[ETH_GSTRING_LEN];
405 } ethtool_test_keys[] = {
406  { "nvram test (online) " },
407  { "link test (online) " },
408  { "register test (offline)" },
409  { "memory test (offline)" },
410  { "mac loopback test (offline)" },
411  { "phy loopback test (offline)" },
412  { "ext loopback test (offline)" },
413  { "interrupt test (offline)" },
414 };
415 
416 #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
417 
418 
419 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
420 {
421  writel(val, tp->regs + off);
422 }
423 
424 static u32 tg3_read32(struct tg3 *tp, u32 off)
425 {
426  return readl(tp->regs + off);
427 }
428 
429 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
430 {
431  writel(val, tp->aperegs + off);
432 }
433 
434 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
435 {
436  return readl(tp->aperegs + off);
437 }
438 
439 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
440 {
441  unsigned long flags;
442 
443  spin_lock_irqsave(&tp->indirect_lock, flags);
444  pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
445  pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
446  spin_unlock_irqrestore(&tp->indirect_lock, flags);
447 }
448 
449 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
450 {
451  writel(val, tp->regs + off);
452  readl(tp->regs + off);
453 }
454 
455 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
456 {
457  unsigned long flags;
458  u32 val;
459 
460  spin_lock_irqsave(&tp->indirect_lock, flags);
461  pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
462  pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
463  spin_unlock_irqrestore(&tp->indirect_lock, flags);
464  return val;
465 }
466 
467 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
468 {
469  unsigned long flags;
470 
472  pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
473  TG3_64BIT_REG_LOW, val);
474  return;
475  }
476  if (off == TG3_RX_STD_PROD_IDX_REG) {
477  pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
478  TG3_64BIT_REG_LOW, val);
479  return;
480  }
481 
482  spin_lock_irqsave(&tp->indirect_lock, flags);
483  pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
484  pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
485  spin_unlock_irqrestore(&tp->indirect_lock, flags);
486 
487  /* In indirect mode when disabling interrupts, we also need
488  * to clear the interrupt bit in the GRC local ctrl register.
489  */
490  if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
491  (val == 0x1)) {
492  pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
494  }
495 }
496 
497 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
498 {
499  unsigned long flags;
500  u32 val;
501 
502  spin_lock_irqsave(&tp->indirect_lock, flags);
503  pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
504  pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
505  spin_unlock_irqrestore(&tp->indirect_lock, flags);
506  return val;
507 }
508 
509 /* usec_wait specifies the wait time in usec when writing to certain registers
510  * where it is unsafe to read back the register without some delay.
511  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
512  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
513  */
514 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
515 {
516  if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
517  /* Non-posted methods */
518  tp->write32(tp, off, val);
519  else {
520  /* Posted method */
521  tg3_write32(tp, off, val);
522  if (usec_wait)
523  udelay(usec_wait);
524  tp->read32(tp, off);
525  }
526  /* Wait again after the read for the posted method to guarantee that
527  * the wait time is met.
528  */
529  if (usec_wait)
530  udelay(usec_wait);
531 }
532 
533 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
534 {
535  tp->write32_mbox(tp, off, val);
536  if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
537  tp->read32_mbox(tp, off);
538 }
539 
540 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
541 {
542  void __iomem *mbox = tp->regs + off;
543  writel(val, mbox);
544  if (tg3_flag(tp, TXD_MBOX_HWBUG))
545  writel(val, mbox);
546  if (tg3_flag(tp, MBOX_WRITE_REORDER))
547  readl(mbox);
548 }
549 
550 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
551 {
552  return readl(tp->regs + off + GRCMBOX_BASE);
553 }
554 
555 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
556 {
557  writel(val, tp->regs + off + GRCMBOX_BASE);
558 }
559 
560 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
561 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
562 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
563 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
564 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
565 
566 #define tw32(reg, val) tp->write32(tp, reg, val)
567 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
568 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
569 #define tr32(reg) tp->read32(tp, reg)
570 
571 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
572 {
573  unsigned long flags;
574 
576  (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
577  return;
578 
579  spin_lock_irqsave(&tp->indirect_lock, flags);
580  if (tg3_flag(tp, SRAM_USE_CONFIG)) {
581  pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
582  pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
583 
584  /* Always leave this as zero. */
585  pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
586  } else {
589 
590  /* Always leave this as zero. */
592  }
593  spin_unlock_irqrestore(&tp->indirect_lock, flags);
594 }
595 
596 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
597 {
598  unsigned long flags;
599 
601  (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
602  *val = 0;
603  return;
604  }
605 
606  spin_lock_irqsave(&tp->indirect_lock, flags);
607  if (tg3_flag(tp, SRAM_USE_CONFIG)) {
608  pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
609  pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
610 
611  /* Always leave this as zero. */
612  pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
613  } else {
615  *val = tr32(TG3PCI_MEM_WIN_DATA);
616 
617  /* Always leave this as zero. */
619  }
620  spin_unlock_irqrestore(&tp->indirect_lock, flags);
621 }
622 
623 static void tg3_ape_lock_init(struct tg3 *tp)
624 {
625  int i;
626  u32 regbase, bit;
627 
629  regbase = TG3_APE_LOCK_GRANT;
630  else
631  regbase = TG3_APE_PER_LOCK_GRANT;
632 
633  /* Make sure the driver hasn't any stale locks. */
634  for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
635  switch (i) {
636  case TG3_APE_LOCK_PHY0:
637  case TG3_APE_LOCK_PHY1:
638  case TG3_APE_LOCK_PHY2:
639  case TG3_APE_LOCK_PHY3:
640  bit = APE_LOCK_GRANT_DRIVER;
641  break;
642  default:
643  if (!tp->pci_fn)
644  bit = APE_LOCK_GRANT_DRIVER;
645  else
646  bit = 1 << tp->pci_fn;
647  }
648  tg3_ape_write32(tp, regbase + 4 * i, bit);
649  }
650 
651 }
652 
653 static int tg3_ape_lock(struct tg3 *tp, int locknum)
654 {
655  int i, off;
656  int ret = 0;
657  u32 status, req, gnt, bit;
658 
659  if (!tg3_flag(tp, ENABLE_APE))
660  return 0;
661 
662  switch (locknum) {
663  case TG3_APE_LOCK_GPIO:
665  return 0;
666  case TG3_APE_LOCK_GRC:
667  case TG3_APE_LOCK_MEM:
668  if (!tp->pci_fn)
669  bit = APE_LOCK_REQ_DRIVER;
670  else
671  bit = 1 << tp->pci_fn;
672  break;
673  case TG3_APE_LOCK_PHY0:
674  case TG3_APE_LOCK_PHY1:
675  case TG3_APE_LOCK_PHY2:
676  case TG3_APE_LOCK_PHY3:
677  bit = APE_LOCK_REQ_DRIVER;
678  break;
679  default:
680  return -EINVAL;
681  }
682 
684  req = TG3_APE_LOCK_REQ;
685  gnt = TG3_APE_LOCK_GRANT;
686  } else {
687  req = TG3_APE_PER_LOCK_REQ;
689  }
690 
691  off = 4 * locknum;
692 
693  tg3_ape_write32(tp, req + off, bit);
694 
695  /* Wait for up to 1 millisecond to acquire lock. */
696  for (i = 0; i < 100; i++) {
697  status = tg3_ape_read32(tp, gnt + off);
698  if (status == bit)
699  break;
700  udelay(10);
701  }
702 
703  if (status != bit) {
704  /* Revoke the lock request. */
705  tg3_ape_write32(tp, gnt + off, bit);
706  ret = -EBUSY;
707  }
708 
709  return ret;
710 }
711 
712 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
713 {
714  u32 gnt, bit;
715 
716  if (!tg3_flag(tp, ENABLE_APE))
717  return;
718 
719  switch (locknum) {
720  case TG3_APE_LOCK_GPIO:
722  return;
723  case TG3_APE_LOCK_GRC:
724  case TG3_APE_LOCK_MEM:
725  if (!tp->pci_fn)
726  bit = APE_LOCK_GRANT_DRIVER;
727  else
728  bit = 1 << tp->pci_fn;
729  break;
730  case TG3_APE_LOCK_PHY0:
731  case TG3_APE_LOCK_PHY1:
732  case TG3_APE_LOCK_PHY2:
733  case TG3_APE_LOCK_PHY3:
734  bit = APE_LOCK_GRANT_DRIVER;
735  break;
736  default:
737  return;
738  }
739 
741  gnt = TG3_APE_LOCK_GRANT;
742  else
744 
745  tg3_ape_write32(tp, gnt + 4 * locknum, bit);
746 }
747 
748 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
749 {
750  u32 apedata;
751 
752  while (timeout_us) {
753  if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
754  return -EBUSY;
755 
756  apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
757  if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
758  break;
759 
760  tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
761 
762  udelay(10);
763  timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
764  }
765 
766  return timeout_us ? 0 : -EBUSY;
767 }
768 
769 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
770 {
771  u32 i, apedata;
772 
773  for (i = 0; i < timeout_us / 10; i++) {
774  apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
775 
776  if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
777  break;
778 
779  udelay(10);
780  }
781 
782  return i == timeout_us / 10;
783 }
784 
785 static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
786  u32 len)
787 {
788  int err;
789  u32 i, bufoff, msgoff, maxlen, apedata;
790 
791  if (!tg3_flag(tp, APE_HAS_NCSI))
792  return 0;
793 
794  apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
795  if (apedata != APE_SEG_SIG_MAGIC)
796  return -ENODEV;
797 
798  apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
799  if (!(apedata & APE_FW_STATUS_READY))
800  return -EAGAIN;
801 
802  bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
804  msgoff = bufoff + 2 * sizeof(u32);
805  maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
806 
807  while (len) {
808  u32 length;
809 
810  /* Cap xfer sizes to scratchpad limits. */
811  length = (len > maxlen) ? maxlen : len;
812  len -= length;
813 
814  apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
815  if (!(apedata & APE_FW_STATUS_READY))
816  return -EAGAIN;
817 
818  /* Wait for up to 1 msec for APE to service previous event. */
819  err = tg3_ape_event_lock(tp, 1000);
820  if (err)
821  return err;
822 
823  apedata = APE_EVENT_STATUS_DRIVER_EVNT |
826  tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
827 
828  tg3_ape_write32(tp, bufoff, base_off);
829  tg3_ape_write32(tp, bufoff + sizeof(u32), length);
830 
831  tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
832  tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
833 
834  base_off += length;
835 
836  if (tg3_ape_wait_for_event(tp, 30000))
837  return -EAGAIN;
838 
839  for (i = 0; length; i += 4, length -= 4) {
840  u32 val = tg3_ape_read32(tp, msgoff + i);
841  memcpy(data, &val, sizeof(u32));
842  data++;
843  }
844  }
845 
846  return 0;
847 }
848 
849 static int tg3_ape_send_event(struct tg3 *tp, u32 event)
850 {
851  int err;
852  u32 apedata;
853 
854  apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
855  if (apedata != APE_SEG_SIG_MAGIC)
856  return -EAGAIN;
857 
858  apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
859  if (!(apedata & APE_FW_STATUS_READY))
860  return -EAGAIN;
861 
862  /* Wait for up to 1 millisecond for APE to service previous event. */
863  err = tg3_ape_event_lock(tp, 1000);
864  if (err)
865  return err;
866 
867  tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
869 
870  tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
871  tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
872 
873  return 0;
874 }
875 
876 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
877 {
878  u32 event;
879  u32 apedata;
880 
881  if (!tg3_flag(tp, ENABLE_APE))
882  return;
883 
884  switch (kind) {
885  case RESET_KIND_INIT:
886  tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
888  tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
890  apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
891  tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
892  tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
894  tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
896  tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
898 
900  break;
901  case RESET_KIND_SHUTDOWN:
902  /* With the interface we are currently using,
903  * APE does not track driver state. Wiping
904  * out the HOST SEGMENT SIGNATURE forces
905  * the APE to assume OS absent status.
906  */
907  tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
908 
909  if (device_may_wakeup(&tp->pdev->dev) &&
910  tg3_flag(tp, WOL_ENABLE)) {
911  tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
913  apedata = TG3_APE_HOST_DRVR_STATE_WOL;
914  } else
916 
917  tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
918 
920  break;
921  case RESET_KIND_SUSPEND:
923  break;
924  default:
925  return;
926  }
927 
929 
930  tg3_ape_send_event(tp, event);
931 }
932 
933 static void tg3_disable_ints(struct tg3 *tp)
934 {
935  int i;
936 
939  for (i = 0; i < tp->irq_max; i++)
940  tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
941 }
942 
943 static void tg3_enable_ints(struct tg3 *tp)
944 {
945  int i;
946 
947  tp->irq_sync = 0;
948  wmb();
949 
952 
954  for (i = 0; i < tp->irq_cnt; i++) {
955  struct tg3_napi *tnapi = &tp->napi[i];
956 
957  tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
958  if (tg3_flag(tp, 1SHOT_MSI))
959  tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
960 
961  tp->coal_now |= tnapi->coal_now;
962  }
963 
964  /* Force an initial interrupt */
965  if (!tg3_flag(tp, TAGGED_STATUS) &&
966  (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
968  else
969  tw32(HOSTCC_MODE, tp->coal_now);
970 
971  tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
972 }
973 
974 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
975 {
976  struct tg3 *tp = tnapi->tp;
977  struct tg3_hw_status *sblk = tnapi->hw_status;
978  unsigned int work_exists = 0;
979 
980  /* check for phy events */
981  if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
982  if (sblk->status & SD_STATUS_LINK_CHG)
983  work_exists = 1;
984  }
985 
986  /* check for TX work to do */
987  if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
988  work_exists = 1;
989 
990  /* check for RX work to do */
991  if (tnapi->rx_rcb_prod_idx &&
992  *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
993  work_exists = 1;
994 
995  return work_exists;
996 }
997 
998 /* tg3_int_reenable
999  * similar to tg3_enable_ints, but it accurately determines whether there
1000  * is new work pending and can return without flushing the PIO write
1001  * which reenables interrupts
1002  */
1003 static void tg3_int_reenable(struct tg3_napi *tnapi)
1004 {
1005  struct tg3 *tp = tnapi->tp;
1006 
1007  tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1008  mmiowb();
1009 
1010  /* When doing tagged status, this work check is unnecessary.
1011  * The last_tag we write above tells the chip which piece of
1012  * work we've completed.
1013  */
1014  if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
1016  HOSTCC_MODE_ENABLE | tnapi->coal_now);
1017 }
1018 
1019 static void tg3_switch_clocks(struct tg3 *tp)
1020 {
1021  u32 clock_ctrl;
1022  u32 orig_clock_ctrl;
1023 
1024  if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
1025  return;
1026 
1027  clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1028 
1029  orig_clock_ctrl = clock_ctrl;
1030  clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1032  0x1f);
1033  tp->pci_clock_ctrl = clock_ctrl;
1034 
1035  if (tg3_flag(tp, 5705_PLUS)) {
1036  if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
1038  clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1039  }
1040  } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
1042  clock_ctrl |
1043  (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1044  40);
1046  clock_ctrl | (CLOCK_CTRL_ALTCLK),
1047  40);
1048  }
1049  tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1050 }
1051 
1052 #define PHY_BUSY_LOOPS 5000
1053 
1054 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1055 {
1056  u32 frame_val;
1057  unsigned int loops;
1058  int ret;
1059 
1060  if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1062  (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1063  udelay(80);
1064  }
1065 
1066  tg3_ape_lock(tp, tp->phy_ape_lock);
1067 
1068  *val = 0x0;
1069 
1070  frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1072  frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1074  frame_val |= (MI_COM_CMD_READ | MI_COM_START);
1075 
1076  tw32_f(MAC_MI_COM, frame_val);
1077 
1078  loops = PHY_BUSY_LOOPS;
1079  while (loops != 0) {
1080  udelay(10);
1081  frame_val = tr32(MAC_MI_COM);
1082 
1083  if ((frame_val & MI_COM_BUSY) == 0) {
1084  udelay(5);
1085  frame_val = tr32(MAC_MI_COM);
1086  break;
1087  }
1088  loops -= 1;
1089  }
1090 
1091  ret = -EBUSY;
1092  if (loops != 0) {
1093  *val = frame_val & MI_COM_DATA_MASK;
1094  ret = 0;
1095  }
1096 
1097  if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1098  tw32_f(MAC_MI_MODE, tp->mi_mode);
1099  udelay(80);
1100  }
1101 
1102  tg3_ape_unlock(tp, tp->phy_ape_lock);
1103 
1104  return ret;
1105 }
1106 
1107 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1108 {
1109  u32 frame_val;
1110  unsigned int loops;
1111  int ret;
1112 
1113  if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1114  (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1115  return 0;
1116 
1117  if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1119  (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1120  udelay(80);
1121  }
1122 
1123  tg3_ape_lock(tp, tp->phy_ape_lock);
1124 
1125  frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1127  frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1129  frame_val |= (val & MI_COM_DATA_MASK);
1130  frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1131 
1132  tw32_f(MAC_MI_COM, frame_val);
1133 
1134  loops = PHY_BUSY_LOOPS;
1135  while (loops != 0) {
1136  udelay(10);
1137  frame_val = tr32(MAC_MI_COM);
1138  if ((frame_val & MI_COM_BUSY) == 0) {
1139  udelay(5);
1140  frame_val = tr32(MAC_MI_COM);
1141  break;
1142  }
1143  loops -= 1;
1144  }
1145 
1146  ret = -EBUSY;
1147  if (loops != 0)
1148  ret = 0;
1149 
1150  if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1151  tw32_f(MAC_MI_MODE, tp->mi_mode);
1152  udelay(80);
1153  }
1154 
1155  tg3_ape_unlock(tp, tp->phy_ape_lock);
1156 
1157  return ret;
1158 }
1159 
1160 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1161 {
1162  int err;
1163 
1164  err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1165  if (err)
1166  goto done;
1167 
1168  err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1169  if (err)
1170  goto done;
1171 
1172  err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1173  MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1174  if (err)
1175  goto done;
1176 
1177  err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1178 
1179 done:
1180  return err;
1181 }
1182 
1183 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1184 {
1185  int err;
1186 
1187  err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1188  if (err)
1189  goto done;
1190 
1191  err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1192  if (err)
1193  goto done;
1194 
1195  err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1196  MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1197  if (err)
1198  goto done;
1199 
1200  err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1201 
1202 done:
1203  return err;
1204 }
1205 
1206 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1207 {
1208  int err;
1209 
1210  err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1211  if (!err)
1212  err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1213 
1214  return err;
1215 }
1216 
1217 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1218 {
1219  int err;
1220 
1221  err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1222  if (!err)
1223  err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1224 
1225  return err;
1226 }
1227 
1228 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1229 {
1230  int err;
1231 
1232  err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1235  if (!err)
1236  err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1237 
1238  return err;
1239 }
1240 
1241 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1242 {
1243  if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1244  set |= MII_TG3_AUXCTL_MISC_WREN;
1245 
1246  return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1247 }
1248 
1249 #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \
1250  tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1251  MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \
1252  MII_TG3_AUXCTL_ACTL_TX_6DB)
1253 
1254 #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \
1255  tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
1256  MII_TG3_AUXCTL_ACTL_TX_6DB);
1257 
1258 static int tg3_bmcr_reset(struct tg3 *tp)
1259 {
1260  u32 phy_control;
1261  int limit, err;
1262 
1263  /* OK, reset it, and poll the BMCR_RESET bit until it
1264  * clears or we time out.
1265  */
1266  phy_control = BMCR_RESET;
1267  err = tg3_writephy(tp, MII_BMCR, phy_control);
1268  if (err != 0)
1269  return -EBUSY;
1270 
1271  limit = 5000;
1272  while (limit--) {
1273  err = tg3_readphy(tp, MII_BMCR, &phy_control);
1274  if (err != 0)
1275  return -EBUSY;
1276 
1277  if ((phy_control & BMCR_RESET) == 0) {
1278  udelay(40);
1279  break;
1280  }
1281  udelay(10);
1282  }
1283  if (limit < 0)
1284  return -EBUSY;
1285 
1286  return 0;
1287 }
1288 
1289 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1290 {
1291  struct tg3 *tp = bp->priv;
1292  u32 val;
1293 
1294  spin_lock_bh(&tp->lock);
1295 
1296  if (tg3_readphy(tp, reg, &val))
1297  val = -EIO;
1298 
1299  spin_unlock_bh(&tp->lock);
1300 
1301  return val;
1302 }
1303 
1304 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1305 {
1306  struct tg3 *tp = bp->priv;
1307  u32 ret = 0;
1308 
1309  spin_lock_bh(&tp->lock);
1310 
1311  if (tg3_writephy(tp, reg, val))
1312  ret = -EIO;
1313 
1314  spin_unlock_bh(&tp->lock);
1315 
1316  return ret;
1317 }
1318 
1319 static int tg3_mdio_reset(struct mii_bus *bp)
1320 {
1321  return 0;
1322 }
1323 
1324 static void tg3_mdio_config_5785(struct tg3 *tp)
1325 {
1326  u32 val;
1327  struct phy_device *phydev;
1328 
1329  phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1330  switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1331  case PHY_ID_BCM50610:
1332  case PHY_ID_BCM50610M:
1334  break;
1335  case PHY_ID_BCMAC131:
1337  break;
1338  case PHY_ID_RTL8211C:
1340  break;
1341  case PHY_ID_RTL8201E:
1343  break;
1344  default:
1345  return;
1346  }
1347 
1348  if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1349  tw32(MAC_PHYCFG2, val);
1350 
1351  val = tr32(MAC_PHYCFG1);
1352  val &= ~(MAC_PHYCFG1_RGMII_INT |
1355  tw32(MAC_PHYCFG1, val);
1356 
1357  return;
1358  }
1359 
1360  if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1367 
1368  tw32(MAC_PHYCFG2, val);
1369 
1370  val = tr32(MAC_PHYCFG1);
1373  if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1374  if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1376  if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1378  }
1381  tw32(MAC_PHYCFG1, val);
1382 
1383  val = tr32(MAC_EXT_RGMII_MODE);
1384  val &= ~(MAC_RGMII_MODE_RX_INT_B |
1391  if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1392  if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1393  val |= MAC_RGMII_MODE_RX_INT_B |
1397  if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1398  val |= MAC_RGMII_MODE_TX_ENABLE |
1401  }
1402  tw32(MAC_EXT_RGMII_MODE, val);
1403 }
1404 
1405 static void tg3_mdio_start(struct tg3 *tp)
1406 {
1408  tw32_f(MAC_MI_MODE, tp->mi_mode);
1409  udelay(80);
1410 
1411  if (tg3_flag(tp, MDIOBUS_INITED) &&
1413  tg3_mdio_config_5785(tp);
1414 }
1415 
1416 static int tg3_mdio_init(struct tg3 *tp)
1417 {
1418  int i;
1419  u32 reg;
1420  struct phy_device *phydev;
1421 
1422  if (tg3_flag(tp, 5717_PLUS)) {
1423  u32 is_serdes;
1424 
1425  tp->phy_addr = tp->pci_fn + 1;
1426 
1428  is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1429  else
1430  is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1432  if (is_serdes)
1433  tp->phy_addr += 7;
1434  } else
1435  tp->phy_addr = TG3_PHY_MII_ADDR;
1436 
1437  tg3_mdio_start(tp);
1438 
1439  if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1440  return 0;
1441 
1442  tp->mdio_bus = mdiobus_alloc();
1443  if (tp->mdio_bus == NULL)
1444  return -ENOMEM;
1445 
1446  tp->mdio_bus->name = "tg3 mdio bus";
1447  snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1448  (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1449  tp->mdio_bus->priv = tp;
1450  tp->mdio_bus->parent = &tp->pdev->dev;
1451  tp->mdio_bus->read = &tg3_mdio_read;
1452  tp->mdio_bus->write = &tg3_mdio_write;
1453  tp->mdio_bus->reset = &tg3_mdio_reset;
1454  tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1455  tp->mdio_bus->irq = &tp->mdio_irq[0];
1456 
1457  for (i = 0; i < PHY_MAX_ADDR; i++)
1458  tp->mdio_bus->irq[i] = PHY_POLL;
1459 
1460  /* The bus registration will look for all the PHYs on the mdio bus.
1461  * Unfortunately, it does not ensure the PHY is powered up before
1462  * accessing the PHY ID registers. A chip reset is the
1463  * quickest way to bring the device back to an operational state..
1464  */
1465  if (tg3_readphy(tp, MII_BMCR, &reg) || (reg & BMCR_PDOWN))
1466  tg3_bmcr_reset(tp);
1467 
1468  i = mdiobus_register(tp->mdio_bus);
1469  if (i) {
1470  dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1471  mdiobus_free(tp->mdio_bus);
1472  return i;
1473  }
1474 
1475  phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1476 
1477  if (!phydev || !phydev->drv) {
1478  dev_warn(&tp->pdev->dev, "No PHY devices\n");
1480  mdiobus_free(tp->mdio_bus);
1481  return -ENODEV;
1482  }
1483 
1484  switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1485  case PHY_ID_BCM57780:
1488  break;
1489  case PHY_ID_BCM50610:
1490  case PHY_ID_BCM50610M:
1495  if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1497  if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1499  if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1501  /* fallthru */
1502  case PHY_ID_RTL8211C:
1504  break;
1505  case PHY_ID_RTL8201E:
1506  case PHY_ID_BCMAC131:
1510  break;
1511  }
1512 
1513  tg3_flag_set(tp, MDIOBUS_INITED);
1514 
1516  tg3_mdio_config_5785(tp);
1517 
1518  return 0;
1519 }
1520 
1521 static void tg3_mdio_fini(struct tg3 *tp)
1522 {
1523  if (tg3_flag(tp, MDIOBUS_INITED)) {
1524  tg3_flag_clear(tp, MDIOBUS_INITED);
1526  mdiobus_free(tp->mdio_bus);
1527  }
1528 }
1529 
1530 /* tp->lock is held. */
1531 static inline void tg3_generate_fw_event(struct tg3 *tp)
1532 {
1533  u32 val;
1534 
1535  val = tr32(GRC_RX_CPU_EVENT);
1536  val |= GRC_RX_CPU_DRIVER_EVENT;
1537  tw32_f(GRC_RX_CPU_EVENT, val);
1538 
1540 }
1541 
1542 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1543 
1544 /* tp->lock is held. */
1545 static void tg3_wait_for_event_ack(struct tg3 *tp)
1546 {
1547  int i;
1548  unsigned int delay_cnt;
1549  long time_remain;
1550 
1551  /* If enough time has passed, no wait is necessary. */
1552  time_remain = (long)(tp->last_event_jiffies + 1 +
1554  (long)jiffies;
1555  if (time_remain < 0)
1556  return;
1557 
1558  /* Check if we can shorten the wait time. */
1559  delay_cnt = jiffies_to_usecs(time_remain);
1560  if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1561  delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1562  delay_cnt = (delay_cnt >> 3) + 1;
1563 
1564  for (i = 0; i < delay_cnt; i++) {
1566  break;
1567  udelay(8);
1568  }
1569 }
1570 
1571 /* tp->lock is held. */
1572 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
1573 {
1574  u32 reg, val;
1575 
1576  val = 0;
1577  if (!tg3_readphy(tp, MII_BMCR, &reg))
1578  val = reg << 16;
1579  if (!tg3_readphy(tp, MII_BMSR, &reg))
1580  val |= (reg & 0xffff);
1581  *data++ = val;
1582 
1583  val = 0;
1584  if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1585  val = reg << 16;
1586  if (!tg3_readphy(tp, MII_LPA, &reg))
1587  val |= (reg & 0xffff);
1588  *data++ = val;
1589 
1590  val = 0;
1591  if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1592  if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1593  val = reg << 16;
1594  if (!tg3_readphy(tp, MII_STAT1000, &reg))
1595  val |= (reg & 0xffff);
1596  }
1597  *data++ = val;
1598 
1599  if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1600  val = reg << 16;
1601  else
1602  val = 0;
1603  *data++ = val;
1604 }
1605 
1606 /* tp->lock is held. */
1607 static void tg3_ump_link_report(struct tg3 *tp)
1608 {
1609  u32 data[4];
1610 
1611  if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1612  return;
1613 
1614  tg3_phy_gather_ump_data(tp, data);
1615 
1616  tg3_wait_for_event_ack(tp);
1617 
1618  tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1619  tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1620  tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1621  tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1622  tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1623  tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
1624 
1625  tg3_generate_fw_event(tp);
1626 }
1627 
1628 /* tp->lock is held. */
1629 static void tg3_stop_fw(struct tg3 *tp)
1630 {
1631  if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1632  /* Wait for RX cpu to ACK the previous event. */
1633  tg3_wait_for_event_ack(tp);
1634 
1635  tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1636 
1637  tg3_generate_fw_event(tp);
1638 
1639  /* Wait for RX cpu to ACK this event. */
1640  tg3_wait_for_event_ack(tp);
1641  }
1642 }
1643 
1644 /* tp->lock is held. */
1645 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1646 {
1647  tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1649 
1650  if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1651  switch (kind) {
1652  case RESET_KIND_INIT:
1653  tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1654  DRV_STATE_START);
1655  break;
1656 
1657  case RESET_KIND_SHUTDOWN:
1658  tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1660  break;
1661 
1662  case RESET_KIND_SUSPEND:
1663  tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1665  break;
1666 
1667  default:
1668  break;
1669  }
1670  }
1671 
1672  if (kind == RESET_KIND_INIT ||
1673  kind == RESET_KIND_SUSPEND)
1674  tg3_ape_driver_state_change(tp, kind);
1675 }
1676 
1677 /* tp->lock is held. */
1678 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1679 {
1680  if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1681  switch (kind) {
1682  case RESET_KIND_INIT:
1683  tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1685  break;
1686 
1687  case RESET_KIND_SHUTDOWN:
1688  tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1690  break;
1691 
1692  default:
1693  break;
1694  }
1695  }
1696 
1697  if (kind == RESET_KIND_SHUTDOWN)
1698  tg3_ape_driver_state_change(tp, kind);
1699 }
1700 
1701 /* tp->lock is held. */
1702 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1703 {
1704  if (tg3_flag(tp, ENABLE_ASF)) {
1705  switch (kind) {
1706  case RESET_KIND_INIT:
1707  tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1708  DRV_STATE_START);
1709  break;
1710 
1711  case RESET_KIND_SHUTDOWN:
1712  tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1714  break;
1715 
1716  case RESET_KIND_SUSPEND:
1717  tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1719  break;
1720 
1721  default:
1722  break;
1723  }
1724  }
1725 }
1726 
1727 static int tg3_poll_fw(struct tg3 *tp)
1728 {
1729  int i;
1730  u32 val;
1731 
1733  /* Wait up to 20ms for init done. */
1734  for (i = 0; i < 200; i++) {
1736  return 0;
1737  udelay(100);
1738  }
1739  return -ENODEV;
1740  }
1741 
1742  /* Wait for firmware initialization to complete. */
1743  for (i = 0; i < 100000; i++) {
1744  tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1745  if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1746  break;
1747  udelay(10);
1748  }
1749 
1750  /* Chip might not be fitted with firmware. Some Sun onboard
1751  * parts are configured like that. So don't signal the timeout
1752  * of the above loop as an error, but do report the lack of
1753  * running firmware once.
1754  */
1755  if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1756  tg3_flag_set(tp, NO_FWARE_REPORTED);
1757 
1758  netdev_info(tp->dev, "No firmware running\n");
1759  }
1760 
1761  if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) {
1762  /* The 57765 A0 needs a little more
1763  * time to do some important work.
1764  */
1765  mdelay(10);
1766  }
1767 
1768  return 0;
1769 }
1770 
1771 static void tg3_link_report(struct tg3 *tp)
1772 {
1773  if (!netif_carrier_ok(tp->dev)) {
1774  netif_info(tp, link, tp->dev, "Link is down\n");
1775  tg3_ump_link_report(tp);
1776  } else if (netif_msg_link(tp)) {
1777  netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1778  (tp->link_config.active_speed == SPEED_1000 ?
1779  1000 :
1780  (tp->link_config.active_speed == SPEED_100 ?
1781  100 : 10)),
1782  (tp->link_config.active_duplex == DUPLEX_FULL ?
1783  "full" : "half"));
1784 
1785  netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1786  (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1787  "on" : "off",
1788  (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1789  "on" : "off");
1790 
1791  if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1792  netdev_info(tp->dev, "EEE is %s\n",
1793  tp->setlpicnt ? "enabled" : "disabled");
1794 
1795  tg3_ump_link_report(tp);
1796  }
1797 }
1798 
1799 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1800 {
1801  u16 miireg;
1802 
1803  if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1804  miireg = ADVERTISE_1000XPAUSE;
1805  else if (flow_ctrl & FLOW_CTRL_TX)
1806  miireg = ADVERTISE_1000XPSE_ASYM;
1807  else if (flow_ctrl & FLOW_CTRL_RX)
1809  else
1810  miireg = 0;
1811 
1812  return miireg;
1813 }
1814 
1815 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1816 {
1817  u8 cap = 0;
1818 
1819  if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1820  cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1821  } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1822  if (lcladv & ADVERTISE_1000XPAUSE)
1823  cap = FLOW_CTRL_RX;
1824  if (rmtadv & ADVERTISE_1000XPAUSE)
1825  cap = FLOW_CTRL_TX;
1826  }
1827 
1828  return cap;
1829 }
1830 
1831 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1832 {
1833  u8 autoneg;
1834  u8 flowctrl = 0;
1835  u32 old_rx_mode = tp->rx_mode;
1836  u32 old_tx_mode = tp->tx_mode;
1837 
1838  if (tg3_flag(tp, USE_PHYLIB))
1839  autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1840  else
1841  autoneg = tp->link_config.autoneg;
1842 
1843  if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1844  if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1845  flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1846  else
1847  flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1848  } else
1849  flowctrl = tp->link_config.flowctrl;
1850 
1851  tp->link_config.active_flowctrl = flowctrl;
1852 
1853  if (flowctrl & FLOW_CTRL_RX)
1855  else
1857 
1858  if (old_rx_mode != tp->rx_mode)
1859  tw32_f(MAC_RX_MODE, tp->rx_mode);
1860 
1861  if (flowctrl & FLOW_CTRL_TX)
1863  else
1865 
1866  if (old_tx_mode != tp->tx_mode)
1867  tw32_f(MAC_TX_MODE, tp->tx_mode);
1868 }
1869 
1870 static void tg3_adjust_link(struct net_device *dev)
1871 {
1872  u8 oldflowctrl, linkmesg = 0;
1873  u32 mac_mode, lcl_adv, rmt_adv;
1874  struct tg3 *tp = netdev_priv(dev);
1875  struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1876 
1877  spin_lock_bh(&tp->lock);
1878 
1879  mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1881 
1882  oldflowctrl = tp->link_config.active_flowctrl;
1883 
1884  if (phydev->link) {
1885  lcl_adv = 0;
1886  rmt_adv = 0;
1887 
1888  if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1889  mac_mode |= MAC_MODE_PORT_MODE_MII;
1890  else if (phydev->speed == SPEED_1000 ||
1892  mac_mode |= MAC_MODE_PORT_MODE_GMII;
1893  else
1894  mac_mode |= MAC_MODE_PORT_MODE_MII;
1895 
1896  if (phydev->duplex == DUPLEX_HALF)
1897  mac_mode |= MAC_MODE_HALF_DUPLEX;
1898  else {
1899  lcl_adv = mii_advertise_flowctrl(
1900  tp->link_config.flowctrl);
1901 
1902  if (phydev->pause)
1903  rmt_adv = LPA_PAUSE_CAP;
1904  if (phydev->asym_pause)
1905  rmt_adv |= LPA_PAUSE_ASYM;
1906  }
1907 
1908  tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1909  } else
1910  mac_mode |= MAC_MODE_PORT_MODE_GMII;
1911 
1912  if (mac_mode != tp->mac_mode) {
1913  tp->mac_mode = mac_mode;
1914  tw32_f(MAC_MODE, tp->mac_mode);
1915  udelay(40);
1916  }
1917 
1919  if (phydev->speed == SPEED_10)
1920  tw32(MAC_MI_STAT,
1923  else
1925  }
1926 
1927  if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1929  ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1930  (6 << TX_LENGTHS_IPG_SHIFT) |
1931  (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1932  else
1934  ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1935  (6 << TX_LENGTHS_IPG_SHIFT) |
1936  (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1937 
1938  if (phydev->link != tp->old_link ||
1939  phydev->speed != tp->link_config.active_speed ||
1940  phydev->duplex != tp->link_config.active_duplex ||
1941  oldflowctrl != tp->link_config.active_flowctrl)
1942  linkmesg = 1;
1943 
1944  tp->old_link = phydev->link;
1945  tp->link_config.active_speed = phydev->speed;
1946  tp->link_config.active_duplex = phydev->duplex;
1947 
1948  spin_unlock_bh(&tp->lock);
1949 
1950  if (linkmesg)
1951  tg3_link_report(tp);
1952 }
1953 
1954 static int tg3_phy_init(struct tg3 *tp)
1955 {
1956  struct phy_device *phydev;
1957 
1959  return 0;
1960 
1961  /* Bring the PHY back to a known state. */
1962  tg3_bmcr_reset(tp);
1963 
1964  phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1965 
1966  /* Attach the MAC to the PHY. */
1967  phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1968  phydev->dev_flags, phydev->interface);
1969  if (IS_ERR(phydev)) {
1970  dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
1971  return PTR_ERR(phydev);
1972  }
1973 
1974  /* Mask with MAC supported features. */
1975  switch (phydev->interface) {
1978  if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
1979  phydev->supported &= (PHY_GBIT_FEATURES |
1980  SUPPORTED_Pause |
1982  break;
1983  }
1984  /* fallthru */
1986  phydev->supported &= (PHY_BASIC_FEATURES |
1987  SUPPORTED_Pause |
1989  break;
1990  default:
1991  phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1992  return -EINVAL;
1993  }
1994 
1996 
1997  phydev->advertising = phydev->supported;
1998 
1999  return 0;
2000 }
2001 
2002 static void tg3_phy_start(struct tg3 *tp)
2003 {
2004  struct phy_device *phydev;
2005 
2006  if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2007  return;
2008 
2009  phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2010 
2011  if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2013  phydev->speed = tp->link_config.speed;
2014  phydev->duplex = tp->link_config.duplex;
2015  phydev->autoneg = tp->link_config.autoneg;
2016  phydev->advertising = tp->link_config.advertising;
2017  }
2018 
2019  phy_start(phydev);
2020 
2021  phy_start_aneg(phydev);
2022 }
2023 
2024 static void tg3_phy_stop(struct tg3 *tp)
2025 {
2026  if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2027  return;
2028 
2029  phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
2030 }
2031 
2032 static void tg3_phy_fini(struct tg3 *tp)
2033 {
2034  if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2035  phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
2037  }
2038 }
2039 
2040 static int tg3_phy_set_extloopbk(struct tg3 *tp)
2041 {
2042  int err;
2043  u32 val;
2044 
2045  if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2046  return 0;
2047 
2048  if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2049  /* Cannot do read-modify-write on 5401 */
2050  err = tg3_phy_auxctl_write(tp,
2053  0x4c20);
2054  goto done;
2055  }
2056 
2057  err = tg3_phy_auxctl_read(tp,
2059  if (err)
2060  return err;
2061 
2063  err = tg3_phy_auxctl_write(tp,
2065 
2066 done:
2067  return err;
2068 }
2069 
2070 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2071 {
2072  u32 phytest;
2073 
2074  if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2075  u32 phy;
2076 
2077  tg3_writephy(tp, MII_TG3_FET_TEST,
2078  phytest | MII_TG3_FET_SHADOW_EN);
2079  if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2080  if (enable)
2082  else
2084  tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2085  }
2086  tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2087  }
2088 }
2089 
2090 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2091 {
2092  u32 reg;
2093 
2094  if (!tg3_flag(tp, 5705_PLUS) ||
2095  (tg3_flag(tp, 5717_PLUS) &&
2097  return;
2098 
2099  if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2100  tg3_phy_fet_toggle_apd(tp, enable);
2101  return;
2102  }
2103 
2104  reg = MII_TG3_MISC_SHDW_WREN |
2110  if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
2112 
2113  tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2114 
2115 
2116  reg = MII_TG3_MISC_SHDW_WREN |
2119  if (enable)
2121 
2122  tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
2123 }
2124 
2125 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
2126 {
2127  u32 phy;
2128 
2129  if (!tg3_flag(tp, 5705_PLUS) ||
2131  return;
2132 
2133  if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2134  u32 ephy;
2135 
2136  if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2138 
2139  tg3_writephy(tp, MII_TG3_FET_TEST,
2140  ephy | MII_TG3_FET_SHADOW_EN);
2141  if (!tg3_readphy(tp, reg, &phy)) {
2142  if (enable)
2144  else
2146  tg3_writephy(tp, reg, phy);
2147  }
2148  tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2149  }
2150  } else {
2151  int ret;
2152 
2153  ret = tg3_phy_auxctl_read(tp,
2155  if (!ret) {
2156  if (enable)
2158  else
2160  tg3_phy_auxctl_write(tp,
2162  }
2163  }
2164 }
2165 
2166 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2167 {
2168  int ret;
2169  u32 val;
2170 
2172  return;
2173 
2174  ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2175  if (!ret)
2176  tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2178 }
2179 
2180 static void tg3_phy_apply_otp(struct tg3 *tp)
2181 {
2182  u32 otp, phy;
2183 
2184  if (!tp->phy_otp)
2185  return;
2186 
2187  otp = tp->phy_otp;
2188 
2190  return;
2191 
2192  phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2194  tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2195 
2196  phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2198  tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2199 
2200  phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2202  tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2203 
2204  phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2205  tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2206 
2207  phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2208  tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2209 
2210  phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2212  tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2213 
2215 }
2216 
2217 static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up)
2218 {
2219  u32 val;
2220 
2221  if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2222  return;
2223 
2224  tp->setlpicnt = 0;
2225 
2226  if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2227  current_link_up == 1 &&
2228  tp->link_config.active_duplex == DUPLEX_FULL &&
2229  (tp->link_config.active_speed == SPEED_100 ||
2230  tp->link_config.active_speed == SPEED_1000)) {
2231  u32 eeectl;
2232 
2233  if (tp->link_config.active_speed == SPEED_1000)
2235  else
2237 
2238  tw32(TG3_CPMU_EEE_CTRL, eeectl);
2239 
2240  tg3_phy_cl45_read(tp, MDIO_MMD_AN,
2241  TG3_CL45_D7_EEERES_STAT, &val);
2242 
2243  if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2245  tp->setlpicnt = 2;
2246  }
2247 
2248  if (!tp->setlpicnt) {
2249  if (current_link_up == 1 &&
2251  tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2253  }
2254 
2255  val = tr32(TG3_CPMU_EEE_MODE);
2257  }
2258 }
2259 
2260 static void tg3_phy_eee_enable(struct tg3 *tp)
2261 {
2262  u32 val;
2263 
2264  if (tp->link_config.active_speed == SPEED_1000 &&
2267  tg3_flag(tp, 57765_CLASS)) &&
2269  val = MII_TG3_DSP_TAP26_ALNOKO |
2271  tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2273  }
2274 
2275  val = tr32(TG3_CPMU_EEE_MODE);
2277 }
2278 
2279 static int tg3_wait_macro_done(struct tg3 *tp)
2280 {
2281  int limit = 100;
2282 
2283  while (limit--) {
2284  u32 tmp32;
2285 
2286  if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2287  if ((tmp32 & 0x1000) == 0)
2288  break;
2289  }
2290  }
2291  if (limit < 0)
2292  return -EBUSY;
2293 
2294  return 0;
2295 }
2296 
2297 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2298 {
2299  static const u32 test_pat[4][6] = {
2300  { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2301  { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2302  { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2303  { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2304  };
2305  int chan;
2306 
2307  for (chan = 0; chan < 4; chan++) {
2308  int i;
2309 
2310  tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2311  (chan * 0x2000) | 0x0200);
2312  tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2313 
2314  for (i = 0; i < 6; i++)
2315  tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2316  test_pat[chan][i]);
2317 
2318  tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2319  if (tg3_wait_macro_done(tp)) {
2320  *resetp = 1;
2321  return -EBUSY;
2322  }
2323 
2324  tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2325  (chan * 0x2000) | 0x0200);
2326  tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2327  if (tg3_wait_macro_done(tp)) {
2328  *resetp = 1;
2329  return -EBUSY;
2330  }
2331 
2332  tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2333  if (tg3_wait_macro_done(tp)) {
2334  *resetp = 1;
2335  return -EBUSY;
2336  }
2337 
2338  for (i = 0; i < 6; i += 2) {
2339  u32 low, high;
2340 
2341  if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2342  tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2343  tg3_wait_macro_done(tp)) {
2344  *resetp = 1;
2345  return -EBUSY;
2346  }
2347  low &= 0x7fff;
2348  high &= 0x000f;
2349  if (low != test_pat[chan][i] ||
2350  high != test_pat[chan][i+1]) {
2351  tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2352  tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2353  tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2354 
2355  return -EBUSY;
2356  }
2357  }
2358  }
2359 
2360  return 0;
2361 }
2362 
2363 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2364 {
2365  int chan;
2366 
2367  for (chan = 0; chan < 4; chan++) {
2368  int i;
2369 
2370  tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2371  (chan * 0x2000) | 0x0200);
2372  tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2373  for (i = 0; i < 6; i++)
2374  tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2375  tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2376  if (tg3_wait_macro_done(tp))
2377  return -EBUSY;
2378  }
2379 
2380  return 0;
2381 }
2382 
2383 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2384 {
2385  u32 reg32, phy9_orig;
2386  int retries, do_phy_reset, err;
2387 
2388  retries = 10;
2389  do_phy_reset = 1;
2390  do {
2391  if (do_phy_reset) {
2392  err = tg3_bmcr_reset(tp);
2393  if (err)
2394  return err;
2395  do_phy_reset = 0;
2396  }
2397 
2398  /* Disable transmitter and interrupt. */
2399  if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
2400  continue;
2401 
2402  reg32 |= 0x3000;
2403  tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2404 
2405  /* Set full-duplex, 1000 mbps. */
2406  tg3_writephy(tp, MII_BMCR,
2408 
2409  /* Set to master mode. */
2410  if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2411  continue;
2412 
2413  tg3_writephy(tp, MII_CTRL1000,
2415 
2416  err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
2417  if (err)
2418  return err;
2419 
2420  /* Block the PHY control access. */
2421  tg3_phydsp_write(tp, 0x8005, 0x0800);
2422 
2423  err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2424  if (!err)
2425  break;
2426  } while (--retries);
2427 
2428  err = tg3_phy_reset_chanpat(tp);
2429  if (err)
2430  return err;
2431 
2432  tg3_phydsp_write(tp, 0x8005, 0x0000);
2433 
2434  tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2435  tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2436 
2438 
2439  tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2440 
2441  if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
2442  reg32 &= ~0x3000;
2443  tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2444  } else if (!err)
2445  err = -EBUSY;
2446 
2447  return err;
2448 }
2449 
2450 /* This will reset the tigon3 PHY if there is no valid
2451  * link unless the FORCE argument is non-zero.
2452  */
2453 static int tg3_phy_reset(struct tg3 *tp)
2454 {
2455  u32 val, cpmuctrl;
2456  int err;
2457 
2459  val = tr32(GRC_MISC_CFG);
2461  udelay(40);
2462  }
2463  err = tg3_readphy(tp, MII_BMSR, &val);
2464  err |= tg3_readphy(tp, MII_BMSR, &val);
2465  if (err != 0)
2466  return -EBUSY;
2467 
2468  if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
2469  netif_carrier_off(tp->dev);
2470  tg3_link_report(tp);
2471  }
2472 
2476  err = tg3_phy_reset_5703_4_5(tp);
2477  if (err)
2478  return err;
2479  goto out;
2480  }
2481 
2482  cpmuctrl = 0;
2485  cpmuctrl = tr32(TG3_CPMU_CTRL);
2486  if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2488  cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2489  }
2490 
2491  err = tg3_bmcr_reset(tp);
2492  if (err)
2493  return err;
2494 
2495  if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2497  tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2498 
2499  tw32(TG3_CPMU_CTRL, cpmuctrl);
2500  }
2501 
2505  if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2507  val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2508  udelay(40);
2510  }
2511  }
2512 
2513  if (tg3_flag(tp, 5717_PLUS) &&
2515  return 0;
2516 
2517  tg3_phy_apply_otp(tp);
2518 
2519  if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2520  tg3_phy_toggle_apd(tp, true);
2521  else
2522  tg3_phy_toggle_apd(tp, false);
2523 
2524 out:
2525  if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2527  tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2528  tg3_phydsp_write(tp, 0x000a, 0x0323);
2530  }
2531 
2532  if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2533  tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2534  tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2535  }
2536 
2537  if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2538  if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2539  tg3_phydsp_write(tp, 0x000a, 0x310b);
2540  tg3_phydsp_write(tp, 0x201f, 0x9506);
2541  tg3_phydsp_write(tp, 0x401f, 0x14e2);
2543  }
2544  } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2545  if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
2546  tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2547  if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2548  tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2549  tg3_writephy(tp, MII_TG3_TEST1,
2550  MII_TG3_TEST1_TRIM_EN | 0x4);
2551  } else
2552  tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2553 
2555  }
2556  }
2557 
2558  /* Set Extended packet length bit (bit 14) on all chips that */
2559  /* support jumbo frames */
2560  if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2561  /* Cannot do read-modify-write on 5401 */
2562  tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2563  } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2564  /* Set bit 14 with read-modify-write to preserve other bits */
2565  err = tg3_phy_auxctl_read(tp,
2567  if (!err)
2568  tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2570  }
2571 
2572  /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2573  * jumbo frames transmission.
2574  */
2575  if (tg3_flag(tp, JUMBO_CAPABLE)) {
2576  if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2577  tg3_writephy(tp, MII_TG3_EXT_CTRL,
2579  }
2580 
2582  /* adjust output voltage */
2583  tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2584  }
2585 
2586  tg3_phy_toggle_automdix(tp, 1);
2587  tg3_phy_set_wirespeed(tp);
2588  return 0;
2589 }
2590 
2591 #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2592 #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2593 #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2594  TG3_GPIO_MSG_NEED_VAUX)
2595 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2596  ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2597  (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2598  (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2599  (TG3_GPIO_MSG_DRVR_PRES << 12))
2600 
2601 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2602  ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2603  (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2604  (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2605  (TG3_GPIO_MSG_NEED_VAUX << 12))
2606 
2607 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2608 {
2609  u32 status, shift;
2610 
2613  status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2614  else
2615  status = tr32(TG3_CPMU_DRV_STATUS);
2616 
2617  shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2618  status &= ~(TG3_GPIO_MSG_MASK << shift);
2619  status |= (newstat << shift);
2620 
2623  tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2624  else
2625  tw32(TG3_CPMU_DRV_STATUS, status);
2626 
2627  return status >> TG3_APE_GPIO_MSG_SHIFT;
2628 }
2629 
2630 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2631 {
2632  if (!tg3_flag(tp, IS_NIC))
2633  return 0;
2634 
2638  if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2639  return -EIO;
2640 
2641  tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2642 
2645 
2646  tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2647  } else {
2650  }
2651 
2652  return 0;
2653 }
2654 
2655 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2656 {
2657  u32 grc_local_ctrl;
2658 
2659  if (!tg3_flag(tp, IS_NIC) ||
2662  return;
2663 
2664  grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2665 
2667  grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2669 
2671  grc_local_ctrl,
2673 
2675  grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2677 }
2678 
2679 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2680 {
2681  if (!tg3_flag(tp, IS_NIC))
2682  return;
2683 
2693  } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2694  tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2695  /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2696  u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2701  tp->grc_local_ctrl;
2702  tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2704 
2705  grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2706  tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2708 
2709  grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2710  tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2712  } else {
2713  u32 no_gpio2;
2714  u32 grc_local_ctrl = 0;
2715 
2716  /* Workaround to prevent overdrawing Amps. */
2718  grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2720  grc_local_ctrl,
2722  }
2723 
2724  /* On 5753 and variants, GPIO2 cannot be used. */
2725  no_gpio2 = tp->nic_sram_data_cfg &
2727 
2728  grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2733  if (no_gpio2) {
2734  grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2736  }
2738  tp->grc_local_ctrl | grc_local_ctrl,
2740 
2741  grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2742 
2744  tp->grc_local_ctrl | grc_local_ctrl,
2746 
2747  if (!no_gpio2) {
2748  grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2750  tp->grc_local_ctrl | grc_local_ctrl,
2752  }
2753  }
2754 }
2755 
2756 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2757 {
2758  u32 msg = 0;
2759 
2760  /* Serialize power state transitions */
2761  if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2762  return;
2763 
2764  if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2765  msg = TG3_GPIO_MSG_NEED_VAUX;
2766 
2767  msg = tg3_set_function_status(tp, msg);
2768 
2770  goto done;
2771 
2773  tg3_pwrsrc_switch_to_vaux(tp);
2774  else
2775  tg3_pwrsrc_die_with_vmain(tp);
2776 
2777 done:
2778  tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2779 }
2780 
2781 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2782 {
2783  bool need_vaux = false;
2784 
2785  /* The GPIOs do something completely different on 57765. */
2786  if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2787  return;
2788 
2792  tg3_frob_aux_power_5717(tp, include_wol ?
2793  tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2794  return;
2795  }
2796 
2797  if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2798  struct net_device *dev_peer;
2799 
2800  dev_peer = pci_get_drvdata(tp->pdev_peer);
2801 
2802  /* remove_one() may have been run on the peer. */
2803  if (dev_peer) {
2804  struct tg3 *tp_peer = netdev_priv(dev_peer);
2805 
2806  if (tg3_flag(tp_peer, INIT_COMPLETE))
2807  return;
2808 
2809  if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2810  tg3_flag(tp_peer, ENABLE_ASF))
2811  need_vaux = true;
2812  }
2813  }
2814 
2815  if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2816  tg3_flag(tp, ENABLE_ASF))
2817  need_vaux = true;
2818 
2819  if (need_vaux)
2820  tg3_pwrsrc_switch_to_vaux(tp);
2821  else
2822  tg3_pwrsrc_die_with_vmain(tp);
2823 }
2824 
2825 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2826 {
2827  if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2828  return 1;
2829  else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
2830  if (speed != SPEED_10)
2831  return 1;
2832  } else if (speed == SPEED_10)
2833  return 1;
2834 
2835  return 0;
2836 }
2837 
2838 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2839 {
2840  u32 val;
2841 
2842  if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
2844  u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2845  u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2846 
2847  sg_dig_ctrl |=
2849  tw32(SG_DIG_CTRL, sg_dig_ctrl);
2850  tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2851  }
2852  return;
2853  }
2854 
2856  tg3_bmcr_reset(tp);
2857  val = tr32(GRC_MISC_CFG);
2859  udelay(40);
2860  return;
2861  } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2862  u32 phytest;
2863  if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2864  u32 phy;
2865 
2866  tg3_writephy(tp, MII_ADVERTISE, 0);
2867  tg3_writephy(tp, MII_BMCR,
2869 
2870  tg3_writephy(tp, MII_TG3_FET_TEST,
2871  phytest | MII_TG3_FET_SHADOW_EN);
2872  if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2874  tg3_writephy(tp,
2876  phy);
2877  }
2878  tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2879  }
2880  return;
2881  } else if (do_low_power) {
2882  tg3_writephy(tp, MII_TG3_EXT_CTRL,
2884 
2888  tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
2889  }
2890 
2891  /* The PHY should not be powered down on some chips because
2892  * of bugs.
2893  */
2897  (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) ||
2899  !tp->pci_fn))
2900  return;
2901 
2908  }
2909 
2910  tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2911 }
2912 
2913 /* tp->lock is held. */
2914 static int tg3_nvram_lock(struct tg3 *tp)
2915 {
2916  if (tg3_flag(tp, NVRAM)) {
2917  int i;
2918 
2919  if (tp->nvram_lock_cnt == 0) {
2921  for (i = 0; i < 8000; i++) {
2922  if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2923  break;
2924  udelay(20);
2925  }
2926  if (i == 8000) {
2928  return -ENODEV;
2929  }
2930  }
2931  tp->nvram_lock_cnt++;
2932  }
2933  return 0;
2934 }
2935 
2936 /* tp->lock is held. */
2937 static void tg3_nvram_unlock(struct tg3 *tp)
2938 {
2939  if (tg3_flag(tp, NVRAM)) {
2940  if (tp->nvram_lock_cnt > 0)
2941  tp->nvram_lock_cnt--;
2942  if (tp->nvram_lock_cnt == 0)
2944  }
2945 }
2946 
2947 /* tp->lock is held. */
2948 static void tg3_enable_nvram_access(struct tg3 *tp)
2949 {
2950  if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2951  u32 nvaccess = tr32(NVRAM_ACCESS);
2952 
2953  tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2954  }
2955 }
2956 
2957 /* tp->lock is held. */
2958 static void tg3_disable_nvram_access(struct tg3 *tp)
2959 {
2960  if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
2961  u32 nvaccess = tr32(NVRAM_ACCESS);
2962 
2963  tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2964  }
2965 }
2966 
2967 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2968  u32 offset, u32 *val)
2969 {
2970  u32 tmp;
2971  int i;
2972 
2973  if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2974  return -EINVAL;
2975 
2980  tmp |
2981  (0 << EEPROM_ADDR_DEVID_SHIFT) |
2982  ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2985 
2986  for (i = 0; i < 1000; i++) {
2987  tmp = tr32(GRC_EEPROM_ADDR);
2988 
2989  if (tmp & EEPROM_ADDR_COMPLETE)
2990  break;
2991  msleep(1);
2992  }
2993  if (!(tmp & EEPROM_ADDR_COMPLETE))
2994  return -EBUSY;
2995 
2996  tmp = tr32(GRC_EEPROM_DATA);
2997 
2998  /*
2999  * The data will always be opposite the native endian
3000  * format. Perform a blind byteswap to compensate.
3001  */
3002  *val = swab32(tmp);
3003 
3004  return 0;
3005 }
3006 
3007 #define NVRAM_CMD_TIMEOUT 10000
3008 
3009 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3010 {
3011  int i;
3012 
3013  tw32(NVRAM_CMD, nvram_cmd);
3014  for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3015  udelay(10);
3016  if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3017  udelay(10);
3018  break;
3019  }
3020  }
3021 
3022  if (i == NVRAM_CMD_TIMEOUT)
3023  return -EBUSY;
3024 
3025  return 0;
3026 }
3027 
3028 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3029 {
3030  if (tg3_flag(tp, NVRAM) &&
3031  tg3_flag(tp, NVRAM_BUFFERED) &&
3032  tg3_flag(tp, FLASH) &&
3033  !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3034  (tp->nvram_jedecnum == JEDEC_ATMEL))
3035 
3036  addr = ((addr / tp->nvram_pagesize) <<
3038  (addr % tp->nvram_pagesize);
3039 
3040  return addr;
3041 }
3042 
3043 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3044 {
3045  if (tg3_flag(tp, NVRAM) &&
3046  tg3_flag(tp, NVRAM_BUFFERED) &&
3047  tg3_flag(tp, FLASH) &&
3048  !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3049  (tp->nvram_jedecnum == JEDEC_ATMEL))
3050 
3051  addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3052  tp->nvram_pagesize) +
3053  (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3054 
3055  return addr;
3056 }
3057 
3058 /* NOTE: Data read in from NVRAM is byteswapped according to
3059  * the byteswapping settings for all other register accesses.
3060  * tg3 devices are BE devices, so on a BE machine, the data
3061  * returned will be exactly as it is seen in NVRAM. On a LE
3062  * machine, the 32-bit value will be byteswapped.
3063  */
3064 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3065 {
3066  int ret;
3067 
3068  if (!tg3_flag(tp, NVRAM))
3069  return tg3_nvram_read_using_eeprom(tp, offset, val);
3070 
3071  offset = tg3_nvram_phys_addr(tp, offset);
3072 
3073  if (offset > NVRAM_ADDR_MSK)
3074  return -EINVAL;
3075 
3076  ret = tg3_nvram_lock(tp);
3077  if (ret)
3078  return ret;
3079 
3080  tg3_enable_nvram_access(tp);
3081 
3082  tw32(NVRAM_ADDR, offset);
3083  ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3085 
3086  if (ret == 0)
3087  *val = tr32(NVRAM_RDDATA);
3088 
3089  tg3_disable_nvram_access(tp);
3090 
3091  tg3_nvram_unlock(tp);
3092 
3093  return ret;
3094 }
3095 
3096 /* Ensures NVRAM data is in bytestream format. */
3097 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
3098 {
3099  u32 v;
3100  int res = tg3_nvram_read(tp, offset, &v);
3101  if (!res)
3102  *val = cpu_to_be32(v);
3103  return res;
3104 }
3105 
3106 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3107  u32 offset, u32 len, u8 *buf)
3108 {
3109  int i, j, rc = 0;
3110  u32 val;
3111 
3112  for (i = 0; i < len; i += 4) {
3113  u32 addr;
3114  __be32 data;
3115 
3116  addr = offset + i;
3117 
3118  memcpy(&data, buf + i, 4);
3119 
3120  /*
3121  * The SEEPROM interface expects the data to always be opposite
3122  * the native endian format. We accomplish this by reversing
3123  * all the operations that would have been performed on the
3124  * data from a call to tg3_nvram_read_be32().
3125  */
3127 
3128  val = tr32(GRC_EEPROM_ADDR);
3130 
3133  tw32(GRC_EEPROM_ADDR, val |
3134  (0 << EEPROM_ADDR_DEVID_SHIFT) |
3135  (addr & EEPROM_ADDR_ADDR_MASK) |
3138 
3139  for (j = 0; j < 1000; j++) {
3140  val = tr32(GRC_EEPROM_ADDR);
3141 
3142  if (val & EEPROM_ADDR_COMPLETE)
3143  break;
3144  msleep(1);
3145  }
3146  if (!(val & EEPROM_ADDR_COMPLETE)) {
3147  rc = -EBUSY;
3148  break;
3149  }
3150  }
3151 
3152  return rc;
3153 }
3154 
3155 /* offset and length are dword aligned */
3156 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3157  u8 *buf)
3158 {
3159  int ret = 0;
3160  u32 pagesize = tp->nvram_pagesize;
3161  u32 pagemask = pagesize - 1;
3162  u32 nvram_cmd;
3163  u8 *tmp;
3164 
3165  tmp = kmalloc(pagesize, GFP_KERNEL);
3166  if (tmp == NULL)
3167  return -ENOMEM;
3168 
3169  while (len) {
3170  int j;
3171  u32 phy_addr, page_off, size;
3172 
3173  phy_addr = offset & ~pagemask;
3174 
3175  for (j = 0; j < pagesize; j += 4) {
3176  ret = tg3_nvram_read_be32(tp, phy_addr + j,
3177  (__be32 *) (tmp + j));
3178  if (ret)
3179  break;
3180  }
3181  if (ret)
3182  break;
3183 
3184  page_off = offset & pagemask;
3185  size = pagesize;
3186  if (len < size)
3187  size = len;
3188 
3189  len -= size;
3190 
3191  memcpy(tmp + page_off, buf, size);
3192 
3193  offset = offset + (pagesize - page_off);
3194 
3195  tg3_enable_nvram_access(tp);
3196 
3197  /*
3198  * Before we can erase the flash page, we need
3199  * to issue a special "write enable" command.
3200  */
3201  nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3202 
3203  if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3204  break;
3205 
3206  /* Erase the target page */
3207  tw32(NVRAM_ADDR, phy_addr);
3208 
3209  nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3211 
3212  if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3213  break;
3214 
3215  /* Issue another write enable to start the write. */
3216  nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3217 
3218  if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3219  break;
3220 
3221  for (j = 0; j < pagesize; j += 4) {
3222  __be32 data;
3223 
3224  data = *((__be32 *) (tmp + j));
3225 
3226  tw32(NVRAM_WRDATA, be32_to_cpu(data));
3227 
3228  tw32(NVRAM_ADDR, phy_addr + j);
3229 
3230  nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3231  NVRAM_CMD_WR;
3232 
3233  if (j == 0)
3234  nvram_cmd |= NVRAM_CMD_FIRST;
3235  else if (j == (pagesize - 4))
3236  nvram_cmd |= NVRAM_CMD_LAST;
3237 
3238  ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3239  if (ret)
3240  break;
3241  }
3242  if (ret)
3243  break;
3244  }
3245 
3246  nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3247  tg3_nvram_exec_cmd(tp, nvram_cmd);
3248 
3249  kfree(tmp);
3250 
3251  return ret;
3252 }
3253 
3254 /* offset and length are dword aligned */
3255 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3256  u8 *buf)
3257 {
3258  int i, ret = 0;
3259 
3260  for (i = 0; i < len; i += 4, offset += 4) {
3261  u32 page_off, phy_addr, nvram_cmd;
3262  __be32 data;
3263 
3264  memcpy(&data, buf + i, 4);
3265  tw32(NVRAM_WRDATA, be32_to_cpu(data));
3266 
3267  page_off = offset % tp->nvram_pagesize;
3268 
3269  phy_addr = tg3_nvram_phys_addr(tp, offset);
3270 
3271  nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3272 
3273  if (page_off == 0 || i == 0)
3274  nvram_cmd |= NVRAM_CMD_FIRST;
3275  if (page_off == (tp->nvram_pagesize - 4))
3276  nvram_cmd |= NVRAM_CMD_LAST;
3277 
3278  if (i == (len - 4))
3279  nvram_cmd |= NVRAM_CMD_LAST;
3280 
3281  if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3282  !tg3_flag(tp, FLASH) ||
3283  !tg3_flag(tp, 57765_PLUS))
3284  tw32(NVRAM_ADDR, phy_addr);
3285 
3287  !tg3_flag(tp, 5755_PLUS) &&
3288  (tp->nvram_jedecnum == JEDEC_ST) &&
3289  (nvram_cmd & NVRAM_CMD_FIRST)) {
3290  u32 cmd;
3291 
3293  ret = tg3_nvram_exec_cmd(tp, cmd);
3294  if (ret)
3295  break;
3296  }
3297  if (!tg3_flag(tp, FLASH)) {
3298  /* We always do complete word writes to eeprom. */
3299  nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3300  }
3301 
3302  ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3303  if (ret)
3304  break;
3305  }
3306  return ret;
3307 }
3308 
3309 /* offset and length are dword aligned */
3310 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3311 {
3312  int ret;
3313 
3314  if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3317  udelay(40);
3318  }
3319 
3320  if (!tg3_flag(tp, NVRAM)) {
3321  ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3322  } else {
3323  u32 grc_mode;
3324 
3325  ret = tg3_nvram_lock(tp);
3326  if (ret)
3327  return ret;
3328 
3329  tg3_enable_nvram_access(tp);
3330  if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3331  tw32(NVRAM_WRITE1, 0x406);
3332 
3333  grc_mode = tr32(GRC_MODE);
3334  tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3335 
3336  if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3337  ret = tg3_nvram_write_block_buffered(tp, offset, len,
3338  buf);
3339  } else {
3340  ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3341  buf);
3342  }
3343 
3344  grc_mode = tr32(GRC_MODE);
3345  tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3346 
3347  tg3_disable_nvram_access(tp);
3348  tg3_nvram_unlock(tp);
3349  }
3350 
3351  if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3353  udelay(40);
3354  }
3355 
3356  return ret;
3357 }
3358 
3359 #define RX_CPU_SCRATCH_BASE 0x30000
3360 #define RX_CPU_SCRATCH_SIZE 0x04000
3361 #define TX_CPU_SCRATCH_BASE 0x34000
3362 #define TX_CPU_SCRATCH_SIZE 0x04000
3363 
3364 /* tp->lock is held. */
3365 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
3366 {
3367  int i;
3368 
3369  BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3370 
3372  u32 val = tr32(GRC_VCPU_EXT_CTRL);
3373 
3375  return 0;
3376  }
3377  if (offset == RX_CPU_BASE) {
3378  for (i = 0; i < 10000; i++) {
3379  tw32(offset + CPU_STATE, 0xffffffff);
3380  tw32(offset + CPU_MODE, CPU_MODE_HALT);
3381  if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3382  break;
3383  }
3384 
3385  tw32(offset + CPU_STATE, 0xffffffff);
3386  tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
3387  udelay(10);
3388  } else {
3389  for (i = 0; i < 10000; i++) {
3390  tw32(offset + CPU_STATE, 0xffffffff);
3391  tw32(offset + CPU_MODE, CPU_MODE_HALT);
3392  if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
3393  break;
3394  }
3395  }
3396 
3397  if (i >= 10000) {
3398  netdev_err(tp->dev, "%s timed out, %s CPU\n",
3399  __func__, offset == RX_CPU_BASE ? "RX" : "TX");
3400  return -ENODEV;
3401  }
3402 
3403  /* Clear firmware's nvram arbitration. */
3404  if (tg3_flag(tp, NVRAM))
3406  return 0;
3407 }
3408 
3409 struct fw_info {
3410  unsigned int fw_base;
3411  unsigned int fw_len;
3412  const __be32 *fw_data;
3413 };
3414 
3415 /* tp->lock is held. */
3416 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3417  u32 cpu_scratch_base, int cpu_scratch_size,
3418  struct fw_info *info)
3419 {
3420  int err, lock_err, i;
3421  void (*write_op)(struct tg3 *, u32, u32);
3422 
3423  if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3424  netdev_err(tp->dev,
3425  "%s: Trying to load TX cpu firmware which is 5705\n",
3426  __func__);
3427  return -EINVAL;
3428  }
3429 
3430  if (tg3_flag(tp, 5705_PLUS))
3431  write_op = tg3_write_mem;
3432  else
3433  write_op = tg3_write_indirect_reg32;
3434 
3435  /* It is possible that bootcode is still loading at this point.
3436  * Get the nvram lock first before halting the cpu.
3437  */
3438  lock_err = tg3_nvram_lock(tp);
3439  err = tg3_halt_cpu(tp, cpu_base);
3440  if (!lock_err)
3441  tg3_nvram_unlock(tp);
3442  if (err)
3443  goto out;
3444 
3445  for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3446  write_op(tp, cpu_scratch_base + i, 0);
3447  tw32(cpu_base + CPU_STATE, 0xffffffff);
3448  tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
3449  for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
3450  write_op(tp, (cpu_scratch_base +
3451  (info->fw_base & 0xffff) +
3452  (i * sizeof(u32))),
3453  be32_to_cpu(info->fw_data[i]));
3454 
3455  err = 0;
3456 
3457 out:
3458  return err;
3459 }
3460 
3461 /* tp->lock is held. */
3462 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3463 {
3464  struct fw_info info;
3465  const __be32 *fw_data;
3466  int err, i;
3467 
3468  fw_data = (void *)tp->fw->data;
3469 
3470  /* Firmware blob starts with version numbers, followed by
3471  start address and length. We are setting complete length.
3472  length = end_address_of_bss - start_address_of_text.
3473  Remainder is the blob to be loaded contiguously
3474  from start address. */
3475 
3476  info.fw_base = be32_to_cpu(fw_data[1]);
3477  info.fw_len = tp->fw->size - 12;
3478  info.fw_data = &fw_data[3];
3479 
3480  err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3482  &info);
3483  if (err)
3484  return err;
3485 
3486  err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3488  &info);
3489  if (err)
3490  return err;
3491 
3492  /* Now startup only the RX cpu. */
3493  tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3494  tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
3495 
3496  for (i = 0; i < 5; i++) {
3497  if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
3498  break;
3499  tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3501  tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
3502  udelay(1000);
3503  }
3504  if (i >= 5) {
3505  netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3506  "should be %08x\n", __func__,
3507  tr32(RX_CPU_BASE + CPU_PC), info.fw_base);
3508  return -ENODEV;
3509  }
3510  tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3511  tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
3512 
3513  return 0;
3514 }
3515 
3516 /* tp->lock is held. */
3517 static int tg3_load_tso_firmware(struct tg3 *tp)
3518 {
3519  struct fw_info info;
3520  const __be32 *fw_data;
3521  unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3522  int err, i;
3523 
3524  if (tg3_flag(tp, HW_TSO_1) ||
3525  tg3_flag(tp, HW_TSO_2) ||
3526  tg3_flag(tp, HW_TSO_3))
3527  return 0;
3528 
3529  fw_data = (void *)tp->fw->data;
3530 
3531  /* Firmware blob starts with version numbers, followed by
3532  start address and length. We are setting complete length.
3533  length = end_address_of_bss - start_address_of_text.
3534  Remainder is the blob to be loaded contiguously
3535  from start address. */
3536 
3537  info.fw_base = be32_to_cpu(fw_data[1]);
3538  cpu_scratch_size = tp->fw_len;
3539  info.fw_len = tp->fw->size - 12;
3540  info.fw_data = &fw_data[3];
3541 
3543  cpu_base = RX_CPU_BASE;
3544  cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3545  } else {
3546  cpu_base = TX_CPU_BASE;
3547  cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3548  cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3549  }
3550 
3551  err = tg3_load_firmware_cpu(tp, cpu_base,
3552  cpu_scratch_base, cpu_scratch_size,
3553  &info);
3554  if (err)
3555  return err;
3556 
3557  /* Now startup the cpu. */
3558  tw32(cpu_base + CPU_STATE, 0xffffffff);
3559  tw32_f(cpu_base + CPU_PC, info.fw_base);
3560 
3561  for (i = 0; i < 5; i++) {
3562  if (tr32(cpu_base + CPU_PC) == info.fw_base)
3563  break;
3564  tw32(cpu_base + CPU_STATE, 0xffffffff);
3565  tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3566  tw32_f(cpu_base + CPU_PC, info.fw_base);
3567  udelay(1000);
3568  }
3569  if (i >= 5) {
3570  netdev_err(tp->dev,
3571  "%s fails to set CPU PC, is %08x should be %08x\n",
3572  __func__, tr32(cpu_base + CPU_PC), info.fw_base);
3573  return -ENODEV;
3574  }
3575  tw32(cpu_base + CPU_STATE, 0xffffffff);
3576  tw32_f(cpu_base + CPU_MODE, 0x00000000);
3577  return 0;
3578 }
3579 
3580 
3581 /* tp->lock is held. */
3582 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
3583 {
3584  u32 addr_high, addr_low;
3585  int i;
3586 
3587  addr_high = ((tp->dev->dev_addr[0] << 8) |
3588  tp->dev->dev_addr[1]);
3589  addr_low = ((tp->dev->dev_addr[2] << 24) |
3590  (tp->dev->dev_addr[3] << 16) |
3591  (tp->dev->dev_addr[4] << 8) |
3592  (tp->dev->dev_addr[5] << 0));
3593  for (i = 0; i < 4; i++) {
3594  if (i == 1 && skip_mac_1)
3595  continue;
3596  tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
3597  tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
3598  }
3599 
3602  for (i = 0; i < 12; i++) {
3603  tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
3604  tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
3605  }
3606  }
3607 
3608  addr_high = (tp->dev->dev_addr[0] +
3609  tp->dev->dev_addr[1] +
3610  tp->dev->dev_addr[2] +
3611  tp->dev->dev_addr[3] +
3612  tp->dev->dev_addr[4] +
3613  tp->dev->dev_addr[5]) &
3615  tw32(MAC_TX_BACKOFF_SEED, addr_high);
3616 }
3617 
3618 static void tg3_enable_register_access(struct tg3 *tp)
3619 {
3620  /*
3621  * Make sure register accesses (indirect or otherwise) will function
3622  * correctly.
3623  */
3624  pci_write_config_dword(tp->pdev,
3626 }
3627 
3628 static int tg3_power_up(struct tg3 *tp)
3629 {
3630  int err;
3631 
3632  tg3_enable_register_access(tp);
3633 
3634  err = pci_set_power_state(tp->pdev, PCI_D0);
3635  if (!err) {
3636  /* Switch out of Vaux if it is a NIC */
3637  tg3_pwrsrc_switch_to_vmain(tp);
3638  } else {
3639  netdev_err(tp->dev, "Transition to D0 failed\n");
3640  }
3641 
3642  return err;
3643 }
3644 
3645 static int tg3_setup_phy(struct tg3 *, int);
3646 
3647 static int tg3_power_down_prepare(struct tg3 *tp)
3648 {
3649  u32 misc_host_ctrl;
3650  bool device_should_wake, do_low_power;
3651 
3652  tg3_enable_register_access(tp);
3653 
3654  /* Restore the CLKREQ setting. */
3655  if (tg3_flag(tp, CLKREQ_BUG))
3656  pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
3658 
3659  misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
3661  misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
3662 
3663  device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
3664  tg3_flag(tp, WOL_ENABLE);
3665 
3666  if (tg3_flag(tp, USE_PHYLIB)) {
3667  do_low_power = false;
3668  if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
3670  struct phy_device *phydev;
3671  u32 phyid, advertising;
3672 
3673  phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
3674 
3676 
3677  tp->link_config.speed = phydev->speed;
3678  tp->link_config.duplex = phydev->duplex;
3679  tp->link_config.autoneg = phydev->autoneg;
3680  tp->link_config.advertising = phydev->advertising;
3681 
3682  advertising = ADVERTISED_TP |
3686 
3687  if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
3688  if (tg3_flag(tp, WOL_SPEED_100MB))
3689  advertising |=
3693  else
3694  advertising |= ADVERTISED_10baseT_Full;
3695  }
3696 
3697  phydev->advertising = advertising;
3698 
3699  phy_start_aneg(phydev);
3700 
3701  phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
3702  if (phyid != PHY_ID_BCMAC131) {
3703  phyid &= PHY_BCM_OUI_MASK;
3704  if (phyid == PHY_BCM_OUI_1 ||
3705  phyid == PHY_BCM_OUI_2 ||
3706  phyid == PHY_BCM_OUI_3)
3707  do_low_power = true;
3708  }
3709  }
3710  } else {
3711  do_low_power = true;
3712 
3713  if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
3715 
3716  if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
3717  tg3_setup_phy(tp, 0);
3718  }
3719 
3721  u32 val;
3722 
3723  val = tr32(GRC_VCPU_EXT_CTRL);
3725  } else if (!tg3_flag(tp, ENABLE_ASF)) {
3726  int i;
3727  u32 val;
3728 
3729  for (i = 0; i < 200; i++) {
3730  tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
3731  if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
3732  break;
3733  msleep(1);
3734  }
3735  }
3736  if (tg3_flag(tp, WOL_CAP))
3737  tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
3739  WOL_DRV_WOL |
3741 
3742  if (device_should_wake) {
3743  u32 mac_mode;
3744 
3745  if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
3746  if (do_low_power &&
3747  !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
3748  tg3_phy_auxctl_write(tp,
3753  udelay(40);
3754  }
3755 
3756  if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3757  mac_mode = MAC_MODE_PORT_MODE_GMII;
3758  else
3759  mac_mode = MAC_MODE_PORT_MODE_MII;
3760 
3761  mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
3762  if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
3763  ASIC_REV_5700) {
3764  u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
3765  SPEED_100 : SPEED_10;
3766  if (tg3_5700_link_polarity(tp, speed))
3767  mac_mode |= MAC_MODE_LINK_POLARITY;
3768  else
3769  mac_mode &= ~MAC_MODE_LINK_POLARITY;
3770  }
3771  } else {
3772  mac_mode = MAC_MODE_PORT_MODE_TBI;
3773  }
3774 
3775  if (!tg3_flag(tp, 5750_PLUS))
3776  tw32(MAC_LED_CTRL, tp->led_ctrl);
3777 
3778  mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
3779  if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
3780  (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
3781  mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
3782 
3783  if (tg3_flag(tp, ENABLE_APE))
3784  mac_mode |= MAC_MODE_APE_TX_EN |
3787 
3788  tw32_f(MAC_MODE, mac_mode);
3789  udelay(100);
3790 
3792  udelay(10);
3793  }
3794 
3795  if (!tg3_flag(tp, WOL_SPEED_100MB) &&
3798  u32 base_val;
3799 
3800  base_val = tp->pci_clock_ctrl;
3801  base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
3803 
3806  } else if (tg3_flag(tp, 5780_CLASS) ||
3807  tg3_flag(tp, CPMU_PRESENT) ||
3809  /* do nothing */
3810  } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
3811  u32 newbits1, newbits2;
3812 
3815  newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
3818  newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
3819  } else if (tg3_flag(tp, 5705_PLUS)) {
3820  newbits1 = CLOCK_CTRL_625_CORE;
3821  newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
3822  } else {
3823  newbits1 = CLOCK_CTRL_ALTCLK;
3824  newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
3825  }
3826 
3828  40);
3829 
3831  40);
3832 
3833  if (!tg3_flag(tp, 5705_PLUS)) {
3834  u32 newbits3;
3835 
3838  newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
3841  } else {
3842  newbits3 = CLOCK_CTRL_44MHZ_CORE;
3843  }
3844 
3846  tp->pci_clock_ctrl | newbits3, 40);
3847  }
3848  }
3849 
3850  if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
3851  tg3_power_down_phy(tp, do_low_power);
3852 
3853  tg3_frob_aux_power(tp, true);
3854 
3855  /* Workaround for unstable PLL clock */
3858  u32 val = tr32(0x7d00);
3859 
3860  val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
3861  tw32(0x7d00, val);
3862  if (!tg3_flag(tp, ENABLE_ASF)) {
3863  int err;
3864 
3865  err = tg3_nvram_lock(tp);
3866  tg3_halt_cpu(tp, RX_CPU_BASE);
3867  if (!err)
3868  tg3_nvram_unlock(tp);
3869  }
3870  }
3871 
3872  tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
3873 
3874  return 0;
3875 }
3876 
3877 static void tg3_power_down(struct tg3 *tp)
3878 {
3879  tg3_power_down_prepare(tp);
3880 
3881  pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
3883 }
3884 
3885 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
3886 {
3887  switch (val & MII_TG3_AUX_STAT_SPDMASK) {
3889  *speed = SPEED_10;
3890  *duplex = DUPLEX_HALF;
3891  break;
3892 
3894  *speed = SPEED_10;
3895  *duplex = DUPLEX_FULL;
3896  break;
3897 
3899  *speed = SPEED_100;
3900  *duplex = DUPLEX_HALF;
3901  break;
3902 
3904  *speed = SPEED_100;
3905  *duplex = DUPLEX_FULL;
3906  break;
3907 
3909  *speed = SPEED_1000;
3910  *duplex = DUPLEX_HALF;
3911  break;
3912 
3914  *speed = SPEED_1000;
3915  *duplex = DUPLEX_FULL;
3916  break;
3917 
3918  default:
3919  if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3920  *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
3921  SPEED_10;
3922  *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
3923  DUPLEX_HALF;
3924  break;
3925  }
3926  *speed = SPEED_UNKNOWN;
3927  *duplex = DUPLEX_UNKNOWN;
3928  break;
3929  }
3930 }
3931 
3932 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
3933 {
3934  int err = 0;
3935  u32 val, new_adv;
3936 
3937  new_adv = ADVERTISE_CSMA;
3938  new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
3939  new_adv |= mii_advertise_flowctrl(flowctrl);
3940 
3941  err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
3942  if (err)
3943  goto done;
3944 
3945  if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
3946  new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
3947 
3948  if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3951 
3952  err = tg3_writephy(tp, MII_CTRL1000, new_adv);
3953  if (err)
3954  goto done;
3955  }
3956 
3957  if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
3958  goto done;
3959 
3962 
3963  err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
3964  if (!err) {
3965  u32 err2;
3966 
3967  val = 0;
3968  /* Advertise 100-BaseTX EEE ability */
3969  if (advertise & ADVERTISED_100baseT_Full)
3970  val |= MDIO_AN_EEE_ADV_100TX;
3971  /* Advertise 1000-BaseT EEE ability */
3972  if (advertise & ADVERTISED_1000baseT_Full)
3973  val |= MDIO_AN_EEE_ADV_1000T;
3974  err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3975  if (err)
3976  val = 0;
3977 
3978  switch (GET_ASIC_REV(tp->pci_chip_rev_id)) {
3979  case ASIC_REV_5717:
3980  case ASIC_REV_57765:
3981  case ASIC_REV_57766:
3982  case ASIC_REV_5719:
3983  /* If we advertised any eee advertisements above... */
3984  if (val)
3985  val = MII_TG3_DSP_TAP26_ALNOKO |
3988  tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
3989  /* Fall through */
3990  case ASIC_REV_5720:
3991  if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
3992  tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
3994  }
3995 
3996  err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
3997  if (!err)
3998  err = err2;
3999  }
4000 
4001 done:
4002  return err;
4003 }
4004 
4005 static void tg3_phy_copper_begin(struct tg3 *tp)
4006 {
4007  if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4009  u32 adv, fc;
4010 
4011  if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
4012  adv = ADVERTISED_10baseT_Half |
4014  if (tg3_flag(tp, WOL_SPEED_100MB))
4015  adv |= ADVERTISED_100baseT_Half |
4017 
4018  fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
4019  } else {
4020  adv = tp->link_config.advertising;
4022  adv &= ~(ADVERTISED_1000baseT_Half |
4024 
4025  fc = tp->link_config.flowctrl;
4026  }
4027 
4028  tg3_phy_autoneg_cfg(tp, adv, fc);
4029 
4030  tg3_writephy(tp, MII_BMCR,
4032  } else {
4033  int i;
4034  u32 bmcr, orig_bmcr;
4035 
4036  tp->link_config.active_speed = tp->link_config.speed;
4037  tp->link_config.active_duplex = tp->link_config.duplex;
4038 
4039  bmcr = 0;
4040  switch (tp->link_config.speed) {
4041  default:
4042  case SPEED_10:
4043  break;
4044 
4045  case SPEED_100:
4046  bmcr |= BMCR_SPEED100;
4047  break;
4048 
4049  case SPEED_1000:
4050  bmcr |= BMCR_SPEED1000;
4051  break;
4052  }
4053 
4054  if (tp->link_config.duplex == DUPLEX_FULL)
4055  bmcr |= BMCR_FULLDPLX;
4056 
4057  if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4058  (bmcr != orig_bmcr)) {
4059  tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4060  for (i = 0; i < 1500; i++) {
4061  u32 tmp;
4062 
4063  udelay(10);
4064  if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4065  tg3_readphy(tp, MII_BMSR, &tmp))
4066  continue;
4067  if (!(tmp & BMSR_LSTATUS)) {
4068  udelay(40);
4069  break;
4070  }
4071  }
4072  tg3_writephy(tp, MII_BMCR, bmcr);
4073  udelay(40);
4074  }
4075  }
4076 }
4077 
4078 static int tg3_init_5401phy_dsp(struct tg3 *tp)
4079 {
4080  int err;
4081 
4082  /* Turn off tap power management. */
4083  /* Set Extended packet length bit */
4084  err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
4085 
4086  err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4087  err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4088  err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4089  err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4090  err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
4091 
4092  udelay(40);
4093 
4094  return err;
4095 }
4096 
4097 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
4098 {
4099  u32 advmsk, tgtadv, advertising;
4100 
4101  advertising = tp->link_config.advertising;
4102  tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
4103 
4104  advmsk = ADVERTISE_ALL;
4105  if (tp->link_config.active_duplex == DUPLEX_FULL) {
4106  tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
4108  }
4109 
4110  if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4111  return false;
4112 
4113  if ((*lcladv & advmsk) != tgtadv)
4114  return false;
4115 
4116  if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4117  u32 tg3_ctrl;
4118 
4119  tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
4120 
4121  if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
4122  return false;
4123 
4124  if (tgtadv &&
4128  tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4130  } else {
4131  tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4132  }
4133 
4134  if (tg3_ctrl != tgtadv)
4135  return false;
4136  }
4137 
4138  return true;
4139 }
4140 
4141 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4142 {
4143  u32 lpeth = 0;
4144 
4145  if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4146  u32 val;
4147 
4148  if (tg3_readphy(tp, MII_STAT1000, &val))
4149  return false;
4150 
4151  lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4152  }
4153 
4154  if (tg3_readphy(tp, MII_LPA, rmtadv))
4155  return false;
4156 
4157  lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4158  tp->link_config.rmt_adv = lpeth;
4159 
4160  return true;
4161 }
4162 
4163 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
4164 {
4165  int current_link_up;
4166  u32 bmsr, val;
4167  u32 lcl_adv, rmt_adv;
4168  u16 current_speed;
4169  u8 current_duplex;
4170  int i, err;
4171 
4172  tw32(MAC_EVENT, 0);
4173 
4179  udelay(40);
4180 
4181  if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4183  (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4184  udelay(80);
4185  }
4186 
4187  tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
4188 
4189  /* Some third-party PHYs need to be reset on link going
4190  * down.
4191  */
4195  netif_carrier_ok(tp->dev)) {
4196  tg3_readphy(tp, MII_BMSR, &bmsr);
4197  if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4198  !(bmsr & BMSR_LSTATUS))
4199  force_reset = 1;
4200  }
4201  if (force_reset)
4202  tg3_phy_reset(tp);
4203 
4204  if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
4205  tg3_readphy(tp, MII_BMSR, &bmsr);
4206  if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
4207  !tg3_flag(tp, INIT_COMPLETE))
4208  bmsr = 0;
4209 
4210  if (!(bmsr & BMSR_LSTATUS)) {
4211  err = tg3_init_5401phy_dsp(tp);
4212  if (err)
4213  return err;
4214 
4215  tg3_readphy(tp, MII_BMSR, &bmsr);
4216  for (i = 0; i < 1000; i++) {
4217  udelay(10);
4218  if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4219  (bmsr & BMSR_LSTATUS)) {
4220  udelay(40);
4221  break;
4222  }
4223  }
4224 
4225  if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4227  !(bmsr & BMSR_LSTATUS) &&
4228  tp->link_config.active_speed == SPEED_1000) {
4229  err = tg3_phy_reset(tp);
4230  if (!err)
4231  err = tg3_init_5401phy_dsp(tp);
4232  if (err)
4233  return err;
4234  }
4235  }
4236  } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
4238  /* 5701 {A0,B0} CRC bug workaround */
4239  tg3_writephy(tp, 0x15, 0x0a75);
4240  tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4241  tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4242  tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4243  }
4244 
4245  /* Clear pending interrupts... */
4246  tg3_readphy(tp, MII_TG3_ISTAT, &val);
4247  tg3_readphy(tp, MII_TG3_ISTAT, &val);
4248 
4250  tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
4251  else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
4252  tg3_writephy(tp, MII_TG3_IMASK, ~0);
4253 
4256  if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4257  tg3_writephy(tp, MII_TG3_EXT_CTRL,
4259  else
4260  tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4261  }
4262 
4263  current_link_up = 0;
4264  current_speed = SPEED_UNKNOWN;
4265  current_duplex = DUPLEX_UNKNOWN;
4267  tp->link_config.rmt_adv = 0;
4268 
4270  err = tg3_phy_auxctl_read(tp,
4272  &val);
4273  if (!err && !(val & (1 << 10))) {
4274  tg3_phy_auxctl_write(tp,
4276  val | (1 << 10));
4277  goto relink;
4278  }
4279  }
4280 
4281  bmsr = 0;
4282  for (i = 0; i < 100; i++) {
4283  tg3_readphy(tp, MII_BMSR, &bmsr);
4284  if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4285  (bmsr & BMSR_LSTATUS))
4286  break;
4287  udelay(40);
4288  }
4289 
4290  if (bmsr & BMSR_LSTATUS) {
4291  u32 aux_stat, bmcr;
4292 
4293  tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4294  for (i = 0; i < 2000; i++) {
4295  udelay(10);
4296  if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4297  aux_stat)
4298  break;
4299  }
4300 
4301  tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4302  &current_speed,
4303  &current_duplex);
4304 
4305  bmcr = 0;
4306  for (i = 0; i < 200; i++) {
4307  tg3_readphy(tp, MII_BMCR, &bmcr);
4308  if (tg3_readphy(tp, MII_BMCR, &bmcr))
4309  continue;
4310  if (bmcr && bmcr != 0x7fff)
4311  break;
4312  udelay(10);
4313  }
4314 
4315  lcl_adv = 0;
4316  rmt_adv = 0;
4317 
4318  tp->link_config.active_speed = current_speed;
4319  tp->link_config.active_duplex = current_duplex;
4320 
4321  if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4322  if ((bmcr & BMCR_ANENABLE) &&
4323  tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
4324  tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
4325  current_link_up = 1;
4326  } else {
4327  if (!(bmcr & BMCR_ANENABLE) &&
4328  tp->link_config.speed == current_speed &&
4329  tp->link_config.duplex == current_duplex &&
4330  tp->link_config.flowctrl ==
4331  tp->link_config.active_flowctrl) {
4332  current_link_up = 1;
4333  }
4334  }
4335 
4336  if (current_link_up == 1 &&
4337  tp->link_config.active_duplex == DUPLEX_FULL) {
4338  u32 reg, bit;
4339 
4340  if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4341  reg = MII_TG3_FET_GEN_STAT;
4343  } else {
4344  reg = MII_TG3_EXT_STAT;
4345  bit = MII_TG3_EXT_STAT_MDIX;
4346  }
4347 
4348  if (!tg3_readphy(tp, reg, &val) && (val & bit))
4350 
4351  tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
4352  }
4353  }
4354 
4355 relink:
4356  if (current_link_up == 0 || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4357  tg3_phy_copper_begin(tp);
4358 
4359  tg3_readphy(tp, MII_BMSR, &bmsr);
4360  if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4362  current_link_up = 1;
4363  }
4364 
4366  if (current_link_up == 1) {
4367  if (tp->link_config.active_speed == SPEED_100 ||
4368  tp->link_config.active_speed == SPEED_10)
4370  else
4372  } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
4374  else
4376 
4378  if (tp->link_config.active_duplex == DUPLEX_HALF)
4380 
4382  if (current_link_up == 1 &&
4383  tg3_5700_link_polarity(tp, tp->link_config.active_speed))
4385  else
4387  }
4388 
4389  /* ??? Without this setting Netgear GA302T PHY does not
4390  * ??? send/receive packets...
4391  */
4392  if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
4395  tw32_f(MAC_MI_MODE, tp->mi_mode);
4396  udelay(80);
4397  }
4398 
4399  tw32_f(MAC_MODE, tp->mac_mode);
4400  udelay(40);
4401 
4402  tg3_phy_eee_adjust(tp, current_link_up);
4403 
4404  if (tg3_flag(tp, USE_LINKCHG_REG)) {
4405  /* Polled via timer. */
4406  tw32_f(MAC_EVENT, 0);
4407  } else {
4409  }
4410  udelay(40);
4411 
4413  current_link_up == 1 &&
4414  tp->link_config.active_speed == SPEED_1000 &&
4415  (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
4416  udelay(120);
4420  udelay(40);
4421  tg3_write_mem(tp,
4424  }
4425 
4426  /* Prevent send BD corruption. */
4427  if (tg3_flag(tp, CLKREQ_BUG)) {
4428  if (tp->link_config.active_speed == SPEED_100 ||
4429  tp->link_config.active_speed == SPEED_10)
4430  pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
4432  else
4433  pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4435  }
4436 
4437  if (current_link_up != netif_carrier_ok(tp->dev)) {
4438  if (current_link_up)
4439  netif_carrier_on(tp->dev);
4440  else
4441  netif_carrier_off(tp->dev);
4442  tg3_link_report(tp);
4443  }
4444 
4445  return 0;
4446 }
4447 
4449  int state;
4450 #define ANEG_STATE_UNKNOWN 0
4451 #define ANEG_STATE_AN_ENABLE 1
4452 #define ANEG_STATE_RESTART_INIT 2
4453 #define ANEG_STATE_RESTART 3
4454 #define ANEG_STATE_DISABLE_LINK_OK 4
4455 #define ANEG_STATE_ABILITY_DETECT_INIT 5
4456 #define ANEG_STATE_ABILITY_DETECT 6
4457 #define ANEG_STATE_ACK_DETECT_INIT 7
4458 #define ANEG_STATE_ACK_DETECT 8
4459 #define ANEG_STATE_COMPLETE_ACK_INIT 9
4460 #define ANEG_STATE_COMPLETE_ACK 10
4461 #define ANEG_STATE_IDLE_DETECT_INIT 11
4462 #define ANEG_STATE_IDLE_DETECT 12
4463 #define ANEG_STATE_LINK_OK 13
4464 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
4465 #define ANEG_STATE_NEXT_PAGE_WAIT 15
4466 
4467  u32 flags;
4468 #define MR_AN_ENABLE 0x00000001
4469 #define MR_RESTART_AN 0x00000002
4470 #define MR_AN_COMPLETE 0x00000004
4471 #define MR_PAGE_RX 0x00000008
4472 #define MR_NP_LOADED 0x00000010
4473 #define MR_TOGGLE_TX 0x00000020
4474 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
4475 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
4476 #define MR_LP_ADV_SYM_PAUSE 0x00000100
4477 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
4478 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
4479 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
4480 #define MR_LP_ADV_NEXT_PAGE 0x00001000
4481 #define MR_TOGGLE_RX 0x00002000
4482 #define MR_NP_RX 0x00004000
4483 
4484 #define MR_LINK_OK 0x80000000
4485 
4486  unsigned long link_time, cur_time;
4487 
4490 
4492 
4494 #define ANEG_CFG_NP 0x00000080
4495 #define ANEG_CFG_ACK 0x00000040
4496 #define ANEG_CFG_RF2 0x00000020
4497 #define ANEG_CFG_RF1 0x00000010
4498 #define ANEG_CFG_PS2 0x00000001
4499 #define ANEG_CFG_PS1 0x00008000
4500 #define ANEG_CFG_HD 0x00004000
4501 #define ANEG_CFG_FD 0x00002000
4502 #define ANEG_CFG_INVAL 0x00001f06
4503 
4504 };
4505 #define ANEG_OK 0
4506 #define ANEG_DONE 1
4507 #define ANEG_TIMER_ENAB 2
4508 #define ANEG_FAILED -1
4509 
4510 #define ANEG_STATE_SETTLE_TIME 10000
4511 
4512 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
4513  struct tg3_fiber_aneginfo *ap)
4514 {
4515  u16 flowctrl;
4516  unsigned long delta;
4517  u32 rx_cfg_reg;
4518  int ret;
4519 
4520  if (ap->state == ANEG_STATE_UNKNOWN) {
4521  ap->rxconfig = 0;
4522  ap->link_time = 0;
4523  ap->cur_time = 0;
4524  ap->ability_match_cfg = 0;
4525  ap->ability_match_count = 0;
4526  ap->ability_match = 0;
4527  ap->idle_match = 0;
4528  ap->ack_match = 0;
4529  }
4530  ap->cur_time++;
4531 
4533  rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
4534 
4535  if (rx_cfg_reg != ap->ability_match_cfg) {
4536  ap->ability_match_cfg = rx_cfg_reg;
4537  ap->ability_match = 0;
4538  ap->ability_match_count = 0;
4539  } else {
4540  if (++ap->ability_match_count > 1) {
4541  ap->ability_match = 1;
4542  ap->ability_match_cfg = rx_cfg_reg;
4543  }
4544  }
4545  if (rx_cfg_reg & ANEG_CFG_ACK)
4546  ap->ack_match = 1;
4547  else
4548  ap->ack_match = 0;
4549 
4550  ap->idle_match = 0;
4551  } else {
4552  ap->idle_match = 1;
4553  ap->ability_match_cfg = 0;
4554  ap->ability_match_count = 0;
4555  ap->ability_match = 0;
4556  ap->ack_match = 0;
4557 
4558  rx_cfg_reg = 0;
4559  }
4560 
4561  ap->rxconfig = rx_cfg_reg;
4562  ret = ANEG_OK;
4563 
4564  switch (ap->state) {
4565  case ANEG_STATE_UNKNOWN:
4566  if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
4568 
4569  /* fallthru */
4570  case ANEG_STATE_AN_ENABLE:
4571  ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
4572  if (ap->flags & MR_AN_ENABLE) {
4573  ap->link_time = 0;
4574  ap->cur_time = 0;
4575  ap->ability_match_cfg = 0;
4576  ap->ability_match_count = 0;
4577  ap->ability_match = 0;
4578  ap->idle_match = 0;
4579  ap->ack_match = 0;
4580 
4582  } else {
4584  }
4585  break;
4586 
4588  ap->link_time = ap->cur_time;
4589  ap->flags &= ~(MR_NP_LOADED);
4590  ap->txconfig = 0;
4591  tw32(MAC_TX_AUTO_NEG, 0);
4593  tw32_f(MAC_MODE, tp->mac_mode);
4594  udelay(40);
4595 
4596  ret = ANEG_TIMER_ENAB;
4597  ap->state = ANEG_STATE_RESTART;
4598 
4599  /* fallthru */
4600  case ANEG_STATE_RESTART:
4601  delta = ap->cur_time - ap->link_time;
4602  if (delta > ANEG_STATE_SETTLE_TIME)
4604  else
4605  ret = ANEG_TIMER_ENAB;
4606  break;
4607 
4609  ret = ANEG_DONE;
4610  break;
4611 
4613  ap->flags &= ~(MR_TOGGLE_TX);
4614  ap->txconfig = ANEG_CFG_FD;
4615  flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4616  if (flowctrl & ADVERTISE_1000XPAUSE)
4617  ap->txconfig |= ANEG_CFG_PS1;
4618  if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4619  ap->txconfig |= ANEG_CFG_PS2;
4622  tw32_f(MAC_MODE, tp->mac_mode);
4623  udelay(40);
4624 
4626  break;
4627 
4629  if (ap->ability_match != 0 && ap->rxconfig != 0)
4631  break;
4632 
4634  ap->txconfig |= ANEG_CFG_ACK;
4637  tw32_f(MAC_MODE, tp->mac_mode);
4638  udelay(40);
4639 
4641 
4642  /* fallthru */
4643  case ANEG_STATE_ACK_DETECT:
4644  if (ap->ack_match != 0) {
4645  if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
4646  (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
4648  } else {
4650  }
4651  } else if (ap->ability_match != 0 &&
4652  ap->rxconfig == 0) {
4654  }
4655  break;
4656 
4658  if (ap->rxconfig & ANEG_CFG_INVAL) {
4659  ret = ANEG_FAILED;
4660  break;
4661  }
4662  ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
4669  MR_TOGGLE_RX |
4670  MR_NP_RX);
4671  if (ap->rxconfig & ANEG_CFG_FD)
4673  if (ap->rxconfig & ANEG_CFG_HD)
4675  if (ap->rxconfig & ANEG_CFG_PS1)
4676  ap->flags |= MR_LP_ADV_SYM_PAUSE;
4677  if (ap->rxconfig & ANEG_CFG_PS2)
4678  ap->flags |= MR_LP_ADV_ASYM_PAUSE;
4679  if (ap->rxconfig & ANEG_CFG_RF1)
4681  if (ap->rxconfig & ANEG_CFG_RF2)
4683  if (ap->rxconfig & ANEG_CFG_NP)
4684  ap->flags |= MR_LP_ADV_NEXT_PAGE;
4685 
4686  ap->link_time = ap->cur_time;
4687 
4688  ap->flags ^= (MR_TOGGLE_TX);
4689  if (ap->rxconfig & 0x0008)
4690  ap->flags |= MR_TOGGLE_RX;
4691  if (ap->rxconfig & ANEG_CFG_NP)
4692  ap->flags |= MR_NP_RX;
4693  ap->flags |= MR_PAGE_RX;
4694 
4696  ret = ANEG_TIMER_ENAB;
4697  break;
4698 
4700  if (ap->ability_match != 0 &&
4701  ap->rxconfig == 0) {
4703  break;
4704  }
4705  delta = ap->cur_time - ap->link_time;
4706  if (delta > ANEG_STATE_SETTLE_TIME) {
4707  if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
4709  } else {
4710  if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
4711  !(ap->flags & MR_NP_RX)) {
4713  } else {
4714  ret = ANEG_FAILED;
4715  }
4716  }
4717  }
4718  break;
4719 
4721  ap->link_time = ap->cur_time;
4723  tw32_f(MAC_MODE, tp->mac_mode);
4724  udelay(40);
4725 
4727  ret = ANEG_TIMER_ENAB;
4728  break;
4729 
4731  if (ap->ability_match != 0 &&
4732  ap->rxconfig == 0) {
4734  break;
4735  }
4736  delta = ap->cur_time - ap->link_time;
4737  if (delta > ANEG_STATE_SETTLE_TIME) {
4738  /* XXX another gem from the Broadcom driver :( */
4739  ap->state = ANEG_STATE_LINK_OK;
4740  }
4741  break;
4742 
4743  case ANEG_STATE_LINK_OK:
4744  ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
4745  ret = ANEG_DONE;
4746  break;
4747 
4749  /* ??? unimplemented */
4750  break;
4751 
4753  /* ??? unimplemented */
4754  break;
4755 
4756  default:
4757  ret = ANEG_FAILED;
4758  break;
4759  }
4760 
4761  return ret;
4762 }
4763 
4764 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
4765 {
4766  int res = 0;
4767  struct tg3_fiber_aneginfo aninfo;
4768  int status = ANEG_FAILED;
4769  unsigned int tick;
4770  u32 tmp;
4771 
4772  tw32_f(MAC_TX_AUTO_NEG, 0);
4773 
4774  tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
4776  udelay(40);
4777 
4779  udelay(40);
4780 
4781  memset(&aninfo, 0, sizeof(aninfo));
4782  aninfo.flags |= MR_AN_ENABLE;
4783  aninfo.state = ANEG_STATE_UNKNOWN;
4784  aninfo.cur_time = 0;
4785  tick = 0;
4786  while (++tick < 195000) {
4787  status = tg3_fiber_aneg_smachine(tp, &aninfo);
4788  if (status == ANEG_DONE || status == ANEG_FAILED)
4789  break;
4790 
4791  udelay(1);
4792  }
4793 
4795  tw32_f(MAC_MODE, tp->mac_mode);
4796  udelay(40);
4797 
4798  *txflags = aninfo.txconfig;
4799  *rxflags = aninfo.flags;
4800 
4801  if (status == ANEG_DONE &&
4802  (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
4804  res = 1;
4805 
4806  return res;
4807 }
4808 
4809 static void tg3_init_bcm8002(struct tg3 *tp)
4810 {
4811  u32 mac_status = tr32(MAC_STATUS);
4812  int i;
4813 
4814  /* Reset when initting first time or we have a link. */
4815  if (tg3_flag(tp, INIT_COMPLETE) &&
4816  !(mac_status & MAC_STATUS_PCS_SYNCED))
4817  return;
4818 
4819  /* Set PLL lock range. */
4820  tg3_writephy(tp, 0x16, 0x8007);
4821 
4822  /* SW reset */
4823  tg3_writephy(tp, MII_BMCR, BMCR_RESET);
4824 
4825  /* Wait for reset to complete. */
4826  /* XXX schedule_timeout() ... */
4827  for (i = 0; i < 500; i++)
4828  udelay(10);
4829 
4830  /* Config mode; select PMA/Ch 1 regs. */
4831  tg3_writephy(tp, 0x10, 0x8411);
4832 
4833  /* Enable auto-lock and comdet, select txclk for tx. */
4834  tg3_writephy(tp, 0x11, 0x0a10);
4835 
4836  tg3_writephy(tp, 0x18, 0x00a0);
4837  tg3_writephy(tp, 0x16, 0x41ff);
4838 
4839  /* Assert and deassert POR. */
4840  tg3_writephy(tp, 0x13, 0x0400);
4841  udelay(40);
4842  tg3_writephy(tp, 0x13, 0x0000);
4843 
4844  tg3_writephy(tp, 0x11, 0x0a50);
4845  udelay(40);
4846  tg3_writephy(tp, 0x11, 0x0a10);
4847 
4848  /* Wait for signal to stabilize */
4849  /* XXX schedule_timeout() ... */
4850  for (i = 0; i < 15000; i++)
4851  udelay(10);
4852 
4853  /* Deselect the channel register so we can read the PHYID
4854  * later.
4855  */
4856  tg3_writephy(tp, 0x10, 0x8011);
4857 }
4858 
4859 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
4860 {
4861  u16 flowctrl;
4862  u32 sg_dig_ctrl, sg_dig_status;
4863  u32 serdes_cfg, expected_sg_dig_ctrl;
4864  int workaround, port_a;
4865  int current_link_up;
4866 
4867  serdes_cfg = 0;
4868  expected_sg_dig_ctrl = 0;
4869  workaround = 0;
4870  port_a = 1;
4871  current_link_up = 0;
4872 
4873  if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
4875  workaround = 1;
4877  port_a = 0;
4878 
4879  /* preserve bits 0-11,13,14 for signal pre-emphasis */
4880  /* preserve bits 20-23 for voltage regulator */
4881  serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
4882  }
4883 
4884  sg_dig_ctrl = tr32(SG_DIG_CTRL);
4885 
4886  if (tp->link_config.autoneg != AUTONEG_ENABLE) {
4887  if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
4888  if (workaround) {
4889  u32 val = serdes_cfg;
4890 
4891  if (port_a)
4892  val |= 0xc010000;
4893  else
4894  val |= 0x4010000;
4895  tw32_f(MAC_SERDES_CFG, val);
4896  }
4897 
4899  }
4900  if (mac_status & MAC_STATUS_PCS_SYNCED) {
4901  tg3_setup_flow_control(tp, 0, 0);
4902  current_link_up = 1;
4903  }
4904  goto out;
4905  }
4906 
4907  /* Want auto-negotiation. */
4908  expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
4909 
4910  flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4911  if (flowctrl & ADVERTISE_1000XPAUSE)
4912  expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
4913  if (flowctrl & ADVERTISE_1000XPSE_ASYM)
4914  expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
4915 
4916  if (sg_dig_ctrl != expected_sg_dig_ctrl) {
4917  if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
4918  tp->serdes_counter &&
4919  ((mac_status & (MAC_STATUS_PCS_SYNCED |
4920  MAC_STATUS_RCVD_CFG)) ==
4921  MAC_STATUS_PCS_SYNCED)) {
4922  tp->serdes_counter--;
4923  current_link_up = 1;
4924  goto out;
4925  }
4926 restart_autoneg:
4927  if (workaround)
4928  tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
4929  tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
4930  udelay(5);
4931  tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
4932 
4935  } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
4937  sg_dig_status = tr32(SG_DIG_STATUS);
4938  mac_status = tr32(MAC_STATUS);
4939 
4940  if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
4941  (mac_status & MAC_STATUS_PCS_SYNCED)) {
4942  u32 local_adv = 0, remote_adv = 0;
4943 
4944  if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
4945  local_adv |= ADVERTISE_1000XPAUSE;
4946  if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
4947  local_adv |= ADVERTISE_1000XPSE_ASYM;
4948 
4949  if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
4950  remote_adv |= LPA_1000XPAUSE;
4951  if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
4952  remote_adv |= LPA_1000XPAUSE_ASYM;
4953 
4954  tp->link_config.rmt_adv =
4955  mii_adv_to_ethtool_adv_x(remote_adv);
4956 
4957  tg3_setup_flow_control(tp, local_adv, remote_adv);
4958  current_link_up = 1;
4959  tp->serdes_counter = 0;
4961  } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
4962  if (tp->serdes_counter)
4963  tp->serdes_counter--;
4964  else {
4965  if (workaround) {
4966  u32 val = serdes_cfg;
4967 
4968  if (port_a)
4969  val |= 0xc010000;
4970  else
4971  val |= 0x4010000;
4972 
4973  tw32_f(MAC_SERDES_CFG, val);
4974  }
4975 
4977  udelay(40);
4978 
4979  /* Link parallel detection - link is up */
4980  /* only if we have PCS_SYNC and not */
4981  /* receiving config code words */
4982  mac_status = tr32(MAC_STATUS);
4983  if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
4984  !(mac_status & MAC_STATUS_RCVD_CFG)) {
4985  tg3_setup_flow_control(tp, 0, 0);
4986  current_link_up = 1;
4987  tp->phy_flags |=
4989  tp->serdes_counter =
4991  } else
4992  goto restart_autoneg;
4993  }
4994  }
4995  } else {
4998  }
4999 
5000 out:
5001  return current_link_up;
5002 }
5003 
5004 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
5005 {
5006  int current_link_up = 0;
5007 
5008  if (!(mac_status & MAC_STATUS_PCS_SYNCED))
5009  goto out;
5010 
5011  if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5012  u32 txflags, rxflags;
5013  int i;
5014 
5015  if (fiber_autoneg(tp, &txflags, &rxflags)) {
5016  u32 local_adv = 0, remote_adv = 0;
5017 
5018  if (txflags & ANEG_CFG_PS1)
5019  local_adv |= ADVERTISE_1000XPAUSE;
5020  if (txflags & ANEG_CFG_PS2)
5021  local_adv |= ADVERTISE_1000XPSE_ASYM;
5022 
5023  if (rxflags & MR_LP_ADV_SYM_PAUSE)
5024  remote_adv |= LPA_1000XPAUSE;
5025  if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5026  remote_adv |= LPA_1000XPAUSE_ASYM;
5027 
5028  tp->link_config.rmt_adv =
5029  mii_adv_to_ethtool_adv_x(remote_adv);
5030 
5031  tg3_setup_flow_control(tp, local_adv, remote_adv);
5032 
5033  current_link_up = 1;
5034  }
5035  for (i = 0; i < 30; i++) {
5036  udelay(20);
5040  udelay(40);
5041  if ((tr32(MAC_STATUS) &
5043  MAC_STATUS_CFG_CHANGED)) == 0)
5044  break;
5045  }
5046 
5047  mac_status = tr32(MAC_STATUS);
5048  if (current_link_up == 0 &&
5049  (mac_status & MAC_STATUS_PCS_SYNCED) &&
5050  !(mac_status & MAC_STATUS_RCVD_CFG))
5051  current_link_up = 1;
5052  } else {
5053  tg3_setup_flow_control(tp, 0, 0);
5054 
5055  /* Forcing 1000FD link up. */
5056  current_link_up = 1;
5057 
5059  udelay(40);
5060 
5061  tw32_f(MAC_MODE, tp->mac_mode);
5062  udelay(40);
5063  }
5064 
5065 out:
5066  return current_link_up;
5067 }
5068 
5069 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
5070 {
5071  u32 orig_pause_cfg;
5072  u16 orig_active_speed;
5073  u8 orig_active_duplex;
5074  u32 mac_status;
5075  int current_link_up;
5076  int i;
5077 
5078  orig_pause_cfg = tp->link_config.active_flowctrl;
5079  orig_active_speed = tp->link_config.active_speed;
5080  orig_active_duplex = tp->link_config.active_duplex;
5081 
5082  if (!tg3_flag(tp, HW_AUTONEG) &&
5083  netif_carrier_ok(tp->dev) &&
5084  tg3_flag(tp, INIT_COMPLETE)) {
5085  mac_status = tr32(MAC_STATUS);
5086  mac_status &= (MAC_STATUS_PCS_SYNCED |
5090  if (mac_status == (MAC_STATUS_PCS_SYNCED |
5094  return 0;
5095  }
5096  }
5097 
5098  tw32_f(MAC_TX_AUTO_NEG, 0);
5099 
5102  tw32_f(MAC_MODE, tp->mac_mode);
5103  udelay(40);
5104 
5105  if (tp->phy_id == TG3_PHY_ID_BCM8002)
5106  tg3_init_bcm8002(tp);
5107 
5108  /* Enable link change event even when serdes polling. */
5110  udelay(40);
5111 
5112  current_link_up = 0;
5113  tp->link_config.rmt_adv = 0;
5114  mac_status = tr32(MAC_STATUS);
5115 
5116  if (tg3_flag(tp, HW_AUTONEG))
5117  current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5118  else
5119  current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5120 
5121  tp->napi[0].hw_status->status =
5123  (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
5124 
5125  for (i = 0; i < 100; i++) {
5128  udelay(5);
5132  break;
5133  }
5134 
5135  mac_status = tr32(MAC_STATUS);
5136  if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
5137  current_link_up = 0;
5138  if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5139  tp->serdes_counter == 0) {
5140  tw32_f(MAC_MODE, (tp->mac_mode |
5142  udelay(1);
5143  tw32_f(MAC_MODE, tp->mac_mode);
5144  }
5145  }
5146 
5147  if (current_link_up == 1) {
5148  tp->link_config.active_speed = SPEED_1000;
5149  tp->link_config.active_duplex = DUPLEX_FULL;
5150  tw32(MAC_LED_CTRL, (tp->led_ctrl |
5153  } else {
5154  tp->link_config.active_speed = SPEED_UNKNOWN;
5155  tp->link_config.active_duplex = DUPLEX_UNKNOWN;
5156  tw32(MAC_LED_CTRL, (tp->led_ctrl |
5159  }
5160 
5161  if (current_link_up != netif_carrier_ok(tp->dev)) {
5162  if (current_link_up)
5163  netif_carrier_on(tp->dev);
5164  else
5165  netif_carrier_off(tp->dev);
5166  tg3_link_report(tp);
5167  } else {
5168  u32 now_pause_cfg = tp->link_config.active_flowctrl;
5169  if (orig_pause_cfg != now_pause_cfg ||
5170  orig_active_speed != tp->link_config.active_speed ||
5171  orig_active_duplex != tp->link_config.active_duplex)
5172  tg3_link_report(tp);
5173  }
5174 
5175  return 0;
5176 }
5177 
5178 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
5179 {
5180  int current_link_up, err = 0;
5181  u32 bmsr, bmcr;
5182  u16 current_speed;
5183  u8 current_duplex;
5184  u32 local_adv, remote_adv;
5185 
5187  tw32_f(MAC_MODE, tp->mac_mode);
5188  udelay(40);
5189 
5190  tw32(MAC_EVENT, 0);
5191 
5197  udelay(40);
5198 
5199  if (force_reset)
5200  tg3_phy_reset(tp);
5201 
5202  current_link_up = 0;
5203  current_speed = SPEED_UNKNOWN;
5204  current_duplex = DUPLEX_UNKNOWN;
5205  tp->link_config.rmt_adv = 0;
5206 
5207  err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5208  err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5211  bmsr |= BMSR_LSTATUS;
5212  else
5213  bmsr &= ~BMSR_LSTATUS;
5214  }
5215 
5216  err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5217 
5218  if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
5220  /* do nothing, just check for link up at the end */
5221  } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5222  u32 adv, newadv;
5223 
5224  err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5225  newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5226  ADVERTISE_1000XPAUSE |
5227  ADVERTISE_1000XPSE_ASYM |
5228  ADVERTISE_SLCT);
5229 
5230  newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5231  newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
5232 
5233  if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5234  tg3_writephy(tp, MII_ADVERTISE, newadv);
5235  bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5236  tg3_writephy(tp, MII_BMCR, bmcr);
5237 
5241 
5242  return err;
5243  }
5244  } else {
5245  u32 new_bmcr;
5246 
5247  bmcr &= ~BMCR_SPEED1000;
5248  new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5249 
5250  if (tp->link_config.duplex == DUPLEX_FULL)
5251  new_bmcr |= BMCR_FULLDPLX;
5252 
5253  if (new_bmcr != bmcr) {
5254  /* BMCR_SPEED1000 is a reserved bit that needs
5255  * to be set on write.
5256  */
5257  new_bmcr |= BMCR_SPEED1000;
5258 
5259  /* Force a linkdown */
5260  if (netif_carrier_ok(tp->dev)) {
5261  u32 adv;
5262 
5263  err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5264  adv &= ~(ADVERTISE_1000XFULL |
5266  ADVERTISE_SLCT);
5267  tg3_writephy(tp, MII_ADVERTISE, adv);
5268  tg3_writephy(tp, MII_BMCR, bmcr |
5269  BMCR_ANRESTART |
5270  BMCR_ANENABLE);
5271  udelay(10);
5272  netif_carrier_off(tp->dev);
5273  }
5274  tg3_writephy(tp, MII_BMCR, new_bmcr);
5275  bmcr = new_bmcr;
5276  err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5277  err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5278  if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
5279  ASIC_REV_5714) {
5281  bmsr |= BMSR_LSTATUS;
5282  else
5283  bmsr &= ~BMSR_LSTATUS;
5284  }
5286  }
5287  }
5288 
5289  if (bmsr & BMSR_LSTATUS) {
5290  current_speed = SPEED_1000;
5291  current_link_up = 1;
5292  if (bmcr & BMCR_FULLDPLX)
5293  current_duplex = DUPLEX_FULL;
5294  else
5295  current_duplex = DUPLEX_HALF;
5296 
5297  local_adv = 0;
5298  remote_adv = 0;
5299 
5300  if (bmcr & BMCR_ANENABLE) {
5301  u32 common;
5302 
5303  err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5304  err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5305  common = local_adv & remote_adv;
5306  if (common & (ADVERTISE_1000XHALF |
5308  if (common & ADVERTISE_1000XFULL)
5309  current_duplex = DUPLEX_FULL;
5310  else
5311  current_duplex = DUPLEX_HALF;
5312 
5313  tp->link_config.rmt_adv =
5314  mii_adv_to_ethtool_adv_x(remote_adv);
5315  } else if (!tg3_flag(tp, 5780_CLASS)) {
5316  /* Link is up via parallel detect */
5317  } else {
5318  current_link_up = 0;
5319  }
5320  }
5321  }
5322 
5323  if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
5324  tg3_setup_flow_control(tp, local_adv, remote_adv);
5325 
5327  if (tp->link_config.active_duplex == DUPLEX_HALF)
5329 
5330  tw32_f(MAC_MODE, tp->mac_mode);
5331  udelay(40);
5332 
5334 
5335  tp->link_config.active_speed = current_speed;
5336  tp->link_config.active_duplex = current_duplex;
5337 
5338  if (current_link_up != netif_carrier_ok(tp->dev)) {
5339  if (current_link_up)
5340  netif_carrier_on(tp->dev);
5341  else {
5342  netif_carrier_off(tp->dev);
5344  }
5345  tg3_link_report(tp);
5346  }
5347  return err;
5348 }
5349 
5350 static void tg3_serdes_parallel_detect(struct tg3 *tp)
5351 {
5352  if (tp->serdes_counter) {
5353  /* Give autoneg time to complete. */
5354  tp->serdes_counter--;
5355  return;
5356  }
5357 
5358  if (!netif_carrier_ok(tp->dev) &&
5359  (tp->link_config.autoneg == AUTONEG_ENABLE)) {
5360  u32 bmcr;
5361 
5362  tg3_readphy(tp, MII_BMCR, &bmcr);
5363  if (bmcr & BMCR_ANENABLE) {
5364  u32 phy1, phy2;
5365 
5366  /* Select shadow register 0x1f */
5367  tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
5368  tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
5369 
5370  /* Select expansion interrupt status register */
5371  tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5373  tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5374  tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5375 
5376  if ((phy1 & 0x10) && !(phy2 & 0x20)) {
5377  /* We have signal detect and not receiving
5378  * config code words, link is up by parallel
5379  * detection.
5380  */
5381 
5382  bmcr &= ~BMCR_ANENABLE;
5383  bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
5384  tg3_writephy(tp, MII_BMCR, bmcr);
5386  }
5387  }
5388  } else if (netif_carrier_ok(tp->dev) &&
5389  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
5391  u32 phy2;
5392 
5393  /* Select expansion interrupt status register */
5394  tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
5396  tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
5397  if (phy2 & 0x20) {
5398  u32 bmcr;
5399 
5400  /* Config code words received, turn on autoneg. */
5401  tg3_readphy(tp, MII_BMCR, &bmcr);
5402  tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
5403 
5405 
5406  }
5407  }
5408 }
5409 
5410 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
5411 {
5412  u32 val;
5413  int err;
5414 
5415  if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
5416  err = tg3_setup_fiber_phy(tp, force_reset);
5417  else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
5418  err = tg3_setup_fiber_mii_phy(tp, force_reset);
5419  else
5420  err = tg3_setup_copper_phy(tp, force_reset);
5421 
5423  u32 scale;
5424 
5426  if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
5427  scale = 65;
5428  else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
5429  scale = 6;
5430  else
5431  scale = 12;
5432 
5434  val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
5435  tw32(GRC_MISC_CFG, val);
5436  }
5437 
5438  val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5439  (6 << TX_LENGTHS_IPG_SHIFT);
5441  val |= tr32(MAC_TX_LENGTHS) &
5444 
5445  if (tp->link_config.active_speed == SPEED_1000 &&
5446  tp->link_config.active_duplex == DUPLEX_HALF)
5447  tw32(MAC_TX_LENGTHS, val |
5448  (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
5449  else
5450  tw32(MAC_TX_LENGTHS, val |
5451  (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5452 
5453  if (!tg3_flag(tp, 5705_PLUS)) {
5454  if (netif_carrier_ok(tp->dev)) {
5456  tp->coal.stats_block_coalesce_usecs);
5457  } else {
5459  }
5460  }
5461 
5462  if (tg3_flag(tp, ASPM_WORKAROUND)) {
5463  val = tr32(PCIE_PWR_MGMT_THRESH);
5464  if (!netif_carrier_ok(tp->dev))
5465  val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
5466  tp->pwrmgmt_thresh;
5467  else
5469  tw32(PCIE_PWR_MGMT_THRESH, val);
5470  }
5471 
5472  return err;
5473 }
5474 
5475 static inline int tg3_irq_sync(struct tg3 *tp)
5476 {
5477  return tp->irq_sync;
5478 }
5479 
5480 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
5481 {
5482  int i;
5483 
5484  dst = (u32 *)((u8 *)dst + off);
5485  for (i = 0; i < len; i += sizeof(u32))
5486  *dst++ = tr32(off + i);
5487 }
5488 
5489 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
5490 {
5491  tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
5492  tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
5493  tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
5494  tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
5495  tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
5496  tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
5497  tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
5498  tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
5499  tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
5500  tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
5501  tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
5502  tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
5503  tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
5504  tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
5505  tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
5506  tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
5507  tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
5508  tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
5509  tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
5510 
5511  if (tg3_flag(tp, SUPPORT_MSIX))
5512  tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
5513 
5514  tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
5515  tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
5516  tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
5517  tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
5518  tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
5519  tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
5520  tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
5521  tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
5522 
5523  if (!tg3_flag(tp, 5705_PLUS)) {
5524  tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
5525  tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
5526  tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
5527  }
5528 
5529  tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
5530  tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
5531  tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
5532  tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
5533  tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
5534 
5535  if (tg3_flag(tp, NVRAM))
5536  tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
5537 }
5538 
5539 static void tg3_dump_state(struct tg3 *tp)
5540 {
5541  int i;
5542  u32 *regs;
5543 
5544  regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
5545  if (!regs) {
5546  netdev_err(tp->dev, "Failed allocating register dump buffer\n");
5547  return;
5548  }
5549 
5550  if (tg3_flag(tp, PCI_EXPRESS)) {
5551  /* Read up to but not including private PCI registers */
5552  for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
5553  regs[i / sizeof(u32)] = tr32(i);
5554  } else
5555  tg3_dump_legacy_regs(tp, regs);
5556 
5557  for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
5558  if (!regs[i + 0] && !regs[i + 1] &&
5559  !regs[i + 2] && !regs[i + 3])
5560  continue;
5561 
5562  netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
5563  i * 4,
5564  regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
5565  }
5566 
5567  kfree(regs);
5568 
5569  for (i = 0; i < tp->irq_cnt; i++) {
5570  struct tg3_napi *tnapi = &tp->napi[i];
5571 
5572  /* SW status block */
5573  netdev_err(tp->dev,
5574  "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
5575  i,
5576  tnapi->hw_status->status,
5577  tnapi->hw_status->status_tag,
5578  tnapi->hw_status->rx_jumbo_consumer,
5579  tnapi->hw_status->rx_consumer,
5580  tnapi->hw_status->rx_mini_consumer,
5581  tnapi->hw_status->idx[0].rx_producer,
5582  tnapi->hw_status->idx[0].tx_consumer);
5583 
5584  netdev_err(tp->