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twl4030.c
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1 /*
2  * ALSA SoC TWL4030 codec driver
3  *
4  * Author: Steve Sakoman, <[email protected]>
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * version 2 as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful, but
11  * WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13  * General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18  * 02110-1301 USA
19  *
20  */
21 
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/pm.h>
27 #include <linux/i2c.h>
28 #include <linux/platform_device.h>
29 #include <linux/of.h>
30 #include <linux/of_gpio.h>
31 #include <linux/i2c/twl.h>
32 #include <linux/slab.h>
33 #include <linux/gpio.h>
34 #include <sound/core.h>
35 #include <sound/pcm.h>
36 #include <sound/pcm_params.h>
37 #include <sound/soc.h>
38 #include <sound/initval.h>
39 #include <sound/tlv.h>
40 
41 /* Register descriptions are here */
42 #include <linux/mfd/twl4030-audio.h>
43 
44 /* Shadow register used by the audio driver */
45 #define TWL4030_REG_SW_SHADOW 0x4A
46 #define TWL4030_CACHEREGNUM (TWL4030_REG_SW_SHADOW + 1)
47 
48 /* TWL4030_REG_SW_SHADOW (0x4A) Fields */
49 #define TWL4030_HFL_EN 0x01
50 #define TWL4030_HFR_EN 0x02
51 
52 /*
53  * twl4030 register cache & default register settings
54  */
55 static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
56  0x00, /* this register not used */
57  0x00, /* REG_CODEC_MODE (0x1) */
58  0x00, /* REG_OPTION (0x2) */
59  0x00, /* REG_UNKNOWN (0x3) */
60  0x00, /* REG_MICBIAS_CTL (0x4) */
61  0x00, /* REG_ANAMICL (0x5) */
62  0x00, /* REG_ANAMICR (0x6) */
63  0x00, /* REG_AVADC_CTL (0x7) */
64  0x00, /* REG_ADCMICSEL (0x8) */
65  0x00, /* REG_DIGMIXING (0x9) */
66  0x0f, /* REG_ATXL1PGA (0xA) */
67  0x0f, /* REG_ATXR1PGA (0xB) */
68  0x0f, /* REG_AVTXL2PGA (0xC) */
69  0x0f, /* REG_AVTXR2PGA (0xD) */
70  0x00, /* REG_AUDIO_IF (0xE) */
71  0x00, /* REG_VOICE_IF (0xF) */
72  0x3f, /* REG_ARXR1PGA (0x10) */
73  0x3f, /* REG_ARXL1PGA (0x11) */
74  0x3f, /* REG_ARXR2PGA (0x12) */
75  0x3f, /* REG_ARXL2PGA (0x13) */
76  0x25, /* REG_VRXPGA (0x14) */
77  0x00, /* REG_VSTPGA (0x15) */
78  0x00, /* REG_VRX2ARXPGA (0x16) */
79  0x00, /* REG_AVDAC_CTL (0x17) */
80  0x00, /* REG_ARX2VTXPGA (0x18) */
81  0x32, /* REG_ARXL1_APGA_CTL (0x19) */
82  0x32, /* REG_ARXR1_APGA_CTL (0x1A) */
83  0x32, /* REG_ARXL2_APGA_CTL (0x1B) */
84  0x32, /* REG_ARXR2_APGA_CTL (0x1C) */
85  0x00, /* REG_ATX2ARXPGA (0x1D) */
86  0x00, /* REG_BT_IF (0x1E) */
87  0x55, /* REG_BTPGA (0x1F) */
88  0x00, /* REG_BTSTPGA (0x20) */
89  0x00, /* REG_EAR_CTL (0x21) */
90  0x00, /* REG_HS_SEL (0x22) */
91  0x00, /* REG_HS_GAIN_SET (0x23) */
92  0x00, /* REG_HS_POPN_SET (0x24) */
93  0x00, /* REG_PREDL_CTL (0x25) */
94  0x00, /* REG_PREDR_CTL (0x26) */
95  0x00, /* REG_PRECKL_CTL (0x27) */
96  0x00, /* REG_PRECKR_CTL (0x28) */
97  0x00, /* REG_HFL_CTL (0x29) */
98  0x00, /* REG_HFR_CTL (0x2A) */
99  0x05, /* REG_ALC_CTL (0x2B) */
100  0x00, /* REG_ALC_SET1 (0x2C) */
101  0x00, /* REG_ALC_SET2 (0x2D) */
102  0x00, /* REG_BOOST_CTL (0x2E) */
103  0x00, /* REG_SOFTVOL_CTL (0x2F) */
104  0x13, /* REG_DTMF_FREQSEL (0x30) */
105  0x00, /* REG_DTMF_TONEXT1H (0x31) */
106  0x00, /* REG_DTMF_TONEXT1L (0x32) */
107  0x00, /* REG_DTMF_TONEXT2H (0x33) */
108  0x00, /* REG_DTMF_TONEXT2L (0x34) */
109  0x79, /* REG_DTMF_TONOFF (0x35) */
110  0x11, /* REG_DTMF_WANONOFF (0x36) */
111  0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
112  0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
113  0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
114  0x06, /* REG_APLL_CTL (0x3A) */
115  0x00, /* REG_DTMF_CTL (0x3B) */
116  0x44, /* REG_DTMF_PGA_CTL2 (0x3C) */
117  0x69, /* REG_DTMF_PGA_CTL1 (0x3D) */
118  0x00, /* REG_MISC_SET_1 (0x3E) */
119  0x00, /* REG_PCMBTMUX (0x3F) */
120  0x00, /* not used (0x40) */
121  0x00, /* not used (0x41) */
122  0x00, /* not used (0x42) */
123  0x00, /* REG_RX_PATH_SEL (0x43) */
124  0x32, /* REG_VDL_APGA_CTL (0x44) */
125  0x00, /* REG_VIBRA_CTL (0x45) */
126  0x00, /* REG_VIBRA_SET (0x46) */
127  0x00, /* REG_VIBRA_PWM_SET (0x47) */
128  0x00, /* REG_ANAMIC_GAIN (0x48) */
129  0x00, /* REG_MISC_SET_2 (0x49) */
130  0x00, /* REG_SW_SHADOW (0x4A) - Shadow, non HW register */
131 };
132 
133 /* codec private data */
134 struct twl4030_priv {
135  struct snd_soc_codec codec;
136 
137  unsigned int codec_powered;
138 
139  /* reference counts of AIF/APLL users */
140  unsigned int apll_enabled;
141 
142  struct snd_pcm_substream *master_substream;
143  struct snd_pcm_substream *slave_substream;
144 
145  unsigned int configured;
146  unsigned int rate;
147  unsigned int sample_bits;
148  unsigned int channels;
149 
150  unsigned int sysclk;
151 
152  /* Output (with associated amp) states */
153  u8 hsl_enabled, hsr_enabled;
154  u8 earpiece_enabled;
155  u8 predrivel_enabled, predriver_enabled;
156  u8 carkitl_enabled, carkitr_enabled;
157 
158  struct twl4030_codec_data *pdata;
159 };
160 
161 /*
162  * read twl4030 register cache
163  */
164 static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
165  unsigned int reg)
166 {
167  u8 *cache = codec->reg_cache;
168 
169  if (reg >= TWL4030_CACHEREGNUM)
170  return -EIO;
171 
172  return cache[reg];
173 }
174 
175 /*
176  * write twl4030 register cache
177  */
178 static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
179  u8 reg, u8 value)
180 {
181  u8 *cache = codec->reg_cache;
182 
183  if (reg >= TWL4030_CACHEREGNUM)
184  return;
185  cache[reg] = value;
186 }
187 
188 /*
189  * write to the twl4030 register space
190  */
191 static int twl4030_write(struct snd_soc_codec *codec,
192  unsigned int reg, unsigned int value)
193 {
194  struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
195  int write_to_reg = 0;
196 
197  twl4030_write_reg_cache(codec, reg, value);
198  if (likely(reg < TWL4030_REG_SW_SHADOW)) {
199  /* Decide if the given register can be written */
200  switch (reg) {
201  case TWL4030_REG_EAR_CTL:
202  if (twl4030->earpiece_enabled)
203  write_to_reg = 1;
204  break;
205  case TWL4030_REG_PREDL_CTL:
206  if (twl4030->predrivel_enabled)
207  write_to_reg = 1;
208  break;
209  case TWL4030_REG_PREDR_CTL:
210  if (twl4030->predriver_enabled)
211  write_to_reg = 1;
212  break;
213  case TWL4030_REG_PRECKL_CTL:
214  if (twl4030->carkitl_enabled)
215  write_to_reg = 1;
216  break;
217  case TWL4030_REG_PRECKR_CTL:
218  if (twl4030->carkitr_enabled)
219  write_to_reg = 1;
220  break;
221  case TWL4030_REG_HS_GAIN_SET:
222  if (twl4030->hsl_enabled || twl4030->hsr_enabled)
223  write_to_reg = 1;
224  break;
225  default:
226  /* All other register can be written */
227  write_to_reg = 1;
228  break;
229  }
230  if (write_to_reg)
231  return twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
232  value, reg);
233  }
234  return 0;
235 }
236 
237 static inline void twl4030_wait_ms(int time)
238 {
239  if (time < 60) {
240  time *= 1000;
241  usleep_range(time, time + 500);
242  } else {
243  msleep(time);
244  }
245 }
246 
247 static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
248 {
249  struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
250  int mode;
251 
252  if (enable == twl4030->codec_powered)
253  return;
254 
255  if (enable)
256  mode = twl4030_audio_enable_resource(TWL4030_AUDIO_RES_POWER);
257  else
258  mode = twl4030_audio_disable_resource(TWL4030_AUDIO_RES_POWER);
259 
260  if (mode >= 0) {
261  twl4030_write_reg_cache(codec, TWL4030_REG_CODEC_MODE, mode);
262  twl4030->codec_powered = enable;
263  }
264 
265  /* REVISIT: this delay is present in TI sample drivers */
266  /* but there seems to be no TRM requirement for it */
267  udelay(10);
268 }
269 
270 static inline void twl4030_check_defaults(struct snd_soc_codec *codec)
271 {
272  int i, difference = 0;
273  u8 val;
274 
275  dev_dbg(codec->dev, "Checking TWL audio default configuration\n");
276  for (i = 1; i <= TWL4030_REG_MISC_SET_2; i++) {
277  twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &val, i);
278  if (val != twl4030_reg[i]) {
279  difference++;
280  dev_dbg(codec->dev,
281  "Reg 0x%02x: chip: 0x%02x driver: 0x%02x\n",
282  i, val, twl4030_reg[i]);
283  }
284  }
285  dev_dbg(codec->dev, "Found %d non-matching registers. %s\n",
286  difference, difference ? "Not OK" : "OK");
287 }
288 
289 static inline void twl4030_reset_registers(struct snd_soc_codec *codec)
290 {
291  int i;
292 
293  /* set all audio section registers to reasonable defaults */
294  for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
295  if (i != TWL4030_REG_APLL_CTL)
296  twl4030_write(codec, i, twl4030_reg[i]);
297 
298 }
299 
300 static void twl4030_setup_pdata_of(struct twl4030_codec_data *pdata,
301  struct device_node *node)
302 {
303  int value;
304 
305  of_property_read_u32(node, "ti,digimic_delay",
306  &pdata->digimic_delay);
307  of_property_read_u32(node, "ti,ramp_delay_value",
308  &pdata->ramp_delay_value);
309  of_property_read_u32(node, "ti,offset_cncl_path",
310  &pdata->offset_cncl_path);
311  if (!of_property_read_u32(node, "ti,hs_extmute", &value))
312  pdata->hs_extmute = value;
313 
314  pdata->hs_extmute_gpio = of_get_named_gpio(node,
315  "ti,hs_extmute_gpio", 0);
316  if (gpio_is_valid(pdata->hs_extmute_gpio))
317  pdata->hs_extmute = 1;
318 }
319 
320 static struct twl4030_codec_data *twl4030_get_pdata(struct snd_soc_codec *codec)
321 {
322  struct twl4030_codec_data *pdata = dev_get_platdata(codec->dev);
323  struct device_node *twl4030_codec_node = NULL;
324 
325  twl4030_codec_node = of_find_node_by_name(codec->dev->parent->of_node,
326  "codec");
327 
328  if (!pdata && twl4030_codec_node) {
329  pdata = devm_kzalloc(codec->dev,
330  sizeof(struct twl4030_codec_data),
331  GFP_KERNEL);
332  if (!pdata) {
333  dev_err(codec->dev, "Can not allocate memory\n");
334  return NULL;
335  }
336  twl4030_setup_pdata_of(pdata, twl4030_codec_node);
337  }
338 
339  return pdata;
340 }
341 
342 static void twl4030_init_chip(struct snd_soc_codec *codec)
343 {
344  struct twl4030_codec_data *pdata;
345  struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
346  u8 reg, byte;
347  int i = 0;
348 
349  pdata = twl4030_get_pdata(codec);
350 
351  if (pdata && pdata->hs_extmute &&
352  gpio_is_valid(pdata->hs_extmute_gpio)) {
353  int ret;
354 
355  if (!pdata->hs_extmute_gpio)
356  dev_warn(codec->dev,
357  "Extmute GPIO is 0 is this correct?\n");
358 
359  ret = gpio_request_one(pdata->hs_extmute_gpio,
360  GPIOF_OUT_INIT_LOW, "hs_extmute");
361  if (ret) {
362  dev_err(codec->dev, "Failed to get hs_extmute GPIO\n");
363  pdata->hs_extmute_gpio = -1;
364  }
365  }
366 
367  /* Check defaults, if instructed before anything else */
368  if (pdata && pdata->check_defaults)
369  twl4030_check_defaults(codec);
370 
371  /* Reset registers, if no setup data or if instructed to do so */
372  if (!pdata || (pdata && pdata->reset_registers))
373  twl4030_reset_registers(codec);
374 
375  /* Refresh APLL_CTL register from HW */
376  twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
377  TWL4030_REG_APLL_CTL);
378  twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, byte);
379 
380  /* anti-pop when changing analog gain */
381  reg = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
382  twl4030_write(codec, TWL4030_REG_MISC_SET_1,
383  reg | TWL4030_SMOOTH_ANAVOL_EN);
384 
385  twl4030_write(codec, TWL4030_REG_OPTION,
386  TWL4030_ATXL1_EN | TWL4030_ATXR1_EN |
387  TWL4030_ARXL2_EN | TWL4030_ARXR2_EN);
388 
389  /* REG_ARXR2_APGA_CTL reset according to the TRM: 0dB, DA_EN */
390  twl4030_write(codec, TWL4030_REG_ARXR2_APGA_CTL, 0x32);
391 
392  /* Machine dependent setup */
393  if (!pdata)
394  return;
395 
396  twl4030->pdata = pdata;
397 
398  reg = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
399  reg &= ~TWL4030_RAMP_DELAY;
400  reg |= (pdata->ramp_delay_value << 2);
401  twl4030_write_reg_cache(codec, TWL4030_REG_HS_POPN_SET, reg);
402 
403  /* initiate offset cancellation */
404  twl4030_codec_enable(codec, 1);
405 
406  reg = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
407  reg &= ~TWL4030_OFFSET_CNCL_SEL;
408  reg |= pdata->offset_cncl_path;
409  twl4030_write(codec, TWL4030_REG_ANAMICL,
410  reg | TWL4030_CNCL_OFFSET_START);
411 
412  /*
413  * Wait for offset cancellation to complete.
414  * Since this takes a while, do not slam the i2c.
415  * Start polling the status after ~20ms.
416  */
417  msleep(20);
418  do {
419  usleep_range(1000, 2000);
420  twl_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
421  TWL4030_REG_ANAMICL);
422  } while ((i++ < 100) &&
423  ((byte & TWL4030_CNCL_OFFSET_START) ==
424  TWL4030_CNCL_OFFSET_START));
425 
426  /* Make sure that the reg_cache has the same value as the HW */
427  twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
428 
429  twl4030_codec_enable(codec, 0);
430 }
431 
432 static void twl4030_apll_enable(struct snd_soc_codec *codec, int enable)
433 {
434  struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
435  int status = -1;
436 
437  if (enable) {
438  twl4030->apll_enabled++;
439  if (twl4030->apll_enabled == 1)
440  status = twl4030_audio_enable_resource(
441  TWL4030_AUDIO_RES_APLL);
442  } else {
443  twl4030->apll_enabled--;
444  if (!twl4030->apll_enabled)
445  status = twl4030_audio_disable_resource(
446  TWL4030_AUDIO_RES_APLL);
447  }
448 
449  if (status >= 0)
450  twl4030_write_reg_cache(codec, TWL4030_REG_APLL_CTL, status);
451 }
452 
453 /* Earpiece */
454 static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
455  SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
456  SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
457  SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
458  SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
459 };
460 
461 /* PreDrive Left */
462 static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
463  SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
464  SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
465  SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
466  SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
467 };
468 
469 /* PreDrive Right */
470 static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
471  SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
472  SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
473  SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
474  SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
475 };
476 
477 /* Headset Left */
478 static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
479  SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
480  SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
481  SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
482 };
483 
484 /* Headset Right */
485 static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
486  SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
487  SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
488  SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
489 };
490 
491 /* Carkit Left */
492 static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
493  SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
494  SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
495  SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
496 };
497 
498 /* Carkit Right */
499 static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
500  SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
501  SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
502  SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
503 };
504 
505 /* Handsfree Left */
506 static const char *twl4030_handsfreel_texts[] =
507  {"Voice", "AudioL1", "AudioL2", "AudioR2"};
508 
509 static const struct soc_enum twl4030_handsfreel_enum =
510  SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
511  ARRAY_SIZE(twl4030_handsfreel_texts),
512  twl4030_handsfreel_texts);
513 
514 static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
515 SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
516 
517 /* Handsfree Left virtual mute */
518 static const struct snd_kcontrol_new twl4030_dapm_handsfreelmute_control =
519  SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 0, 1, 0);
520 
521 /* Handsfree Right */
522 static const char *twl4030_handsfreer_texts[] =
523  {"Voice", "AudioR1", "AudioR2", "AudioL2"};
524 
525 static const struct soc_enum twl4030_handsfreer_enum =
526  SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
527  ARRAY_SIZE(twl4030_handsfreer_texts),
528  twl4030_handsfreer_texts);
529 
530 static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
531 SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
532 
533 /* Handsfree Right virtual mute */
534 static const struct snd_kcontrol_new twl4030_dapm_handsfreermute_control =
535  SOC_DAPM_SINGLE("Switch", TWL4030_REG_SW_SHADOW, 1, 1, 0);
536 
537 /* Vibra */
538 /* Vibra audio path selection */
539 static const char *twl4030_vibra_texts[] =
540  {"AudioL1", "AudioR1", "AudioL2", "AudioR2"};
541 
542 static const struct soc_enum twl4030_vibra_enum =
543  SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 2,
544  ARRAY_SIZE(twl4030_vibra_texts),
545  twl4030_vibra_texts);
546 
547 static const struct snd_kcontrol_new twl4030_dapm_vibra_control =
548 SOC_DAPM_ENUM("Route", twl4030_vibra_enum);
549 
550 /* Vibra path selection: local vibrator (PWM) or audio driven */
551 static const char *twl4030_vibrapath_texts[] =
552  {"Local vibrator", "Audio"};
553 
554 static const struct soc_enum twl4030_vibrapath_enum =
555  SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 4,
556  ARRAY_SIZE(twl4030_vibrapath_texts),
557  twl4030_vibrapath_texts);
558 
559 static const struct snd_kcontrol_new twl4030_dapm_vibrapath_control =
560 SOC_DAPM_ENUM("Route", twl4030_vibrapath_enum);
561 
562 /* Left analog microphone selection */
563 static const struct snd_kcontrol_new twl4030_dapm_analoglmic_controls[] = {
564  SOC_DAPM_SINGLE("Main Mic Capture Switch",
565  TWL4030_REG_ANAMICL, 0, 1, 0),
566  SOC_DAPM_SINGLE("Headset Mic Capture Switch",
567  TWL4030_REG_ANAMICL, 1, 1, 0),
568  SOC_DAPM_SINGLE("AUXL Capture Switch",
569  TWL4030_REG_ANAMICL, 2, 1, 0),
570  SOC_DAPM_SINGLE("Carkit Mic Capture Switch",
571  TWL4030_REG_ANAMICL, 3, 1, 0),
572 };
573 
574 /* Right analog microphone selection */
575 static const struct snd_kcontrol_new twl4030_dapm_analogrmic_controls[] = {
576  SOC_DAPM_SINGLE("Sub Mic Capture Switch", TWL4030_REG_ANAMICR, 0, 1, 0),
577  SOC_DAPM_SINGLE("AUXR Capture Switch", TWL4030_REG_ANAMICR, 2, 1, 0),
578 };
579 
580 /* TX1 L/R Analog/Digital microphone selection */
581 static const char *twl4030_micpathtx1_texts[] =
582  {"Analog", "Digimic0"};
583 
584 static const struct soc_enum twl4030_micpathtx1_enum =
585  SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
586  ARRAY_SIZE(twl4030_micpathtx1_texts),
587  twl4030_micpathtx1_texts);
588 
589 static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
590 SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
591 
592 /* TX2 L/R Analog/Digital microphone selection */
593 static const char *twl4030_micpathtx2_texts[] =
594  {"Analog", "Digimic1"};
595 
596 static const struct soc_enum twl4030_micpathtx2_enum =
597  SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
598  ARRAY_SIZE(twl4030_micpathtx2_texts),
599  twl4030_micpathtx2_texts);
600 
601 static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
602 SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
603 
604 /* Analog bypass for AudioR1 */
605 static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
606  SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
607 
608 /* Analog bypass for AudioL1 */
609 static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
610  SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
611 
612 /* Analog bypass for AudioR2 */
613 static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
614  SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
615 
616 /* Analog bypass for AudioL2 */
617 static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
618  SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
619 
620 /* Analog bypass for Voice */
621 static const struct snd_kcontrol_new twl4030_dapm_abypassv_control =
622  SOC_DAPM_SINGLE("Switch", TWL4030_REG_VDL_APGA_CTL, 2, 1, 0);
623 
624 /* Digital bypass gain, mute instead of -30dB */
625 static const unsigned int twl4030_dapm_dbypass_tlv[] = {
626  TLV_DB_RANGE_HEAD(3),
627  0, 1, TLV_DB_SCALE_ITEM(-3000, 600, 1),
628  2, 3, TLV_DB_SCALE_ITEM(-2400, 0, 0),
629  4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
630 };
631 
632 /* Digital bypass left (TX1L -> RX2L) */
633 static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
634  SOC_DAPM_SINGLE_TLV("Volume",
635  TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
636  twl4030_dapm_dbypass_tlv);
637 
638 /* Digital bypass right (TX1R -> RX2R) */
639 static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
640  SOC_DAPM_SINGLE_TLV("Volume",
641  TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
642  twl4030_dapm_dbypass_tlv);
643 
644 /*
645  * Voice Sidetone GAIN volume control:
646  * from -51 to -10 dB in 1 dB steps (mute instead of -51 dB)
647  */
648 static DECLARE_TLV_DB_SCALE(twl4030_dapm_dbypassv_tlv, -5100, 100, 1);
649 
650 /* Digital bypass voice: sidetone (VUL -> VDL)*/
651 static const struct snd_kcontrol_new twl4030_dapm_dbypassv_control =
652  SOC_DAPM_SINGLE_TLV("Volume",
653  TWL4030_REG_VSTPGA, 0, 0x29, 0,
654  twl4030_dapm_dbypassv_tlv);
655 
656 /*
657  * Output PGA builder:
658  * Handle the muting and unmuting of the given output (turning off the
659  * amplifier associated with the output pin)
660  * On mute bypass the reg_cache and write 0 to the register
661  * On unmute: restore the register content from the reg_cache
662  * Outputs handled in this way: Earpiece, PreDrivL/R, CarkitL/R
663  */
664 #define TWL4030_OUTPUT_PGA(pin_name, reg, mask) \
665 static int pin_name##pga_event(struct snd_soc_dapm_widget *w, \
666  struct snd_kcontrol *kcontrol, int event) \
667 { \
668  struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec); \
669  \
670  switch (event) { \
671  case SND_SOC_DAPM_POST_PMU: \
672  twl4030->pin_name##_enabled = 1; \
673  twl4030_write(w->codec, reg, \
674  twl4030_read_reg_cache(w->codec, reg)); \
675  break; \
676  case SND_SOC_DAPM_POST_PMD: \
677  twl4030->pin_name##_enabled = 0; \
678  twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, \
679  0, reg); \
680  break; \
681  } \
682  return 0; \
683 }
684 
685 TWL4030_OUTPUT_PGA(earpiece, TWL4030_REG_EAR_CTL, TWL4030_EAR_GAIN);
686 TWL4030_OUTPUT_PGA(predrivel, TWL4030_REG_PREDL_CTL, TWL4030_PREDL_GAIN);
687 TWL4030_OUTPUT_PGA(predriver, TWL4030_REG_PREDR_CTL, TWL4030_PREDR_GAIN);
688 TWL4030_OUTPUT_PGA(carkitl, TWL4030_REG_PRECKL_CTL, TWL4030_PRECKL_GAIN);
689 TWL4030_OUTPUT_PGA(carkitr, TWL4030_REG_PRECKR_CTL, TWL4030_PRECKR_GAIN);
690 
691 static void handsfree_ramp(struct snd_soc_codec *codec, int reg, int ramp)
692 {
693  unsigned char hs_ctl;
694 
695  hs_ctl = twl4030_read_reg_cache(codec, reg);
696 
697  if (ramp) {
698  /* HF ramp-up */
699  hs_ctl |= TWL4030_HF_CTL_REF_EN;
700  twl4030_write(codec, reg, hs_ctl);
701  udelay(10);
702  hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
703  twl4030_write(codec, reg, hs_ctl);
704  udelay(40);
705  hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
706  hs_ctl |= TWL4030_HF_CTL_HB_EN;
707  twl4030_write(codec, reg, hs_ctl);
708  } else {
709  /* HF ramp-down */
710  hs_ctl &= ~TWL4030_HF_CTL_LOOP_EN;
711  hs_ctl &= ~TWL4030_HF_CTL_HB_EN;
712  twl4030_write(codec, reg, hs_ctl);
713  hs_ctl &= ~TWL4030_HF_CTL_RAMP_EN;
714  twl4030_write(codec, reg, hs_ctl);
715  udelay(40);
716  hs_ctl &= ~TWL4030_HF_CTL_REF_EN;
717  twl4030_write(codec, reg, hs_ctl);
718  }
719 }
720 
721 static int handsfreelpga_event(struct snd_soc_dapm_widget *w,
722  struct snd_kcontrol *kcontrol, int event)
723 {
724  switch (event) {
725  case SND_SOC_DAPM_POST_PMU:
726  handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 1);
727  break;
728  case SND_SOC_DAPM_POST_PMD:
729  handsfree_ramp(w->codec, TWL4030_REG_HFL_CTL, 0);
730  break;
731  }
732  return 0;
733 }
734 
735 static int handsfreerpga_event(struct snd_soc_dapm_widget *w,
736  struct snd_kcontrol *kcontrol, int event)
737 {
738  switch (event) {
739  case SND_SOC_DAPM_POST_PMU:
740  handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 1);
741  break;
742  case SND_SOC_DAPM_POST_PMD:
743  handsfree_ramp(w->codec, TWL4030_REG_HFR_CTL, 0);
744  break;
745  }
746  return 0;
747 }
748 
749 static int vibramux_event(struct snd_soc_dapm_widget *w,
750  struct snd_kcontrol *kcontrol, int event)
751 {
752  twl4030_write(w->codec, TWL4030_REG_VIBRA_SET, 0xff);
753  return 0;
754 }
755 
756 static int apll_event(struct snd_soc_dapm_widget *w,
757  struct snd_kcontrol *kcontrol, int event)
758 {
759  switch (event) {
760  case SND_SOC_DAPM_PRE_PMU:
761  twl4030_apll_enable(w->codec, 1);
762  break;
763  case SND_SOC_DAPM_POST_PMD:
764  twl4030_apll_enable(w->codec, 0);
765  break;
766  }
767  return 0;
768 }
769 
770 static int aif_event(struct snd_soc_dapm_widget *w,
771  struct snd_kcontrol *kcontrol, int event)
772 {
773  u8 audio_if;
774 
775  audio_if = twl4030_read_reg_cache(w->codec, TWL4030_REG_AUDIO_IF);
776  switch (event) {
777  case SND_SOC_DAPM_PRE_PMU:
778  /* Enable AIF */
779  /* enable the PLL before we use it to clock the DAI */
780  twl4030_apll_enable(w->codec, 1);
781 
782  twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
783  audio_if | TWL4030_AIF_EN);
784  break;
785  case SND_SOC_DAPM_POST_PMD:
786  /* disable the DAI before we stop it's source PLL */
787  twl4030_write(w->codec, TWL4030_REG_AUDIO_IF,
788  audio_if & ~TWL4030_AIF_EN);
789  twl4030_apll_enable(w->codec, 0);
790  break;
791  }
792  return 0;
793 }
794 
795 static void headset_ramp(struct snd_soc_codec *codec, int ramp)
796 {
797  unsigned char hs_gain, hs_pop;
798  struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
799  struct twl4030_codec_data *pdata = twl4030->pdata;
800  /* Base values for ramp delay calculation: 2^19 - 2^26 */
801  unsigned int ramp_base[] = {524288, 1048576, 2097152, 4194304,
802  8388608, 16777216, 33554432, 67108864};
803  unsigned int delay;
804 
805  hs_gain = twl4030_read_reg_cache(codec, TWL4030_REG_HS_GAIN_SET);
806  hs_pop = twl4030_read_reg_cache(codec, TWL4030_REG_HS_POPN_SET);
807  delay = (ramp_base[(hs_pop & TWL4030_RAMP_DELAY) >> 2] /
808  twl4030->sysclk) + 1;
809 
810  /* Enable external mute control, this dramatically reduces
811  * the pop-noise */
812  if (pdata && pdata->hs_extmute) {
813  if (gpio_is_valid(pdata->hs_extmute_gpio)) {
814  gpio_set_value(pdata->hs_extmute_gpio, 1);
815  } else {
816  hs_pop |= TWL4030_EXTMUTE;
817  twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
818  }
819  }
820 
821  if (ramp) {
822  /* Headset ramp-up according to the TRM */
823  hs_pop |= TWL4030_VMID_EN;
824  twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
825  /* Actually write to the register */
826  twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
827  hs_gain,
828  TWL4030_REG_HS_GAIN_SET);
829  hs_pop |= TWL4030_RAMP_EN;
830  twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
831  /* Wait ramp delay time + 1, so the VMID can settle */
832  twl4030_wait_ms(delay);
833  } else {
834  /* Headset ramp-down _not_ according to
835  * the TRM, but in a way that it is working */
836  hs_pop &= ~TWL4030_RAMP_EN;
837  twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
838  /* Wait ramp delay time + 1, so the VMID can settle */
839  twl4030_wait_ms(delay);
840  /* Bypass the reg_cache to mute the headset */
841  twl_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
842  hs_gain & (~0x0f),
843  TWL4030_REG_HS_GAIN_SET);
844 
845  hs_pop &= ~TWL4030_VMID_EN;
846  twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
847  }
848 
849  /* Disable external mute */
850  if (pdata && pdata->hs_extmute) {
851  if (gpio_is_valid(pdata->hs_extmute_gpio)) {
852  gpio_set_value(pdata->hs_extmute_gpio, 0);
853  } else {
854  hs_pop &= ~TWL4030_EXTMUTE;
855  twl4030_write(codec, TWL4030_REG_HS_POPN_SET, hs_pop);
856  }
857  }
858 }
859 
860 static int headsetlpga_event(struct snd_soc_dapm_widget *w,
861  struct snd_kcontrol *kcontrol, int event)
862 {
863  struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
864 
865  switch (event) {
866  case SND_SOC_DAPM_POST_PMU:
867  /* Do the ramp-up only once */
868  if (!twl4030->hsr_enabled)
869  headset_ramp(w->codec, 1);
870 
871  twl4030->hsl_enabled = 1;
872  break;
873  case SND_SOC_DAPM_POST_PMD:
874  /* Do the ramp-down only if both headsetL/R is disabled */
875  if (!twl4030->hsr_enabled)
876  headset_ramp(w->codec, 0);
877 
878  twl4030->hsl_enabled = 0;
879  break;
880  }
881  return 0;
882 }
883 
884 static int headsetrpga_event(struct snd_soc_dapm_widget *w,
885  struct snd_kcontrol *kcontrol, int event)
886 {
887  struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
888 
889  switch (event) {
890  case SND_SOC_DAPM_POST_PMU:
891  /* Do the ramp-up only once */
892  if (!twl4030->hsl_enabled)
893  headset_ramp(w->codec, 1);
894 
895  twl4030->hsr_enabled = 1;
896  break;
897  case SND_SOC_DAPM_POST_PMD:
898  /* Do the ramp-down only if both headsetL/R is disabled */
899  if (!twl4030->hsl_enabled)
900  headset_ramp(w->codec, 0);
901 
902  twl4030->hsr_enabled = 0;
903  break;
904  }
905  return 0;
906 }
907 
908 static int digimic_event(struct snd_soc_dapm_widget *w,
909  struct snd_kcontrol *kcontrol, int event)
910 {
911  struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(w->codec);
912  struct twl4030_codec_data *pdata = twl4030->pdata;
913 
914  if (pdata && pdata->digimic_delay)
915  twl4030_wait_ms(pdata->digimic_delay);
916  return 0;
917 }
918 
919 /*
920  * Some of the gain controls in TWL (mostly those which are associated with
921  * the outputs) are implemented in an interesting way:
922  * 0x0 : Power down (mute)
923  * 0x1 : 6dB
924  * 0x2 : 0 dB
925  * 0x3 : -6 dB
926  * Inverting not going to help with these.
927  * Custom volsw and volsw_2r get/put functions to handle these gain bits.
928  */
929 static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
930  struct snd_ctl_elem_value *ucontrol)
931 {
932  struct soc_mixer_control *mc =
933  (struct soc_mixer_control *)kcontrol->private_value;
934  struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
935  unsigned int reg = mc->reg;
936  unsigned int shift = mc->shift;
937  unsigned int rshift = mc->rshift;
938  int max = mc->max;
939  int mask = (1 << fls(max)) - 1;
940 
941  ucontrol->value.integer.value[0] =
942  (snd_soc_read(codec, reg) >> shift) & mask;
943  if (ucontrol->value.integer.value[0])
944  ucontrol->value.integer.value[0] =
945  max + 1 - ucontrol->value.integer.value[0];
946 
947  if (shift != rshift) {
948  ucontrol->value.integer.value[1] =
949  (snd_soc_read(codec, reg) >> rshift) & mask;
950  if (ucontrol->value.integer.value[1])
951  ucontrol->value.integer.value[1] =
952  max + 1 - ucontrol->value.integer.value[1];
953  }
954 
955  return 0;
956 }
957 
958 static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
959  struct snd_ctl_elem_value *ucontrol)
960 {
961  struct soc_mixer_control *mc =
962  (struct soc_mixer_control *)kcontrol->private_value;
963  struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
964  unsigned int reg = mc->reg;
965  unsigned int shift = mc->shift;
966  unsigned int rshift = mc->rshift;
967  int max = mc->max;
968  int mask = (1 << fls(max)) - 1;
969  unsigned short val, val2, val_mask;
970 
971  val = (ucontrol->value.integer.value[0] & mask);
972 
973  val_mask = mask << shift;
974  if (val)
975  val = max + 1 - val;
976  val = val << shift;
977  if (shift != rshift) {
978  val2 = (ucontrol->value.integer.value[1] & mask);
979  val_mask |= mask << rshift;
980  if (val2)
981  val2 = max + 1 - val2;
982  val |= val2 << rshift;
983  }
984  return snd_soc_update_bits(codec, reg, val_mask, val);
985 }
986 
987 static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
988  struct snd_ctl_elem_value *ucontrol)
989 {
990  struct soc_mixer_control *mc =
991  (struct soc_mixer_control *)kcontrol->private_value;
992  struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
993  unsigned int reg = mc->reg;
994  unsigned int reg2 = mc->rreg;
995  unsigned int shift = mc->shift;
996  int max = mc->max;
997  int mask = (1<<fls(max))-1;
998 
999  ucontrol->value.integer.value[0] =
1000  (snd_soc_read(codec, reg) >> shift) & mask;
1001  ucontrol->value.integer.value[1] =
1002  (snd_soc_read(codec, reg2) >> shift) & mask;
1003 
1004  if (ucontrol->value.integer.value[0])
1005  ucontrol->value.integer.value[0] =
1006  max + 1 - ucontrol->value.integer.value[0];
1007  if (ucontrol->value.integer.value[1])
1008  ucontrol->value.integer.value[1] =
1009  max + 1 - ucontrol->value.integer.value[1];
1010 
1011  return 0;
1012 }
1013 
1014 static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
1015  struct snd_ctl_elem_value *ucontrol)
1016 {
1017  struct soc_mixer_control *mc =
1018  (struct soc_mixer_control *)kcontrol->private_value;
1019  struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1020  unsigned int reg = mc->reg;
1021  unsigned int reg2 = mc->rreg;
1022  unsigned int shift = mc->shift;
1023  int max = mc->max;
1024  int mask = (1 << fls(max)) - 1;
1025  int err;
1026  unsigned short val, val2, val_mask;
1027 
1028  val_mask = mask << shift;
1029  val = (ucontrol->value.integer.value[0] & mask);
1030  val2 = (ucontrol->value.integer.value[1] & mask);
1031 
1032  if (val)
1033  val = max + 1 - val;
1034  if (val2)
1035  val2 = max + 1 - val2;
1036 
1037  val = val << shift;
1038  val2 = val2 << shift;
1039 
1040  err = snd_soc_update_bits(codec, reg, val_mask, val);
1041  if (err < 0)
1042  return err;
1043 
1044  err = snd_soc_update_bits(codec, reg2, val_mask, val2);
1045  return err;
1046 }
1047 
1048 /* Codec operation modes */
1049 static const char *twl4030_op_modes_texts[] = {
1050  "Option 2 (voice/audio)", "Option 1 (audio)"
1051 };
1052 
1053 static const struct soc_enum twl4030_op_modes_enum =
1054  SOC_ENUM_SINGLE(TWL4030_REG_CODEC_MODE, 0,
1055  ARRAY_SIZE(twl4030_op_modes_texts),
1056  twl4030_op_modes_texts);
1057 
1058 static int snd_soc_put_twl4030_opmode_enum_double(struct snd_kcontrol *kcontrol,
1059  struct snd_ctl_elem_value *ucontrol)
1060 {
1061  struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1062  struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1063  struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1064  unsigned short val;
1065  unsigned short mask;
1066 
1067  if (twl4030->configured) {
1068  dev_err(codec->dev,
1069  "operation mode cannot be changed on-the-fly\n");
1070  return -EBUSY;
1071  }
1072 
1073  if (ucontrol->value.enumerated.item[0] > e->max - 1)
1074  return -EINVAL;
1075 
1076  val = ucontrol->value.enumerated.item[0] << e->shift_l;
1077  mask = e->mask << e->shift_l;
1078  if (e->shift_l != e->shift_r) {
1079  if (ucontrol->value.enumerated.item[1] > e->max - 1)
1080  return -EINVAL;
1081  val |= ucontrol->value.enumerated.item[1] << e->shift_r;
1082  mask |= e->mask << e->shift_r;
1083  }
1084 
1085  return snd_soc_update_bits(codec, e->reg, mask, val);
1086 }
1087 
1088 /*
1089  * FGAIN volume control:
1090  * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
1091  */
1092 static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
1093 
1094 /*
1095  * CGAIN volume control:
1096  * 0 dB to 12 dB in 6 dB steps
1097  * value 2 and 3 means 12 dB
1098  */
1099 static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
1100 
1101 /*
1102  * Voice Downlink GAIN volume control:
1103  * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
1104  */
1105 static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
1106 
1107 /*
1108  * Analog playback gain
1109  * -24 dB to 12 dB in 2 dB steps
1110  */
1111 static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
1112 
1113 /*
1114  * Gain controls tied to outputs
1115  * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
1116  */
1117 static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
1118 
1119 /*
1120  * Gain control for earpiece amplifier
1121  * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
1122  */
1123 static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
1124 
1125 /*
1126  * Capture gain after the ADCs
1127  * from 0 dB to 31 dB in 1 dB steps
1128  */
1129 static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
1130 
1131 /*
1132  * Gain control for input amplifiers
1133  * 0 dB to 30 dB in 6 dB steps
1134  */
1135 static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
1136 
1137 /* AVADC clock priority */
1138 static const char *twl4030_avadc_clk_priority_texts[] = {
1139  "Voice high priority", "HiFi high priority"
1140 };
1141 
1142 static const struct soc_enum twl4030_avadc_clk_priority_enum =
1143  SOC_ENUM_SINGLE(TWL4030_REG_AVADC_CTL, 2,
1144  ARRAY_SIZE(twl4030_avadc_clk_priority_texts),
1145  twl4030_avadc_clk_priority_texts);
1146 
1147 static const char *twl4030_rampdelay_texts[] = {
1148  "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
1149  "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
1150  "3495/2581/1748 ms"
1151 };
1152 
1153 static const struct soc_enum twl4030_rampdelay_enum =
1154  SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
1155  ARRAY_SIZE(twl4030_rampdelay_texts),
1156  twl4030_rampdelay_texts);
1157 
1158 /* Vibra H-bridge direction mode */
1159 static const char *twl4030_vibradirmode_texts[] = {
1160  "Vibra H-bridge direction", "Audio data MSB",
1161 };
1162 
1163 static const struct soc_enum twl4030_vibradirmode_enum =
1164  SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 5,
1165  ARRAY_SIZE(twl4030_vibradirmode_texts),
1166  twl4030_vibradirmode_texts);
1167 
1168 /* Vibra H-bridge direction */
1169 static const char *twl4030_vibradir_texts[] = {
1170  "Positive polarity", "Negative polarity",
1171 };
1172 
1173 static const struct soc_enum twl4030_vibradir_enum =
1174  SOC_ENUM_SINGLE(TWL4030_REG_VIBRA_CTL, 1,
1175  ARRAY_SIZE(twl4030_vibradir_texts),
1176  twl4030_vibradir_texts);
1177 
1178 /* Digimic Left and right swapping */
1179 static const char *twl4030_digimicswap_texts[] = {
1180  "Not swapped", "Swapped",
1181 };
1182 
1183 static const struct soc_enum twl4030_digimicswap_enum =
1184  SOC_ENUM_SINGLE(TWL4030_REG_MISC_SET_1, 0,
1185  ARRAY_SIZE(twl4030_digimicswap_texts),
1186  twl4030_digimicswap_texts);
1187 
1188 static const struct snd_kcontrol_new twl4030_snd_controls[] = {
1189  /* Codec operation mode control */
1190  SOC_ENUM_EXT("Codec Operation Mode", twl4030_op_modes_enum,
1191  snd_soc_get_enum_double,
1192  snd_soc_put_twl4030_opmode_enum_double),
1193 
1194  /* Common playback gain controls */
1195  SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
1196  TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1197  0, 0x3f, 0, digital_fine_tlv),
1198  SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
1199  TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1200  0, 0x3f, 0, digital_fine_tlv),
1201 
1202  SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
1203  TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
1204  6, 0x2, 0, digital_coarse_tlv),
1205  SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
1206  TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
1207  6, 0x2, 0, digital_coarse_tlv),
1208 
1209  SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
1210  TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1211  3, 0x12, 1, analog_tlv),
1212  SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
1213  TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1214  3, 0x12, 1, analog_tlv),
1215  SOC_DOUBLE_R("DAC1 Analog Playback Switch",
1216  TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
1217  1, 1, 0),
1218  SOC_DOUBLE_R("DAC2 Analog Playback Switch",
1219  TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
1220  1, 1, 0),
1221 
1222  /* Common voice downlink gain controls */
1223  SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
1224  TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
1225 
1226  SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
1227  TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
1228 
1229  SOC_SINGLE("DAC Voice Analog Downlink Switch",
1230  TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
1231 
1232  /* Separate output gain controls */
1233  SOC_DOUBLE_R_EXT_TLV("PreDriv Playback Volume",
1234  TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
1235  4, 3, 0, snd_soc_get_volsw_r2_twl4030,
1236  snd_soc_put_volsw_r2_twl4030, output_tvl),
1237 
1238  SOC_DOUBLE_EXT_TLV("Headset Playback Volume",
1239  TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, snd_soc_get_volsw_twl4030,
1240  snd_soc_put_volsw_twl4030, output_tvl),
1241 
1242  SOC_DOUBLE_R_EXT_TLV("Carkit Playback Volume",
1243  TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
1244  4, 3, 0, snd_soc_get_volsw_r2_twl4030,
1245  snd_soc_put_volsw_r2_twl4030, output_tvl),
1246 
1247  SOC_SINGLE_EXT_TLV("Earpiece Playback Volume",
1248  TWL4030_REG_EAR_CTL, 4, 3, 0, snd_soc_get_volsw_twl4030,
1249  snd_soc_put_volsw_twl4030, output_ear_tvl),
1250 
1251  /* Common capture gain controls */
1252  SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
1253  TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
1254  0, 0x1f, 0, digital_capture_tlv),
1255  SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
1256  TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
1257  0, 0x1f, 0, digital_capture_tlv),
1258 
1259  SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
1260  0, 3, 5, 0, input_gain_tlv),
1261 
1262  SOC_ENUM("AVADC Clock Priority", twl4030_avadc_clk_priority_enum),
1263 
1264  SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
1265 
1266  SOC_ENUM("Vibra H-bridge mode", twl4030_vibradirmode_enum),
1267  SOC_ENUM("Vibra H-bridge direction", twl4030_vibradir_enum),
1268 
1269  SOC_ENUM("Digimic LR Swap", twl4030_digimicswap_enum),
1270 };
1271 
1272 static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
1273  /* Left channel inputs */
1274  SND_SOC_DAPM_INPUT("MAINMIC"),
1275  SND_SOC_DAPM_INPUT("HSMIC"),
1276  SND_SOC_DAPM_INPUT("AUXL"),
1277  SND_SOC_DAPM_INPUT("CARKITMIC"),
1278  /* Right channel inputs */
1279  SND_SOC_DAPM_INPUT("SUBMIC"),
1280  SND_SOC_DAPM_INPUT("AUXR"),
1281  /* Digital microphones (Stereo) */
1282  SND_SOC_DAPM_INPUT("DIGIMIC0"),
1283  SND_SOC_DAPM_INPUT("DIGIMIC1"),
1284 
1285  /* Outputs */
1286  SND_SOC_DAPM_OUTPUT("EARPIECE"),
1287  SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
1288  SND_SOC_DAPM_OUTPUT("PREDRIVER"),
1289  SND_SOC_DAPM_OUTPUT("HSOL"),
1290  SND_SOC_DAPM_OUTPUT("HSOR"),
1291  SND_SOC_DAPM_OUTPUT("CARKITL"),
1292  SND_SOC_DAPM_OUTPUT("CARKITR"),
1293  SND_SOC_DAPM_OUTPUT("HFL"),
1294  SND_SOC_DAPM_OUTPUT("HFR"),
1295  SND_SOC_DAPM_OUTPUT("VIBRA"),
1296 
1297  /* AIF and APLL clocks for running DAIs (including loopback) */
1298  SND_SOC_DAPM_OUTPUT("Virtual HiFi OUT"),
1299  SND_SOC_DAPM_INPUT("Virtual HiFi IN"),
1300  SND_SOC_DAPM_OUTPUT("Virtual Voice OUT"),
1301 
1302  /* DACs */
1303  SND_SOC_DAPM_DAC("DAC Right1", NULL, SND_SOC_NOPM, 0, 0),
1304  SND_SOC_DAPM_DAC("DAC Left1", NULL, SND_SOC_NOPM, 0, 0),
1305  SND_SOC_DAPM_DAC("DAC Right2", NULL, SND_SOC_NOPM, 0, 0),
1306  SND_SOC_DAPM_DAC("DAC Left2", NULL, SND_SOC_NOPM, 0, 0),
1307  SND_SOC_DAPM_DAC("DAC Voice", NULL, SND_SOC_NOPM, 0, 0),
1308 
1309  /* Analog bypasses */
1310  SND_SOC_DAPM_SWITCH("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1311  &twl4030_dapm_abypassr1_control),
1312  SND_SOC_DAPM_SWITCH("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
1313  &twl4030_dapm_abypassl1_control),
1314  SND_SOC_DAPM_SWITCH("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1315  &twl4030_dapm_abypassr2_control),
1316  SND_SOC_DAPM_SWITCH("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
1317  &twl4030_dapm_abypassl2_control),
1318  SND_SOC_DAPM_SWITCH("Voice Analog Loopback", SND_SOC_NOPM, 0, 0,
1319  &twl4030_dapm_abypassv_control),
1320 
1321  /* Master analog loopback switch */
1322  SND_SOC_DAPM_SUPPLY("FM Loop Enable", TWL4030_REG_MISC_SET_1, 5, 0,
1323  NULL, 0),
1324 
1325  /* Digital bypasses */
1326  SND_SOC_DAPM_SWITCH("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
1327  &twl4030_dapm_dbypassl_control),
1328  SND_SOC_DAPM_SWITCH("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
1329  &twl4030_dapm_dbypassr_control),
1330  SND_SOC_DAPM_SWITCH("Voice Digital Loopback", SND_SOC_NOPM, 0, 0,
1331  &twl4030_dapm_dbypassv_control),
1332 
1333  /* Digital mixers, power control for the physical DACs */
1334  SND_SOC_DAPM_MIXER("Digital R1 Playback Mixer",
1335  TWL4030_REG_AVDAC_CTL, 0, 0, NULL, 0),
1336  SND_SOC_DAPM_MIXER("Digital L1 Playback Mixer",
1337  TWL4030_REG_AVDAC_CTL, 1, 0, NULL, 0),
1338  SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1339  TWL4030_REG_AVDAC_CTL, 2, 0, NULL, 0),
1340  SND_SOC_DAPM_MIXER("Digital L2 Playback Mixer",
1341  TWL4030_REG_AVDAC_CTL, 3, 0, NULL, 0),
1342  SND_SOC_DAPM_MIXER("Digital Voice Playback Mixer",
1343  TWL4030_REG_AVDAC_CTL, 4, 0, NULL, 0),
1344 
1345  /* Analog mixers, power control for the physical PGAs */
1346  SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer",
1347  TWL4030_REG_ARXR1_APGA_CTL, 0, 0, NULL, 0),
1348  SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer",
1349  TWL4030_REG_ARXL1_APGA_CTL, 0, 0, NULL, 0),
1350  SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1351  TWL4030_REG_ARXR2_APGA_CTL, 0, 0, NULL, 0),
1352  SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer",
1353  TWL4030_REG_ARXL2_APGA_CTL, 0, 0, NULL, 0),
1354  SND_SOC_DAPM_MIXER("Analog Voice Playback Mixer",
1355  TWL4030_REG_VDL_APGA_CTL, 0, 0, NULL, 0),
1356 
1357  SND_SOC_DAPM_SUPPLY("APLL Enable", SND_SOC_NOPM, 0, 0, apll_event,
1358  SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1359 
1360  SND_SOC_DAPM_SUPPLY("AIF Enable", SND_SOC_NOPM, 0, 0, aif_event,
1361  SND_SOC_DAPM_PRE_PMU|SND_SOC_DAPM_POST_PMD),
1362 
1363  /* Output MIXER controls */
1364  /* Earpiece */
1365  SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
1366  &twl4030_dapm_earpiece_controls[0],
1367  ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
1368  SND_SOC_DAPM_PGA_E("Earpiece PGA", SND_SOC_NOPM,
1369  0, 0, NULL, 0, earpiecepga_event,
1370  SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1371  /* PreDrivL/R */
1372  SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
1373  &twl4030_dapm_predrivel_controls[0],
1374  ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
1375  SND_SOC_DAPM_PGA_E("PredriveL PGA", SND_SOC_NOPM,
1376  0, 0, NULL, 0, predrivelpga_event,
1377  SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1378  SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
1379  &twl4030_dapm_predriver_controls[0],
1380  ARRAY_SIZE(twl4030_dapm_predriver_controls)),
1381  SND_SOC_DAPM_PGA_E("PredriveR PGA", SND_SOC_NOPM,
1382  0, 0, NULL, 0, predriverpga_event,
1383  SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1384  /* HeadsetL/R */
1385  SND_SOC_DAPM_MIXER("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
1386  &twl4030_dapm_hsol_controls[0],
1387  ARRAY_SIZE(twl4030_dapm_hsol_controls)),
1388  SND_SOC_DAPM_PGA_E("HeadsetL PGA", SND_SOC_NOPM,
1389  0, 0, NULL, 0, headsetlpga_event,
1390  SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1391  SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
1392  &twl4030_dapm_hsor_controls[0],
1393  ARRAY_SIZE(twl4030_dapm_hsor_controls)),
1394  SND_SOC_DAPM_PGA_E("HeadsetR PGA", SND_SOC_NOPM,
1395  0, 0, NULL, 0, headsetrpga_event,
1396  SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1397  /* CarkitL/R */
1398  SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
1399  &twl4030_dapm_carkitl_controls[0],
1400  ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
1401  SND_SOC_DAPM_PGA_E("CarkitL PGA", SND_SOC_NOPM,
1402  0, 0, NULL, 0, carkitlpga_event,
1403  SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1404  SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
1405  &twl4030_dapm_carkitr_controls[0],
1406  ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
1407  SND_SOC_DAPM_PGA_E("CarkitR PGA", SND_SOC_NOPM,
1408  0, 0, NULL, 0, carkitrpga_event,
1409  SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1410 
1411  /* Output MUX controls */
1412  /* HandsfreeL/R */
1413  SND_SOC_DAPM_MUX("HandsfreeL Mux", SND_SOC_NOPM, 0, 0,
1414  &twl4030_dapm_handsfreel_control),
1415  SND_SOC_DAPM_SWITCH("HandsfreeL", SND_SOC_NOPM, 0, 0,
1416  &twl4030_dapm_handsfreelmute_control),
1417  SND_SOC_DAPM_PGA_E("HandsfreeL PGA", SND_SOC_NOPM,
1418  0, 0, NULL, 0, handsfreelpga_event,
1419  SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1420  SND_SOC_DAPM_MUX("HandsfreeR Mux", SND_SOC_NOPM, 5, 0,
1421  &twl4030_dapm_handsfreer_control),
1422  SND_SOC_DAPM_SWITCH("HandsfreeR", SND_SOC_NOPM, 0, 0,
1423  &twl4030_dapm_handsfreermute_control),
1424  SND_SOC_DAPM_PGA_E("HandsfreeR PGA", SND_SOC_NOPM,
1425  0, 0, NULL, 0, handsfreerpga_event,
1426  SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
1427  /* Vibra */
1428  SND_SOC_DAPM_MUX_E("Vibra Mux", TWL4030_REG_VIBRA_CTL, 0, 0,
1429  &twl4030_dapm_vibra_control, vibramux_event,
1430  SND_SOC_DAPM_PRE_PMU),
1431  SND_SOC_DAPM_MUX("Vibra Route", SND_SOC_NOPM, 0, 0,
1432  &twl4030_dapm_vibrapath_control),
1433 
1434  /* Introducing four virtual ADC, since TWL4030 have four channel for
1435  capture */
1436  SND_SOC_DAPM_ADC("ADC Virtual Left1", NULL, SND_SOC_NOPM, 0, 0),
1437  SND_SOC_DAPM_ADC("ADC Virtual Right1", NULL, SND_SOC_NOPM, 0, 0),
1438  SND_SOC_DAPM_ADC("ADC Virtual Left2", NULL, SND_SOC_NOPM, 0, 0),
1439  SND_SOC_DAPM_ADC("ADC Virtual Right2", NULL, SND_SOC_NOPM, 0, 0),
1440 
1441  /* Analog/Digital mic path selection.
1442  TX1 Left/Right: either analog Left/Right or Digimic0
1443  TX2 Left/Right: either analog Left/Right or Digimic1 */
1444  SND_SOC_DAPM_MUX("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
1445  &twl4030_dapm_micpathtx1_control),
1446  SND_SOC_DAPM_MUX("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
1447  &twl4030_dapm_micpathtx2_control),
1448 
1449  /* Analog input mixers for the capture amplifiers */
1450  SND_SOC_DAPM_MIXER("Analog Left",
1451  TWL4030_REG_ANAMICL, 4, 0,
1452  &twl4030_dapm_analoglmic_controls[0],
1453  ARRAY_SIZE(twl4030_dapm_analoglmic_controls)),
1454  SND_SOC_DAPM_MIXER("Analog Right",
1455  TWL4030_REG_ANAMICR, 4, 0,
1456  &twl4030_dapm_analogrmic_controls[0],
1457  ARRAY_SIZE(twl4030_dapm_analogrmic_controls)),
1458 
1459  SND_SOC_DAPM_PGA("ADC Physical Left",
1460  TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
1461  SND_SOC_DAPM_PGA("ADC Physical Right",
1462  TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
1463 
1464  SND_SOC_DAPM_PGA_E("Digimic0 Enable",
1465  TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0,
1466  digimic_event, SND_SOC_DAPM_POST_PMU),
1467  SND_SOC_DAPM_PGA_E("Digimic1 Enable",
1468  TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0,
1469  digimic_event, SND_SOC_DAPM_POST_PMU),
1470 
1471  SND_SOC_DAPM_SUPPLY("micbias1 select", TWL4030_REG_MICBIAS_CTL, 5, 0,
1472  NULL, 0),
1473  SND_SOC_DAPM_SUPPLY("micbias2 select", TWL4030_REG_MICBIAS_CTL, 6, 0,
1474  NULL, 0),
1475 
1476  SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
1477  SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
1478  SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
1479 
1480 };
1481 
1482 static const struct snd_soc_dapm_route intercon[] = {
1483  /* Stream -> DAC mapping */
1484  {"DAC Right1", NULL, "HiFi Playback"},
1485  {"DAC Left1", NULL, "HiFi Playback"},
1486  {"DAC Right2", NULL, "HiFi Playback"},
1487  {"DAC Left2", NULL, "HiFi Playback"},
1488  {"DAC Voice", NULL, "Voice Playback"},
1489 
1490  /* ADC -> Stream mapping */
1491  {"HiFi Capture", NULL, "ADC Virtual Left1"},
1492  {"HiFi Capture", NULL, "ADC Virtual Right1"},
1493  {"HiFi Capture", NULL, "ADC Virtual Left2"},
1494  {"HiFi Capture", NULL, "ADC Virtual Right2"},
1495  {"Voice Capture", NULL, "ADC Virtual Left1"},
1496  {"Voice Capture", NULL, "ADC Virtual Right1"},
1497  {"Voice Capture", NULL, "ADC Virtual Left2"},
1498  {"Voice Capture", NULL, "ADC Virtual Right2"},
1499 
1500  {"Digital L1 Playback Mixer", NULL, "DAC Left1"},
1501  {"Digital R1 Playback Mixer", NULL, "DAC Right1"},
1502  {"Digital L2 Playback Mixer", NULL, "DAC Left2"},
1503  {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1504  {"Digital Voice Playback Mixer", NULL, "DAC Voice"},
1505 
1506  /* Supply for the digital part (APLL) */
1507  {"Digital Voice Playback Mixer", NULL, "APLL Enable"},
1508 
1509  {"DAC Left1", NULL, "AIF Enable"},
1510  {"DAC Right1", NULL, "AIF Enable"},
1511  {"DAC Left2", NULL, "AIF Enable"},
1512  {"DAC Right1", NULL, "AIF Enable"},
1513 
1514  {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
1515  {"Digital L2 Playback Mixer", NULL, "AIF Enable"},
1516 
1517  {"Analog L1 Playback Mixer", NULL, "Digital L1 Playback Mixer"},
1518  {"Analog R1 Playback Mixer", NULL, "Digital R1 Playback Mixer"},
1519  {"Analog L2 Playback Mixer", NULL, "Digital L2 Playback Mixer"},
1520  {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1521  {"Analog Voice Playback Mixer", NULL, "Digital Voice Playback Mixer"},
1522 
1523  /* Internal playback routings */
1524  /* Earpiece */
1525  {"Earpiece Mixer", "Voice", "Analog Voice Playback Mixer"},
1526  {"Earpiece Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1527  {"Earpiece Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1528  {"Earpiece Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1529  {"Earpiece PGA", NULL, "Earpiece Mixer"},
1530  /* PreDrivL */
1531  {"PredriveL Mixer", "Voice", "Analog Voice Playback Mixer"},
1532  {"PredriveL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1533  {"PredriveL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1534  {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1535  {"PredriveL PGA", NULL, "PredriveL Mixer"},
1536  /* PreDrivR */
1537  {"PredriveR Mixer", "Voice", "Analog Voice Playback Mixer"},
1538  {"PredriveR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1539  {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1540  {"PredriveR Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1541  {"PredriveR PGA", NULL, "PredriveR Mixer"},
1542  /* HeadsetL */
1543  {"HeadsetL Mixer", "Voice", "Analog Voice Playback Mixer"},
1544  {"HeadsetL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1545  {"HeadsetL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1546  {"HeadsetL PGA", NULL, "HeadsetL Mixer"},
1547  /* HeadsetR */
1548  {"HeadsetR Mixer", "Voice", "Analog Voice Playback Mixer"},
1549  {"HeadsetR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1550  {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1551  {"HeadsetR PGA", NULL, "HeadsetR Mixer"},
1552  /* CarkitL */
1553  {"CarkitL Mixer", "Voice", "Analog Voice Playback Mixer"},
1554  {"CarkitL Mixer", "AudioL1", "Analog L1 Playback Mixer"},
1555  {"CarkitL Mixer", "AudioL2", "Analog L2 Playback Mixer"},
1556  {"CarkitL PGA", NULL, "CarkitL Mixer"},
1557  /* CarkitR */
1558  {"CarkitR Mixer", "Voice", "Analog Voice Playback Mixer"},
1559  {"CarkitR Mixer", "AudioR1", "Analog R1 Playback Mixer"},
1560  {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1561  {"CarkitR PGA", NULL, "CarkitR Mixer"},
1562  /* HandsfreeL */
1563  {"HandsfreeL Mux", "Voice", "Analog Voice Playback Mixer"},
1564  {"HandsfreeL Mux", "AudioL1", "Analog L1 Playback Mixer"},
1565  {"HandsfreeL Mux", "AudioL2", "Analog L2 Playback Mixer"},
1566  {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
1567  {"HandsfreeL", "Switch", "HandsfreeL Mux"},
1568  {"HandsfreeL PGA", NULL, "HandsfreeL"},
1569  /* HandsfreeR */
1570  {"HandsfreeR Mux", "Voice", "Analog Voice Playback Mixer"},
1571  {"HandsfreeR Mux", "AudioR1", "Analog R1 Playback Mixer"},
1572  {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1573  {"HandsfreeR Mux", "AudioL2", "Analog L2 Playback Mixer"},
1574  {"HandsfreeR", "Switch", "HandsfreeR Mux"},
1575  {"HandsfreeR PGA", NULL, "HandsfreeR"},
1576  /* Vibra */
1577  {"Vibra Mux", "AudioL1", "DAC Left1"},
1578  {"Vibra Mux", "AudioR1", "DAC Right1"},
1579  {"Vibra Mux", "AudioL2", "DAC Left2"},
1580  {"Vibra Mux", "AudioR2", "DAC Right2"},
1581 
1582  /* outputs */
1583  /* Must be always connected (for AIF and APLL) */
1584  {"Virtual HiFi OUT", NULL, "DAC Left1"},
1585  {"Virtual HiFi OUT", NULL, "DAC Right1"},
1586  {"Virtual HiFi OUT", NULL, "DAC Left2"},
1587  {"Virtual HiFi OUT", NULL, "DAC Right2"},
1588  /* Must be always connected (for APLL) */
1589  {"Virtual Voice OUT", NULL, "Digital Voice Playback Mixer"},
1590  /* Physical outputs */
1591  {"EARPIECE", NULL, "Earpiece PGA"},
1592  {"PREDRIVEL", NULL, "PredriveL PGA"},
1593  {"PREDRIVER", NULL, "PredriveR PGA"},
1594  {"HSOL", NULL, "HeadsetL PGA"},
1595  {"HSOR", NULL, "HeadsetR PGA"},
1596  {"CARKITL", NULL, "CarkitL PGA"},
1597  {"CARKITR", NULL, "CarkitR PGA"},
1598  {"HFL", NULL, "HandsfreeL PGA"},
1599  {"HFR", NULL, "HandsfreeR PGA"},
1600  {"Vibra Route", "Audio", "Vibra Mux"},
1601  {"VIBRA", NULL, "Vibra Route"},
1602 
1603  /* Capture path */
1604  /* Must be always connected (for AIF and APLL) */
1605  {"ADC Virtual Left1", NULL, "Virtual HiFi IN"},
1606  {"ADC Virtual Right1", NULL, "Virtual HiFi IN"},
1607  {"ADC Virtual Left2", NULL, "Virtual HiFi IN"},
1608  {"ADC Virtual Right2", NULL, "Virtual HiFi IN"},
1609  /* Physical inputs */
1610  {"Analog Left", "Main Mic Capture Switch", "MAINMIC"},
1611  {"Analog Left", "Headset Mic Capture Switch", "HSMIC"},
1612  {"Analog Left", "AUXL Capture Switch", "AUXL"},
1613  {"Analog Left", "Carkit Mic Capture Switch", "CARKITMIC"},
1614 
1615  {"Analog Right", "Sub Mic Capture Switch", "SUBMIC"},
1616  {"Analog Right", "AUXR Capture Switch", "AUXR"},
1617 
1618  {"ADC Physical Left", NULL, "Analog Left"},
1619  {"ADC Physical Right", NULL, "Analog Right"},
1620 
1621  {"Digimic0 Enable", NULL, "DIGIMIC0"},
1622  {"Digimic1 Enable", NULL, "DIGIMIC1"},
1623 
1624  {"DIGIMIC0", NULL, "micbias1 select"},
1625  {"DIGIMIC1", NULL, "micbias2 select"},
1626 
1627  /* TX1 Left capture path */
1628  {"TX1 Capture Route", "Analog", "ADC Physical Left"},
1629  {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1630  /* TX1 Right capture path */
1631  {"TX1 Capture Route", "Analog", "ADC Physical Right"},
1632  {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
1633  /* TX2 Left capture path */
1634  {"TX2 Capture Route", "Analog", "ADC Physical Left"},
1635  {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1636  /* TX2 Right capture path */
1637  {"TX2 Capture Route", "Analog", "ADC Physical Right"},
1638  {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
1639 
1640  {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
1641  {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
1642  {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
1643  {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
1644 
1645  {"ADC Virtual Left1", NULL, "AIF Enable"},
1646  {"ADC Virtual Right1", NULL, "AIF Enable"},
1647  {"ADC Virtual Left2", NULL, "AIF Enable"},
1648  {"ADC Virtual Right2", NULL, "AIF Enable"},
1649 
1650  /* Analog bypass routes */
1651  {"Right1 Analog Loopback", "Switch", "Analog Right"},
1652  {"Left1 Analog Loopback", "Switch", "Analog Left"},
1653  {"Right2 Analog Loopback", "Switch", "Analog Right"},
1654  {"Left2 Analog Loopback", "Switch", "Analog Left"},
1655  {"Voice Analog Loopback", "Switch", "Analog Left"},
1656 
1657  /* Supply for the Analog loopbacks */
1658  {"Right1 Analog Loopback", NULL, "FM Loop Enable"},
1659  {"Left1 Analog Loopback", NULL, "FM Loop Enable"},
1660  {"Right2 Analog Loopback", NULL, "FM Loop Enable"},
1661  {"Left2 Analog Loopback", NULL, "FM Loop Enable"},
1662  {"Voice Analog Loopback", NULL, "FM Loop Enable"},
1663 
1664  {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
1665  {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
1666  {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1667  {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
1668  {"Analog Voice Playback Mixer", NULL, "Voice Analog Loopback"},
1669 
1670  /* Digital bypass routes */
1671  {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
1672  {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
1673  {"Voice Digital Loopback", "Volume", "TX2 Capture Route"},
1674 
1675  {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
1676  {"Digital L2 Playback Mixer", NULL, "Left Digital Loopback"},
1677  {"Digital Voice Playback Mixer", NULL, "Voice Digital Loopback"},
1678 
1679 };
1680 
1681 static int twl4030_set_bias_level(struct snd_soc_codec *codec,
1682  enum snd_soc_bias_level level)
1683 {
1684  switch (level) {
1685  case SND_SOC_BIAS_ON:
1686  break;
1687  case SND_SOC_BIAS_PREPARE:
1688  break;
1689  case SND_SOC_BIAS_STANDBY:
1690  if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
1691  twl4030_codec_enable(codec, 1);
1692  break;
1693  case SND_SOC_BIAS_OFF:
1694  twl4030_codec_enable(codec, 0);
1695  break;
1696  }
1697  codec->dapm.bias_level = level;
1698 
1699  return 0;
1700 }
1701 
1702 static void twl4030_constraints(struct twl4030_priv *twl4030,
1703  struct snd_pcm_substream *mst_substream)
1704 {
1705  struct snd_pcm_substream *slv_substream;
1706 
1707  /* Pick the stream, which need to be constrained */
1708  if (mst_substream == twl4030->master_substream)
1709  slv_substream = twl4030->slave_substream;
1710  else if (mst_substream == twl4030->slave_substream)
1711  slv_substream = twl4030->master_substream;
1712  else /* This should not happen.. */
1713  return;
1714 
1715  /* Set the constraints according to the already configured stream */
1716  snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1717  SNDRV_PCM_HW_PARAM_RATE,
1718  twl4030->rate,
1719  twl4030->rate);
1720 
1721  snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1722  SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
1723  twl4030->sample_bits,
1724  twl4030->sample_bits);
1725 
1726  snd_pcm_hw_constraint_minmax(slv_substream->runtime,
1727  SNDRV_PCM_HW_PARAM_CHANNELS,
1728  twl4030->channels,
1729  twl4030->channels);
1730 }
1731 
1732 /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
1733  * capture has to be enabled/disabled. */
1734 static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
1735  int enable)
1736 {
1737  u8 reg, mask;
1738 
1739  reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
1740 
1741  if (direction == SNDRV_PCM_STREAM_PLAYBACK)
1742  mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
1743  else
1744  mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
1745 
1746  if (enable)
1747  reg |= mask;
1748  else
1749  reg &= ~mask;
1750 
1751  twl4030_write(codec, TWL4030_REG_OPTION, reg);
1752 }
1753 
1754 static int twl4030_startup(struct snd_pcm_substream *substream,
1755  struct snd_soc_dai *dai)
1756 {
1757  struct snd_soc_codec *codec = dai->codec;
1758  struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1759 
1760  if (twl4030->master_substream) {
1761  twl4030->slave_substream = substream;
1762  /* The DAI has one configuration for playback and capture, so
1763  * if the DAI has been already configured then constrain this
1764  * substream to match it. */
1765  if (twl4030->configured)
1766  twl4030_constraints(twl4030, twl4030->master_substream);
1767  } else {
1768  if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
1769  TWL4030_OPTION_1)) {
1770  /* In option2 4 channel is not supported, set the
1771  * constraint for the first stream for channels, the
1772  * second stream will 'inherit' this cosntraint */
1773  snd_pcm_hw_constraint_minmax(substream->runtime,
1774  SNDRV_PCM_HW_PARAM_CHANNELS,
1775  2, 2);
1776  }
1777  twl4030->master_substream = substream;
1778  }
1779 
1780  return 0;
1781 }
1782 
1783 static void twl4030_shutdown(struct snd_pcm_substream *substream,
1784  struct snd_soc_dai *dai)
1785 {
1786  struct snd_soc_codec *codec = dai->codec;
1787  struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1788 
1789  if (twl4030->master_substream == substream)
1790  twl4030->master_substream = twl4030->slave_substream;
1791 
1792  twl4030->slave_substream = NULL;
1793 
1794  /* If all streams are closed, or the remaining stream has not yet
1795  * been configured than set the DAI as not configured. */
1796  if (!twl4030->master_substream)
1797  twl4030->configured = 0;
1798  else if (!twl4030->master_substream->runtime->channels)
1799  twl4030->configured = 0;
1800 
1801  /* If the closing substream had 4 channel, do the necessary cleanup */
1802  if (substream->runtime->channels == 4)
1803  twl4030_tdm_enable(codec, substream->stream, 0);
1804 }
1805 
1806 static int twl4030_hw_params(struct snd_pcm_substream *substream,
1807  struct snd_pcm_hw_params *params,
1808  struct snd_soc_dai *dai)
1809 {
1810  struct snd_soc_codec *codec = dai->codec;
1811  struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1812  u8 mode, old_mode, format, old_format;
1813 
1814  /* If the substream has 4 channel, do the necessary setup */
1815  if (params_channels(params) == 4) {
1816  format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1817  mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
1818 
1819  /* Safety check: are we in the correct operating mode and
1820  * the interface is in TDM mode? */
1821  if ((mode & TWL4030_OPTION_1) &&
1822  ((format & TWL4030_AIF_FORMAT) == TWL4030_AIF_FORMAT_TDM))
1823  twl4030_tdm_enable(codec, substream->stream, 1);
1824  else
1825  return -EINVAL;
1826  }
1827 
1828  if (twl4030->configured)
1829  /* Ignoring hw_params for already configured DAI */
1830  return 0;
1831 
1832  /* bit rate */
1833  old_mode = twl4030_read_reg_cache(codec,
1834  TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
1835  mode = old_mode & ~TWL4030_APLL_RATE;
1836 
1837  switch (params_rate(params)) {
1838  case 8000:
1839  mode |= TWL4030_APLL_RATE_8000;
1840  break;
1841  case 11025:
1842  mode |= TWL4030_APLL_RATE_11025;
1843  break;
1844  case 12000:
1845  mode |= TWL4030_APLL_RATE_12000;
1846  break;
1847  case 16000:
1848  mode |= TWL4030_APLL_RATE_16000;
1849  break;
1850  case 22050:
1851  mode |= TWL4030_APLL_RATE_22050;
1852  break;
1853  case 24000:
1854  mode |= TWL4030_APLL_RATE_24000;
1855  break;
1856  case 32000:
1857  mode |= TWL4030_APLL_RATE_32000;
1858  break;
1859  case 44100:
1860  mode |= TWL4030_APLL_RATE_44100;
1861  break;
1862  case 48000:
1863  mode |= TWL4030_APLL_RATE_48000;
1864  break;
1865  case 96000:
1866  mode |= TWL4030_APLL_RATE_96000;
1867  break;
1868  default:
1869  dev_err(codec->dev, "%s: unknown rate %d\n", __func__,
1870  params_rate(params));
1871  return -EINVAL;
1872  }
1873 
1874  /* sample size */
1875  old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1876  format = old_format;
1877  format &= ~TWL4030_DATA_WIDTH;
1878  switch (params_format(params)) {
1879  case SNDRV_PCM_FORMAT_S16_LE:
1880  format |= TWL4030_DATA_WIDTH_16S_16W;
1881  break;
1882  case SNDRV_PCM_FORMAT_S32_LE:
1883  format |= TWL4030_DATA_WIDTH_32S_24W;
1884  break;
1885  default:
1886  dev_err(codec->dev, "%s: unknown format %d\n", __func__,
1887  params_format(params));
1888  return -EINVAL;
1889  }
1890 
1891  if (format != old_format || mode != old_mode) {
1892  if (twl4030->codec_powered) {
1893  /*
1894  * If the codec is powered, than we need to toggle the
1895  * codec power.
1896  */
1897  twl4030_codec_enable(codec, 0);
1898  twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1899  twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1900  twl4030_codec_enable(codec, 1);
1901  } else {
1902  twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
1903  twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1904  }
1905  }
1906 
1907  /* Store the important parameters for the DAI configuration and set
1908  * the DAI as configured */
1909  twl4030->configured = 1;
1910  twl4030->rate = params_rate(params);
1911  twl4030->sample_bits = hw_param_interval(params,
1912  SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
1913  twl4030->channels = params_channels(params);
1914 
1915  /* If both playback and capture streams are open, and one of them
1916  * is setting the hw parameters right now (since we are here), set
1917  * constraints to the other stream to match the current one. */
1918  if (twl4030->slave_substream)
1919  twl4030_constraints(twl4030, substream);
1920 
1921  return 0;
1922 }
1923 
1924 static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1925  int clk_id, unsigned int freq, int dir)
1926 {
1927  struct snd_soc_codec *codec = codec_dai->codec;
1928  struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1929 
1930  switch (freq) {
1931  case 19200000:
1932  case 26000000:
1933  case 38400000:
1934  break;
1935  default:
1936  dev_err(codec->dev, "Unsupported HFCLKIN: %u\n", freq);
1937  return -EINVAL;
1938  }
1939 
1940  if ((freq / 1000) != twl4030->sysclk) {
1941  dev_err(codec->dev,
1942  "Mismatch in HFCLKIN: %u (configured: %u)\n",
1943  freq, twl4030->sysclk * 1000);
1944  return -EINVAL;
1945  }
1946 
1947  return 0;
1948 }
1949 
1950 static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
1951  unsigned int fmt)
1952 {
1953  struct snd_soc_codec *codec = codec_dai->codec;
1954  struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
1955  u8 old_format, format;
1956 
1957  /* get format */
1958  old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
1959  format = old_format;
1960 
1961  /* set master/slave audio interface */
1962  switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1963  case SND_SOC_DAIFMT_CBM_CFM:
1964  format &= ~(TWL4030_AIF_SLAVE_EN);
1965  format &= ~(TWL4030_CLK256FS_EN);
1966  break;
1967  case SND_SOC_DAIFMT_CBS_CFS:
1968  format |= TWL4030_AIF_SLAVE_EN;
1969  format |= TWL4030_CLK256FS_EN;
1970  break;
1971  default:
1972  return -EINVAL;
1973  }
1974 
1975  /* interface format */
1976  format &= ~TWL4030_AIF_FORMAT;
1977  switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1978  case SND_SOC_DAIFMT_I2S:
1979  format |= TWL4030_AIF_FORMAT_CODEC;
1980  break;
1981  case SND_SOC_DAIFMT_DSP_A:
1982  format |= TWL4030_AIF_FORMAT_TDM;
1983  break;
1984  default:
1985  return -EINVAL;
1986  }
1987 
1988  if (format != old_format) {
1989  if (twl4030->codec_powered) {
1990  /*
1991  * If the codec is powered, than we need to toggle the
1992  * codec power.
1993  */
1994  twl4030_codec_enable(codec, 0);
1995  twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1996  twl4030_codec_enable(codec, 1);
1997  } else {
1998  twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
1999  }
2000  }
2001 
2002  return 0;
2003 }
2004 
2005 static int twl4030_set_tristate(struct snd_soc_dai *dai, int tristate)
2006 {
2007  struct snd_soc_codec *codec = dai->codec;
2008  u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
2009 
2010  if (tristate)
2011  reg |= TWL4030_AIF_TRI_EN;
2012  else
2013  reg &= ~TWL4030_AIF_TRI_EN;
2014 
2015  return twl4030_write(codec, TWL4030_REG_AUDIO_IF, reg);
2016 }
2017 
2018 /* In case of voice mode, the RX1 L(VRX) for downlink and the TX2 L/R
2019  * (VTXL, VTXR) for uplink has to be enabled/disabled. */
2020 static void twl4030_voice_enable(struct snd_soc_codec *codec, int direction,
2021  int enable)
2022 {
2023  u8 reg, mask;
2024 
2025  reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
2026 
2027  if (direction == SNDRV_PCM_STREAM_PLAYBACK)
2028  mask = TWL4030_ARXL1_VRX_EN;
2029  else
2030  mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
2031 
2032  if (enable)
2033  reg |= mask;
2034  else
2035  reg &= ~mask;
2036 
2037  twl4030_write(codec, TWL4030_REG_OPTION, reg);
2038 }
2039 
2040 static int twl4030_voice_startup(struct snd_pcm_substream *substream,
2041  struct snd_soc_dai *dai)
2042 {
2043  struct snd_soc_codec *codec = dai->codec;
2044  struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
2045  u8 mode;
2046 
2047  /* If the system master clock is not 26MHz, the voice PCM interface is
2048  * not available.
2049  */
2050  if (twl4030->sysclk != 26000) {
2051  dev_err(codec->dev,
2052  "%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",
2053  __func__, twl4030->sysclk);
2054  return -EINVAL;
2055  }
2056 
2057  /* If the codec mode is not option2, the voice PCM interface is not
2058  * available.
2059  */
2060  mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2061  & TWL4030_OPT_MODE;
2062 
2063  if (mode != TWL4030_OPTION_2) {
2064  dev_err(codec->dev, "%s: the codec mode is not option2\n",
2065  __func__);
2066  return -EINVAL;
2067  }
2068 
2069  return 0;
2070 }
2071 
2072 static void twl4030_voice_shutdown(struct snd_pcm_substream *substream,
2073  struct snd_soc_dai *dai)
2074 {
2075  struct snd_soc_codec *codec = dai->codec;
2076 
2077  /* Enable voice digital filters */
2078  twl4030_voice_enable(codec, substream->stream, 0);
2079 }
2080 
2081 static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
2082  struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
2083 {
2084  struct snd_soc_codec *codec = dai->codec;
2085  struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
2086  u8 old_mode, mode;
2087 
2088  /* Enable voice digital filters */
2089  twl4030_voice_enable(codec, substream->stream, 1);
2090 
2091  /* bit rate */
2092  old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
2093  & ~(TWL4030_CODECPDZ);
2094  mode = old_mode;
2095 
2096  switch (params_rate(params)) {
2097  case 8000:
2098  mode &= ~(TWL4030_SEL_16K);
2099  break;
2100  case 16000:
2101  mode |= TWL4030_SEL_16K;
2102  break;
2103  default:
2104  dev_err(codec->dev, "%s: unknown rate %d\n", __func__,
2105  params_rate(params));
2106  return -EINVAL;
2107  }
2108 
2109  if (mode != old_mode) {
2110  if (twl4030->codec_powered) {
2111  /*
2112  * If the codec is powered, than we need to toggle the
2113  * codec power.
2114  */
2115  twl4030_codec_enable(codec, 0);
2116  twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2117  twl4030_codec_enable(codec, 1);
2118  } else {
2119  twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
2120  }
2121  }
2122 
2123  return 0;
2124 }
2125 
2126 static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
2127  int clk_id, unsigned int freq, int dir)
2128 {
2129  struct snd_soc_codec *codec = codec_dai->codec;
2130  struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
2131 
2132  if (freq != 26000000) {
2133  dev_err(codec->dev,
2134  "%s: HFCLKIN is %u KHz, voice interface needs 26MHz\n",
2135  __func__, freq / 1000);
2136  return -EINVAL;
2137  }
2138  if ((freq / 1000) != twl4030->sysclk) {
2139  dev_err(codec->dev,
2140  "Mismatch in HFCLKIN: %u (configured: %u)\n",
2141  freq, twl4030->sysclk * 1000);
2142  return -EINVAL;
2143  }
2144  return 0;
2145 }
2146 
2147 static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
2148  unsigned int fmt)
2149 {
2150  struct snd_soc_codec *codec = codec_dai->codec;
2151  struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
2152  u8 old_format, format;
2153 
2154  /* get format */
2155  old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2156  format = old_format;
2157 
2158  /* set master/slave audio interface */
2159  switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2160  case SND_SOC_DAIFMT_CBM_CFM:
2161  format &= ~(TWL4030_VIF_SLAVE_EN);
2162  break;
2163  case SND_SOC_DAIFMT_CBS_CFS:
2164  format |= TWL4030_VIF_SLAVE_EN;
2165  break;
2166  default:
2167  return -EINVAL;
2168  }
2169 
2170  /* clock inversion */
2171  switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2172  case SND_SOC_DAIFMT_IB_NF:
2173  format &= ~(TWL4030_VIF_FORMAT);
2174  break;
2175  case SND_SOC_DAIFMT_NB_IF:
2176  format |= TWL4030_VIF_FORMAT;
2177  break;
2178  default:
2179  return -EINVAL;
2180  }
2181 
2182  if (format != old_format) {
2183  if (twl4030->codec_powered) {
2184  /*
2185  * If the codec is powered, than we need to toggle the
2186  * codec power.
2187  */
2188  twl4030_codec_enable(codec, 0);
2189  twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2190  twl4030_codec_enable(codec, 1);
2191  } else {
2192  twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
2193  }
2194  }
2195 
2196  return 0;
2197 }
2198 
2199 static int twl4030_voice_set_tristate(struct snd_soc_dai *dai, int tristate)
2200 {
2201  struct snd_soc_codec *codec = dai->codec;
2202  u8 reg = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
2203 
2204  if (tristate)
2205  reg |= TWL4030_VIF_TRI_EN;
2206  else
2207  reg &= ~TWL4030_VIF_TRI_EN;
2208 
2209  return twl4030_write(codec, TWL4030_REG_VOICE_IF, reg);
2210 }
2211 
2212 #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
2213 #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2214 
2215 static const struct snd_soc_dai_ops twl4030_dai_hifi_ops = {
2216  .startup = twl4030_startup,
2217  .shutdown = twl4030_shutdown,
2218  .hw_params = twl4030_hw_params,
2219  .set_sysclk = twl4030_set_dai_sysclk,
2220  .set_fmt = twl4030_set_dai_fmt,
2221  .set_tristate = twl4030_set_tristate,
2222 };
2223 
2224 static const struct snd_soc_dai_ops twl4030_dai_voice_ops = {
2225  .startup = twl4030_voice_startup,
2226  .shutdown = twl4030_voice_shutdown,
2227  .hw_params = twl4030_voice_hw_params,
2228  .set_sysclk = twl4030_voice_set_dai_sysclk,
2229  .set_fmt = twl4030_voice_set_dai_fmt,
2230  .set_tristate = twl4030_voice_set_tristate,
2231 };
2232 
2233 static struct snd_soc_dai_driver twl4030_dai[] = {
2234 {
2235  .name = "twl4030-hifi",
2236  .playback = {
2237  .stream_name = "HiFi Playback",
2238  .channels_min = 2,
2239  .channels_max = 4,
2240  .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
2241  .formats = TWL4030_FORMATS,
2242  .sig_bits = 24,},
2243  .capture = {
2244  .stream_name = "HiFi Capture",
2245  .channels_min = 2,
2246  .channels_max = 4,
2247  .rates = TWL4030_RATES,
2248  .formats = TWL4030_FORMATS,
2249  .sig_bits = 24,},
2250  .ops = &twl4030_dai_hifi_ops,
2251 },
2252 {
2253  .name = "twl4030-voice",
2254  .playback = {
2255  .stream_name = "Voice Playback",
2256  .channels_min = 1,
2257  .channels_max = 1,
2258  .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2259  .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2260  .capture = {
2261  .stream_name = "Voice Capture",
2262  .channels_min = 1,
2263  .channels_max = 2,
2264  .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
2265  .formats = SNDRV_PCM_FMTBIT_S16_LE,},
2266  .ops = &twl4030_dai_voice_ops,
2267 },
2268 };
2269 
2270 static int twl4030_soc_suspend(struct snd_soc_codec *codec)
2271 {
2272  twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2273  return 0;
2274 }
2275 
2276 static int twl4030_soc_resume(struct snd_soc_codec *codec)
2277 {
2278  twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
2279  return 0;
2280 }
2281 
2282 static int twl4030_soc_probe(struct snd_soc_codec *codec)
2283 {
2284  struct twl4030_priv *twl4030;
2285 
2286  twl4030 = devm_kzalloc(codec->dev, sizeof(struct twl4030_priv),
2287  GFP_KERNEL);
2288  if (twl4030 == NULL) {
2289  dev_err(codec->dev, "Can not allocate memory\n");
2290  return -ENOMEM;
2291  }
2292  snd_soc_codec_set_drvdata(codec, twl4030);
2293  /* Set the defaults, and power up the codec */
2294  twl4030->sysclk = twl4030_audio_get_mclk() / 1000;
2295 
2296  twl4030_init_chip(codec);
2297 
2298  return 0;
2299 }
2300 
2301 static int twl4030_soc_remove(struct snd_soc_codec *codec)
2302 {
2303  struct twl4030_priv *twl4030 = snd_soc_codec_get_drvdata(codec);
2304  struct twl4030_codec_data *pdata = twl4030->pdata;
2305 
2306  /* Reset registers to their chip default before leaving */
2307  twl4030_reset_registers(codec);
2308  twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
2309 
2310  if (pdata && pdata->hs_extmute && gpio_is_valid(pdata->hs_extmute_gpio))
2311  gpio_free(pdata->hs_extmute_gpio);
2312 
2313  return 0;
2314 }
2315 
2316 static struct snd_soc_codec_driver soc_codec_dev_twl4030 = {
2317  .probe = twl4030_soc_probe,
2318  .remove = twl4030_soc_remove,
2319  .suspend = twl4030_soc_suspend,
2320  .resume = twl4030_soc_resume,
2321  .read = twl4030_read_reg_cache,
2322  .write = twl4030_write,
2323  .set_bias_level = twl4030_set_bias_level,
2324  .idle_bias_off = true,
2325  .reg_cache_size = sizeof(twl4030_reg),
2326  .reg_word_size = sizeof(u8),
2327  .reg_cache_default = twl4030_reg,
2328 
2329  .controls = twl4030_snd_controls,
2330  .num_controls = ARRAY_SIZE(twl4030_snd_controls),
2331  .dapm_widgets = twl4030_dapm_widgets,
2332  .num_dapm_widgets = ARRAY_SIZE(twl4030_dapm_widgets),
2333  .dapm_routes = intercon,
2334  .num_dapm_routes = ARRAY_SIZE(intercon),
2335 };
2336 
2337 static int __devinit twl4030_codec_probe(struct platform_device *pdev)
2338 {
2339  return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_twl4030,
2340  twl4030_dai, ARRAY_SIZE(twl4030_dai));
2341 }
2342 
2343 static int __devexit twl4030_codec_remove(struct platform_device *pdev)
2344 {
2345  snd_soc_unregister_codec(&pdev->dev);
2346  return 0;
2347 }
2348 
2349 MODULE_ALIAS("platform:twl4030-codec");
2350 
2351 static struct platform_driver twl4030_codec_driver = {
2352  .probe = twl4030_codec_probe,
2353  .remove = __devexit_p(twl4030_codec_remove),
2354  .driver = {
2355  .name = "twl4030-codec",
2356  .owner = THIS_MODULE,
2357  },
2358 };
2359 
2360 module_platform_driver(twl4030_codec_driver);
2361 
2362 MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
2363 MODULE_AUTHOR("Steve Sakoman");
2364 MODULE_LICENSE("GPL");
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