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ux500_msp_i2s.c
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1 /*
2  * Copyright (C) ST-Ericsson SA 2012
3  *
4  * Author: Ola Lilja <[email protected]>,
5  * Roger Nilsson <[email protected]>,
6  * Sandeep Kaushik <[email protected]>
7  * for ST-Ericsson.
8  *
9  * License terms:
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License version 2 as published
13  * by the Free Software Foundation.
14  */
15 
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/pinctrl/consumer.h>
19 #include <linux/delay.h>
20 #include <linux/slab.h>
21 #include <linux/io.h>
22 #include <linux/of.h>
23 
24 #include <mach/hardware.h>
25 #include <mach/msp.h>
26 
27 #include <sound/soc.h>
28 
29 #include "ux500_msp_i2s.h"
30 
31 /* MSP1/3 Tx/Rx usage protection */
32 static DEFINE_SPINLOCK(msp_rxtx_lock);
33 
34  /* Protocol desciptors */
35 static const struct msp_protdesc prot_descs[] = {
36  { /* I2S */
37  MSP_SINGLE_PHASE,
38  MSP_SINGLE_PHASE,
39  MSP_PHASE2_START_MODE_IMEDIATE,
40  MSP_PHASE2_START_MODE_IMEDIATE,
41  MSP_BTF_MS_BIT_FIRST,
42  MSP_BTF_MS_BIT_FIRST,
43  MSP_FRAME_LEN_1,
44  MSP_FRAME_LEN_1,
45  MSP_FRAME_LEN_1,
46  MSP_FRAME_LEN_1,
47  MSP_ELEM_LEN_32,
48  MSP_ELEM_LEN_32,
49  MSP_ELEM_LEN_32,
50  MSP_ELEM_LEN_32,
51  MSP_DELAY_1,
52  MSP_DELAY_1,
53  MSP_RISING_EDGE,
54  MSP_FALLING_EDGE,
55  MSP_FSYNC_POL_ACT_LO,
56  MSP_FSYNC_POL_ACT_LO,
57  MSP_SWAP_NONE,
58  MSP_SWAP_NONE,
59  MSP_COMPRESS_MODE_LINEAR,
60  MSP_EXPAND_MODE_LINEAR,
61  MSP_FSYNC_IGNORE,
62  31,
63  15,
64  32,
65  }, { /* PCM */
66  MSP_DUAL_PHASE,
67  MSP_DUAL_PHASE,
68  MSP_PHASE2_START_MODE_FSYNC,
69  MSP_PHASE2_START_MODE_FSYNC,
70  MSP_BTF_MS_BIT_FIRST,
71  MSP_BTF_MS_BIT_FIRST,
72  MSP_FRAME_LEN_1,
73  MSP_FRAME_LEN_1,
74  MSP_FRAME_LEN_1,
75  MSP_FRAME_LEN_1,
76  MSP_ELEM_LEN_16,
77  MSP_ELEM_LEN_16,
78  MSP_ELEM_LEN_16,
79  MSP_ELEM_LEN_16,
80  MSP_DELAY_0,
81  MSP_DELAY_0,
82  MSP_RISING_EDGE,
83  MSP_FALLING_EDGE,
84  MSP_FSYNC_POL_ACT_HI,
85  MSP_FSYNC_POL_ACT_HI,
86  MSP_SWAP_NONE,
87  MSP_SWAP_NONE,
88  MSP_COMPRESS_MODE_LINEAR,
89  MSP_EXPAND_MODE_LINEAR,
90  MSP_FSYNC_IGNORE,
91  255,
92  0,
93  256,
94  }, { /* Companded PCM */
95  MSP_SINGLE_PHASE,
96  MSP_SINGLE_PHASE,
97  MSP_PHASE2_START_MODE_FSYNC,
98  MSP_PHASE2_START_MODE_FSYNC,
99  MSP_BTF_MS_BIT_FIRST,
100  MSP_BTF_MS_BIT_FIRST,
101  MSP_FRAME_LEN_1,
102  MSP_FRAME_LEN_1,
103  MSP_FRAME_LEN_1,
104  MSP_FRAME_LEN_1,
105  MSP_ELEM_LEN_8,
106  MSP_ELEM_LEN_8,
107  MSP_ELEM_LEN_8,
108  MSP_ELEM_LEN_8,
109  MSP_DELAY_0,
110  MSP_DELAY_0,
111  MSP_RISING_EDGE,
112  MSP_RISING_EDGE,
113  MSP_FSYNC_POL_ACT_HI,
114  MSP_FSYNC_POL_ACT_HI,
115  MSP_SWAP_NONE,
116  MSP_SWAP_NONE,
117  MSP_COMPRESS_MODE_LINEAR,
118  MSP_EXPAND_MODE_LINEAR,
119  MSP_FSYNC_IGNORE,
120  255,
121  0,
122  256,
123  },
124 };
125 
126 static void set_prot_desc_tx(struct ux500_msp *msp,
127  struct msp_protdesc *protdesc,
128  enum msp_data_size data_size)
129 {
130  u32 temp_reg = 0;
131 
132  temp_reg |= MSP_P2_ENABLE_BIT(protdesc->tx_phase_mode);
133  temp_reg |= MSP_P2_START_MODE_BIT(protdesc->tx_phase2_start_mode);
134  temp_reg |= MSP_P1_FRAME_LEN_BITS(protdesc->tx_frame_len_1);
135  temp_reg |= MSP_P2_FRAME_LEN_BITS(protdesc->tx_frame_len_2);
136  if (msp->def_elem_len) {
137  temp_reg |= MSP_P1_ELEM_LEN_BITS(protdesc->tx_elem_len_1);
138  temp_reg |= MSP_P2_ELEM_LEN_BITS(protdesc->tx_elem_len_2);
139  } else {
140  temp_reg |= MSP_P1_ELEM_LEN_BITS(data_size);
141  temp_reg |= MSP_P2_ELEM_LEN_BITS(data_size);
142  }
143  temp_reg |= MSP_DATA_DELAY_BITS(protdesc->tx_data_delay);
144  temp_reg |= MSP_SET_ENDIANNES_BIT(protdesc->tx_byte_order);
145  temp_reg |= MSP_FSYNC_POL(protdesc->tx_fsync_pol);
146  temp_reg |= MSP_DATA_WORD_SWAP(protdesc->tx_half_word_swap);
147  temp_reg |= MSP_SET_COMPANDING_MODE(protdesc->compression_mode);
148  temp_reg |= MSP_SET_FSYNC_IGNORE(protdesc->frame_sync_ignore);
149 
150  writel(temp_reg, msp->registers + MSP_TCF);
151 }
152 
153 static void set_prot_desc_rx(struct ux500_msp *msp,
154  struct msp_protdesc *protdesc,
155  enum msp_data_size data_size)
156 {
157  u32 temp_reg = 0;
158 
159  temp_reg |= MSP_P2_ENABLE_BIT(protdesc->rx_phase_mode);
160  temp_reg |= MSP_P2_START_MODE_BIT(protdesc->rx_phase2_start_mode);
161  temp_reg |= MSP_P1_FRAME_LEN_BITS(protdesc->rx_frame_len_1);
162  temp_reg |= MSP_P2_FRAME_LEN_BITS(protdesc->rx_frame_len_2);
163  if (msp->def_elem_len) {
164  temp_reg |= MSP_P1_ELEM_LEN_BITS(protdesc->rx_elem_len_1);
165  temp_reg |= MSP_P2_ELEM_LEN_BITS(protdesc->rx_elem_len_2);
166  } else {
167  temp_reg |= MSP_P1_ELEM_LEN_BITS(data_size);
168  temp_reg |= MSP_P2_ELEM_LEN_BITS(data_size);
169  }
170 
171  temp_reg |= MSP_DATA_DELAY_BITS(protdesc->rx_data_delay);
172  temp_reg |= MSP_SET_ENDIANNES_BIT(protdesc->rx_byte_order);
173  temp_reg |= MSP_FSYNC_POL(protdesc->rx_fsync_pol);
174  temp_reg |= MSP_DATA_WORD_SWAP(protdesc->rx_half_word_swap);
175  temp_reg |= MSP_SET_COMPANDING_MODE(protdesc->expansion_mode);
176  temp_reg |= MSP_SET_FSYNC_IGNORE(protdesc->frame_sync_ignore);
177 
178  writel(temp_reg, msp->registers + MSP_RCF);
179 }
180 
181 static int configure_protocol(struct ux500_msp *msp,
182  struct ux500_msp_config *config)
183 {
184  struct msp_protdesc *protdesc;
185  enum msp_data_size data_size;
186  u32 temp_reg = 0;
187 
188  data_size = config->data_size;
189  msp->def_elem_len = config->def_elem_len;
190  if (config->default_protdesc == 1) {
191  if (config->protocol >= MSP_INVALID_PROTOCOL) {
192  dev_err(msp->dev, "%s: ERROR: Invalid protocol!\n",
193  __func__);
194  return -EINVAL;
195  }
196  protdesc =
197  (struct msp_protdesc *)&prot_descs[config->protocol];
198  } else {
199  protdesc = (struct msp_protdesc *)&config->protdesc;
200  }
201 
202  if (data_size < MSP_DATA_BITS_DEFAULT || data_size > MSP_DATA_BITS_32) {
203  dev_err(msp->dev,
204  "%s: ERROR: Invalid data-size requested (data_size = %d)!\n",
205  __func__, data_size);
206  return -EINVAL;
207  }
208 
209  if (config->direction & MSP_DIR_TX)
210  set_prot_desc_tx(msp, protdesc, data_size);
211  if (config->direction & MSP_DIR_RX)
212  set_prot_desc_rx(msp, protdesc, data_size);
213 
214  /* The code below should not be separated. */
215  temp_reg = readl(msp->registers + MSP_GCR) & ~TX_CLK_POL_RISING;
216  temp_reg |= MSP_TX_CLKPOL_BIT(~protdesc->tx_clk_pol);
217  writel(temp_reg, msp->registers + MSP_GCR);
218  temp_reg = readl(msp->registers + MSP_GCR) & ~RX_CLK_POL_RISING;
219  temp_reg |= MSP_RX_CLKPOL_BIT(protdesc->rx_clk_pol);
220  writel(temp_reg, msp->registers + MSP_GCR);
221 
222  return 0;
223 }
224 
225 static int setup_bitclk(struct ux500_msp *msp, struct ux500_msp_config *config)
226 {
227  u32 reg_val_GCR;
228  u32 frame_per = 0;
229  u32 sck_div = 0;
230  u32 frame_width = 0;
231  u32 temp_reg = 0;
232  struct msp_protdesc *protdesc = NULL;
233 
234  reg_val_GCR = readl(msp->registers + MSP_GCR);
235  writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR);
236 
237  if (config->default_protdesc)
238  protdesc =
239  (struct msp_protdesc *)&prot_descs[config->protocol];
240  else
241  protdesc = (struct msp_protdesc *)&config->protdesc;
242 
243  switch (config->protocol) {
244  case MSP_PCM_PROTOCOL:
245  case MSP_PCM_COMPAND_PROTOCOL:
246  frame_width = protdesc->frame_width;
247  sck_div = config->f_inputclk / (config->frame_freq *
248  (protdesc->clocks_per_frame));
249  frame_per = protdesc->frame_period;
250  break;
251  case MSP_I2S_PROTOCOL:
252  frame_width = protdesc->frame_width;
253  sck_div = config->f_inputclk / (config->frame_freq *
254  (protdesc->clocks_per_frame));
255  frame_per = protdesc->frame_period;
256  break;
257  default:
258  dev_err(msp->dev, "%s: ERROR: Unknown protocol (%d)!\n",
259  __func__,
260  config->protocol);
261  return -EINVAL;
262  }
263 
264  temp_reg = (sck_div - 1) & SCK_DIV_MASK;
265  temp_reg |= FRAME_WIDTH_BITS(frame_width);
266  temp_reg |= FRAME_PERIOD_BITS(frame_per);
267  writel(temp_reg, msp->registers + MSP_SRG);
268 
269  msp->f_bitclk = (config->f_inputclk)/(sck_div + 1);
270 
271  /* Enable bit-clock */
272  udelay(100);
273  reg_val_GCR = readl(msp->registers + MSP_GCR);
274  writel(reg_val_GCR | SRG_ENABLE, msp->registers + MSP_GCR);
275  udelay(100);
276 
277  return 0;
278 }
279 
280 static int configure_multichannel(struct ux500_msp *msp,
281  struct ux500_msp_config *config)
282 {
283  struct msp_protdesc *protdesc;
284  struct msp_multichannel_config *mcfg;
285  u32 reg_val_MCR;
286 
287  if (config->default_protdesc == 1) {
288  if (config->protocol >= MSP_INVALID_PROTOCOL) {
289  dev_err(msp->dev,
290  "%s: ERROR: Invalid protocol (%d)!\n",
291  __func__, config->protocol);
292  return -EINVAL;
293  }
294  protdesc = (struct msp_protdesc *)
295  &prot_descs[config->protocol];
296  } else {
297  protdesc = (struct msp_protdesc *)&config->protdesc;
298  }
299 
300  mcfg = &config->multichannel_config;
301  if (mcfg->tx_multichannel_enable) {
302  if (protdesc->tx_phase_mode == MSP_SINGLE_PHASE) {
303  reg_val_MCR = readl(msp->registers + MSP_MCR);
304  writel(reg_val_MCR | (mcfg->tx_multichannel_enable ?
305  1 << TMCEN_BIT : 0),
306  msp->registers + MSP_MCR);
307  writel(mcfg->tx_channel_0_enable,
308  msp->registers + MSP_TCE0);
309  writel(mcfg->tx_channel_1_enable,
310  msp->registers + MSP_TCE1);
311  writel(mcfg->tx_channel_2_enable,
312  msp->registers + MSP_TCE2);
313  writel(mcfg->tx_channel_3_enable,
314  msp->registers + MSP_TCE3);
315  } else {
316  dev_err(msp->dev,
317  "%s: ERROR: Only single-phase supported (TX-mode: %d)!\n",
318  __func__, protdesc->tx_phase_mode);
319  return -EINVAL;
320  }
321  }
322  if (mcfg->rx_multichannel_enable) {
323  if (protdesc->rx_phase_mode == MSP_SINGLE_PHASE) {
324  reg_val_MCR = readl(msp->registers + MSP_MCR);
325  writel(reg_val_MCR | (mcfg->rx_multichannel_enable ?
326  1 << RMCEN_BIT : 0),
327  msp->registers + MSP_MCR);
328  writel(mcfg->rx_channel_0_enable,
329  msp->registers + MSP_RCE0);
330  writel(mcfg->rx_channel_1_enable,
331  msp->registers + MSP_RCE1);
332  writel(mcfg->rx_channel_2_enable,
333  msp->registers + MSP_RCE2);
334  writel(mcfg->rx_channel_3_enable,
335  msp->registers + MSP_RCE3);
336  } else {
337  dev_err(msp->dev,
338  "%s: ERROR: Only single-phase supported (RX-mode: %d)!\n",
339  __func__, protdesc->rx_phase_mode);
340  return -EINVAL;
341  }
342  if (mcfg->rx_comparison_enable_mode) {
343  reg_val_MCR = readl(msp->registers + MSP_MCR);
344  writel(reg_val_MCR |
345  (mcfg->rx_comparison_enable_mode << RCMPM_BIT),
346  msp->registers + MSP_MCR);
347 
348  writel(mcfg->comparison_mask,
349  msp->registers + MSP_RCM);
350  writel(mcfg->comparison_value,
351  msp->registers + MSP_RCV);
352 
353  }
354  }
355 
356  return 0;
357 }
358 
359 static int enable_msp(struct ux500_msp *msp, struct ux500_msp_config *config)
360 {
361  int status = 0, retval = 0;
362  u32 reg_val_DMACR, reg_val_GCR;
363  unsigned long flags;
364 
365  /* Check msp state whether in RUN or CONFIGURED Mode */
366  if (msp->msp_state == MSP_STATE_IDLE) {
367  spin_lock_irqsave(&msp_rxtx_lock, flags);
368  if (msp->pinctrl_rxtx_ref == 0 &&
369  !(IS_ERR(msp->pinctrl_p) || IS_ERR(msp->pinctrl_def))) {
370  retval = pinctrl_select_state(msp->pinctrl_p,
371  msp->pinctrl_def);
372  if (retval)
373  pr_err("could not set MSP defstate\n");
374  }
375  if (!retval)
376  msp->pinctrl_rxtx_ref++;
377  spin_unlock_irqrestore(&msp_rxtx_lock, flags);
378  }
379 
380  /* Configure msp with protocol dependent settings */
381  configure_protocol(msp, config);
382  setup_bitclk(msp, config);
383  if (config->multichannel_configured == 1) {
384  status = configure_multichannel(msp, config);
385  if (status)
386  dev_warn(msp->dev,
387  "%s: WARN: configure_multichannel failed (%d)!\n",
388  __func__, status);
389  }
390 
391  /* Make sure the correct DMA-directions are configured */
392  if ((config->direction & MSP_DIR_RX) && (!msp->dma_cfg_rx)) {
393  dev_err(msp->dev, "%s: ERROR: MSP RX-mode is not configured!",
394  __func__);
395  return -EINVAL;
396  }
397  if ((config->direction == MSP_DIR_TX) && (!msp->dma_cfg_tx)) {
398  dev_err(msp->dev, "%s: ERROR: MSP TX-mode is not configured!",
399  __func__);
400  return -EINVAL;
401  }
402 
403  reg_val_DMACR = readl(msp->registers + MSP_DMACR);
404  if (config->direction & MSP_DIR_RX)
405  reg_val_DMACR |= RX_DMA_ENABLE;
406  if (config->direction & MSP_DIR_TX)
407  reg_val_DMACR |= TX_DMA_ENABLE;
408  writel(reg_val_DMACR, msp->registers + MSP_DMACR);
409 
410  writel(config->iodelay, msp->registers + MSP_IODLY);
411 
412  /* Enable frame generation logic */
413  reg_val_GCR = readl(msp->registers + MSP_GCR);
414  writel(reg_val_GCR | FRAME_GEN_ENABLE, msp->registers + MSP_GCR);
415 
416  return status;
417 }
418 
419 static void flush_fifo_rx(struct ux500_msp *msp)
420 {
421  u32 reg_val_DR, reg_val_GCR, reg_val_FLR;
422  u32 limit = 32;
423 
424  reg_val_GCR = readl(msp->registers + MSP_GCR);
425  writel(reg_val_GCR | RX_ENABLE, msp->registers + MSP_GCR);
426 
427  reg_val_FLR = readl(msp->registers + MSP_FLR);
428  while (!(reg_val_FLR & RX_FIFO_EMPTY) && limit--) {
429  reg_val_DR = readl(msp->registers + MSP_DR);
430  reg_val_FLR = readl(msp->registers + MSP_FLR);
431  }
432 
433  writel(reg_val_GCR, msp->registers + MSP_GCR);
434 }
435 
436 static void flush_fifo_tx(struct ux500_msp *msp)
437 {
438  u32 reg_val_TSTDR, reg_val_GCR, reg_val_FLR;
439  u32 limit = 32;
440 
441  reg_val_GCR = readl(msp->registers + MSP_GCR);
442  writel(reg_val_GCR | TX_ENABLE, msp->registers + MSP_GCR);
443  writel(MSP_ITCR_ITEN | MSP_ITCR_TESTFIFO, msp->registers + MSP_ITCR);
444 
445  reg_val_FLR = readl(msp->registers + MSP_FLR);
446  while (!(reg_val_FLR & TX_FIFO_EMPTY) && limit--) {
447  reg_val_TSTDR = readl(msp->registers + MSP_TSTDR);
448  reg_val_FLR = readl(msp->registers + MSP_FLR);
449  }
450  writel(0x0, msp->registers + MSP_ITCR);
451  writel(reg_val_GCR, msp->registers + MSP_GCR);
452 }
453 
454 int ux500_msp_i2s_open(struct ux500_msp *msp,
455  struct ux500_msp_config *config)
456 {
457  u32 old_reg, new_reg, mask;
458  int res;
459  unsigned int tx_sel, rx_sel, tx_busy, rx_busy;
460 
461  if (in_interrupt()) {
462  dev_err(msp->dev,
463  "%s: ERROR: Open called in interrupt context!\n",
464  __func__);
465  return -1;
466  }
467 
468  tx_sel = (config->direction & MSP_DIR_TX) > 0;
469  rx_sel = (config->direction & MSP_DIR_RX) > 0;
470  if (!tx_sel && !rx_sel) {
471  dev_err(msp->dev, "%s: Error: No direction selected!\n",
472  __func__);
473  return -EINVAL;
474  }
475 
476  tx_busy = (msp->dir_busy & MSP_DIR_TX) > 0;
477  rx_busy = (msp->dir_busy & MSP_DIR_RX) > 0;
478  if (tx_busy && tx_sel) {
479  dev_err(msp->dev, "%s: Error: TX is in use!\n", __func__);
480  return -EBUSY;
481  }
482  if (rx_busy && rx_sel) {
483  dev_err(msp->dev, "%s: Error: RX is in use!\n", __func__);
484  return -EBUSY;
485  }
486 
487  msp->dir_busy |= (tx_sel ? MSP_DIR_TX : 0) | (rx_sel ? MSP_DIR_RX : 0);
488 
489  /* First do the global config register */
490  mask = RX_CLK_SEL_MASK | TX_CLK_SEL_MASK | RX_FSYNC_MASK |
491  TX_FSYNC_MASK | RX_SYNC_SEL_MASK | TX_SYNC_SEL_MASK |
492  RX_FIFO_ENABLE_MASK | TX_FIFO_ENABLE_MASK | SRG_CLK_SEL_MASK |
493  LOOPBACK_MASK | TX_EXTRA_DELAY_MASK;
494 
495  new_reg = (config->tx_clk_sel | config->rx_clk_sel |
496  config->rx_fsync_pol | config->tx_fsync_pol |
497  config->rx_fsync_sel | config->tx_fsync_sel |
498  config->rx_fifo_config | config->tx_fifo_config |
499  config->srg_clk_sel | config->loopback_enable |
500  config->tx_data_enable);
501 
502  old_reg = readl(msp->registers + MSP_GCR);
503  old_reg &= ~mask;
504  new_reg |= old_reg;
505  writel(new_reg, msp->registers + MSP_GCR);
506 
507  res = enable_msp(msp, config);
508  if (res < 0) {
509  dev_err(msp->dev, "%s: ERROR: enable_msp failed (%d)!\n",
510  __func__, res);
511  return -EBUSY;
512  }
513  if (config->loopback_enable & 0x80)
514  msp->loopback_enable = 1;
515 
516  /* Flush FIFOs */
517  flush_fifo_tx(msp);
518  flush_fifo_rx(msp);
519 
520  msp->msp_state = MSP_STATE_CONFIGURED;
521  return 0;
522 }
523 
524 static void disable_msp_rx(struct ux500_msp *msp)
525 {
526  u32 reg_val_GCR, reg_val_DMACR, reg_val_IMSC;
527 
528  reg_val_GCR = readl(msp->registers + MSP_GCR);
529  writel(reg_val_GCR & ~RX_ENABLE, msp->registers + MSP_GCR);
530  reg_val_DMACR = readl(msp->registers + MSP_DMACR);
531  writel(reg_val_DMACR & ~RX_DMA_ENABLE, msp->registers + MSP_DMACR);
532  reg_val_IMSC = readl(msp->registers + MSP_IMSC);
533  writel(reg_val_IMSC &
534  ~(RX_SERVICE_INT | RX_OVERRUN_ERROR_INT),
535  msp->registers + MSP_IMSC);
536 
537  msp->dir_busy &= ~MSP_DIR_RX;
538 }
539 
540 static void disable_msp_tx(struct ux500_msp *msp)
541 {
542  u32 reg_val_GCR, reg_val_DMACR, reg_val_IMSC;
543 
544  reg_val_GCR = readl(msp->registers + MSP_GCR);
545  writel(reg_val_GCR & ~TX_ENABLE, msp->registers + MSP_GCR);
546  reg_val_DMACR = readl(msp->registers + MSP_DMACR);
547  writel(reg_val_DMACR & ~TX_DMA_ENABLE, msp->registers + MSP_DMACR);
548  reg_val_IMSC = readl(msp->registers + MSP_IMSC);
549  writel(reg_val_IMSC &
550  ~(TX_SERVICE_INT | TX_UNDERRUN_ERR_INT),
551  msp->registers + MSP_IMSC);
552 
553  msp->dir_busy &= ~MSP_DIR_TX;
554 }
555 
556 static int disable_msp(struct ux500_msp *msp, unsigned int dir)
557 {
558  u32 reg_val_GCR;
559  int status = 0;
560  unsigned int disable_tx, disable_rx;
561 
562  reg_val_GCR = readl(msp->registers + MSP_GCR);
563  disable_tx = dir & MSP_DIR_TX;
564  disable_rx = dir & MSP_DIR_TX;
565  if (disable_tx && disable_rx) {
566  reg_val_GCR = readl(msp->registers + MSP_GCR);
567  writel(reg_val_GCR | LOOPBACK_MASK,
568  msp->registers + MSP_GCR);
569 
570  /* Flush TX-FIFO */
571  flush_fifo_tx(msp);
572 
573  /* Disable TX-channel */
574  writel((readl(msp->registers + MSP_GCR) &
575  (~TX_ENABLE)), msp->registers + MSP_GCR);
576 
577  /* Flush RX-FIFO */
578  flush_fifo_rx(msp);
579 
580  /* Disable Loopback and Receive channel */
581  writel((readl(msp->registers + MSP_GCR) &
582  (~(RX_ENABLE | LOOPBACK_MASK))),
583  msp->registers + MSP_GCR);
584 
585  disable_msp_tx(msp);
586  disable_msp_rx(msp);
587  } else if (disable_tx)
588  disable_msp_tx(msp);
589  else if (disable_rx)
590  disable_msp_rx(msp);
591 
592  return status;
593 }
594 
595 int ux500_msp_i2s_trigger(struct ux500_msp *msp, int cmd, int direction)
596 {
597  u32 reg_val_GCR, enable_bit;
598 
599  if (msp->msp_state == MSP_STATE_IDLE) {
600  dev_err(msp->dev, "%s: ERROR: MSP is not configured!\n",
601  __func__);
602  return -EINVAL;
603  }
604 
605  switch (cmd) {
606  case SNDRV_PCM_TRIGGER_START:
607  case SNDRV_PCM_TRIGGER_RESUME:
608  case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
609  if (direction == SNDRV_PCM_STREAM_PLAYBACK)
610  enable_bit = TX_ENABLE;
611  else
612  enable_bit = RX_ENABLE;
613  reg_val_GCR = readl(msp->registers + MSP_GCR);
614  writel(reg_val_GCR | enable_bit, msp->registers + MSP_GCR);
615  break;
616 
617  case SNDRV_PCM_TRIGGER_STOP:
618  case SNDRV_PCM_TRIGGER_SUSPEND:
619  case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
620  if (direction == SNDRV_PCM_STREAM_PLAYBACK)
621  disable_msp_tx(msp);
622  else
623  disable_msp_rx(msp);
624  break;
625  default:
626  return -EINVAL;
627  break;
628  }
629 
630  return 0;
631 }
632 
633 int ux500_msp_i2s_close(struct ux500_msp *msp, unsigned int dir)
634 {
635  int status = 0, retval = 0;
636  unsigned long flags;
637 
638  dev_dbg(msp->dev, "%s: Enter (dir = 0x%01x).\n", __func__, dir);
639 
640  status = disable_msp(msp, dir);
641  if (msp->dir_busy == 0) {
642  /* disable sample rate and frame generators */
643  msp->msp_state = MSP_STATE_IDLE;
644  writel((readl(msp->registers + MSP_GCR) &
645  (~(FRAME_GEN_ENABLE | SRG_ENABLE))),
646  msp->registers + MSP_GCR);
647 
648  spin_lock_irqsave(&msp_rxtx_lock, flags);
649  WARN_ON(!msp->pinctrl_rxtx_ref);
650  msp->pinctrl_rxtx_ref--;
651  if (msp->pinctrl_rxtx_ref == 0 &&
652  !(IS_ERR(msp->pinctrl_p) || IS_ERR(msp->pinctrl_sleep))) {
653  retval = pinctrl_select_state(msp->pinctrl_p,
654  msp->pinctrl_sleep);
655  if (retval)
656  pr_err("could not set MSP sleepstate\n");
657  }
658  spin_unlock_irqrestore(&msp_rxtx_lock, flags);
659 
660  writel(0, msp->registers + MSP_GCR);
661  writel(0, msp->registers + MSP_TCF);
662  writel(0, msp->registers + MSP_RCF);
663  writel(0, msp->registers + MSP_DMACR);
664  writel(0, msp->registers + MSP_SRG);
665  writel(0, msp->registers + MSP_MCR);
666  writel(0, msp->registers + MSP_RCM);
667  writel(0, msp->registers + MSP_RCV);
668  writel(0, msp->registers + MSP_TCE0);
669  writel(0, msp->registers + MSP_TCE1);
670  writel(0, msp->registers + MSP_TCE2);
671  writel(0, msp->registers + MSP_TCE3);
672  writel(0, msp->registers + MSP_RCE0);
673  writel(0, msp->registers + MSP_RCE1);
674  writel(0, msp->registers + MSP_RCE2);
675  writel(0, msp->registers + MSP_RCE3);
676  }
677 
678  return status;
679 
680 }
681 
682 int ux500_msp_i2s_init_msp(struct platform_device *pdev,
683  struct ux500_msp **msp_p,
684  struct msp_i2s_platform_data *platform_data)
685 {
686  struct resource *res = NULL;
687  struct i2s_controller *i2s_cont;
688  struct device_node *np = pdev->dev.of_node;
689  struct ux500_msp *msp;
690 
691  *msp_p = devm_kzalloc(&pdev->dev, sizeof(struct ux500_msp), GFP_KERNEL);
692  msp = *msp_p;
693  if (!msp)
694  return -ENOMEM;
695 
696  if (np) {
697  if (!platform_data) {
698  platform_data = devm_kzalloc(&pdev->dev,
699  sizeof(struct msp_i2s_platform_data), GFP_KERNEL);
700  if (!platform_data)
701  return -ENOMEM;
702  }
703  } else
704  if (!platform_data)
705  return -EINVAL;
706 
707  dev_dbg(&pdev->dev, "%s: Enter (name: %s, id: %d).\n", __func__,
708  pdev->name, platform_data->id);
709 
710  msp->id = platform_data->id;
711  msp->dev = &pdev->dev;
712  msp->dma_cfg_rx = platform_data->msp_i2s_dma_rx;
713  msp->dma_cfg_tx = platform_data->msp_i2s_dma_tx;
714 
715  res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
716  if (res == NULL) {
717  dev_err(&pdev->dev, "%s: ERROR: Unable to get resource!\n",
718  __func__);
719  return -ENOMEM;
720  }
721 
722  msp->registers = devm_ioremap(&pdev->dev, res->start,
723  resource_size(res));
724  if (msp->registers == NULL) {
725  dev_err(&pdev->dev, "%s: ERROR: ioremap failed!\n", __func__);
726  return -ENOMEM;
727  }
728 
729  msp->msp_state = MSP_STATE_IDLE;
730  msp->loopback_enable = 0;
731 
732  /* I2S-controller is allocated and added in I2S controller class. */
733  i2s_cont = devm_kzalloc(&pdev->dev, sizeof(*i2s_cont), GFP_KERNEL);
734  if (!i2s_cont) {
735  dev_err(&pdev->dev,
736  "%s: ERROR: Failed to allocate I2S-controller!\n",
737  __func__);
738  return -ENOMEM;
739  }
740  i2s_cont->dev.parent = &pdev->dev;
741  i2s_cont->data = (void *)msp;
742  i2s_cont->id = (s16)msp->id;
743  snprintf(i2s_cont->name, sizeof(i2s_cont->name), "ux500-msp-i2s.%04x",
744  msp->id);
745  dev_dbg(&pdev->dev, "I2S device-name: '%s'\n", i2s_cont->name);
746  msp->i2s_cont = i2s_cont;
747 
748  msp->pinctrl_p = pinctrl_get(msp->dev);
749  if (IS_ERR(msp->pinctrl_p))
750  dev_err(&pdev->dev, "could not get MSP pinctrl\n");
751  else {
752  msp->pinctrl_def = pinctrl_lookup_state(msp->pinctrl_p,
753  PINCTRL_STATE_DEFAULT);
754  if (IS_ERR(msp->pinctrl_def)) {
755  dev_err(&pdev->dev,
756  "could not get MSP defstate (%li)\n",
757  PTR_ERR(msp->pinctrl_def));
758  }
759  msp->pinctrl_sleep = pinctrl_lookup_state(msp->pinctrl_p,
760  PINCTRL_STATE_SLEEP);
761  if (IS_ERR(msp->pinctrl_sleep))
762  dev_err(&pdev->dev,
763  "could not get MSP idlestate (%li)\n",
764  PTR_ERR(msp->pinctrl_def));
765  }
766 
767  return 0;
768 }
769 
770 void ux500_msp_i2s_cleanup_msp(struct platform_device *pdev,
771  struct ux500_msp *msp)
772 {
773  dev_dbg(msp->dev, "%s: Enter (id = %d).\n", __func__, msp->id);
774 
775  device_unregister(&msp->i2s_cont->dev);
776 }
777 
778 MODULE_LICENSE("GPL v2");
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