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wm8983.c
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1 /*
2  * wm8983.c -- WM8983 ALSA SoC Audio driver
3  *
4  * Copyright 2011 Wolfson Microelectronics plc
5  *
6  * Author: Dimitris Papastamos <[email protected]>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12 
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/pm.h>
18 #include <linux/i2c.h>
19 #include <linux/regmap.h>
20 #include <linux/spi/spi.h>
21 #include <linux/slab.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/initval.h>
27 #include <sound/tlv.h>
28 
29 #include "wm8983.h"
30 
31 static const struct reg_default wm8983_defaults[] = {
32  { 0x01, 0x0000 }, /* R1 - Power management 1 */
33  { 0x02, 0x0000 }, /* R2 - Power management 2 */
34  { 0x03, 0x0000 }, /* R3 - Power management 3 */
35  { 0x04, 0x0050 }, /* R4 - Audio Interface */
36  { 0x05, 0x0000 }, /* R5 - Companding control */
37  { 0x06, 0x0140 }, /* R6 - Clock Gen control */
38  { 0x07, 0x0000 }, /* R7 - Additional control */
39  { 0x08, 0x0000 }, /* R8 - GPIO Control */
40  { 0x09, 0x0000 }, /* R9 - Jack Detect Control 1 */
41  { 0x0A, 0x0000 }, /* R10 - DAC Control */
42  { 0x0B, 0x00FF }, /* R11 - Left DAC digital Vol */
43  { 0x0C, 0x00FF }, /* R12 - Right DAC digital vol */
44  { 0x0D, 0x0000 }, /* R13 - Jack Detect Control 2 */
45  { 0x0E, 0x0100 }, /* R14 - ADC Control */
46  { 0x0F, 0x00FF }, /* R15 - Left ADC Digital Vol */
47  { 0x10, 0x00FF }, /* R16 - Right ADC Digital Vol */
48  { 0x12, 0x012C }, /* R18 - EQ1 - low shelf */
49  { 0x13, 0x002C }, /* R19 - EQ2 - peak 1 */
50  { 0x14, 0x002C }, /* R20 - EQ3 - peak 2 */
51  { 0x15, 0x002C }, /* R21 - EQ4 - peak 3 */
52  { 0x16, 0x002C }, /* R22 - EQ5 - high shelf */
53  { 0x18, 0x0032 }, /* R24 - DAC Limiter 1 */
54  { 0x19, 0x0000 }, /* R25 - DAC Limiter 2 */
55  { 0x1B, 0x0000 }, /* R27 - Notch Filter 1 */
56  { 0x1C, 0x0000 }, /* R28 - Notch Filter 2 */
57  { 0x1D, 0x0000 }, /* R29 - Notch Filter 3 */
58  { 0x1E, 0x0000 }, /* R30 - Notch Filter 4 */
59  { 0x20, 0x0038 }, /* R32 - ALC control 1 */
60  { 0x21, 0x000B }, /* R33 - ALC control 2 */
61  { 0x22, 0x0032 }, /* R34 - ALC control 3 */
62  { 0x23, 0x0000 }, /* R35 - Noise Gate */
63  { 0x24, 0x0008 }, /* R36 - PLL N */
64  { 0x25, 0x000C }, /* R37 - PLL K 1 */
65  { 0x26, 0x0093 }, /* R38 - PLL K 2 */
66  { 0x27, 0x00E9 }, /* R39 - PLL K 3 */
67  { 0x29, 0x0000 }, /* R41 - 3D control */
68  { 0x2A, 0x0000 }, /* R42 - OUT4 to ADC */
69  { 0x2B, 0x0000 }, /* R43 - Beep control */
70  { 0x2C, 0x0033 }, /* R44 - Input ctrl */
71  { 0x2D, 0x0010 }, /* R45 - Left INP PGA gain ctrl */
72  { 0x2E, 0x0010 }, /* R46 - Right INP PGA gain ctrl */
73  { 0x2F, 0x0100 }, /* R47 - Left ADC BOOST ctrl */
74  { 0x30, 0x0100 }, /* R48 - Right ADC BOOST ctrl */
75  { 0x31, 0x0002 }, /* R49 - Output ctrl */
76  { 0x32, 0x0001 }, /* R50 - Left mixer ctrl */
77  { 0x33, 0x0001 }, /* R51 - Right mixer ctrl */
78  { 0x34, 0x0039 }, /* R52 - LOUT1 (HP) volume ctrl */
79  { 0x35, 0x0039 }, /* R53 - ROUT1 (HP) volume ctrl */
80  { 0x36, 0x0039 }, /* R54 - LOUT2 (SPK) volume ctrl */
81  { 0x37, 0x0039 }, /* R55 - ROUT2 (SPK) volume ctrl */
82  { 0x38, 0x0001 }, /* R56 - OUT3 mixer ctrl */
83  { 0x39, 0x0001 }, /* R57 - OUT4 (MONO) mix ctrl */
84  { 0x3D, 0x0000 }, /* R61 - BIAS CTRL */
85 };
86 
87 static const struct wm8983_reg_access {
88  u16 read; /* Mask of readable bits */
89  u16 write; /* Mask of writable bits */
90 } wm8983_access_masks[WM8983_MAX_REGISTER + 1] = {
91  [0x00] = { 0x0000, 0x01FF }, /* R0 - Software Reset */
92  [0x01] = { 0x0000, 0x01FF }, /* R1 - Power management 1 */
93  [0x02] = { 0x0000, 0x01FF }, /* R2 - Power management 2 */
94  [0x03] = { 0x0000, 0x01EF }, /* R3 - Power management 3 */
95  [0x04] = { 0x0000, 0x01FF }, /* R4 - Audio Interface */
96  [0x05] = { 0x0000, 0x003F }, /* R5 - Companding control */
97  [0x06] = { 0x0000, 0x01FD }, /* R6 - Clock Gen control */
98  [0x07] = { 0x0000, 0x000F }, /* R7 - Additional control */
99  [0x08] = { 0x0000, 0x003F }, /* R8 - GPIO Control */
100  [0x09] = { 0x0000, 0x0070 }, /* R9 - Jack Detect Control 1 */
101  [0x0A] = { 0x0000, 0x004F }, /* R10 - DAC Control */
102  [0x0B] = { 0x0000, 0x01FF }, /* R11 - Left DAC digital Vol */
103  [0x0C] = { 0x0000, 0x01FF }, /* R12 - Right DAC digital vol */
104  [0x0D] = { 0x0000, 0x00FF }, /* R13 - Jack Detect Control 2 */
105  [0x0E] = { 0x0000, 0x01FB }, /* R14 - ADC Control */
106  [0x0F] = { 0x0000, 0x01FF }, /* R15 - Left ADC Digital Vol */
107  [0x10] = { 0x0000, 0x01FF }, /* R16 - Right ADC Digital Vol */
108  [0x12] = { 0x0000, 0x017F }, /* R18 - EQ1 - low shelf */
109  [0x13] = { 0x0000, 0x017F }, /* R19 - EQ2 - peak 1 */
110  [0x14] = { 0x0000, 0x017F }, /* R20 - EQ3 - peak 2 */
111  [0x15] = { 0x0000, 0x017F }, /* R21 - EQ4 - peak 3 */
112  [0x16] = { 0x0000, 0x007F }, /* R22 - EQ5 - high shelf */
113  [0x18] = { 0x0000, 0x01FF }, /* R24 - DAC Limiter 1 */
114  [0x19] = { 0x0000, 0x007F }, /* R25 - DAC Limiter 2 */
115  [0x1B] = { 0x0000, 0x01FF }, /* R27 - Notch Filter 1 */
116  [0x1C] = { 0x0000, 0x017F }, /* R28 - Notch Filter 2 */
117  [0x1D] = { 0x0000, 0x017F }, /* R29 - Notch Filter 3 */
118  [0x1E] = { 0x0000, 0x017F }, /* R30 - Notch Filter 4 */
119  [0x20] = { 0x0000, 0x01BF }, /* R32 - ALC control 1 */
120  [0x21] = { 0x0000, 0x00FF }, /* R33 - ALC control 2 */
121  [0x22] = { 0x0000, 0x01FF }, /* R34 - ALC control 3 */
122  [0x23] = { 0x0000, 0x000F }, /* R35 - Noise Gate */
123  [0x24] = { 0x0000, 0x001F }, /* R36 - PLL N */
124  [0x25] = { 0x0000, 0x003F }, /* R37 - PLL K 1 */
125  [0x26] = { 0x0000, 0x01FF }, /* R38 - PLL K 2 */
126  [0x27] = { 0x0000, 0x01FF }, /* R39 - PLL K 3 */
127  [0x29] = { 0x0000, 0x000F }, /* R41 - 3D control */
128  [0x2A] = { 0x0000, 0x01E7 }, /* R42 - OUT4 to ADC */
129  [0x2B] = { 0x0000, 0x01BF }, /* R43 - Beep control */
130  [0x2C] = { 0x0000, 0x0177 }, /* R44 - Input ctrl */
131  [0x2D] = { 0x0000, 0x01FF }, /* R45 - Left INP PGA gain ctrl */
132  [0x2E] = { 0x0000, 0x01FF }, /* R46 - Right INP PGA gain ctrl */
133  [0x2F] = { 0x0000, 0x0177 }, /* R47 - Left ADC BOOST ctrl */
134  [0x30] = { 0x0000, 0x0177 }, /* R48 - Right ADC BOOST ctrl */
135  [0x31] = { 0x0000, 0x007F }, /* R49 - Output ctrl */
136  [0x32] = { 0x0000, 0x01FF }, /* R50 - Left mixer ctrl */
137  [0x33] = { 0x0000, 0x01FF }, /* R51 - Right mixer ctrl */
138  [0x34] = { 0x0000, 0x01FF }, /* R52 - LOUT1 (HP) volume ctrl */
139  [0x35] = { 0x0000, 0x01FF }, /* R53 - ROUT1 (HP) volume ctrl */
140  [0x36] = { 0x0000, 0x01FF }, /* R54 - LOUT2 (SPK) volume ctrl */
141  [0x37] = { 0x0000, 0x01FF }, /* R55 - ROUT2 (SPK) volume ctrl */
142  [0x38] = { 0x0000, 0x004F }, /* R56 - OUT3 mixer ctrl */
143  [0x39] = { 0x0000, 0x00FF }, /* R57 - OUT4 (MONO) mix ctrl */
144  [0x3D] = { 0x0000, 0x0100 } /* R61 - BIAS CTRL */
145 };
146 
147 /* vol/gain update regs */
148 static const int vol_update_regs[] = {
149  WM8983_LEFT_DAC_DIGITAL_VOL,
150  WM8983_RIGHT_DAC_DIGITAL_VOL,
151  WM8983_LEFT_ADC_DIGITAL_VOL,
152  WM8983_RIGHT_ADC_DIGITAL_VOL,
153  WM8983_LOUT1_HP_VOLUME_CTRL,
154  WM8983_ROUT1_HP_VOLUME_CTRL,
155  WM8983_LOUT2_SPK_VOLUME_CTRL,
156  WM8983_ROUT2_SPK_VOLUME_CTRL,
157  WM8983_LEFT_INP_PGA_GAIN_CTRL,
158  WM8983_RIGHT_INP_PGA_GAIN_CTRL
159 };
160 
161 struct wm8983_priv {
162  struct regmap *regmap;
163  u32 sysclk;
164  u32 bclk;
165 };
166 
167 static const struct {
168  int div;
169  int ratio;
170 } fs_ratios[] = {
171  { 10, 128 },
172  { 15, 192 },
173  { 20, 256 },
174  { 30, 384 },
175  { 40, 512 },
176  { 60, 768 },
177  { 80, 1024 },
178  { 120, 1536 }
179 };
180 
181 static const int srates[] = { 48000, 32000, 24000, 16000, 12000, 8000 };
182 
183 static const int bclk_divs[] = {
184  1, 2, 4, 8, 16, 32
185 };
186 
187 static int eqmode_get(struct snd_kcontrol *kcontrol,
188  struct snd_ctl_elem_value *ucontrol);
189 static int eqmode_put(struct snd_kcontrol *kcontrol,
190  struct snd_ctl_elem_value *ucontrol);
191 
192 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12700, 50, 1);
193 static const DECLARE_TLV_DB_SCALE(adc_tlv, -12700, 50, 1);
194 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
195 static const DECLARE_TLV_DB_SCALE(lim_thresh_tlv, -600, 100, 0);
196 static const DECLARE_TLV_DB_SCALE(lim_boost_tlv, 0, 100, 0);
197 static const DECLARE_TLV_DB_SCALE(alc_min_tlv, -1200, 600, 0);
198 static const DECLARE_TLV_DB_SCALE(alc_max_tlv, -675, 600, 0);
199 static const DECLARE_TLV_DB_SCALE(alc_tar_tlv, -2250, 150, 0);
200 static const DECLARE_TLV_DB_SCALE(pga_vol_tlv, -1200, 75, 0);
201 static const DECLARE_TLV_DB_SCALE(boost_tlv, -1200, 300, 1);
202 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
203 static const DECLARE_TLV_DB_SCALE(aux_tlv, -1500, 300, 0);
204 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
205 static const DECLARE_TLV_DB_SCALE(pga_boost_tlv, 0, 2000, 0);
206 
207 static const char *alc_sel_text[] = { "Off", "Right", "Left", "Stereo" };
208 static const SOC_ENUM_SINGLE_DECL(alc_sel, WM8983_ALC_CONTROL_1, 7,
209  alc_sel_text);
210 
211 static const char *alc_mode_text[] = { "ALC", "Limiter" };
212 static const SOC_ENUM_SINGLE_DECL(alc_mode, WM8983_ALC_CONTROL_3, 8,
213  alc_mode_text);
214 
215 static const char *filter_mode_text[] = { "Audio", "Application" };
216 static const SOC_ENUM_SINGLE_DECL(filter_mode, WM8983_ADC_CONTROL, 7,
217  filter_mode_text);
218 
219 static const char *eq_bw_text[] = { "Narrow", "Wide" };
220 static const char *eqmode_text[] = { "Capture", "Playback" };
221 static const SOC_ENUM_SINGLE_EXT_DECL(eqmode, eqmode_text);
222 
223 static const char *eq1_cutoff_text[] = {
224  "80Hz", "105Hz", "135Hz", "175Hz"
225 };
226 static const SOC_ENUM_SINGLE_DECL(eq1_cutoff, WM8983_EQ1_LOW_SHELF, 5,
227  eq1_cutoff_text);
228 static const char *eq2_cutoff_text[] = {
229  "230Hz", "300Hz", "385Hz", "500Hz"
230 };
231 static const SOC_ENUM_SINGLE_DECL(eq2_bw, WM8983_EQ2_PEAK_1, 8, eq_bw_text);
232 static const SOC_ENUM_SINGLE_DECL(eq2_cutoff, WM8983_EQ2_PEAK_1, 5,
233  eq2_cutoff_text);
234 static const char *eq3_cutoff_text[] = {
235  "650Hz", "850Hz", "1.1kHz", "1.4kHz"
236 };
237 static const SOC_ENUM_SINGLE_DECL(eq3_bw, WM8983_EQ3_PEAK_2, 8, eq_bw_text);
238 static const SOC_ENUM_SINGLE_DECL(eq3_cutoff, WM8983_EQ3_PEAK_2, 5,
239  eq3_cutoff_text);
240 static const char *eq4_cutoff_text[] = {
241  "1.8kHz", "2.4kHz", "3.2kHz", "4.1kHz"
242 };
243 static const SOC_ENUM_SINGLE_DECL(eq4_bw, WM8983_EQ4_PEAK_3, 8, eq_bw_text);
244 static const SOC_ENUM_SINGLE_DECL(eq4_cutoff, WM8983_EQ4_PEAK_3, 5,
245  eq4_cutoff_text);
246 static const char *eq5_cutoff_text[] = {
247  "5.3kHz", "6.9kHz", "9kHz", "11.7kHz"
248 };
249 static const SOC_ENUM_SINGLE_DECL(eq5_cutoff, WM8983_EQ5_HIGH_SHELF, 5,
250  eq5_cutoff_text);
251 
252 static const char *depth_3d_text[] = {
253  "Off",
254  "6.67%",
255  "13.3%",
256  "20%",
257  "26.7%",
258  "33.3%",
259  "40%",
260  "46.6%",
261  "53.3%",
262  "60%",
263  "66.7%",
264  "73.3%",
265  "80%",
266  "86.7%",
267  "93.3%",
268  "100%"
269 };
270 static const SOC_ENUM_SINGLE_DECL(depth_3d, WM8983_3D_CONTROL, 0,
271  depth_3d_text);
272 
273 static const struct snd_kcontrol_new wm8983_snd_controls[] = {
274  SOC_SINGLE("Digital Loopback Switch", WM8983_COMPANDING_CONTROL,
275  0, 1, 0),
276 
277  SOC_ENUM("ALC Capture Function", alc_sel),
278  SOC_SINGLE_TLV("ALC Capture Max Volume", WM8983_ALC_CONTROL_1,
279  3, 7, 0, alc_max_tlv),
280  SOC_SINGLE_TLV("ALC Capture Min Volume", WM8983_ALC_CONTROL_1,
281  0, 7, 0, alc_min_tlv),
282  SOC_SINGLE_TLV("ALC Capture Target Volume", WM8983_ALC_CONTROL_2,
283  0, 15, 0, alc_tar_tlv),
284  SOC_SINGLE("ALC Capture Attack", WM8983_ALC_CONTROL_3, 0, 10, 0),
285  SOC_SINGLE("ALC Capture Hold", WM8983_ALC_CONTROL_2, 4, 10, 0),
286  SOC_SINGLE("ALC Capture Decay", WM8983_ALC_CONTROL_3, 4, 10, 0),
287  SOC_ENUM("ALC Mode", alc_mode),
288  SOC_SINGLE("ALC Capture NG Switch", WM8983_NOISE_GATE,
289  3, 1, 0),
290  SOC_SINGLE("ALC Capture NG Threshold", WM8983_NOISE_GATE,
291  0, 7, 1),
292 
293  SOC_DOUBLE_R_TLV("Capture Volume", WM8983_LEFT_ADC_DIGITAL_VOL,
294  WM8983_RIGHT_ADC_DIGITAL_VOL, 0, 255, 0, adc_tlv),
295  SOC_DOUBLE_R("Capture PGA ZC Switch", WM8983_LEFT_INP_PGA_GAIN_CTRL,
296  WM8983_RIGHT_INP_PGA_GAIN_CTRL, 7, 1, 0),
297  SOC_DOUBLE_R_TLV("Capture PGA Volume", WM8983_LEFT_INP_PGA_GAIN_CTRL,
298  WM8983_RIGHT_INP_PGA_GAIN_CTRL, 0, 63, 0, pga_vol_tlv),
299 
300  SOC_DOUBLE_R_TLV("Capture PGA Boost Volume",
301  WM8983_LEFT_ADC_BOOST_CTRL, WM8983_RIGHT_ADC_BOOST_CTRL,
302  8, 1, 0, pga_boost_tlv),
303 
304  SOC_DOUBLE("ADC Inversion Switch", WM8983_ADC_CONTROL, 0, 1, 1, 0),
305  SOC_SINGLE("ADC 128x Oversampling Switch", WM8983_ADC_CONTROL, 8, 1, 0),
306 
307  SOC_DOUBLE_R_TLV("Playback Volume", WM8983_LEFT_DAC_DIGITAL_VOL,
308  WM8983_RIGHT_DAC_DIGITAL_VOL, 0, 255, 0, dac_tlv),
309 
310  SOC_SINGLE("DAC Playback Limiter Switch", WM8983_DAC_LIMITER_1, 8, 1, 0),
311  SOC_SINGLE("DAC Playback Limiter Decay", WM8983_DAC_LIMITER_1, 4, 10, 0),
312  SOC_SINGLE("DAC Playback Limiter Attack", WM8983_DAC_LIMITER_1, 0, 11, 0),
313  SOC_SINGLE_TLV("DAC Playback Limiter Threshold", WM8983_DAC_LIMITER_2,
314  4, 7, 1, lim_thresh_tlv),
315  SOC_SINGLE_TLV("DAC Playback Limiter Boost Volume", WM8983_DAC_LIMITER_2,
316  0, 12, 0, lim_boost_tlv),
317  SOC_DOUBLE("DAC Inversion Switch", WM8983_DAC_CONTROL, 0, 1, 1, 0),
318  SOC_SINGLE("DAC Auto Mute Switch", WM8983_DAC_CONTROL, 2, 1, 0),
319  SOC_SINGLE("DAC 128x Oversampling Switch", WM8983_DAC_CONTROL, 3, 1, 0),
320 
321  SOC_DOUBLE_R_TLV("Headphone Playback Volume", WM8983_LOUT1_HP_VOLUME_CTRL,
322  WM8983_ROUT1_HP_VOLUME_CTRL, 0, 63, 0, out_tlv),
323  SOC_DOUBLE_R("Headphone Playback ZC Switch", WM8983_LOUT1_HP_VOLUME_CTRL,
324  WM8983_ROUT1_HP_VOLUME_CTRL, 7, 1, 0),
325  SOC_DOUBLE_R("Headphone Switch", WM8983_LOUT1_HP_VOLUME_CTRL,
326  WM8983_ROUT1_HP_VOLUME_CTRL, 6, 1, 1),
327 
328  SOC_DOUBLE_R_TLV("Speaker Playback Volume", WM8983_LOUT2_SPK_VOLUME_CTRL,
329  WM8983_ROUT2_SPK_VOLUME_CTRL, 0, 63, 0, out_tlv),
330  SOC_DOUBLE_R("Speaker Playback ZC Switch", WM8983_LOUT2_SPK_VOLUME_CTRL,
331  WM8983_ROUT2_SPK_VOLUME_CTRL, 7, 1, 0),
332  SOC_DOUBLE_R("Speaker Switch", WM8983_LOUT2_SPK_VOLUME_CTRL,
333  WM8983_ROUT2_SPK_VOLUME_CTRL, 6, 1, 1),
334 
335  SOC_SINGLE("OUT3 Switch", WM8983_OUT3_MIXER_CTRL,
336  6, 1, 1),
337 
338  SOC_SINGLE("OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
339  6, 1, 1),
340 
341  SOC_SINGLE("High Pass Filter Switch", WM8983_ADC_CONTROL, 8, 1, 0),
342  SOC_ENUM("High Pass Filter Mode", filter_mode),
343  SOC_SINGLE("High Pass Filter Cutoff", WM8983_ADC_CONTROL, 4, 7, 0),
344 
345  SOC_DOUBLE_R_TLV("Aux Bypass Volume",
346  WM8983_LEFT_MIXER_CTRL, WM8983_RIGHT_MIXER_CTRL, 6, 7, 0,
347  aux_tlv),
348 
349  SOC_DOUBLE_R_TLV("Input PGA Bypass Volume",
350  WM8983_LEFT_MIXER_CTRL, WM8983_RIGHT_MIXER_CTRL, 2, 7, 0,
351  bypass_tlv),
352 
353  SOC_ENUM_EXT("Equalizer Function", eqmode, eqmode_get, eqmode_put),
354  SOC_ENUM("EQ1 Cutoff", eq1_cutoff),
355  SOC_SINGLE_TLV("EQ1 Volume", WM8983_EQ1_LOW_SHELF, 0, 24, 1, eq_tlv),
356  SOC_ENUM("EQ2 Bandwith", eq2_bw),
357  SOC_ENUM("EQ2 Cutoff", eq2_cutoff),
358  SOC_SINGLE_TLV("EQ2 Volume", WM8983_EQ2_PEAK_1, 0, 24, 1, eq_tlv),
359  SOC_ENUM("EQ3 Bandwith", eq3_bw),
360  SOC_ENUM("EQ3 Cutoff", eq3_cutoff),
361  SOC_SINGLE_TLV("EQ3 Volume", WM8983_EQ3_PEAK_2, 0, 24, 1, eq_tlv),
362  SOC_ENUM("EQ4 Bandwith", eq4_bw),
363  SOC_ENUM("EQ4 Cutoff", eq4_cutoff),
364  SOC_SINGLE_TLV("EQ4 Volume", WM8983_EQ4_PEAK_3, 0, 24, 1, eq_tlv),
365  SOC_ENUM("EQ5 Cutoff", eq5_cutoff),
366  SOC_SINGLE_TLV("EQ5 Volume", WM8983_EQ5_HIGH_SHELF, 0, 24, 1, eq_tlv),
367 
368  SOC_ENUM("3D Depth", depth_3d),
369 };
370 
371 static const struct snd_kcontrol_new left_out_mixer[] = {
372  SOC_DAPM_SINGLE("Line Switch", WM8983_LEFT_MIXER_CTRL, 1, 1, 0),
373  SOC_DAPM_SINGLE("Aux Switch", WM8983_LEFT_MIXER_CTRL, 5, 1, 0),
374  SOC_DAPM_SINGLE("PCM Switch", WM8983_LEFT_MIXER_CTRL, 0, 1, 0),
375 };
376 
377 static const struct snd_kcontrol_new right_out_mixer[] = {
378  SOC_DAPM_SINGLE("Line Switch", WM8983_RIGHT_MIXER_CTRL, 1, 1, 0),
379  SOC_DAPM_SINGLE("Aux Switch", WM8983_RIGHT_MIXER_CTRL, 5, 1, 0),
380  SOC_DAPM_SINGLE("PCM Switch", WM8983_RIGHT_MIXER_CTRL, 0, 1, 0),
381 };
382 
383 static const struct snd_kcontrol_new left_input_mixer[] = {
384  SOC_DAPM_SINGLE("L2 Switch", WM8983_INPUT_CTRL, 2, 1, 0),
385  SOC_DAPM_SINGLE("MicN Switch", WM8983_INPUT_CTRL, 1, 1, 0),
386  SOC_DAPM_SINGLE("MicP Switch", WM8983_INPUT_CTRL, 0, 1, 0),
387 };
388 
389 static const struct snd_kcontrol_new right_input_mixer[] = {
390  SOC_DAPM_SINGLE("R2 Switch", WM8983_INPUT_CTRL, 6, 1, 0),
391  SOC_DAPM_SINGLE("MicN Switch", WM8983_INPUT_CTRL, 5, 1, 0),
392  SOC_DAPM_SINGLE("MicP Switch", WM8983_INPUT_CTRL, 4, 1, 0),
393 };
394 
395 static const struct snd_kcontrol_new left_boost_mixer[] = {
396  SOC_DAPM_SINGLE_TLV("L2 Volume", WM8983_LEFT_ADC_BOOST_CTRL,
397  4, 7, 0, boost_tlv),
398  SOC_DAPM_SINGLE_TLV("AUXL Volume", WM8983_LEFT_ADC_BOOST_CTRL,
399  0, 7, 0, boost_tlv)
400 };
401 
402 static const struct snd_kcontrol_new out3_mixer[] = {
403  SOC_DAPM_SINGLE("LMIX2OUT3 Switch", WM8983_OUT3_MIXER_CTRL,
404  1, 1, 0),
405  SOC_DAPM_SINGLE("LDAC2OUT3 Switch", WM8983_OUT3_MIXER_CTRL,
406  0, 1, 0),
407 };
408 
409 static const struct snd_kcontrol_new out4_mixer[] = {
410  SOC_DAPM_SINGLE("LMIX2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
411  4, 1, 0),
412  SOC_DAPM_SINGLE("RMIX2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
413  1, 1, 0),
414  SOC_DAPM_SINGLE("LDAC2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
415  3, 1, 0),
416  SOC_DAPM_SINGLE("RDAC2OUT4 Switch", WM8983_OUT4_MONO_MIX_CTRL,
417  0, 1, 0),
418 };
419 
420 static const struct snd_kcontrol_new right_boost_mixer[] = {
421  SOC_DAPM_SINGLE_TLV("R2 Volume", WM8983_RIGHT_ADC_BOOST_CTRL,
422  4, 7, 0, boost_tlv),
423  SOC_DAPM_SINGLE_TLV("AUXR Volume", WM8983_RIGHT_ADC_BOOST_CTRL,
424  0, 7, 0, boost_tlv)
425 };
426 
427 static const struct snd_soc_dapm_widget wm8983_dapm_widgets[] = {
428  SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8983_POWER_MANAGEMENT_3,
429  0, 0),
430  SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8983_POWER_MANAGEMENT_3,
431  1, 0),
432  SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8983_POWER_MANAGEMENT_2,
433  0, 0),
434  SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8983_POWER_MANAGEMENT_2,
435  1, 0),
436 
437  SND_SOC_DAPM_MIXER("Left Output Mixer", WM8983_POWER_MANAGEMENT_3,
438  2, 0, left_out_mixer, ARRAY_SIZE(left_out_mixer)),
439  SND_SOC_DAPM_MIXER("Right Output Mixer", WM8983_POWER_MANAGEMENT_3,
440  3, 0, right_out_mixer, ARRAY_SIZE(right_out_mixer)),
441 
442  SND_SOC_DAPM_MIXER("Left Input Mixer", WM8983_POWER_MANAGEMENT_2,
443  2, 0, left_input_mixer, ARRAY_SIZE(left_input_mixer)),
444  SND_SOC_DAPM_MIXER("Right Input Mixer", WM8983_POWER_MANAGEMENT_2,
445  3, 0, right_input_mixer, ARRAY_SIZE(right_input_mixer)),
446 
447  SND_SOC_DAPM_MIXER("Left Boost Mixer", WM8983_POWER_MANAGEMENT_2,
448  4, 0, left_boost_mixer, ARRAY_SIZE(left_boost_mixer)),
449  SND_SOC_DAPM_MIXER("Right Boost Mixer", WM8983_POWER_MANAGEMENT_2,
450  5, 0, right_boost_mixer, ARRAY_SIZE(right_boost_mixer)),
451 
452  SND_SOC_DAPM_MIXER("OUT3 Mixer", WM8983_POWER_MANAGEMENT_1,
453  6, 0, out3_mixer, ARRAY_SIZE(out3_mixer)),
454 
455  SND_SOC_DAPM_MIXER("OUT4 Mixer", WM8983_POWER_MANAGEMENT_1,
456  7, 0, out4_mixer, ARRAY_SIZE(out4_mixer)),
457 
458  SND_SOC_DAPM_PGA("Left Capture PGA", WM8983_LEFT_INP_PGA_GAIN_CTRL,
459  6, 1, NULL, 0),
460  SND_SOC_DAPM_PGA("Right Capture PGA", WM8983_RIGHT_INP_PGA_GAIN_CTRL,
461  6, 1, NULL, 0),
462 
463  SND_SOC_DAPM_PGA("Left Headphone Out", WM8983_POWER_MANAGEMENT_2,
464  7, 0, NULL, 0),
465  SND_SOC_DAPM_PGA("Right Headphone Out", WM8983_POWER_MANAGEMENT_2,
466  8, 0, NULL, 0),
467 
468  SND_SOC_DAPM_PGA("Left Speaker Out", WM8983_POWER_MANAGEMENT_3,
469  5, 0, NULL, 0),
470  SND_SOC_DAPM_PGA("Right Speaker Out", WM8983_POWER_MANAGEMENT_3,
471  6, 0, NULL, 0),
472 
473  SND_SOC_DAPM_PGA("OUT3 Out", WM8983_POWER_MANAGEMENT_3,
474  7, 0, NULL, 0),
475 
476  SND_SOC_DAPM_PGA("OUT4 Out", WM8983_POWER_MANAGEMENT_3,
477  8, 0, NULL, 0),
478 
479  SND_SOC_DAPM_SUPPLY("Mic Bias", WM8983_POWER_MANAGEMENT_1, 4, 0,
480  NULL, 0),
481 
482  SND_SOC_DAPM_INPUT("LIN"),
483  SND_SOC_DAPM_INPUT("LIP"),
484  SND_SOC_DAPM_INPUT("RIN"),
485  SND_SOC_DAPM_INPUT("RIP"),
486  SND_SOC_DAPM_INPUT("AUXL"),
487  SND_SOC_DAPM_INPUT("AUXR"),
488  SND_SOC_DAPM_INPUT("L2"),
489  SND_SOC_DAPM_INPUT("R2"),
490  SND_SOC_DAPM_OUTPUT("HPL"),
491  SND_SOC_DAPM_OUTPUT("HPR"),
492  SND_SOC_DAPM_OUTPUT("SPKL"),
493  SND_SOC_DAPM_OUTPUT("SPKR"),
494  SND_SOC_DAPM_OUTPUT("OUT3"),
495  SND_SOC_DAPM_OUTPUT("OUT4")
496 };
497 
498 static const struct snd_soc_dapm_route wm8983_audio_map[] = {
499  { "OUT3 Mixer", "LMIX2OUT3 Switch", "Left Output Mixer" },
500  { "OUT3 Mixer", "LDAC2OUT3 Switch", "Left DAC" },
501 
502  { "OUT3 Out", NULL, "OUT3 Mixer" },
503  { "OUT3", NULL, "OUT3 Out" },
504 
505  { "OUT4 Mixer", "LMIX2OUT4 Switch", "Left Output Mixer" },
506  { "OUT4 Mixer", "RMIX2OUT4 Switch", "Right Output Mixer" },
507  { "OUT4 Mixer", "LDAC2OUT4 Switch", "Left DAC" },
508  { "OUT4 Mixer", "RDAC2OUT4 Switch", "Right DAC" },
509 
510  { "OUT4 Out", NULL, "OUT4 Mixer" },
511  { "OUT4", NULL, "OUT4 Out" },
512 
513  { "Right Output Mixer", "PCM Switch", "Right DAC" },
514  { "Right Output Mixer", "Aux Switch", "AUXR" },
515  { "Right Output Mixer", "Line Switch", "Right Boost Mixer" },
516 
517  { "Left Output Mixer", "PCM Switch", "Left DAC" },
518  { "Left Output Mixer", "Aux Switch", "AUXL" },
519  { "Left Output Mixer", "Line Switch", "Left Boost Mixer" },
520 
521  { "Right Headphone Out", NULL, "Right Output Mixer" },
522  { "HPR", NULL, "Right Headphone Out" },
523 
524  { "Left Headphone Out", NULL, "Left Output Mixer" },
525  { "HPL", NULL, "Left Headphone Out" },
526 
527  { "Right Speaker Out", NULL, "Right Output Mixer" },
528  { "SPKR", NULL, "Right Speaker Out" },
529 
530  { "Left Speaker Out", NULL, "Left Output Mixer" },
531  { "SPKL", NULL, "Left Speaker Out" },
532 
533  { "Right ADC", NULL, "Right Boost Mixer" },
534 
535  { "Right Boost Mixer", "AUXR Volume", "AUXR" },
536  { "Right Boost Mixer", NULL, "Right Capture PGA" },
537  { "Right Boost Mixer", "R2 Volume", "R2" },
538 
539  { "Left ADC", NULL, "Left Boost Mixer" },
540 
541  { "Left Boost Mixer", "AUXL Volume", "AUXL" },
542  { "Left Boost Mixer", NULL, "Left Capture PGA" },
543  { "Left Boost Mixer", "L2 Volume", "L2" },
544 
545  { "Right Capture PGA", NULL, "Right Input Mixer" },
546  { "Left Capture PGA", NULL, "Left Input Mixer" },
547 
548  { "Right Input Mixer", "R2 Switch", "R2" },
549  { "Right Input Mixer", "MicN Switch", "RIN" },
550  { "Right Input Mixer", "MicP Switch", "RIP" },
551 
552  { "Left Input Mixer", "L2 Switch", "L2" },
553  { "Left Input Mixer", "MicN Switch", "LIN" },
554  { "Left Input Mixer", "MicP Switch", "LIP" },
555 };
556 
557 static int eqmode_get(struct snd_kcontrol *kcontrol,
558  struct snd_ctl_elem_value *ucontrol)
559 {
560  struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
561  unsigned int reg;
562 
563  reg = snd_soc_read(codec, WM8983_EQ1_LOW_SHELF);
564  if (reg & WM8983_EQ3DMODE)
565  ucontrol->value.integer.value[0] = 1;
566  else
567  ucontrol->value.integer.value[0] = 0;
568 
569  return 0;
570 }
571 
572 static int eqmode_put(struct snd_kcontrol *kcontrol,
573  struct snd_ctl_elem_value *ucontrol)
574 {
575  struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
576  unsigned int regpwr2, regpwr3;
577  unsigned int reg_eq;
578 
579  if (ucontrol->value.integer.value[0] != 0
580  && ucontrol->value.integer.value[0] != 1)
581  return -EINVAL;
582 
583  reg_eq = snd_soc_read(codec, WM8983_EQ1_LOW_SHELF);
584  switch ((reg_eq & WM8983_EQ3DMODE) >> WM8983_EQ3DMODE_SHIFT) {
585  case 0:
586  if (!ucontrol->value.integer.value[0])
587  return 0;
588  break;
589  case 1:
590  if (ucontrol->value.integer.value[0])
591  return 0;
592  break;
593  }
594 
595  regpwr2 = snd_soc_read(codec, WM8983_POWER_MANAGEMENT_2);
596  regpwr3 = snd_soc_read(codec, WM8983_POWER_MANAGEMENT_3);
597  /* disable the DACs and ADCs */
598  snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_2,
599  WM8983_ADCENR_MASK | WM8983_ADCENL_MASK, 0);
600  snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_3,
601  WM8983_DACENR_MASK | WM8983_DACENL_MASK, 0);
602  /* set the desired eqmode */
603  snd_soc_update_bits(codec, WM8983_EQ1_LOW_SHELF,
604  WM8983_EQ3DMODE_MASK,
605  ucontrol->value.integer.value[0]
606  << WM8983_EQ3DMODE_SHIFT);
607  /* restore DAC/ADC configuration */
608  snd_soc_write(codec, WM8983_POWER_MANAGEMENT_2, regpwr2);
609  snd_soc_write(codec, WM8983_POWER_MANAGEMENT_3, regpwr3);
610  return 0;
611 }
612 
613 static bool wm8983_readable(struct device *dev, unsigned int reg)
614 {
615  if (reg > WM8983_MAX_REGISTER)
616  return 0;
617 
618  return wm8983_access_masks[reg].read != 0;
619 }
620 
621 static int wm8983_dac_mute(struct snd_soc_dai *dai, int mute)
622 {
623  struct snd_soc_codec *codec = dai->codec;
624 
625  return snd_soc_update_bits(codec, WM8983_DAC_CONTROL,
626  WM8983_SOFTMUTE_MASK,
627  !!mute << WM8983_SOFTMUTE_SHIFT);
628 }
629 
630 static int wm8983_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
631 {
632  struct snd_soc_codec *codec = dai->codec;
633  u16 format, master, bcp, lrp;
634 
635  switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
636  case SND_SOC_DAIFMT_I2S:
637  format = 0x2;
638  break;
639  case SND_SOC_DAIFMT_RIGHT_J:
640  format = 0x0;
641  break;
642  case SND_SOC_DAIFMT_LEFT_J:
643  format = 0x1;
644  break;
645  case SND_SOC_DAIFMT_DSP_A:
646  case SND_SOC_DAIFMT_DSP_B:
647  format = 0x3;
648  break;
649  default:
650  dev_err(dai->dev, "Unknown dai format\n");
651  return -EINVAL;
652  }
653 
654  snd_soc_update_bits(codec, WM8983_AUDIO_INTERFACE,
655  WM8983_FMT_MASK, format << WM8983_FMT_SHIFT);
656 
657  switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
658  case SND_SOC_DAIFMT_CBM_CFM:
659  master = 1;
660  break;
661  case SND_SOC_DAIFMT_CBS_CFS:
662  master = 0;
663  break;
664  default:
665  dev_err(dai->dev, "Unknown master/slave configuration\n");
666  return -EINVAL;
667  }
668 
669  snd_soc_update_bits(codec, WM8983_CLOCK_GEN_CONTROL,
670  WM8983_MS_MASK, master << WM8983_MS_SHIFT);
671 
672  /* FIXME: We don't currently support DSP A/B modes */
673  switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
674  case SND_SOC_DAIFMT_DSP_A:
675  case SND_SOC_DAIFMT_DSP_B:
676  dev_err(dai->dev, "DSP A/B modes are not supported\n");
677  return -EINVAL;
678  default:
679  break;
680  }
681 
682  bcp = lrp = 0;
683  switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
684  case SND_SOC_DAIFMT_NB_NF:
685  break;
686  case SND_SOC_DAIFMT_IB_IF:
687  bcp = lrp = 1;
688  break;
689  case SND_SOC_DAIFMT_IB_NF:
690  bcp = 1;
691  break;
692  case SND_SOC_DAIFMT_NB_IF:
693  lrp = 1;
694  break;
695  default:
696  dev_err(dai->dev, "Unknown polarity configuration\n");
697  return -EINVAL;
698  }
699 
700  snd_soc_update_bits(codec, WM8983_AUDIO_INTERFACE,
701  WM8983_LRCP_MASK, lrp << WM8983_LRCP_SHIFT);
702  snd_soc_update_bits(codec, WM8983_AUDIO_INTERFACE,
703  WM8983_BCP_MASK, bcp << WM8983_BCP_SHIFT);
704  return 0;
705 }
706 
707 static int wm8983_hw_params(struct snd_pcm_substream *substream,
708  struct snd_pcm_hw_params *params,
709  struct snd_soc_dai *dai)
710 {
711  int i;
712  struct snd_soc_codec *codec = dai->codec;
713  struct wm8983_priv *wm8983 = snd_soc_codec_get_drvdata(codec);
714  u16 blen, srate_idx;
715  u32 tmp;
716  int srate_best;
717  int ret;
718 
719  ret = snd_soc_params_to_bclk(params);
720  if (ret < 0) {
721  dev_err(codec->dev, "Failed to convert params to bclk: %d\n", ret);
722  return ret;
723  }
724 
725  wm8983->bclk = ret;
726 
727  switch (params_format(params)) {
728  case SNDRV_PCM_FORMAT_S16_LE:
729  blen = 0x0;
730  break;
731  case SNDRV_PCM_FORMAT_S20_3LE:
732  blen = 0x1;
733  break;
734  case SNDRV_PCM_FORMAT_S24_LE:
735  blen = 0x2;
736  break;
737  case SNDRV_PCM_FORMAT_S32_LE:
738  blen = 0x3;
739  break;
740  default:
741  dev_err(dai->dev, "Unsupported word length %u\n",
742  params_format(params));
743  return -EINVAL;
744  }
745 
746  snd_soc_update_bits(codec, WM8983_AUDIO_INTERFACE,
747  WM8983_WL_MASK, blen << WM8983_WL_SHIFT);
748 
749  /*
750  * match to the nearest possible sample rate and rely
751  * on the array index to configure the SR register
752  */
753  srate_idx = 0;
754  srate_best = abs(srates[0] - params_rate(params));
755  for (i = 1; i < ARRAY_SIZE(srates); ++i) {
756  if (abs(srates[i] - params_rate(params)) >= srate_best)
757  continue;
758  srate_idx = i;
759  srate_best = abs(srates[i] - params_rate(params));
760  }
761 
762  dev_dbg(dai->dev, "Selected SRATE = %d\n", srates[srate_idx]);
763  snd_soc_update_bits(codec, WM8983_ADDITIONAL_CONTROL,
764  WM8983_SR_MASK, srate_idx << WM8983_SR_SHIFT);
765 
766  dev_dbg(dai->dev, "Target BCLK = %uHz\n", wm8983->bclk);
767  dev_dbg(dai->dev, "SYSCLK = %uHz\n", wm8983->sysclk);
768 
769  for (i = 0; i < ARRAY_SIZE(fs_ratios); ++i) {
770  if (wm8983->sysclk / params_rate(params)
771  == fs_ratios[i].ratio)
772  break;
773  }
774 
775  if (i == ARRAY_SIZE(fs_ratios)) {
776  dev_err(dai->dev, "Unable to configure MCLK ratio %u/%u\n",
777  wm8983->sysclk, params_rate(params));
778  return -EINVAL;
779  }
780 
781  dev_dbg(dai->dev, "MCLK ratio = %dfs\n", fs_ratios[i].ratio);
782  snd_soc_update_bits(codec, WM8983_CLOCK_GEN_CONTROL,
783  WM8983_MCLKDIV_MASK, i << WM8983_MCLKDIV_SHIFT);
784 
785  /* select the appropriate bclk divider */
786  tmp = (wm8983->sysclk / fs_ratios[i].div) * 10;
787  for (i = 0; i < ARRAY_SIZE(bclk_divs); ++i) {
788  if (wm8983->bclk == tmp / bclk_divs[i])
789  break;
790  }
791 
792  if (i == ARRAY_SIZE(bclk_divs)) {
793  dev_err(dai->dev, "No matching BCLK divider found\n");
794  return -EINVAL;
795  }
796 
797  dev_dbg(dai->dev, "BCLK div = %d\n", i);
798  snd_soc_update_bits(codec, WM8983_CLOCK_GEN_CONTROL,
799  WM8983_BCLKDIV_MASK, i << WM8983_BCLKDIV_SHIFT);
800 
801  return 0;
802 }
803 
804 struct pll_div {
805  u32 div2:1;
806  u32 n:4;
807  u32 k:24;
808 };
809 
810 #define FIXED_PLL_SIZE ((1ULL << 24) * 10)
811 static int pll_factors(struct pll_div *pll_div, unsigned int target,
812  unsigned int source)
813 {
814  u64 Kpart;
815  unsigned long int K, Ndiv, Nmod;
816 
817  pll_div->div2 = 0;
818  Ndiv = target / source;
819  if (Ndiv < 6) {
820  source >>= 1;
821  pll_div->div2 = 1;
822  Ndiv = target / source;
823  }
824 
825  if (Ndiv < 6 || Ndiv > 12) {
826  printk(KERN_ERR "%s: WM8983 N value is not within"
827  " the recommended range: %lu\n", __func__, Ndiv);
828  return -EINVAL;
829  }
830  pll_div->n = Ndiv;
831 
832  Nmod = target % source;
833  Kpart = FIXED_PLL_SIZE * (u64)Nmod;
834 
835  do_div(Kpart, source);
836 
837  K = Kpart & 0xffffffff;
838  if ((K % 10) >= 5)
839  K += 5;
840  K /= 10;
841  pll_div->k = K;
842  return 0;
843 }
844 
845 static int wm8983_set_pll(struct snd_soc_dai *dai, int pll_id,
846  int source, unsigned int freq_in,
847  unsigned int freq_out)
848 {
849  int ret;
850  struct snd_soc_codec *codec;
851  struct pll_div pll_div;
852 
853  codec = dai->codec;
854  if (freq_in && freq_out) {
855  ret = pll_factors(&pll_div, freq_out * 4 * 2, freq_in);
856  if (ret)
857  return ret;
858  }
859 
860  /* disable the PLL before re-programming it */
861  snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
862  WM8983_PLLEN_MASK, 0);
863 
864  if (!freq_in || !freq_out)
865  return 0;
866 
867  /* set PLLN and PRESCALE */
868  snd_soc_write(codec, WM8983_PLL_N,
869  (pll_div.div2 << WM8983_PLL_PRESCALE_SHIFT)
870  | pll_div.n);
871  /* set PLLK */
872  snd_soc_write(codec, WM8983_PLL_K_3, pll_div.k & 0x1ff);
873  snd_soc_write(codec, WM8983_PLL_K_2, (pll_div.k >> 9) & 0x1ff);
874  snd_soc_write(codec, WM8983_PLL_K_1, (pll_div.k >> 18));
875  /* enable the PLL */
876  snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
877  WM8983_PLLEN_MASK, WM8983_PLLEN);
878  return 0;
879 }
880 
881 static int wm8983_set_sysclk(struct snd_soc_dai *dai,
882  int clk_id, unsigned int freq, int dir)
883 {
884  struct snd_soc_codec *codec = dai->codec;
885  struct wm8983_priv *wm8983 = snd_soc_codec_get_drvdata(codec);
886 
887  switch (clk_id) {
888  case WM8983_CLKSRC_MCLK:
889  snd_soc_update_bits(codec, WM8983_CLOCK_GEN_CONTROL,
890  WM8983_CLKSEL_MASK, 0);
891  break;
892  case WM8983_CLKSRC_PLL:
893  snd_soc_update_bits(codec, WM8983_CLOCK_GEN_CONTROL,
894  WM8983_CLKSEL_MASK, WM8983_CLKSEL);
895  break;
896  default:
897  dev_err(dai->dev, "Unknown clock source: %d\n", clk_id);
898  return -EINVAL;
899  }
900 
901  wm8983->sysclk = freq;
902  return 0;
903 }
904 
905 static int wm8983_set_bias_level(struct snd_soc_codec *codec,
906  enum snd_soc_bias_level level)
907 {
908  struct wm8983_priv *wm8983 = snd_soc_codec_get_drvdata(codec);
909  int ret;
910 
911  switch (level) {
912  case SND_SOC_BIAS_ON:
913  case SND_SOC_BIAS_PREPARE:
914  /* VMID at 100k */
915  snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
916  WM8983_VMIDSEL_MASK,
917  1 << WM8983_VMIDSEL_SHIFT);
918  break;
919  case SND_SOC_BIAS_STANDBY:
920  if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
921  ret = regcache_sync(wm8983->regmap);
922  if (ret < 0) {
923  dev_err(codec->dev, "Failed to sync cache: %d\n", ret);
924  return ret;
925  }
926  /* enable anti-pop features */
927  snd_soc_update_bits(codec, WM8983_OUT4_TO_ADC,
928  WM8983_POBCTRL_MASK | WM8983_DELEN_MASK,
929  WM8983_POBCTRL | WM8983_DELEN);
930  /* enable thermal shutdown */
931  snd_soc_update_bits(codec, WM8983_OUTPUT_CTRL,
932  WM8983_TSDEN_MASK, WM8983_TSDEN);
933  /* enable BIASEN */
934  snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
935  WM8983_BIASEN_MASK, WM8983_BIASEN);
936  /* VMID at 100k */
937  snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
938  WM8983_VMIDSEL_MASK,
939  1 << WM8983_VMIDSEL_SHIFT);
940  msleep(250);
941  /* disable anti-pop features */
942  snd_soc_update_bits(codec, WM8983_OUT4_TO_ADC,
943  WM8983_POBCTRL_MASK |
944  WM8983_DELEN_MASK, 0);
945  }
946 
947  /* VMID at 500k */
948  snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
949  WM8983_VMIDSEL_MASK,
950  2 << WM8983_VMIDSEL_SHIFT);
951  break;
952  case SND_SOC_BIAS_OFF:
953  /* disable thermal shutdown */
954  snd_soc_update_bits(codec, WM8983_OUTPUT_CTRL,
955  WM8983_TSDEN_MASK, 0);
956  /* disable VMIDSEL and BIASEN */
957  snd_soc_update_bits(codec, WM8983_POWER_MANAGEMENT_1,
958  WM8983_VMIDSEL_MASK | WM8983_BIASEN_MASK,
959  0);
960  /* wait for VMID to discharge */
961  msleep(100);
962  snd_soc_write(codec, WM8983_POWER_MANAGEMENT_1, 0);
963  snd_soc_write(codec, WM8983_POWER_MANAGEMENT_2, 0);
964  snd_soc_write(codec, WM8983_POWER_MANAGEMENT_3, 0);
965  break;
966  }
967 
968  codec->dapm.bias_level = level;
969  return 0;
970 }
971 
972 #ifdef CONFIG_PM
973 static int wm8983_suspend(struct snd_soc_codec *codec)
974 {
975  wm8983_set_bias_level(codec, SND_SOC_BIAS_OFF);
976  return 0;
977 }
978 
979 static int wm8983_resume(struct snd_soc_codec *codec)
980 {
981  wm8983_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
982  return 0;
983 }
984 #else
985 #define wm8983_suspend NULL
986 #define wm8983_resume NULL
987 #endif
988 
989 static int wm8983_remove(struct snd_soc_codec *codec)
990 {
991  wm8983_set_bias_level(codec, SND_SOC_BIAS_OFF);
992  return 0;
993 }
994 
995 static int wm8983_probe(struct snd_soc_codec *codec)
996 {
997  int ret;
998  int i;
999 
1000  ret = snd_soc_codec_set_cache_io(codec, 7, 9, SND_SOC_REGMAP);
1001  if (ret < 0) {
1002  dev_err(codec->dev, "Failed to set cache i/o: %d\n", ret);
1003  return ret;
1004  }
1005 
1006  ret = snd_soc_write(codec, WM8983_SOFTWARE_RESET, 0);
1007  if (ret < 0) {
1008  dev_err(codec->dev, "Failed to issue reset: %d\n", ret);
1009  return ret;
1010  }
1011 
1012  /* set the vol/gain update bits */
1013  for (i = 0; i < ARRAY_SIZE(vol_update_regs); ++i)
1014  snd_soc_update_bits(codec, vol_update_regs[i],
1015  0x100, 0x100);
1016 
1017  /* mute all outputs and set PGAs to minimum gain */
1018  for (i = WM8983_LOUT1_HP_VOLUME_CTRL;
1019  i <= WM8983_OUT4_MONO_MIX_CTRL; ++i)
1020  snd_soc_update_bits(codec, i, 0x40, 0x40);
1021 
1022  /* enable soft mute */
1023  snd_soc_update_bits(codec, WM8983_DAC_CONTROL,
1024  WM8983_SOFTMUTE_MASK,
1025  WM8983_SOFTMUTE);
1026 
1027  /* enable BIASCUT */
1028  snd_soc_update_bits(codec, WM8983_BIAS_CTRL,
1029  WM8983_BIASCUT, WM8983_BIASCUT);
1030  return 0;
1031 }
1032 
1033 static const struct snd_soc_dai_ops wm8983_dai_ops = {
1034  .digital_mute = wm8983_dac_mute,
1035  .hw_params = wm8983_hw_params,
1036  .set_fmt = wm8983_set_fmt,
1037  .set_sysclk = wm8983_set_sysclk,
1038  .set_pll = wm8983_set_pll
1039 };
1040 
1041 #define WM8983_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1042  SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1043 
1044 static struct snd_soc_dai_driver wm8983_dai = {
1045  .name = "wm8983-hifi",
1046  .playback = {
1047  .stream_name = "Playback",
1048  .channels_min = 2,
1049  .channels_max = 2,
1050  .rates = SNDRV_PCM_RATE_8000_48000,
1051  .formats = WM8983_FORMATS,
1052  },
1053  .capture = {
1054  .stream_name = "Capture",
1055  .channels_min = 2,
1056  .channels_max = 2,
1057  .rates = SNDRV_PCM_RATE_8000_48000,
1058  .formats = WM8983_FORMATS,
1059  },
1060  .ops = &wm8983_dai_ops,
1061  .symmetric_rates = 1
1062 };
1063 
1064 static struct snd_soc_codec_driver soc_codec_dev_wm8983 = {
1065  .probe = wm8983_probe,
1066  .remove = wm8983_remove,
1067  .suspend = wm8983_suspend,
1068  .resume = wm8983_resume,
1069  .set_bias_level = wm8983_set_bias_level,
1070  .controls = wm8983_snd_controls,
1071  .num_controls = ARRAY_SIZE(wm8983_snd_controls),
1072  .dapm_widgets = wm8983_dapm_widgets,
1073  .num_dapm_widgets = ARRAY_SIZE(wm8983_dapm_widgets),
1074  .dapm_routes = wm8983_audio_map,
1075  .num_dapm_routes = ARRAY_SIZE(wm8983_audio_map),
1076 };
1077 
1078 static const struct regmap_config wm8983_regmap = {
1079  .reg_bits = 7,
1080  .val_bits = 9,
1081 
1082  .reg_defaults = wm8983_defaults,
1083  .num_reg_defaults = ARRAY_SIZE(wm8983_defaults),
1084  .cache_type = REGCACHE_RBTREE,
1085 
1086  .readable_reg = wm8983_readable,
1087 };
1088 
1089 #if defined(CONFIG_SPI_MASTER)
1090 static int __devinit wm8983_spi_probe(struct spi_device *spi)
1091 {
1092  struct wm8983_priv *wm8983;
1093  int ret;
1094 
1095  wm8983 = devm_kzalloc(&spi->dev, sizeof *wm8983, GFP_KERNEL);
1096  if (!wm8983)
1097  return -ENOMEM;
1098 
1099  wm8983->regmap = devm_regmap_init_spi(spi, &wm8983_regmap);
1100  if (IS_ERR(wm8983->regmap)) {
1101  ret = PTR_ERR(wm8983->regmap);
1102  dev_err(&spi->dev, "Failed to init regmap: %d\n", ret);
1103  return ret;
1104  }
1105 
1106  spi_set_drvdata(spi, wm8983);
1107 
1108  ret = snd_soc_register_codec(&spi->dev,
1109  &soc_codec_dev_wm8983, &wm8983_dai, 1);
1110  return ret;
1111 }
1112 
1113 static int __devexit wm8983_spi_remove(struct spi_device *spi)
1114 {
1115  snd_soc_unregister_codec(&spi->dev);
1116  return 0;
1117 }
1118 
1119 static struct spi_driver wm8983_spi_driver = {
1120  .driver = {
1121  .name = "wm8983",
1122  .owner = THIS_MODULE,
1123  },
1124  .probe = wm8983_spi_probe,
1125  .remove = __devexit_p(wm8983_spi_remove)
1126 };
1127 #endif
1128 
1129 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1130 static __devinit int wm8983_i2c_probe(struct i2c_client *i2c,
1131  const struct i2c_device_id *id)
1132 {
1133  struct wm8983_priv *wm8983;
1134  int ret;
1135 
1136  wm8983 = devm_kzalloc(&i2c->dev, sizeof *wm8983, GFP_KERNEL);
1137  if (!wm8983)
1138  return -ENOMEM;
1139 
1140  wm8983->regmap = devm_regmap_init_i2c(i2c, &wm8983_regmap);
1141  if (IS_ERR(wm8983->regmap)) {
1142  ret = PTR_ERR(wm8983->regmap);
1143  dev_err(&i2c->dev, "Failed to init regmap: %d\n", ret);
1144  return ret;
1145  }
1146 
1147  i2c_set_clientdata(i2c, wm8983);
1148 
1149  ret = snd_soc_register_codec(&i2c->dev,
1150  &soc_codec_dev_wm8983, &wm8983_dai, 1);
1151 
1152  return ret;
1153 }
1154 
1155 static __devexit int wm8983_i2c_remove(struct i2c_client *client)
1156 {
1157  snd_soc_unregister_codec(&client->dev);
1158  return 0;
1159 }
1160 
1161 static const struct i2c_device_id wm8983_i2c_id[] = {
1162  { "wm8983", 0 },
1163  { }
1164 };
1165 MODULE_DEVICE_TABLE(i2c, wm8983_i2c_id);
1166 
1167 static struct i2c_driver wm8983_i2c_driver = {
1168  .driver = {
1169  .name = "wm8983",
1170  .owner = THIS_MODULE,
1171  },
1172  .probe = wm8983_i2c_probe,
1173  .remove = __devexit_p(wm8983_i2c_remove),
1174  .id_table = wm8983_i2c_id
1175 };
1176 #endif
1177 
1178 static int __init wm8983_modinit(void)
1179 {
1180  int ret = 0;
1181 
1182 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1183  ret = i2c_add_driver(&wm8983_i2c_driver);
1184  if (ret) {
1185  printk(KERN_ERR "Failed to register wm8983 I2C driver: %d\n",
1186  ret);
1187  }
1188 #endif
1189 #if defined(CONFIG_SPI_MASTER)
1190  ret = spi_register_driver(&wm8983_spi_driver);
1191  if (ret != 0) {
1192  printk(KERN_ERR "Failed to register wm8983 SPI driver: %d\n",
1193  ret);
1194  }
1195 #endif
1196  return ret;
1197 }
1198 module_init(wm8983_modinit);
1199 
1200 static void __exit wm8983_exit(void)
1201 {
1202 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1203  i2c_del_driver(&wm8983_i2c_driver);
1204 #endif
1205 #if defined(CONFIG_SPI_MASTER)
1206  spi_unregister_driver(&wm8983_spi_driver);
1207 #endif
1208 }
1209 module_exit(wm8983_exit);
1210 
1211 MODULE_DESCRIPTION("ASoC WM8983 driver");
1212 MODULE_AUTHOR("Dimitris Papastamos <[email protected]>");
1213 MODULE_LICENSE("GPL");
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