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wm9081.c
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1 /*
2  * wm9081.c -- WM9081 ALSA SoC Audio driver
3  *
4  * Author: Mark Brown
5  *
6  * Copyright 2009-12 Wolfson Microelectronics plc
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12  */
13 
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/pm.h>
20 #include <linux/i2c.h>
21 #include <linux/regmap.h>
22 #include <linux/slab.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
29 
30 #include <sound/wm9081.h>
31 #include "wm9081.h"
32 
33 static struct reg_default wm9081_reg[] = {
34  { 2, 0x00B9 }, /* R2 - Analogue Lineout */
35  { 3, 0x00B9 }, /* R3 - Analogue Speaker PGA */
36  { 4, 0x0001 }, /* R4 - VMID Control */
37  { 5, 0x0068 }, /* R5 - Bias Control 1 */
38  { 7, 0x0000 }, /* R7 - Analogue Mixer */
39  { 8, 0x0000 }, /* R8 - Anti Pop Control */
40  { 9, 0x01DB }, /* R9 - Analogue Speaker 1 */
41  { 10, 0x0018 }, /* R10 - Analogue Speaker 2 */
42  { 11, 0x0180 }, /* R11 - Power Management */
43  { 12, 0x0000 }, /* R12 - Clock Control 1 */
44  { 13, 0x0038 }, /* R13 - Clock Control 2 */
45  { 14, 0x4000 }, /* R14 - Clock Control 3 */
46  { 16, 0x0000 }, /* R16 - FLL Control 1 */
47  { 17, 0x0200 }, /* R17 - FLL Control 2 */
48  { 18, 0x0000 }, /* R18 - FLL Control 3 */
49  { 19, 0x0204 }, /* R19 - FLL Control 4 */
50  { 20, 0x0000 }, /* R20 - FLL Control 5 */
51  { 22, 0x0000 }, /* R22 - Audio Interface 1 */
52  { 23, 0x0002 }, /* R23 - Audio Interface 2 */
53  { 24, 0x0008 }, /* R24 - Audio Interface 3 */
54  { 25, 0x0022 }, /* R25 - Audio Interface 4 */
55  { 27, 0x0006 }, /* R27 - Interrupt Status Mask */
56  { 28, 0x0000 }, /* R28 - Interrupt Polarity */
57  { 29, 0x0000 }, /* R29 - Interrupt Control */
58  { 30, 0x00C0 }, /* R30 - DAC Digital 1 */
59  { 31, 0x0008 }, /* R31 - DAC Digital 2 */
60  { 32, 0x09AF }, /* R32 - DRC 1 */
61  { 33, 0x4201 }, /* R33 - DRC 2 */
62  { 34, 0x0000 }, /* R34 - DRC 3 */
63  { 35, 0x0000 }, /* R35 - DRC 4 */
64  { 38, 0x0000 }, /* R38 - Write Sequencer 1 */
65  { 39, 0x0000 }, /* R39 - Write Sequencer 2 */
66  { 40, 0x0002 }, /* R40 - MW Slave 1 */
67  { 42, 0x0000 }, /* R42 - EQ 1 */
68  { 43, 0x0000 }, /* R43 - EQ 2 */
69  { 44, 0x0FCA }, /* R44 - EQ 3 */
70  { 45, 0x0400 }, /* R45 - EQ 4 */
71  { 46, 0x00B8 }, /* R46 - EQ 5 */
72  { 47, 0x1EB5 }, /* R47 - EQ 6 */
73  { 48, 0xF145 }, /* R48 - EQ 7 */
74  { 49, 0x0B75 }, /* R49 - EQ 8 */
75  { 50, 0x01C5 }, /* R50 - EQ 9 */
76  { 51, 0x169E }, /* R51 - EQ 10 */
77  { 52, 0xF829 }, /* R52 - EQ 11 */
78  { 53, 0x07AD }, /* R53 - EQ 12 */
79  { 54, 0x1103 }, /* R54 - EQ 13 */
80  { 55, 0x1C58 }, /* R55 - EQ 14 */
81  { 56, 0xF373 }, /* R56 - EQ 15 */
82  { 57, 0x0A54 }, /* R57 - EQ 16 */
83  { 58, 0x0558 }, /* R58 - EQ 17 */
84  { 59, 0x0564 }, /* R59 - EQ 18 */
85  { 60, 0x0559 }, /* R60 - EQ 19 */
86  { 61, 0x4000 }, /* R61 - EQ 20 */
87 };
88 
89 static struct {
90  int ratio;
91  int clk_sys_rate;
92 } clk_sys_rates[] = {
93  { 64, 0 },
94  { 128, 1 },
95  { 192, 2 },
96  { 256, 3 },
97  { 384, 4 },
98  { 512, 5 },
99  { 768, 6 },
100  { 1024, 7 },
101  { 1408, 8 },
102  { 1536, 9 },
103 };
104 
105 static struct {
106  int rate;
107  int sample_rate;
108 } sample_rates[] = {
109  { 8000, 0 },
110  { 11025, 1 },
111  { 12000, 2 },
112  { 16000, 3 },
113  { 22050, 4 },
114  { 24000, 5 },
115  { 32000, 6 },
116  { 44100, 7 },
117  { 48000, 8 },
118  { 88200, 9 },
119  { 96000, 10 },
120 };
121 
122 static struct {
123  int div; /* *10 due to .5s */
124  int bclk_div;
125 } bclk_divs[] = {
126  { 10, 0 },
127  { 15, 1 },
128  { 20, 2 },
129  { 30, 3 },
130  { 40, 4 },
131  { 50, 5 },
132  { 55, 6 },
133  { 60, 7 },
134  { 80, 8 },
135  { 100, 9 },
136  { 110, 10 },
137  { 120, 11 },
138  { 160, 12 },
139  { 200, 13 },
140  { 220, 14 },
141  { 240, 15 },
142  { 250, 16 },
143  { 300, 17 },
144  { 320, 18 },
145  { 440, 19 },
146  { 480, 20 },
147 };
148 
149 struct wm9081_priv {
150  struct regmap *regmap;
151  int sysclk_source;
152  int mclk_rate;
153  int sysclk_rate;
154  int fs;
155  int bclk;
156  int master;
157  int fll_fref;
158  int fll_fout;
159  int tdm_width;
160  struct wm9081_pdata pdata;
161 };
162 
163 static bool wm9081_volatile_register(struct device *dev, unsigned int reg)
164 {
165  switch (reg) {
166  case WM9081_SOFTWARE_RESET:
167  case WM9081_INTERRUPT_STATUS:
168  return true;
169  default:
170  return false;
171  }
172 }
173 
174 static bool wm9081_readable_register(struct device *dev, unsigned int reg)
175 {
176  switch (reg) {
177  case WM9081_SOFTWARE_RESET:
178  case WM9081_ANALOGUE_LINEOUT:
179  case WM9081_ANALOGUE_SPEAKER_PGA:
180  case WM9081_VMID_CONTROL:
181  case WM9081_BIAS_CONTROL_1:
182  case WM9081_ANALOGUE_MIXER:
183  case WM9081_ANTI_POP_CONTROL:
184  case WM9081_ANALOGUE_SPEAKER_1:
185  case WM9081_ANALOGUE_SPEAKER_2:
186  case WM9081_POWER_MANAGEMENT:
187  case WM9081_CLOCK_CONTROL_1:
188  case WM9081_CLOCK_CONTROL_2:
189  case WM9081_CLOCK_CONTROL_3:
190  case WM9081_FLL_CONTROL_1:
191  case WM9081_FLL_CONTROL_2:
192  case WM9081_FLL_CONTROL_3:
193  case WM9081_FLL_CONTROL_4:
194  case WM9081_FLL_CONTROL_5:
195  case WM9081_AUDIO_INTERFACE_1:
196  case WM9081_AUDIO_INTERFACE_2:
197  case WM9081_AUDIO_INTERFACE_3:
198  case WM9081_AUDIO_INTERFACE_4:
199  case WM9081_INTERRUPT_STATUS:
200  case WM9081_INTERRUPT_STATUS_MASK:
201  case WM9081_INTERRUPT_POLARITY:
202  case WM9081_INTERRUPT_CONTROL:
203  case WM9081_DAC_DIGITAL_1:
204  case WM9081_DAC_DIGITAL_2:
205  case WM9081_DRC_1:
206  case WM9081_DRC_2:
207  case WM9081_DRC_3:
208  case WM9081_DRC_4:
209  case WM9081_WRITE_SEQUENCER_1:
210  case WM9081_WRITE_SEQUENCER_2:
211  case WM9081_MW_SLAVE_1:
212  case WM9081_EQ_1:
213  case WM9081_EQ_2:
214  case WM9081_EQ_3:
215  case WM9081_EQ_4:
216  case WM9081_EQ_5:
217  case WM9081_EQ_6:
218  case WM9081_EQ_7:
219  case WM9081_EQ_8:
220  case WM9081_EQ_9:
221  case WM9081_EQ_10:
222  case WM9081_EQ_11:
223  case WM9081_EQ_12:
224  case WM9081_EQ_13:
225  case WM9081_EQ_14:
226  case WM9081_EQ_15:
227  case WM9081_EQ_16:
228  case WM9081_EQ_17:
229  case WM9081_EQ_18:
230  case WM9081_EQ_19:
231  case WM9081_EQ_20:
232  return true;
233  default:
234  return false;
235  }
236 }
237 
238 static int wm9081_reset(struct regmap *map)
239 {
240  return regmap_write(map, WM9081_SOFTWARE_RESET, 0x9081);
241 }
242 
243 static const DECLARE_TLV_DB_SCALE(drc_in_tlv, -4500, 75, 0);
244 static const DECLARE_TLV_DB_SCALE(drc_out_tlv, -2250, 75, 0);
245 static const DECLARE_TLV_DB_SCALE(drc_min_tlv, -1800, 600, 0);
246 static unsigned int drc_max_tlv[] = {
247  TLV_DB_RANGE_HEAD(4),
248  0, 0, TLV_DB_SCALE_ITEM(1200, 0, 0),
249  1, 1, TLV_DB_SCALE_ITEM(1800, 0, 0),
250  2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
251  3, 3, TLV_DB_SCALE_ITEM(3600, 0, 0),
252 };
253 static const DECLARE_TLV_DB_SCALE(drc_qr_tlv, 1200, 600, 0);
254 static const DECLARE_TLV_DB_SCALE(drc_startup_tlv, -300, 50, 0);
255 
256 static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
257 
258 static const DECLARE_TLV_DB_SCALE(in_tlv, -600, 600, 0);
259 static const DECLARE_TLV_DB_SCALE(dac_tlv, -7200, 75, 1);
260 static const DECLARE_TLV_DB_SCALE(out_tlv, -5700, 100, 0);
261 
262 static const char *drc_high_text[] = {
263  "1",
264  "1/2",
265  "1/4",
266  "1/8",
267  "1/16",
268  "0",
269 };
270 
271 static const struct soc_enum drc_high =
272  SOC_ENUM_SINGLE(WM9081_DRC_3, 3, 6, drc_high_text);
273 
274 static const char *drc_low_text[] = {
275  "1",
276  "1/2",
277  "1/4",
278  "1/8",
279  "0",
280 };
281 
282 static const struct soc_enum drc_low =
283  SOC_ENUM_SINGLE(WM9081_DRC_3, 0, 5, drc_low_text);
284 
285 static const char *drc_atk_text[] = {
286  "181us",
287  "181us",
288  "363us",
289  "726us",
290  "1.45ms",
291  "2.9ms",
292  "5.8ms",
293  "11.6ms",
294  "23.2ms",
295  "46.4ms",
296  "92.8ms",
297  "185.6ms",
298 };
299 
300 static const struct soc_enum drc_atk =
301  SOC_ENUM_SINGLE(WM9081_DRC_2, 12, 12, drc_atk_text);
302 
303 static const char *drc_dcy_text[] = {
304  "186ms",
305  "372ms",
306  "743ms",
307  "1.49s",
308  "2.97s",
309  "5.94s",
310  "11.89s",
311  "23.78s",
312  "47.56s",
313 };
314 
315 static const struct soc_enum drc_dcy =
316  SOC_ENUM_SINGLE(WM9081_DRC_2, 8, 9, drc_dcy_text);
317 
318 static const char *drc_qr_dcy_text[] = {
319  "0.725ms",
320  "1.45ms",
321  "5.8ms",
322 };
323 
324 static const struct soc_enum drc_qr_dcy =
325  SOC_ENUM_SINGLE(WM9081_DRC_2, 4, 3, drc_qr_dcy_text);
326 
327 static const char *dac_deemph_text[] = {
328  "None",
329  "32kHz",
330  "44.1kHz",
331  "48kHz",
332 };
333 
334 static const struct soc_enum dac_deemph =
335  SOC_ENUM_SINGLE(WM9081_DAC_DIGITAL_2, 1, 4, dac_deemph_text);
336 
337 static const char *speaker_mode_text[] = {
338  "Class D",
339  "Class AB",
340 };
341 
342 static const struct soc_enum speaker_mode =
343  SOC_ENUM_SINGLE(WM9081_ANALOGUE_SPEAKER_2, 6, 2, speaker_mode_text);
344 
345 static int speaker_mode_get(struct snd_kcontrol *kcontrol,
346  struct snd_ctl_elem_value *ucontrol)
347 {
348  struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
349  unsigned int reg;
350 
351  reg = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
352  if (reg & WM9081_SPK_MODE)
353  ucontrol->value.integer.value[0] = 1;
354  else
355  ucontrol->value.integer.value[0] = 0;
356 
357  return 0;
358 }
359 
360 /*
361  * Stop any attempts to change speaker mode while the speaker is enabled.
362  *
363  * We also have some special anti-pop controls dependent on speaker
364  * mode which must be changed along with the mode.
365  */
366 static int speaker_mode_put(struct snd_kcontrol *kcontrol,
367  struct snd_ctl_elem_value *ucontrol)
368 {
369  struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
370  unsigned int reg_pwr = snd_soc_read(codec, WM9081_POWER_MANAGEMENT);
371  unsigned int reg2 = snd_soc_read(codec, WM9081_ANALOGUE_SPEAKER_2);
372 
373  /* Are we changing anything? */
374  if (ucontrol->value.integer.value[0] ==
375  ((reg2 & WM9081_SPK_MODE) != 0))
376  return 0;
377 
378  /* Don't try to change modes while enabled */
379  if (reg_pwr & WM9081_SPK_ENA)
380  return -EINVAL;
381 
382  if (ucontrol->value.integer.value[0]) {
383  /* Class AB */
384  reg2 &= ~(WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL);
385  reg2 |= WM9081_SPK_MODE;
386  } else {
387  /* Class D */
388  reg2 |= WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL;
389  reg2 &= ~WM9081_SPK_MODE;
390  }
391 
392  snd_soc_write(codec, WM9081_ANALOGUE_SPEAKER_2, reg2);
393 
394  return 0;
395 }
396 
397 static const struct snd_kcontrol_new wm9081_snd_controls[] = {
398 SOC_SINGLE_TLV("IN1 Volume", WM9081_ANALOGUE_MIXER, 1, 1, 1, in_tlv),
399 SOC_SINGLE_TLV("IN2 Volume", WM9081_ANALOGUE_MIXER, 3, 1, 1, in_tlv),
400 
401 SOC_SINGLE_TLV("Playback Volume", WM9081_DAC_DIGITAL_1, 1, 96, 0, dac_tlv),
402 
403 SOC_SINGLE("LINEOUT Switch", WM9081_ANALOGUE_LINEOUT, 7, 1, 1),
404 SOC_SINGLE("LINEOUT ZC Switch", WM9081_ANALOGUE_LINEOUT, 6, 1, 0),
405 SOC_SINGLE_TLV("LINEOUT Volume", WM9081_ANALOGUE_LINEOUT, 0, 63, 0, out_tlv),
406 
407 SOC_SINGLE("DRC Switch", WM9081_DRC_1, 15, 1, 0),
408 SOC_ENUM("DRC High Slope", drc_high),
409 SOC_ENUM("DRC Low Slope", drc_low),
410 SOC_SINGLE_TLV("DRC Input Volume", WM9081_DRC_4, 5, 60, 1, drc_in_tlv),
411 SOC_SINGLE_TLV("DRC Output Volume", WM9081_DRC_4, 0, 30, 1, drc_out_tlv),
412 SOC_SINGLE_TLV("DRC Minimum Volume", WM9081_DRC_2, 2, 3, 1, drc_min_tlv),
413 SOC_SINGLE_TLV("DRC Maximum Volume", WM9081_DRC_2, 0, 3, 0, drc_max_tlv),
414 SOC_ENUM("DRC Attack", drc_atk),
415 SOC_ENUM("DRC Decay", drc_dcy),
416 SOC_SINGLE("DRC Quick Release Switch", WM9081_DRC_1, 2, 1, 0),
417 SOC_SINGLE_TLV("DRC Quick Release Volume", WM9081_DRC_2, 6, 3, 0, drc_qr_tlv),
418 SOC_ENUM("DRC Quick Release Decay", drc_qr_dcy),
419 SOC_SINGLE_TLV("DRC Startup Volume", WM9081_DRC_1, 6, 18, 0, drc_startup_tlv),
420 
421 SOC_SINGLE("EQ Switch", WM9081_EQ_1, 0, 1, 0),
422 
423 SOC_SINGLE("Speaker DC Volume", WM9081_ANALOGUE_SPEAKER_1, 3, 5, 0),
424 SOC_SINGLE("Speaker AC Volume", WM9081_ANALOGUE_SPEAKER_1, 0, 5, 0),
425 SOC_SINGLE("Speaker Switch", WM9081_ANALOGUE_SPEAKER_PGA, 7, 1, 1),
426 SOC_SINGLE("Speaker ZC Switch", WM9081_ANALOGUE_SPEAKER_PGA, 6, 1, 0),
427 SOC_SINGLE_TLV("Speaker Volume", WM9081_ANALOGUE_SPEAKER_PGA, 0, 63, 0,
428  out_tlv),
429 SOC_ENUM("DAC Deemphasis", dac_deemph),
430 SOC_ENUM_EXT("Speaker Mode", speaker_mode, speaker_mode_get, speaker_mode_put),
431 };
432 
433 static const struct snd_kcontrol_new wm9081_eq_controls[] = {
434 SOC_SINGLE_TLV("EQ1 Volume", WM9081_EQ_1, 11, 24, 0, eq_tlv),
435 SOC_SINGLE_TLV("EQ2 Volume", WM9081_EQ_1, 6, 24, 0, eq_tlv),
436 SOC_SINGLE_TLV("EQ3 Volume", WM9081_EQ_1, 1, 24, 0, eq_tlv),
437 SOC_SINGLE_TLV("EQ4 Volume", WM9081_EQ_2, 11, 24, 0, eq_tlv),
438 SOC_SINGLE_TLV("EQ5 Volume", WM9081_EQ_2, 6, 24, 0, eq_tlv),
439 };
440 
441 static const struct snd_kcontrol_new mixer[] = {
442 SOC_DAPM_SINGLE("IN1 Switch", WM9081_ANALOGUE_MIXER, 0, 1, 0),
443 SOC_DAPM_SINGLE("IN2 Switch", WM9081_ANALOGUE_MIXER, 2, 1, 0),
444 SOC_DAPM_SINGLE("Playback Switch", WM9081_ANALOGUE_MIXER, 4, 1, 0),
445 };
446 
447 struct _fll_div {
448  u16 fll_fratio;
449  u16 fll_outdiv;
450  u16 fll_clk_ref_div;
451  u16 n;
452  u16 k;
453 };
454 
455 /* The size in bits of the FLL divide multiplied by 10
456  * to allow rounding later */
457 #define FIXED_FLL_SIZE ((1 << 16) * 10)
458 
459 static struct {
460  unsigned int min;
461  unsigned int max;
462  u16 fll_fratio;
463  int ratio;
464 } fll_fratios[] = {
465  { 0, 64000, 4, 16 },
466  { 64000, 128000, 3, 8 },
467  { 128000, 256000, 2, 4 },
468  { 256000, 1000000, 1, 2 },
469  { 1000000, 13500000, 0, 1 },
470 };
471 
472 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
473  unsigned int Fout)
474 {
475  u64 Kpart;
476  unsigned int K, Ndiv, Nmod, target;
477  unsigned int div;
478  int i;
479 
480  /* Fref must be <=13.5MHz */
481  div = 1;
482  while ((Fref / div) > 13500000) {
483  div *= 2;
484 
485  if (div > 8) {
486  pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
487  Fref);
488  return -EINVAL;
489  }
490  }
491  fll_div->fll_clk_ref_div = div / 2;
492 
493  pr_debug("Fref=%u Fout=%u\n", Fref, Fout);
494 
495  /* Apply the division for our remaining calculations */
496  Fref /= div;
497 
498  /* Fvco should be 90-100MHz; don't check the upper bound */
499  div = 0;
500  target = Fout * 2;
501  while (target < 90000000) {
502  div++;
503  target *= 2;
504  if (div > 7) {
505  pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
506  Fout);
507  return -EINVAL;
508  }
509  }
510  fll_div->fll_outdiv = div;
511 
512  pr_debug("Fvco=%dHz\n", target);
513 
514  /* Find an appropriate FLL_FRATIO and factor it out of the target */
515  for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
516  if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
517  fll_div->fll_fratio = fll_fratios[i].fll_fratio;
518  target /= fll_fratios[i].ratio;
519  break;
520  }
521  }
522  if (i == ARRAY_SIZE(fll_fratios)) {
523  pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
524  return -EINVAL;
525  }
526 
527  /* Now, calculate N.K */
528  Ndiv = target / Fref;
529 
530  fll_div->n = Ndiv;
531  Nmod = target % Fref;
532  pr_debug("Nmod=%d\n", Nmod);
533 
534  /* Calculate fractional part - scale up so we can round. */
535  Kpart = FIXED_FLL_SIZE * (long long)Nmod;
536 
537  do_div(Kpart, Fref);
538 
539  K = Kpart & 0xFFFFFFFF;
540 
541  if ((K % 10) >= 5)
542  K += 5;
543 
544  /* Move down to proper range now rounding is done */
545  fll_div->k = K / 10;
546 
547  pr_debug("N=%x K=%x FLL_FRATIO=%x FLL_OUTDIV=%x FLL_CLK_REF_DIV=%x\n",
548  fll_div->n, fll_div->k,
549  fll_div->fll_fratio, fll_div->fll_outdiv,
550  fll_div->fll_clk_ref_div);
551 
552  return 0;
553 }
554 
555 static int wm9081_set_fll(struct snd_soc_codec *codec, int fll_id,
556  unsigned int Fref, unsigned int Fout)
557 {
558  struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
559  u16 reg1, reg4, reg5;
560  struct _fll_div fll_div;
561  int ret;
562  int clk_sys_reg;
563 
564  /* Any change? */
565  if (Fref == wm9081->fll_fref && Fout == wm9081->fll_fout)
566  return 0;
567 
568  /* Disable the FLL */
569  if (Fout == 0) {
570  dev_dbg(codec->dev, "FLL disabled\n");
571  wm9081->fll_fref = 0;
572  wm9081->fll_fout = 0;
573 
574  return 0;
575  }
576 
577  ret = fll_factors(&fll_div, Fref, Fout);
578  if (ret != 0)
579  return ret;
580 
581  reg5 = snd_soc_read(codec, WM9081_FLL_CONTROL_5);
582  reg5 &= ~WM9081_FLL_CLK_SRC_MASK;
583 
584  switch (fll_id) {
585  case WM9081_SYSCLK_FLL_MCLK:
586  reg5 |= 0x1;
587  break;
588 
589  default:
590  dev_err(codec->dev, "Unknown FLL ID %d\n", fll_id);
591  return -EINVAL;
592  }
593 
594  /* Disable CLK_SYS while we reconfigure */
595  clk_sys_reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
596  if (clk_sys_reg & WM9081_CLK_SYS_ENA)
597  snd_soc_write(codec, WM9081_CLOCK_CONTROL_3,
598  clk_sys_reg & ~WM9081_CLK_SYS_ENA);
599 
600  /* Any FLL configuration change requires that the FLL be
601  * disabled first. */
602  reg1 = snd_soc_read(codec, WM9081_FLL_CONTROL_1);
603  reg1 &= ~WM9081_FLL_ENA;
604  snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
605 
606  /* Apply the configuration */
607  if (fll_div.k)
608  reg1 |= WM9081_FLL_FRAC_MASK;
609  else
610  reg1 &= ~WM9081_FLL_FRAC_MASK;
611  snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1);
612 
613  snd_soc_write(codec, WM9081_FLL_CONTROL_2,
614  (fll_div.fll_outdiv << WM9081_FLL_OUTDIV_SHIFT) |
615  (fll_div.fll_fratio << WM9081_FLL_FRATIO_SHIFT));
616  snd_soc_write(codec, WM9081_FLL_CONTROL_3, fll_div.k);
617 
618  reg4 = snd_soc_read(codec, WM9081_FLL_CONTROL_4);
619  reg4 &= ~WM9081_FLL_N_MASK;
620  reg4 |= fll_div.n << WM9081_FLL_N_SHIFT;
621  snd_soc_write(codec, WM9081_FLL_CONTROL_4, reg4);
622 
623  reg5 &= ~WM9081_FLL_CLK_REF_DIV_MASK;
624  reg5 |= fll_div.fll_clk_ref_div << WM9081_FLL_CLK_REF_DIV_SHIFT;
625  snd_soc_write(codec, WM9081_FLL_CONTROL_5, reg5);
626 
627  /* Set gain to the recommended value */
628  snd_soc_update_bits(codec, WM9081_FLL_CONTROL_4,
629  WM9081_FLL_GAIN_MASK, 0);
630 
631  /* Enable the FLL */
632  snd_soc_write(codec, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA);
633 
634  /* Then bring CLK_SYS up again if it was disabled */
635  if (clk_sys_reg & WM9081_CLK_SYS_ENA)
636  snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, clk_sys_reg);
637 
638  dev_dbg(codec->dev, "FLL enabled at %dHz->%dHz\n", Fref, Fout);
639 
640  wm9081->fll_fref = Fref;
641  wm9081->fll_fout = Fout;
642 
643  return 0;
644 }
645 
646 static int configure_clock(struct snd_soc_codec *codec)
647 {
648  struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
649  int new_sysclk, i, target;
650  unsigned int reg;
651  int ret = 0;
652  int mclkdiv = 0;
653  int fll = 0;
654 
655  switch (wm9081->sysclk_source) {
656  case WM9081_SYSCLK_MCLK:
657  if (wm9081->mclk_rate > 12225000) {
658  mclkdiv = 1;
659  wm9081->sysclk_rate = wm9081->mclk_rate / 2;
660  } else {
661  wm9081->sysclk_rate = wm9081->mclk_rate;
662  }
663  wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK, 0, 0);
664  break;
665 
666  case WM9081_SYSCLK_FLL_MCLK:
667  /* If we have a sample rate calculate a CLK_SYS that
668  * gives us a suitable DAC configuration, plus BCLK.
669  * Ideally we would check to see if we can clock
670  * directly from MCLK and only use the FLL if this is
671  * not the case, though care must be taken with free
672  * running mode.
673  */
674  if (wm9081->master && wm9081->bclk) {
675  /* Make sure we can generate CLK_SYS and BCLK
676  * and that we've got 3MHz for optimal
677  * performance. */
678  for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
679  target = wm9081->fs * clk_sys_rates[i].ratio;
680  new_sysclk = target;
681  if (target >= wm9081->bclk &&
682  target > 3000000)
683  break;
684  }
685 
686  if (i == ARRAY_SIZE(clk_sys_rates))
687  return -EINVAL;
688 
689  } else if (wm9081->fs) {
690  for (i = 0; i < ARRAY_SIZE(clk_sys_rates); i++) {
691  new_sysclk = clk_sys_rates[i].ratio
692  * wm9081->fs;
693  if (new_sysclk > 3000000)
694  break;
695  }
696 
697  if (i == ARRAY_SIZE(clk_sys_rates))
698  return -EINVAL;
699 
700  } else {
701  new_sysclk = 12288000;
702  }
703 
704  ret = wm9081_set_fll(codec, WM9081_SYSCLK_FLL_MCLK,
705  wm9081->mclk_rate, new_sysclk);
706  if (ret == 0) {
707  wm9081->sysclk_rate = new_sysclk;
708 
709  /* Switch SYSCLK over to FLL */
710  fll = 1;
711  } else {
712  wm9081->sysclk_rate = wm9081->mclk_rate;
713  }
714  break;
715 
716  default:
717  return -EINVAL;
718  }
719 
720  reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_1);
721  if (mclkdiv)
722  reg |= WM9081_MCLKDIV2;
723  else
724  reg &= ~WM9081_MCLKDIV2;
725  snd_soc_write(codec, WM9081_CLOCK_CONTROL_1, reg);
726 
727  reg = snd_soc_read(codec, WM9081_CLOCK_CONTROL_3);
728  if (fll)
729  reg |= WM9081_CLK_SRC_SEL;
730  else
731  reg &= ~WM9081_CLK_SRC_SEL;
732  snd_soc_write(codec, WM9081_CLOCK_CONTROL_3, reg);
733 
734  dev_dbg(codec->dev, "CLK_SYS is %dHz\n", wm9081->sysclk_rate);
735 
736  return ret;
737 }
738 
739 static int clk_sys_event(struct snd_soc_dapm_widget *w,
740  struct snd_kcontrol *kcontrol, int event)
741 {
742  struct snd_soc_codec *codec = w->codec;
743  struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
744 
745  /* This should be done on init() for bypass paths */
746  switch (wm9081->sysclk_source) {
747  case WM9081_SYSCLK_MCLK:
748  dev_dbg(codec->dev, "Using %dHz MCLK\n", wm9081->mclk_rate);
749  break;
750  case WM9081_SYSCLK_FLL_MCLK:
751  dev_dbg(codec->dev, "Using %dHz MCLK with FLL\n",
752  wm9081->mclk_rate);
753  break;
754  default:
755  dev_err(codec->dev, "System clock not configured\n");
756  return -EINVAL;
757  }
758 
759  switch (event) {
760  case SND_SOC_DAPM_PRE_PMU:
761  configure_clock(codec);
762  break;
763 
764  case SND_SOC_DAPM_POST_PMD:
765  /* Disable the FLL if it's running */
766  wm9081_set_fll(codec, 0, 0, 0);
767  break;
768  }
769 
770  return 0;
771 }
772 
773 static const struct snd_soc_dapm_widget wm9081_dapm_widgets[] = {
774 SND_SOC_DAPM_INPUT("IN1"),
775 SND_SOC_DAPM_INPUT("IN2"),
776 
777 SND_SOC_DAPM_DAC("DAC", NULL, WM9081_POWER_MANAGEMENT, 0, 0),
778 
779 SND_SOC_DAPM_MIXER_NAMED_CTL("Mixer", SND_SOC_NOPM, 0, 0,
780  mixer, ARRAY_SIZE(mixer)),
781 
782 SND_SOC_DAPM_PGA("LINEOUT PGA", WM9081_POWER_MANAGEMENT, 4, 0, NULL, 0),
783 
784 SND_SOC_DAPM_PGA("Speaker PGA", WM9081_POWER_MANAGEMENT, 2, 0, NULL, 0),
785 SND_SOC_DAPM_OUT_DRV("Speaker", WM9081_POWER_MANAGEMENT, 1, 0, NULL, 0),
786 
787 SND_SOC_DAPM_OUTPUT("LINEOUT"),
788 SND_SOC_DAPM_OUTPUT("SPKN"),
789 SND_SOC_DAPM_OUTPUT("SPKP"),
790 
791 SND_SOC_DAPM_SUPPLY("CLK_SYS", WM9081_CLOCK_CONTROL_3, 0, 0, clk_sys_event,
792  SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
793 SND_SOC_DAPM_SUPPLY("CLK_DSP", WM9081_CLOCK_CONTROL_3, 1, 0, NULL, 0),
794 SND_SOC_DAPM_SUPPLY("TOCLK", WM9081_CLOCK_CONTROL_3, 2, 0, NULL, 0),
795 SND_SOC_DAPM_SUPPLY("TSENSE", WM9081_POWER_MANAGEMENT, 7, 0, NULL, 0),
796 };
797 
798 
799 static const struct snd_soc_dapm_route wm9081_audio_paths[] = {
800  { "DAC", NULL, "CLK_SYS" },
801  { "DAC", NULL, "CLK_DSP" },
802  { "DAC", NULL, "AIF" },
803 
804  { "Mixer", "IN1 Switch", "IN1" },
805  { "Mixer", "IN2 Switch", "IN2" },
806  { "Mixer", "Playback Switch", "DAC" },
807 
808  { "LINEOUT PGA", NULL, "Mixer" },
809  { "LINEOUT PGA", NULL, "TOCLK" },
810  { "LINEOUT PGA", NULL, "CLK_SYS" },
811 
812  { "LINEOUT", NULL, "LINEOUT PGA" },
813 
814  { "Speaker PGA", NULL, "Mixer" },
815  { "Speaker PGA", NULL, "TOCLK" },
816  { "Speaker PGA", NULL, "CLK_SYS" },
817 
818  { "Speaker", NULL, "Speaker PGA" },
819  { "Speaker", NULL, "TSENSE" },
820 
821  { "SPKN", NULL, "Speaker" },
822  { "SPKP", NULL, "Speaker" },
823 };
824 
825 static int wm9081_set_bias_level(struct snd_soc_codec *codec,
826  enum snd_soc_bias_level level)
827 {
828  struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
829 
830  switch (level) {
831  case SND_SOC_BIAS_ON:
832  break;
833 
834  case SND_SOC_BIAS_PREPARE:
835  /* VMID=2*40k */
836  snd_soc_update_bits(codec, WM9081_VMID_CONTROL,
837  WM9081_VMID_SEL_MASK, 0x2);
838 
839  /* Normal bias current */
840  snd_soc_update_bits(codec, WM9081_BIAS_CONTROL_1,
841  WM9081_STBY_BIAS_ENA, 0);
842  break;
843 
844  case SND_SOC_BIAS_STANDBY:
845  /* Initial cold start */
846  if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
847  regcache_cache_only(wm9081->regmap, false);
848  regcache_sync(wm9081->regmap);
849 
850  /* Disable LINEOUT discharge */
851  snd_soc_update_bits(codec, WM9081_ANTI_POP_CONTROL,
852  WM9081_LINEOUT_DISCH, 0);
853 
854  /* Select startup bias source */
855  snd_soc_update_bits(codec, WM9081_BIAS_CONTROL_1,
856  WM9081_BIAS_SRC | WM9081_BIAS_ENA,
857  WM9081_BIAS_SRC | WM9081_BIAS_ENA);
858 
859  /* VMID 2*4k; Soft VMID ramp enable */
860  snd_soc_update_bits(codec, WM9081_VMID_CONTROL,
861  WM9081_VMID_RAMP |
862  WM9081_VMID_SEL_MASK,
863  WM9081_VMID_RAMP | 0x6);
864 
865  mdelay(100);
866 
867  /* Normal bias enable & soft start off */
868  snd_soc_update_bits(codec, WM9081_VMID_CONTROL,
869  WM9081_VMID_RAMP, 0);
870 
871  /* Standard bias source */
872  snd_soc_update_bits(codec, WM9081_BIAS_CONTROL_1,
873  WM9081_BIAS_SRC, 0);
874  }
875 
876  /* VMID 2*240k */
877  snd_soc_update_bits(codec, WM9081_VMID_CONTROL,
878  WM9081_VMID_SEL_MASK, 0x04);
879 
880  /* Standby bias current on */
881  snd_soc_update_bits(codec, WM9081_BIAS_CONTROL_1,
882  WM9081_STBY_BIAS_ENA,
883  WM9081_STBY_BIAS_ENA);
884  break;
885 
886  case SND_SOC_BIAS_OFF:
887  /* Startup bias source and disable bias */
888  snd_soc_update_bits(codec, WM9081_BIAS_CONTROL_1,
889  WM9081_BIAS_SRC | WM9081_BIAS_ENA,
890  WM9081_BIAS_SRC);
891 
892  /* Disable VMID with soft ramping */
893  snd_soc_update_bits(codec, WM9081_VMID_CONTROL,
894  WM9081_VMID_RAMP | WM9081_VMID_SEL_MASK,
895  WM9081_VMID_RAMP);
896 
897  /* Actively discharge LINEOUT */
898  snd_soc_update_bits(codec, WM9081_ANTI_POP_CONTROL,
899  WM9081_LINEOUT_DISCH,
900  WM9081_LINEOUT_DISCH);
901 
902  regcache_cache_only(wm9081->regmap, true);
903  break;
904  }
905 
906  codec->dapm.bias_level = level;
907 
908  return 0;
909 }
910 
911 static int wm9081_set_dai_fmt(struct snd_soc_dai *dai,
912  unsigned int fmt)
913 {
914  struct snd_soc_codec *codec = dai->codec;
915  struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
916  unsigned int aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
917 
918  aif2 &= ~(WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV |
919  WM9081_BCLK_DIR | WM9081_LRCLK_DIR | WM9081_AIF_FMT_MASK);
920 
921  switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
922  case SND_SOC_DAIFMT_CBS_CFS:
923  wm9081->master = 0;
924  break;
925  case SND_SOC_DAIFMT_CBS_CFM:
926  aif2 |= WM9081_LRCLK_DIR;
927  wm9081->master = 1;
928  break;
929  case SND_SOC_DAIFMT_CBM_CFS:
930  aif2 |= WM9081_BCLK_DIR;
931  wm9081->master = 1;
932  break;
933  case SND_SOC_DAIFMT_CBM_CFM:
934  aif2 |= WM9081_LRCLK_DIR | WM9081_BCLK_DIR;
935  wm9081->master = 1;
936  break;
937  default:
938  return -EINVAL;
939  }
940 
941  switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
942  case SND_SOC_DAIFMT_DSP_B:
943  aif2 |= WM9081_AIF_LRCLK_INV;
944  case SND_SOC_DAIFMT_DSP_A:
945  aif2 |= 0x3;
946  break;
947  case SND_SOC_DAIFMT_I2S:
948  aif2 |= 0x2;
949  break;
950  case SND_SOC_DAIFMT_RIGHT_J:
951  break;
952  case SND_SOC_DAIFMT_LEFT_J:
953  aif2 |= 0x1;
954  break;
955  default:
956  return -EINVAL;
957  }
958 
959  switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
960  case SND_SOC_DAIFMT_DSP_A:
961  case SND_SOC_DAIFMT_DSP_B:
962  /* frame inversion not valid for DSP modes */
963  switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
964  case SND_SOC_DAIFMT_NB_NF:
965  break;
966  case SND_SOC_DAIFMT_IB_NF:
967  aif2 |= WM9081_AIF_BCLK_INV;
968  break;
969  default:
970  return -EINVAL;
971  }
972  break;
973 
974  case SND_SOC_DAIFMT_I2S:
975  case SND_SOC_DAIFMT_RIGHT_J:
976  case SND_SOC_DAIFMT_LEFT_J:
977  switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
978  case SND_SOC_DAIFMT_NB_NF:
979  break;
980  case SND_SOC_DAIFMT_IB_IF:
981  aif2 |= WM9081_AIF_BCLK_INV | WM9081_AIF_LRCLK_INV;
982  break;
983  case SND_SOC_DAIFMT_IB_NF:
984  aif2 |= WM9081_AIF_BCLK_INV;
985  break;
986  case SND_SOC_DAIFMT_NB_IF:
987  aif2 |= WM9081_AIF_LRCLK_INV;
988  break;
989  default:
990  return -EINVAL;
991  }
992  break;
993  default:
994  return -EINVAL;
995  }
996 
997  snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
998 
999  return 0;
1000 }
1001 
1002 static int wm9081_hw_params(struct snd_pcm_substream *substream,
1003  struct snd_pcm_hw_params *params,
1004  struct snd_soc_dai *dai)
1005 {
1006  struct snd_soc_codec *codec = dai->codec;
1007  struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
1008  int ret, i, best, best_val, cur_val;
1009  unsigned int clk_ctrl2, aif1, aif2, aif3, aif4;
1010 
1011  clk_ctrl2 = snd_soc_read(codec, WM9081_CLOCK_CONTROL_2);
1012  clk_ctrl2 &= ~(WM9081_CLK_SYS_RATE_MASK | WM9081_SAMPLE_RATE_MASK);
1013 
1014  aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
1015 
1016  aif2 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_2);
1017  aif2 &= ~WM9081_AIF_WL_MASK;
1018 
1019  aif3 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_3);
1020  aif3 &= ~WM9081_BCLK_DIV_MASK;
1021 
1022  aif4 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_4);
1023  aif4 &= ~WM9081_LRCLK_RATE_MASK;
1024 
1025  wm9081->fs = params_rate(params);
1026 
1027  if (wm9081->tdm_width) {
1028  /* If TDM is set up then that fixes our BCLK. */
1029  int slots = ((aif1 & WM9081_AIFDAC_TDM_MODE_MASK) >>
1030  WM9081_AIFDAC_TDM_MODE_SHIFT) + 1;
1031 
1032  wm9081->bclk = wm9081->fs * wm9081->tdm_width * slots;
1033  } else {
1034  /* Otherwise work out a BCLK from the sample size */
1035  wm9081->bclk = 2 * wm9081->fs;
1036 
1037  switch (params_format(params)) {
1038  case SNDRV_PCM_FORMAT_S16_LE:
1039  wm9081->bclk *= 16;
1040  break;
1041  case SNDRV_PCM_FORMAT_S20_3LE:
1042  wm9081->bclk *= 20;
1043  aif2 |= 0x4;
1044  break;
1045  case SNDRV_PCM_FORMAT_S24_LE:
1046  wm9081->bclk *= 24;
1047  aif2 |= 0x8;
1048  break;
1049  case SNDRV_PCM_FORMAT_S32_LE:
1050  wm9081->bclk *= 32;
1051  aif2 |= 0xc;
1052  break;
1053  default:
1054  return -EINVAL;
1055  }
1056  }
1057 
1058  dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm9081->bclk);
1059 
1060  ret = configure_clock(codec);
1061  if (ret != 0)
1062  return ret;
1063 
1064  /* Select nearest CLK_SYS_RATE */
1065  best = 0;
1066  best_val = abs((wm9081->sysclk_rate / clk_sys_rates[0].ratio)
1067  - wm9081->fs);
1068  for (i = 1; i < ARRAY_SIZE(clk_sys_rates); i++) {
1069  cur_val = abs((wm9081->sysclk_rate /
1070  clk_sys_rates[i].ratio) - wm9081->fs);
1071  if (cur_val < best_val) {
1072  best = i;
1073  best_val = cur_val;
1074  }
1075  }
1076  dev_dbg(codec->dev, "Selected CLK_SYS_RATIO of %d\n",
1077  clk_sys_rates[best].ratio);
1078  clk_ctrl2 |= (clk_sys_rates[best].clk_sys_rate
1079  << WM9081_CLK_SYS_RATE_SHIFT);
1080 
1081  /* SAMPLE_RATE */
1082  best = 0;
1083  best_val = abs(wm9081->fs - sample_rates[0].rate);
1084  for (i = 1; i < ARRAY_SIZE(sample_rates); i++) {
1085  /* Closest match */
1086  cur_val = abs(wm9081->fs - sample_rates[i].rate);
1087  if (cur_val < best_val) {
1088  best = i;
1089  best_val = cur_val;
1090  }
1091  }
1092  dev_dbg(codec->dev, "Selected SAMPLE_RATE of %dHz\n",
1093  sample_rates[best].rate);
1094  clk_ctrl2 |= (sample_rates[best].sample_rate
1095  << WM9081_SAMPLE_RATE_SHIFT);
1096 
1097  /* BCLK_DIV */
1098  best = 0;
1099  best_val = INT_MAX;
1100  for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
1101  cur_val = ((wm9081->sysclk_rate * 10) / bclk_divs[i].div)
1102  - wm9081->bclk;
1103  if (cur_val < 0) /* Table is sorted */
1104  break;
1105  if (cur_val < best_val) {
1106  best = i;
1107  best_val = cur_val;
1108  }
1109  }
1110  wm9081->bclk = (wm9081->sysclk_rate * 10) / bclk_divs[best].div;
1111  dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n",
1112  bclk_divs[best].div, wm9081->bclk);
1113  aif3 |= bclk_divs[best].bclk_div;
1114 
1115  /* LRCLK is a simple fraction of BCLK */
1116  dev_dbg(codec->dev, "LRCLK_RATE is %d\n", wm9081->bclk / wm9081->fs);
1117  aif4 |= wm9081->bclk / wm9081->fs;
1118 
1119  /* Apply a ReTune Mobile configuration if it's in use */
1120  if (wm9081->pdata.num_retune_configs) {
1121  struct wm9081_pdata *pdata = &wm9081->pdata;
1122  struct wm9081_retune_mobile_setting *s;
1123  int eq1;
1124 
1125  best = 0;
1126  best_val = abs(pdata->retune_configs[0].rate - wm9081->fs);
1127  for (i = 0; i < pdata->num_retune_configs; i++) {
1128  cur_val = abs(pdata->retune_configs[i].rate -
1129  wm9081->fs);
1130  if (cur_val < best_val) {
1131  best_val = cur_val;
1132  best = i;
1133  }
1134  }
1135  s = &pdata->retune_configs[best];
1136 
1137  dev_dbg(codec->dev, "ReTune Mobile %s tuned for %dHz\n",
1138  s->name, s->rate);
1139 
1140  /* If the EQ is enabled then disable it while we write out */
1141  eq1 = snd_soc_read(codec, WM9081_EQ_1) & WM9081_EQ_ENA;
1142  if (eq1 & WM9081_EQ_ENA)
1143  snd_soc_write(codec, WM9081_EQ_1, 0);
1144 
1145  /* Write out the other values */
1146  for (i = 1; i < ARRAY_SIZE(s->config); i++)
1147  snd_soc_write(codec, WM9081_EQ_1 + i, s->config[i]);
1148 
1149  eq1 |= (s->config[0] & ~WM9081_EQ_ENA);
1150  snd_soc_write(codec, WM9081_EQ_1, eq1);
1151  }
1152 
1153  snd_soc_write(codec, WM9081_CLOCK_CONTROL_2, clk_ctrl2);
1154  snd_soc_write(codec, WM9081_AUDIO_INTERFACE_2, aif2);
1155  snd_soc_write(codec, WM9081_AUDIO_INTERFACE_3, aif3);
1156  snd_soc_write(codec, WM9081_AUDIO_INTERFACE_4, aif4);
1157 
1158  return 0;
1159 }
1160 
1161 static int wm9081_digital_mute(struct snd_soc_dai *codec_dai, int mute)
1162 {
1163  struct snd_soc_codec *codec = codec_dai->codec;
1164  unsigned int reg;
1165 
1166  reg = snd_soc_read(codec, WM9081_DAC_DIGITAL_2);
1167 
1168  if (mute)
1169  reg |= WM9081_DAC_MUTE;
1170  else
1171  reg &= ~WM9081_DAC_MUTE;
1172 
1173  snd_soc_write(codec, WM9081_DAC_DIGITAL_2, reg);
1174 
1175  return 0;
1176 }
1177 
1178 static int wm9081_set_sysclk(struct snd_soc_codec *codec, int clk_id,
1179  int source, unsigned int freq, int dir)
1180 {
1181  struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
1182 
1183  switch (clk_id) {
1184  case WM9081_SYSCLK_MCLK:
1185  case WM9081_SYSCLK_FLL_MCLK:
1186  wm9081->sysclk_source = clk_id;
1187  wm9081->mclk_rate = freq;
1188  break;
1189 
1190  default:
1191  return -EINVAL;
1192  }
1193 
1194  return 0;
1195 }
1196 
1197 static int wm9081_set_tdm_slot(struct snd_soc_dai *dai,
1198  unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1199 {
1200  struct snd_soc_codec *codec = dai->codec;
1201  struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
1202  unsigned int aif1 = snd_soc_read(codec, WM9081_AUDIO_INTERFACE_1);
1203 
1204  aif1 &= ~(WM9081_AIFDAC_TDM_SLOT_MASK | WM9081_AIFDAC_TDM_MODE_MASK);
1205 
1206  if (slots < 0 || slots > 4)
1207  return -EINVAL;
1208 
1209  wm9081->tdm_width = slot_width;
1210 
1211  if (slots == 0)
1212  slots = 1;
1213 
1214  aif1 |= (slots - 1) << WM9081_AIFDAC_TDM_MODE_SHIFT;
1215 
1216  switch (rx_mask) {
1217  case 1:
1218  break;
1219  case 2:
1220  aif1 |= 0x10;
1221  break;
1222  case 4:
1223  aif1 |= 0x20;
1224  break;
1225  case 8:
1226  aif1 |= 0x30;
1227  break;
1228  default:
1229  return -EINVAL;
1230  }
1231 
1232  snd_soc_write(codec, WM9081_AUDIO_INTERFACE_1, aif1);
1233 
1234  return 0;
1235 }
1236 
1237 #define WM9081_RATES SNDRV_PCM_RATE_8000_96000
1238 
1239 #define WM9081_FORMATS \
1240  (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1241  SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1242 
1243 static const struct snd_soc_dai_ops wm9081_dai_ops = {
1244  .hw_params = wm9081_hw_params,
1245  .set_fmt = wm9081_set_dai_fmt,
1246  .digital_mute = wm9081_digital_mute,
1247  .set_tdm_slot = wm9081_set_tdm_slot,
1248 };
1249 
1250 /* We report two channels because the CODEC processes a stereo signal, even
1251  * though it is only capable of handling a mono output.
1252  */
1253 static struct snd_soc_dai_driver wm9081_dai = {
1254  .name = "wm9081-hifi",
1255  .playback = {
1256  .stream_name = "AIF",
1257  .channels_min = 1,
1258  .channels_max = 2,
1259  .rates = WM9081_RATES,
1260  .formats = WM9081_FORMATS,
1261  },
1262  .ops = &wm9081_dai_ops,
1263 };
1264 
1265 static int wm9081_probe(struct snd_soc_codec *codec)
1266 {
1267  struct wm9081_priv *wm9081 = snd_soc_codec_get_drvdata(codec);
1268  int ret;
1269 
1270  codec->control_data = wm9081->regmap;
1271 
1272  ret = snd_soc_codec_set_cache_io(codec, 8, 16, SND_SOC_REGMAP);
1273  if (ret != 0) {
1274  dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1275  return ret;
1276  }
1277 
1278  /* Enable zero cross by default */
1279  snd_soc_update_bits(codec, WM9081_ANALOGUE_LINEOUT,
1280  WM9081_LINEOUTZC, WM9081_LINEOUTZC);
1281  snd_soc_update_bits(codec, WM9081_ANALOGUE_SPEAKER_PGA,
1282  WM9081_SPKPGAZC, WM9081_SPKPGAZC);
1283 
1284  if (!wm9081->pdata.num_retune_configs) {
1285  dev_dbg(codec->dev,
1286  "No ReTune Mobile data, using normal EQ\n");
1287  snd_soc_add_codec_controls(codec, wm9081_eq_controls,
1288  ARRAY_SIZE(wm9081_eq_controls));
1289  }
1290 
1291  return ret;
1292 }
1293 
1294 static int wm9081_remove(struct snd_soc_codec *codec)
1295 {
1296  wm9081_set_bias_level(codec, SND_SOC_BIAS_OFF);
1297  return 0;
1298 }
1299 
1300 static struct snd_soc_codec_driver soc_codec_dev_wm9081 = {
1301  .probe = wm9081_probe,
1302  .remove = wm9081_remove,
1303 
1304  .set_sysclk = wm9081_set_sysclk,
1305  .set_bias_level = wm9081_set_bias_level,
1306 
1307  .idle_bias_off = true,
1308 
1309  .controls = wm9081_snd_controls,
1310  .num_controls = ARRAY_SIZE(wm9081_snd_controls),
1311  .dapm_widgets = wm9081_dapm_widgets,
1312  .num_dapm_widgets = ARRAY_SIZE(wm9081_dapm_widgets),
1313  .dapm_routes = wm9081_audio_paths,
1314  .num_dapm_routes = ARRAY_SIZE(wm9081_audio_paths),
1315 };
1316 
1317 static const struct regmap_config wm9081_regmap = {
1318  .reg_bits = 8,
1319  .val_bits = 16,
1320 
1321  .max_register = WM9081_MAX_REGISTER,
1322  .reg_defaults = wm9081_reg,
1323  .num_reg_defaults = ARRAY_SIZE(wm9081_reg),
1324  .volatile_reg = wm9081_volatile_register,
1325  .readable_reg = wm9081_readable_register,
1326  .cache_type = REGCACHE_RBTREE,
1327 };
1328 
1329 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1330 static __devinit int wm9081_i2c_probe(struct i2c_client *i2c,
1331  const struct i2c_device_id *id)
1332 {
1333  struct wm9081_priv *wm9081;
1334  unsigned int reg;
1335  int ret;
1336 
1337  wm9081 = devm_kzalloc(&i2c->dev, sizeof(struct wm9081_priv),
1338  GFP_KERNEL);
1339  if (wm9081 == NULL)
1340  return -ENOMEM;
1341 
1342  i2c_set_clientdata(i2c, wm9081);
1343 
1344  wm9081->regmap = regmap_init_i2c(i2c, &wm9081_regmap);
1345  if (IS_ERR(wm9081->regmap)) {
1346  ret = PTR_ERR(wm9081->regmap);
1347  dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);
1348  goto err;
1349  }
1350 
1351  ret = regmap_read(wm9081->regmap, WM9081_SOFTWARE_RESET, &reg);
1352  if (ret != 0) {
1353  dev_err(&i2c->dev, "Failed to read chip ID: %d\n", ret);
1354  goto err_regmap;
1355  }
1356  if (reg != 0x9081) {
1357  dev_err(&i2c->dev, "Device is not a WM9081: ID=0x%x\n", reg);
1358  ret = -EINVAL;
1359  goto err_regmap;
1360  }
1361 
1362  ret = wm9081_reset(wm9081->regmap);
1363  if (ret < 0) {
1364  dev_err(&i2c->dev, "Failed to issue reset\n");
1365  goto err_regmap;
1366  }
1367 
1368  if (dev_get_platdata(&i2c->dev))
1369  memcpy(&wm9081->pdata, dev_get_platdata(&i2c->dev),
1370  sizeof(wm9081->pdata));
1371 
1372  reg = 0;
1373  if (wm9081->pdata.irq_high)
1374  reg |= WM9081_IRQ_POL;
1375  if (!wm9081->pdata.irq_cmos)
1376  reg |= WM9081_IRQ_OP_CTRL;
1377  regmap_update_bits(wm9081->regmap, WM9081_INTERRUPT_CONTROL,
1378  WM9081_IRQ_POL | WM9081_IRQ_OP_CTRL, reg);
1379 
1380  regcache_cache_only(wm9081->regmap, true);
1381 
1382  ret = snd_soc_register_codec(&i2c->dev,
1383  &soc_codec_dev_wm9081, &wm9081_dai, 1);
1384  if (ret < 0)
1385  goto err_regmap;
1386 
1387  return 0;
1388 
1389 err_regmap:
1390  regmap_exit(wm9081->regmap);
1391 err:
1392 
1393  return ret;
1394 }
1395 
1396 static __devexit int wm9081_i2c_remove(struct i2c_client *client)
1397 {
1398  struct wm9081_priv *wm9081 = i2c_get_clientdata(client);
1399 
1400  snd_soc_unregister_codec(&client->dev);
1401  regmap_exit(wm9081->regmap);
1402  return 0;
1403 }
1404 
1405 static const struct i2c_device_id wm9081_i2c_id[] = {
1406  { "wm9081", 0 },
1407  { }
1408 };
1409 MODULE_DEVICE_TABLE(i2c, wm9081_i2c_id);
1410 
1411 static struct i2c_driver wm9081_i2c_driver = {
1412  .driver = {
1413  .name = "wm9081",
1414  .owner = THIS_MODULE,
1415  },
1416  .probe = wm9081_i2c_probe,
1417  .remove = __devexit_p(wm9081_i2c_remove),
1418  .id_table = wm9081_i2c_id,
1419 };
1420 #endif
1421 
1422 module_i2c_driver(wm9081_i2c_driver);
1423 
1424 MODULE_DESCRIPTION("ASoC WM9081 driver");
1425 MODULE_AUTHOR("Mark Brown <[email protected]>");
1426 MODULE_LICENSE("GPL");
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