#include <linux/module.h>
#include <linux/uaccess.h>
#include <linux/init.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/of_platform.h>
#include <linux/of_mdio.h>
#include <linux/of_net.h>
#include <linux/phy.h>
#include <linux/interrupt.h>

Data Structures
struct	net_local

Macros
#define	DRIVER_NAME "xilinx_emaclite"

#define	XEL_TXBUFF_OFFSET 0x0 /* Transmit Buffer */

#define	XEL_MDIOADDR_OFFSET 0x07E4 /* MDIO Address Register */

#define	XEL_MDIOWR_OFFSET 0x07E8 /* MDIO Write Data Register */

#define	XEL_MDIORD_OFFSET 0x07EC /* MDIO Read Data Register */

#define	XEL_MDIOCTRL_OFFSET 0x07F0 /* MDIO Control Register */

#define	XEL_GIER_OFFSET 0x07F8 /* GIE Register */

#define	XEL_TSR_OFFSET 0x07FC /* Tx status */

#define	XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */

#define	XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */

#define	XEL_RPLR_OFFSET 0x100C /* Rx packet length */

#define	XEL_RSR_OFFSET 0x17FC /* Rx status */

#define	XEL_BUFFER_OFFSET 0x0800 /* Next Tx/Rx buffer's offset */

#define	XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */

#define	XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */

#define	XEL_MDIOADDR_PHYADR_SHIFT 5

#define	XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */

#define	XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */

#define	XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */

#define	XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */

#define	XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */

#define	XEL_GIER_GIE_MASK 0x80000000 /* Global Enable */

#define	XEL_TSR_XMIT_BUSY_MASK 0x00000001 /* Tx complete */

#define	XEL_TSR_PROGRAM_MASK 0x00000002 /* Program the MAC address */

#define	XEL_TSR_XMIT_IE_MASK 0x00000008 /* Tx interrupt enable bit */

#define	XEL_TSR_XMIT_ACTIVE_MASK

#define	XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK \| XEL_TSR_PROGRAM_MASK)

#define	XEL_RSR_RECV_DONE_MASK 0x00000001 /* Rx complete */

#define	XEL_RSR_RECV_IE_MASK 0x00000008 /* Rx interrupt enable bit */

#define	XEL_TPLR_LENGTH_MASK 0x0000FFFF /* Tx packet length */

#define	XEL_RPLR_LENGTH_MASK 0x0000FFFF /* Rx packet length */

#define	XEL_HEADER_OFFSET 12 /* Offset to length field */

#define	XEL_HEADER_SHIFT 16 /* Shift value for length */

#define	XEL_ARP_PACKET_SIZE 28 /* Max ARP packet size */

#define	XEL_HEADER_IP_LENGTH_OFFSET 16 /* IP Length Offset */

#define	TX_TIMEOUT (60HZ) / Tx timeout is 60 seconds. */

#define	ALIGNMENT 4

#define	BUFFER_ALIGN(adr) ((ALIGNMENT - ((u32) adr)) % ALIGNMENT)

Functions
void	xemaclite_adjust_link (struct net_device *ndev)

	MODULE_DEVICE_TABLE (of, xemaclite_of_match)

	module_platform_driver (xemaclite_of_driver)

	MODULE_AUTHOR ("Xilinx, Inc.")

	MODULE_DESCRIPTION ("Xilinx Ethernet MAC Lite driver")

	MODULE_LICENSE ("GPL")

Macro Definition Documentation

#define ALIGNMENT 4

Definition at line 97 of file xilinx_emaclite.c.

#define BUFFER_ALIGN ( adr ) ((ALIGNMENT - ((u32) adr)) % ALIGNMENT)

Definition at line 100 of file xilinx_emaclite.c.

#define DRIVER_NAME "xilinx_emaclite"

Definition at line 31 of file xilinx_emaclite.c.

#define TX_TIMEOUT (60*HZ) /* Tx timeout is 60 seconds. */

Definition at line 96 of file xilinx_emaclite.c.

#define XEL_ARP_PACKET_SIZE 28 /* Max ARP packet size */

Definition at line 91 of file xilinx_emaclite.c.

#define XEL_BUFFER_OFFSET 0x0800 /* Next Tx/Rx buffer's offset */

Definition at line 47 of file xilinx_emaclite.c.

#define XEL_GIER_GIE_MASK 0x80000000 /* Global Enable */

Definition at line 66 of file xilinx_emaclite.c.

#define XEL_GIER_OFFSET 0x07F8 /* GIE Register */

Definition at line 39 of file xilinx_emaclite.c.

#define XEL_HEADER_IP_LENGTH_OFFSET 16 /* IP Length Offset */

Definition at line 92 of file xilinx_emaclite.c.

#define XEL_HEADER_OFFSET 12 /* Offset to length field */

Definition at line 87 of file xilinx_emaclite.c.

#define XEL_HEADER_SHIFT 16 /* Shift value for length */

Definition at line 88 of file xilinx_emaclite.c.

#define XEL_MDIOADDR_OFFSET 0x07E4 /* MDIO Address Register */

Definition at line 35 of file xilinx_emaclite.c.

#define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */

Definition at line 53 of file xilinx_emaclite.c.

#define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */

Definition at line 51 of file xilinx_emaclite.c.

#define XEL_MDIOADDR_PHYADR_SHIFT 5

Definition at line 52 of file xilinx_emaclite.c.

#define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */

Definition at line 50 of file xilinx_emaclite.c.

#define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */

Definition at line 63 of file xilinx_emaclite.c.

#define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */

Definition at line 62 of file xilinx_emaclite.c.

#define XEL_MDIOCTRL_OFFSET 0x07F0 /* MDIO Control Register */

Definition at line 38 of file xilinx_emaclite.c.

#define XEL_MDIORD_OFFSET 0x07EC /* MDIO Read Data Register */

Definition at line 37 of file xilinx_emaclite.c.

#define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */

Definition at line 59 of file xilinx_emaclite.c.

#define XEL_MDIOWR_OFFSET 0x07E8 /* MDIO Write Data Register */

Definition at line 36 of file xilinx_emaclite.c.

#define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */

Definition at line 56 of file xilinx_emaclite.c.

#define XEL_RPLR_LENGTH_MASK 0x0000FFFF /* Rx packet length */

Definition at line 85 of file xilinx_emaclite.c.

#define XEL_RPLR_OFFSET 0x100C /* Rx packet length */

Definition at line 44 of file xilinx_emaclite.c.

#define XEL_RSR_OFFSET 0x17FC /* Rx status */

Definition at line 45 of file xilinx_emaclite.c.

#define XEL_RSR_RECV_DONE_MASK 0x00000001 /* Rx complete */

Definition at line 78 of file xilinx_emaclite.c.

#define XEL_RSR_RECV_IE_MASK 0x00000008 /* Rx interrupt enable bit */

Definition at line 79 of file xilinx_emaclite.c.

#define XEL_RXBUFF_OFFSET 0x1000 /* Receive Buffer */

Definition at line 43 of file xilinx_emaclite.c.

#define XEL_TPLR_LENGTH_MASK 0x0000FFFF /* Tx packet length */

Definition at line 82 of file xilinx_emaclite.c.

#define XEL_TPLR_OFFSET 0x07F4 /* Tx packet length */

Definition at line 41 of file xilinx_emaclite.c.

#define XEL_TSR_OFFSET 0x07FC /* Tx status */

Definition at line 40 of file xilinx_emaclite.c.

#define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)

Definition at line 75 of file xilinx_emaclite.c.

#define XEL_TSR_PROGRAM_MASK 0x00000002 /* Program the MAC address */

Definition at line 70 of file xilinx_emaclite.c.

#define XEL_TSR_XMIT_ACTIVE_MASK

Value:

0x80000000  /* Buffer is active, SW bit
                         * only. This is not documented
                         * in the HW spec */

Definition at line 72 of file xilinx_emaclite.c.

#define XEL_TSR_XMIT_BUSY_MASK 0x00000001 /* Tx complete */

Definition at line 69 of file xilinx_emaclite.c.

#define XEL_TSR_XMIT_IE_MASK 0x00000008 /* Tx interrupt enable bit */

Definition at line 71 of file xilinx_emaclite.c.

#define XEL_TXBUFF_OFFSET 0x0 /* Transmit Buffer */

Definition at line 34 of file xilinx_emaclite.c.

Function Documentation

MODULE_AUTHOR	(	"	Xilinx,
		Inc."
	)

MODULE_DESCRIPTION ( "Xilinx Ethernet MAC Lite driver" )

MODULE_DEVICE_TABLE	(	of	,
		xemaclite_of_match
	)

MODULE_LICENSE ( "GPL" )

module_platform_driver ( xemaclite_of_driver )

void xemaclite_adjust_link ( struct net_device * ndev )

xemaclite_adjust_link - Link state callback for the Emaclite device : pointer to net_device struct

There's nothing in the Emaclite device to be configured when the link state changes. We just print the status.

Definition at line 897 of file xilinx_emaclite.c.

Data Structures

Macros

Functions

Macro Definition Documentation

Function Documentation