LLVM API Documentation

HexagonInstrInfo.h
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00001 //===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file contains the Hexagon implementation of the TargetInstrInfo class.
00011 //
00012 //===----------------------------------------------------------------------===//
00013 
00014 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
00015 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
00016 
00017 #include "HexagonRegisterInfo.h"
00018 #include "MCTargetDesc/HexagonBaseInfo.h"
00019 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
00020 #include "llvm/Target/TargetFrameLowering.h"
00021 #include "llvm/Target/TargetInstrInfo.h"
00022 
00023 #define GET_INSTRINFO_HEADER
00024 #include "HexagonGenInstrInfo.inc"
00025 
00026 namespace llvm {
00027 
00028 struct EVT;
00029 
00030 class HexagonInstrInfo : public HexagonGenInstrInfo {
00031   virtual void anchor();
00032   const HexagonRegisterInfo RI;
00033   const HexagonSubtarget &Subtarget;
00034   typedef unsigned Opcode_t;
00035 
00036 public:
00037   explicit HexagonInstrInfo(HexagonSubtarget &ST);
00038 
00039   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
00040   /// such, whenever a client has an instance of instruction info, it should
00041   /// always be able to get register info as well (through this method).
00042   ///
00043   const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
00044 
00045   /// isLoadFromStackSlot - If the specified machine instruction is a direct
00046   /// load from a stack slot, return the virtual or physical register number of
00047   /// the destination along with the FrameIndex of the loaded stack slot.  If
00048   /// not, return 0.  This predicate must return 0 if the instruction has
00049   /// any side effects other than loading from the stack slot.
00050   unsigned isLoadFromStackSlot(const MachineInstr *MI,
00051                                int &FrameIndex) const override;
00052 
00053   /// isStoreToStackSlot - If the specified machine instruction is a direct
00054   /// store to a stack slot, return the virtual or physical register number of
00055   /// the source reg along with the FrameIndex of the loaded stack slot.  If
00056   /// not, return 0.  This predicate must return 0 if the instruction has
00057   /// any side effects other than storing to the stack slot.
00058   unsigned isStoreToStackSlot(const MachineInstr *MI,
00059                               int &FrameIndex) const override;
00060 
00061 
00062   bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
00063                          MachineBasicBlock *&FBB,
00064                          SmallVectorImpl<MachineOperand> &Cond,
00065                          bool AllowModify) const override;
00066 
00067   unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
00068 
00069   unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
00070                         MachineBasicBlock *FBB,
00071                         const SmallVectorImpl<MachineOperand> &Cond,
00072                         DebugLoc DL) const override;
00073 
00074   bool analyzeCompare(const MachineInstr *MI,
00075                       unsigned &SrcReg, unsigned &SrcReg2,
00076                       int &Mask, int &Value) const override;
00077 
00078   void copyPhysReg(MachineBasicBlock &MBB,
00079                    MachineBasicBlock::iterator I, DebugLoc DL,
00080                    unsigned DestReg, unsigned SrcReg,
00081                    bool KillSrc) const override;
00082 
00083   void storeRegToStackSlot(MachineBasicBlock &MBB,
00084                            MachineBasicBlock::iterator MBBI,
00085                            unsigned SrcReg, bool isKill, int FrameIndex,
00086                            const TargetRegisterClass *RC,
00087                            const TargetRegisterInfo *TRI) const override;
00088 
00089   void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
00090                       SmallVectorImpl<MachineOperand> &Addr,
00091                       const TargetRegisterClass *RC,
00092                       SmallVectorImpl<MachineInstr*> &NewMIs) const;
00093 
00094   void loadRegFromStackSlot(MachineBasicBlock &MBB,
00095                             MachineBasicBlock::iterator MBBI,
00096                             unsigned DestReg, int FrameIndex,
00097                             const TargetRegisterClass *RC,
00098                             const TargetRegisterInfo *TRI) const override;
00099 
00100   void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
00101                        SmallVectorImpl<MachineOperand> &Addr,
00102                        const TargetRegisterClass *RC,
00103                        SmallVectorImpl<MachineInstr*> &NewMIs) const;
00104 
00105   MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
00106                                       MachineInstr* MI,
00107                                       const SmallVectorImpl<unsigned> &Ops,
00108                                       int FrameIndex) const override;
00109 
00110   MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
00111                                       MachineInstr* MI,
00112                                       const SmallVectorImpl<unsigned> &Ops,
00113                                       MachineInstr* LoadMI) const override {
00114     return nullptr;
00115   }
00116 
00117   unsigned createVR(MachineFunction* MF, MVT VT) const;
00118 
00119   bool isBranch(const MachineInstr *MI) const;
00120   bool isPredicable(MachineInstr *MI) const override;
00121   bool PredicateInstruction(MachineInstr *MI,
00122                     const SmallVectorImpl<MachineOperand> &Cond) const override;
00123 
00124   bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
00125                            unsigned ExtraPredCycles,
00126                            const BranchProbability &Probability) const override;
00127 
00128   bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
00129                            unsigned NumTCycles, unsigned ExtraTCycles,
00130                            MachineBasicBlock &FMBB,
00131                            unsigned NumFCycles, unsigned ExtraFCycles,
00132                            const BranchProbability &Probability) const override;
00133 
00134   bool isPredicated(const MachineInstr *MI) const override;
00135   bool isPredicated(unsigned Opcode) const;
00136   bool isPredicatedTrue(const MachineInstr *MI) const;
00137   bool isPredicatedTrue(unsigned Opcode) const;
00138   bool isPredicatedNew(const MachineInstr *MI) const;
00139   bool isPredicatedNew(unsigned Opcode) const;
00140   bool DefinesPredicate(MachineInstr *MI,
00141                         std::vector<MachineOperand> &Pred) const override;
00142   bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
00143                    const SmallVectorImpl<MachineOperand> &Pred2) const override;
00144 
00145   bool
00146   ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
00147 
00148   bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
00149                            const BranchProbability &Probability) const override;
00150 
00151   DFAPacketizer*
00152   CreateTargetScheduleState(const TargetMachine *TM,
00153                             const ScheduleDAG *DAG) const override;
00154 
00155   bool isSchedulingBoundary(const MachineInstr *MI,
00156                             const MachineBasicBlock *MBB,
00157                             const MachineFunction &MF) const override;
00158   bool isValidOffset(const int Opcode, const int Offset) const;
00159   bool isValidAutoIncImm(const EVT VT, const int Offset) const;
00160   bool isMemOp(const MachineInstr *MI) const;
00161   bool isSpillPredRegOp(const MachineInstr *MI) const;
00162   bool isU6_3Immediate(const int value) const;
00163   bool isU6_2Immediate(const int value) const;
00164   bool isU6_1Immediate(const int value) const;
00165   bool isU6_0Immediate(const int value) const;
00166   bool isS4_3Immediate(const int value) const;
00167   bool isS4_2Immediate(const int value) const;
00168   bool isS4_1Immediate(const int value) const;
00169   bool isS4_0Immediate(const int value) const;
00170   bool isS12_Immediate(const int value) const;
00171   bool isU6_Immediate(const int value) const;
00172   bool isS8_Immediate(const int value) const;
00173   bool isS6_Immediate(const int value) const;
00174 
00175   bool isSaveCalleeSavedRegsCall(const MachineInstr* MI) const;
00176   bool isConditionalTransfer(const MachineInstr* MI) const;
00177   bool isConditionalALU32 (const MachineInstr* MI) const;
00178   bool isConditionalLoad (const MachineInstr* MI) const;
00179   bool isConditionalStore(const MachineInstr* MI) const;
00180   bool isNewValueInst(const MachineInstr* MI) const;
00181   bool isNewValue(const MachineInstr* MI) const;
00182   bool isDotNewInst(const MachineInstr* MI) const;
00183   int GetDotOldOp(const int opc) const;
00184   int GetDotNewOp(const MachineInstr* MI) const;
00185   int GetDotNewPredOp(MachineInstr *MI,
00186                       const MachineBranchProbabilityInfo
00187                       *MBPI) const;
00188   bool mayBeNewStore(const MachineInstr* MI) const;
00189   bool isDeallocRet(const MachineInstr *MI) const;
00190   unsigned getInvertedPredicatedOpcode(const int Opc) const;
00191   bool isExtendable(const MachineInstr* MI) const;
00192   bool isExtended(const MachineInstr* MI) const;
00193   bool isPostIncrement(const MachineInstr* MI) const;
00194   bool isNewValueStore(const MachineInstr* MI) const;
00195   bool isNewValueStore(unsigned Opcode) const;
00196   bool isNewValueJump(const MachineInstr* MI) const;
00197   bool isNewValueJumpCandidate(const MachineInstr *MI) const;
00198 
00199 
00200   void immediateExtend(MachineInstr *MI) const;
00201   bool isConstExtended(MachineInstr *MI) const;
00202   int getDotNewPredJumpOp(MachineInstr *MI,
00203                       const MachineBranchProbabilityInfo *MBPI) const;
00204   unsigned getAddrMode(const MachineInstr* MI) const;
00205   bool isOperandExtended(const MachineInstr *MI,
00206                          unsigned short OperandNum) const;
00207   unsigned short getCExtOpNum(const MachineInstr *MI) const;
00208   int getMinValue(const MachineInstr *MI) const;
00209   int getMaxValue(const MachineInstr *MI) const;
00210   bool NonExtEquivalentExists (const MachineInstr *MI) const;
00211   short getNonExtOpcode(const MachineInstr *MI) const;
00212   bool PredOpcodeHasJMP_c(Opcode_t Opcode) const;
00213   bool PredOpcodeHasNot(Opcode_t Opcode) const;
00214 
00215 private:
00216   int getMatchingCondBranchOpcode(int Opc, bool sense) const;
00217 
00218 };
00219 
00220 }
00221 
00222 #endif

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