llvm::HexagonInstrInfo Class Reference

#include <HexagonInstrInfo.h>

Inheritance diagram for llvm::HexagonInstrInfo:

Collaboration diagram for llvm::HexagonInstrInfo:

List of all members.

Public Member Functions
	HexagonInstrInfo (HexagonSubtarget &ST)
const HexagonRegisterInfo &	getRegisterInfo () const
unsigned	isLoadFromStackSlot (const MachineInstr *MI, int &FrameIndex) const override
unsigned	isStoreToStackSlot (const MachineInstr *MI, int &FrameIndex) const override
bool	AnalyzeBranch (MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override
unsigned	RemoveBranch (MachineBasicBlock &MBB) const override
unsigned	InsertBranch (MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl< MachineOperand > &Cond, DebugLoc DL) const override
bool	analyzeCompare (const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const override
	For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue. Return true if the comparison instruction can be analyzed.
void	copyPhysReg (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override
void	storeRegToStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
void	storeRegToAddr (MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, SmallVectorImpl< MachineInstr * > &NewMIs) const
void	loadRegFromStackSlot (MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override
void	loadRegFromAddr (MachineFunction &MF, unsigned DestReg, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, SmallVectorImpl< MachineInstr * > &NewMIs) const
MachineInstr *	foldMemoryOperandImpl (MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, int FrameIndex) const override
MachineInstr *	foldMemoryOperandImpl (MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, MachineInstr *LoadMI) const override
unsigned	createVR (MachineFunction *MF, MVT VT) const
bool	isBranch (const MachineInstr *MI) const
bool	isPredicable (MachineInstr *MI) const override
bool	PredicateInstruction (MachineInstr *MI, const SmallVectorImpl< MachineOperand > &Cond) const override
bool	isProfitableToIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, unsigned ExtraPredCycles, const BranchProbability &Probability) const override
bool	isProfitableToIfCvt (MachineBasicBlock &TMBB, unsigned NumTCycles, unsigned ExtraTCycles, MachineBasicBlock &FMBB, unsigned NumFCycles, unsigned ExtraFCycles, const BranchProbability &Probability) const override
bool	isPredicated (const MachineInstr *MI) const override
bool	isPredicated (unsigned Opcode) const
bool	isPredicatedTrue (const MachineInstr *MI) const
bool	isPredicatedTrue (unsigned Opcode) const
bool	isPredicatedNew (const MachineInstr *MI) const
bool	isPredicatedNew (unsigned Opcode) const
bool	DefinesPredicate (MachineInstr *MI, std::vector< MachineOperand > &Pred) const override
bool	SubsumesPredicate (const SmallVectorImpl< MachineOperand > &Pred1, const SmallVectorImpl< MachineOperand > &Pred2) const override
bool	ReverseBranchCondition (SmallVectorImpl< MachineOperand > &Cond) const override
bool	isProfitableToDupForIfCvt (MachineBasicBlock &MBB, unsigned NumCycles, const BranchProbability &Probability) const override
DFAPacketizer *	CreateTargetScheduleState (const TargetMachine *TM, const ScheduleDAG *DAG) const override
bool	isSchedulingBoundary (const MachineInstr *MI, const MachineBasicBlock *MBB, const MachineFunction &MF) const override
bool	isValidOffset (const int Opcode, const int Offset) const
bool	isValidAutoIncImm (const EVT VT, const int Offset) const
bool	isMemOp (const MachineInstr *MI) const
bool	isSpillPredRegOp (const MachineInstr *MI) const
bool	isU6_3Immediate (const int value) const
bool	isU6_2Immediate (const int value) const
bool	isU6_1Immediate (const int value) const
bool	isU6_0Immediate (const int value) const
bool	isS4_3Immediate (const int value) const
bool	isS4_2Immediate (const int value) const
bool	isS4_1Immediate (const int value) const
bool	isS4_0Immediate (const int value) const
bool	isS12_Immediate (const int value) const
bool	isU6_Immediate (const int value) const
bool	isS8_Immediate (const int value) const
bool	isS6_Immediate (const int value) const
bool	isSaveCalleeSavedRegsCall (const MachineInstr *MI) const
bool	isConditionalTransfer (const MachineInstr *MI) const
bool	isConditionalALU32 (const MachineInstr *MI) const
bool	isConditionalLoad (const MachineInstr *MI) const
bool	isConditionalStore (const MachineInstr *MI) const
bool	isNewValueInst (const MachineInstr *MI) const
bool	isNewValue (const MachineInstr *MI) const
bool	isDotNewInst (const MachineInstr *MI) const
int	GetDotOldOp (const int opc) const
int	GetDotNewOp (const MachineInstr *MI) const
int	GetDotNewPredOp (MachineInstr *MI, const MachineBranchProbabilityInfo *MBPI) const
bool	mayBeNewStore (const MachineInstr *MI) const
bool	isDeallocRet (const MachineInstr *MI) const
unsigned	getInvertedPredicatedOpcode (const int Opc) const
bool	isExtendable (const MachineInstr *MI) const
bool	isExtended (const MachineInstr *MI) const
bool	isPostIncrement (const MachineInstr *MI) const
bool	isNewValueStore (const MachineInstr *MI) const
bool	isNewValueStore (unsigned Opcode) const
bool	isNewValueJump (const MachineInstr *MI) const
bool	isNewValueJumpCandidate (const MachineInstr *MI) const
void	immediateExtend (MachineInstr *MI) const
bool	isConstExtended (MachineInstr *MI) const
int	getDotNewPredJumpOp (MachineInstr *MI, const MachineBranchProbabilityInfo *MBPI) const
unsigned	getAddrMode (const MachineInstr *MI) const
bool	isOperandExtended (const MachineInstr *MI, unsigned short OperandNum) const
unsigned short	getCExtOpNum (const MachineInstr *MI) const
int	getMinValue (const MachineInstr *MI) const
int	getMaxValue (const MachineInstr *MI) const
bool	NonExtEquivalentExists (const MachineInstr *MI) const
short	getNonExtOpcode (const MachineInstr *MI) const
bool	PredOpcodeHasJMP_c (Opcode_t Opcode) const
bool	PredOpcodeHasNot (Opcode_t Opcode) const

---

Detailed Description

Definition at line 30 of file HexagonInstrInfo.h.

---

Constructor & Destructor Documentation

HexagonInstrInfo::HexagonInstrInfo

(

HexagonSubtarget &

ST

)

[explicit]

Definition at line 64 of file HexagonInstrInfo.cpp.

---

Member Function Documentation

bool HexagonInstrInfo::AnalyzeBranch	(	MachineBasicBlock &	MBB,
		MachineBasicBlock *&	TBB,
		MachineBasicBlock *&	FBB,
		SmallVectorImpl< MachineOperand > &	Cond,
		bool	AllowModify
	)		const [override]

Definition at line 175 of file HexagonInstrInfo.cpp.

References llvm::MachineOperand::CreateImm(), llvm::dbgs(), DEBUG, llvm::MachineInstr::eraseFromParent(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), I, llvm::MachineBasicBlock::instr_begin(), llvm::MachineBasicBlock::instr_end(), llvm::MachineInstr::isBundle(), llvm::MachineBasicBlock::isLayoutSuccessor(), PredOpcodeHasJMP_c(), PredOpcodeHasNot(), and llvm::SmallVectorTemplateBase< T, isPodLike< T >::value >::push_back().

Referenced by InsertBranch().

bool HexagonInstrInfo::analyzeCompare	(	const MachineInstr *	MI,
		unsigned &	SrcReg,
		unsigned &	SrcReg2,
		int &	Mask,
		int &	Value
	)		const [override]

For a comparison instruction, return the source registers in SrcReg and SrcReg2 if having two register operands, and the value it compares against in CmpValue. Return true if the comparison instruction can be analyzed.

Definition at line 342 of file HexagonInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), and llvm::MachineOperand::getReg().

void HexagonInstrInfo::copyPhysReg	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	I,
		DebugLoc	DL,
		unsigned	DestReg,
		unsigned	SrcReg,
		bool	KillSrc
	)		const [override]

Definition at line 416 of file HexagonInstrInfo.cpp.

References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), contains(), llvm::getKillRegState(), and llvm_unreachable.

DFAPacketizer * HexagonInstrInfo::CreateTargetScheduleState	(	const TargetMachine *	TM,
		const ScheduleDAG *	DAG
	)		const [override]

Definition at line 1640 of file HexagonInstrInfo.cpp.

References llvm::TargetSubtargetInfo::getInstrItineraryData(), llvm::TargetMachine::getSubtarget(), and llvm::TargetMachine::getSubtargetImpl().

unsigned HexagonInstrInfo::createVR	(	MachineFunction *	MF,
		MVT	VT
	)		const

Definition at line 566 of file HexagonInstrInfo.cpp.

References llvm::MachineRegisterInfo::createVirtualRegister(), llvm::MVT::f32, llvm::MVT::f64, llvm::MachineFunction::getRegInfo(), llvm::MVT::i1, llvm::MVT::i32, llvm::MVT::i64, and llvm_unreachable.

bool HexagonInstrInfo::DefinesPredicate	(	MachineInstr *	MI,
		std::vector< MachineOperand > &	Pred
	)		const [override]

Definition at line 1036 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isDef(), and llvm::MachineOperand::isReg().

MachineInstr * HexagonInstrInfo::foldMemoryOperandImpl	(	MachineFunction &	MF,
		MachineInstr *	MI,
		const SmallVectorImpl< unsigned > &	Ops,
		int	FrameIndex
	)		const [override]

Definition at line 558 of file HexagonInstrInfo.cpp.

MachineInstr* llvm::HexagonInstrInfo::foldMemoryOperandImpl	(	MachineFunction &	MF,
		MachineInstr *	MI,
		const SmallVectorImpl< unsigned > &	Ops,
		MachineInstr *	LoadMI
	)		const [inline, override]

Definition at line 110 of file HexagonInstrInfo.h.

unsigned HexagonInstrInfo::getAddrMode

(

const MachineInstr *

MI

)

const

Definition at line 1618 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::AddrModeMask, llvm::HexagonII::AddrModePos, F(), llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.

Referenced by getNonExtOpcode(), isPostIncrement(), and NonExtEquivalentExists().

unsigned short HexagonInstrInfo::getCExtOpNum

(

const MachineInstr *

MI

)

const

Definition at line 1755 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::ExtendableOpMask, llvm::HexagonII::ExtendableOpPos, F(), llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.

Referenced by immediateExtend(), and isConstExtended().

int HexagonInstrInfo::GetDotNewOp

(

const MachineInstr *

MI

)

const

Definition at line 1553 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), and llvm_unreachable.

int HexagonInstrInfo::getDotNewPredJumpOp	(	MachineInstr *	MI,
		const MachineBranchProbabilityInfo *	MBPI
	)		const

Definition at line 1717 of file HexagonInstrInfo.cpp.

References llvm::MachineBranchProbabilityInfo::getEdgeProbability(), llvm::MachineOperand::getMBB(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), and llvm_unreachable.

Referenced by GetDotNewPredOp().

int HexagonInstrInfo::GetDotNewPredOp	(	MachineInstr *	MI,
		const MachineBranchProbabilityInfo *	MBPI
	)		const

Definition at line 1581 of file HexagonInstrInfo.cpp.

References getDotNewPredJumpOp(), llvm::MachineInstr::getOpcode(), and llvm_unreachable.

int HexagonInstrInfo::GetDotOldOp

(

const int

opc

)

const

Definition at line 1537 of file HexagonInstrInfo.cpp.

References isNewValueStore(), isPredicated(), and isPredicatedNew().

unsigned HexagonInstrInfo::getInvertedPredicatedOpcode

(

const int

Opc

)

const

Definition at line 733 of file HexagonInstrInfo.cpp.

References isPredicatedTrue(), and llvm_unreachable.

int HexagonInstrInfo::getMaxValue

(

const MachineInstr *

MI

)

const

Definition at line 1775 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::ExtentBitsMask, llvm::HexagonII::ExtentBitsPos, llvm::HexagonII::ExtentSignedMask, llvm::HexagonII::ExtentSignedPos, F(), llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.

Referenced by isConstExtended().

int HexagonInstrInfo::getMinValue

(

const MachineInstr *

MI

)

const

Definition at line 1761 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::ExtentBitsMask, llvm::HexagonII::ExtentBitsPos, llvm::HexagonII::ExtentSignedMask, llvm::HexagonII::ExtentSignedPos, F(), llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::TSFlags.

Referenced by isConstExtended().

short HexagonInstrInfo::getNonExtOpcode

(

const MachineInstr *

MI

)

const

Definition at line 1824 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::Absolute, llvm::HexagonII::BaseImmOffset, getAddrMode(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOpcode(), llvm::MCInstrDesc::mayLoad(), and llvm::MCInstrDesc::mayStore().

const HexagonRegisterInfo& llvm::HexagonInstrInfo::getRegisterInfo

(

)

const [inline]

getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As such, whenever a client has an instance of instruction info, it should always be able to get register info as well (through this method).

Definition at line 43 of file HexagonInstrInfo.h.

Referenced by llvm::HexagonSubtarget::getRegisterInfo(), INITIALIZE_PASS(), isConditionalALU32(), isConditionalLoad(), isConditionalStore(), mayBeNewStore(), and llvm::VirtRegMap::runOnMachineFunction().

void HexagonInstrInfo::immediateExtend

(

MachineInstr *

MI

)

const

immediateExtend - Changes the instruction in place to one using an immediate extender.

Definition at line 1626 of file HexagonInstrInfo.cpp.

References llvm::MachineOperand::addTargetFlag(), getCExtOpNum(), llvm::MachineInstr::getOperand(), llvm::HexagonII::HMOTF_ConstExtended, isConstExtended(), isExtendable(), llvm::MachineOperand::isImm(), and llvm::MachineOperand::isMBB().

Referenced by llvm::HexagonRegisterInfo::eliminateFrameIndex().

unsigned HexagonInstrInfo::InsertBranch	(	MachineBasicBlock &	MBB,
		MachineBasicBlock *	TBB,
		MachineBasicBlock *	FBB,
		const SmallVectorImpl< MachineOperand > &	Cond,
		DebugLoc	DL
	)		const [override]

Definition at line 122 of file HexagonInstrInfo.cpp.

References llvm::MachineInstrBuilder::addMBB(), llvm::MachineInstrBuilder::addReg(), AnalyzeBranch(), llvm::BuildMI(), llvm::SmallVectorBase::empty(), llvm::MachineBasicBlock::getFirstTerminator(), getReg(), isPredicated(), RemoveBranch(), and ReverseBranchCondition().

bool HexagonInstrInfo::isBranch

(

const MachineInstr *

MI

)

const

Definition at line 624 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getDesc(), and llvm::MCInstrDesc::isBranch().

Referenced by isNewValueJump().

bool HexagonInstrInfo::isConditionalALU32

(

const MachineInstr *

MI

)

const

Definition at line 1293 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), getRegisterInfo(), llvm::HexagonSubtarget::hasV4TOps(), and llvm::HexagonRegisterInfo::Subtarget.

bool HexagonInstrInfo::isConditionalLoad

(

const MachineInstr *

MI

)

const

Definition at line 1330 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), getRegisterInfo(), llvm::HexagonSubtarget::hasV4TOps(), and llvm::HexagonRegisterInfo::Subtarget.

bool HexagonInstrInfo::isConditionalStore

(

const MachineInstr *

MI

)

const

Definition at line 1424 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode(), getRegisterInfo(), llvm::HexagonSubtarget::hasV4TOps(), and llvm::HexagonRegisterInfo::Subtarget.

bool HexagonInstrInfo::isConditionalTransfer

(

const MachineInstr *

MI

)

const

Definition at line 1278 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

bool HexagonInstrInfo::isConstExtended

(

MachineInstr *

MI

)

const

Definition at line 1666 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::ExtendableMask, llvm::HexagonII::ExtendablePos, llvm::HexagonII::ExtendedMask, llvm::HexagonII::ExtendedPos, F(), getCExtOpNum(), llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), getMaxValue(), getMinValue(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getTargetFlags(), llvm::HexagonSubtarget::hasV4TOps(), llvm::HexagonII::HMOTF_ConstExtended, isExtendable(), isExtended(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isMBB(), llvm::MachineOperand::isSymbol(), and llvm::MCInstrDesc::TSFlags.

Referenced by llvm::HexagonRegisterInfo::eliminateFrameIndex(), and immediateExtend().

bool HexagonInstrInfo::isDeallocRet

(

const MachineInstr *

MI

)

const

Definition at line 1082 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

bool HexagonInstrInfo::isDotNewInst

(

const MachineInstr *

MI

)

const

Definition at line 1523 of file HexagonInstrInfo.cpp.

References isNewValueInst(), isPredicated(), and isPredicatedNew().

bool HexagonInstrInfo::isExtendable

(

const MachineInstr *

MI

)

const

Definition at line 584 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::ExtendableMask, llvm::HexagonII::ExtendablePos, F(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOpcode(), llvm::HexagonSubtarget::hasV4TOps(), and llvm::MCInstrDesc::TSFlags.

Referenced by immediateExtend(), and isConstExtended().

bool HexagonInstrInfo::isExtended

(

const MachineInstr *

MI

)

const

Definition at line 609 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::ExtendedMask, llvm::HexagonII::ExtendedPos, F(), llvm::MachineInstr::getDesc(), llvm::HexagonII::HMOTF_ConstExtended, I, llvm::MachineInstr::operands_begin(), llvm::MachineInstr::operands_end(), and llvm::MCInstrDesc::TSFlags.

Referenced by isConstExtended().

unsigned HexagonInstrInfo::isLoadFromStackSlot	(	const MachineInstr *	MI,
		int &	FrameIndex
	)		const [override]

isLoadFromStackSlot - If the specified machine instruction is a direct load from a stack slot, return the virtual or physical register number of the destination along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than loading from the stack slot.

Definition at line 75 of file HexagonInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), and llvm::MachineOperand::isImm().

bool HexagonInstrInfo::isMemOp

(

const MachineInstr *

MI

)

const

Definition at line 1218 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

Referenced by llvm::HexagonRegisterInfo::eliminateFrameIndex().

bool HexagonInstrInfo::isNewValue

(

const MachineInstr *

MI

)

const

Definition at line 1516 of file HexagonInstrInfo.cpp.

References F(), llvm::MachineInstr::getDesc(), llvm::HexagonII::NewValueMask, llvm::HexagonII::NewValuePos, and llvm::MCInstrDesc::TSFlags.

Referenced by isNewValueJump().

bool HexagonInstrInfo::isNewValueInst

(

const MachineInstr *

MI

)

const

Definition at line 628 of file HexagonInstrInfo.cpp.

References isNewValueJump(), and isNewValueStore().

Referenced by isDotNewInst().

bool HexagonInstrInfo::isNewValueJump

(

const MachineInstr *

MI

)

const

Definition at line 1506 of file HexagonInstrInfo.cpp.

References isBranch(), and isNewValue().

Referenced by isNewValueInst().

bool HexagonInstrInfo::isNewValueJumpCandidate

(

const MachineInstr *

MI

)

const

Definition at line 1264 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

bool HexagonInstrInfo::isNewValueStore

(

const MachineInstr *

MI

)

const

Definition at line 756 of file HexagonInstrInfo.cpp.

References F(), llvm::MachineInstr::getDesc(), llvm::HexagonII::NVStoreMask, llvm::HexagonII::NVStorePos, and llvm::MCInstrDesc::TSFlags.

Referenced by GetDotOldOp(), and isNewValueInst().

bool HexagonInstrInfo::isNewValueStore

(

unsigned

Opcode

)

const

Definition at line 762 of file HexagonInstrInfo.cpp.

References F(), llvm::HexagonII::NVStoreMask, and llvm::HexagonII::NVStorePos.

bool HexagonInstrInfo::isOperandExtended	(	const MachineInstr *	MI,
		unsigned short	OperandNum
	)		const

Definition at line 1742 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::ExtendableOpMask, llvm::HexagonII::ExtendableOpPos, F(), llvm::MachineInstr::getDesc(), llvm::HexagonSubtarget::hasV4TOps(), and llvm::MCInstrDesc::TSFlags.

bool HexagonInstrInfo::isPostIncrement

(

const MachineInstr *

MI

)

const

Definition at line 1512 of file HexagonInstrInfo.cpp.

References getAddrMode(), and llvm::HexagonII::PostInc.

Referenced by GetPostIncrementOperand().

bool HexagonInstrInfo::isPredicable

(

MachineInstr *

MI

)

const [override]

Definition at line 642 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getDesc(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::HexagonSubtarget::hasV4TOps(), llvm::isInt< 8 >(), llvm::MCInstrDesc::isPredicable(), llvm::AArch64_AM::SXTB, and llvm::AArch64_AM::SXTH.

Referenced by PredicateInstruction().

bool HexagonInstrInfo::isPredicated

(

const MachineInstr *

MI

)

const [override]

Definition at line 982 of file HexagonInstrInfo.cpp.

References F(), llvm::MachineInstr::getDesc(), llvm::HexagonII::PredicatedMask, llvm::HexagonII::PredicatedPos, and llvm::MCInstrDesc::TSFlags.

Referenced by GetDotOldOp(), getPredicatedRegister(), getPredicateSense(), InsertBranch(), isDotNewInst(), isPredicatedNew(), and isPredicatedTrue().

bool HexagonInstrInfo::isPredicated

(

unsigned

Opcode

)

const

Definition at line 988 of file HexagonInstrInfo.cpp.

References F(), llvm::HexagonII::PredicatedMask, and llvm::HexagonII::PredicatedPos.

bool HexagonInstrInfo::isPredicatedNew

(

const MachineInstr *

MI

)

const

Definition at line 1011 of file HexagonInstrInfo.cpp.

References F(), llvm::MachineInstr::getDesc(), isPredicated(), llvm::HexagonII::PredicatedNewMask, llvm::HexagonII::PredicatedNewPos, and llvm::MCInstrDesc::TSFlags.

Referenced by GetDotOldOp(), and isDotNewInst().

bool HexagonInstrInfo::isPredicatedNew

(

unsigned

Opcode

)

const

Definition at line 1018 of file HexagonInstrInfo.cpp.

References F(), isPredicated(), llvm::HexagonII::PredicatedNewMask, and llvm::HexagonII::PredicatedNewPos.

bool HexagonInstrInfo::isPredicatedTrue

(

const MachineInstr *

MI

)

const

Definition at line 994 of file HexagonInstrInfo.cpp.

References F(), llvm::MachineInstr::getDesc(), isPredicated(), llvm::HexagonII::PredicatedFalseMask, llvm::HexagonII::PredicatedFalsePos, and llvm::MCInstrDesc::TSFlags.

Referenced by getInvertedPredicatedOpcode(), and getPredicateSense().

bool HexagonInstrInfo::isPredicatedTrue

(

unsigned

Opcode

)

const

Definition at line 1002 of file HexagonInstrInfo.cpp.

References F(), llvm::HexagonII::PredicatedFalseMask, llvm::HexagonII::PredicatedFalsePos, llvm::HexagonII::PredicatedMask, and llvm::HexagonII::PredicatedPos.

bool HexagonInstrInfo::isProfitableToDupForIfCvt	(	MachineBasicBlock &	MBB,
		unsigned	NumCycles,
		const BranchProbability &	Probability
	)		const [override]

Definition at line 1077 of file HexagonInstrInfo.cpp.

bool HexagonInstrInfo::isProfitableToIfCvt	(	MachineBasicBlock &	MBB,
		unsigned	NumCycles,
		unsigned	ExtraPredCycles,
		const BranchProbability &	Probability
	)		const [override]

Definition at line 956 of file HexagonInstrInfo.cpp.

bool HexagonInstrInfo::isProfitableToIfCvt	(	MachineBasicBlock &	TMBB,
		unsigned	NumTCycles,
		unsigned	ExtraTCycles,
		MachineBasicBlock &	FMBB,
		unsigned	NumFCycles,
		unsigned	ExtraFCycles,
		const BranchProbability &	Probability
	)		const [override]

Definition at line 966 of file HexagonInstrInfo.cpp.

bool llvm::HexagonInstrInfo::isS12_Immediate

(

const int

value

)

const

bool llvm::HexagonInstrInfo::isS4_0Immediate

(

const int

value

)

const

bool llvm::HexagonInstrInfo::isS4_1Immediate

(

const int

value

)

const

bool llvm::HexagonInstrInfo::isS4_2Immediate

(

const int

value

)

const

bool llvm::HexagonInstrInfo::isS4_3Immediate

(

const int

value

)

const

bool llvm::HexagonInstrInfo::isS6_Immediate

(

const int

value

)

const

bool llvm::HexagonInstrInfo::isS8_Immediate

(

const int

value

)

const

bool HexagonInstrInfo::isSaveCalleeSavedRegsCall

(

const MachineInstr *

MI

)

const

Definition at line 638 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

bool HexagonInstrInfo::isSchedulingBoundary	(	const MachineInstr *	MI,
		const MachineBasicBlock *	MBB,
		const MachineFunction &	MF
	)		const [override]

Definition at line 1647 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getDesc(), llvm::MachineInstr::isDebugValue(), llvm::MachineInstr::isInlineAsm(), llvm::MachineInstr::isPosition(), and llvm::MCInstrDesc::isTerminator().

bool HexagonInstrInfo::isSpillPredRegOp

(

const MachineInstr *

MI

)

const

Definition at line 1255 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::getOpcode().

Referenced by llvm::HexagonRegisterInfo::eliminateFrameIndex().

unsigned HexagonInstrInfo::isStoreToStackSlot	(	const MachineInstr *	MI,
		int &	FrameIndex
	)		const [override]

isStoreToStackSlot - If the specified machine instruction is a direct store to a stack slot, return the virtual or physical register number of the source reg along with the FrameIndex of the loaded stack slot. If not, return 0. This predicate must return 0 if the instruction has any side effects other than storing to the stack slot.

Definition at line 102 of file HexagonInstrInfo.cpp.

References llvm::MachineOperand::getImm(), llvm::MachineOperand::getIndex(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineOperand::getReg(), llvm::MachineOperand::isFI(), and llvm::MachineOperand::isImm().

bool llvm::HexagonInstrInfo::isU6_0Immediate

(

const int

value

)

const

bool llvm::HexagonInstrInfo::isU6_1Immediate

(

const int

value

)

const

bool llvm::HexagonInstrInfo::isU6_2Immediate

(

const int

value

)

const

bool llvm::HexagonInstrInfo::isU6_3Immediate

(

const int

value

)

const

bool llvm::HexagonInstrInfo::isU6_Immediate

(

const int

value

)

const

bool HexagonInstrInfo::isValidAutoIncImm	(	const EVT	VT,
		const int	Offset
	)		const

Definition at line 1192 of file HexagonInstrInfo.cpp.

References Hexagon_MEMB_AUTOINC_MAX, Hexagon_MEMB_AUTOINC_MIN, Hexagon_MEMD_AUTOINC_MAX, Hexagon_MEMD_AUTOINC_MIN, Hexagon_MEMH_AUTOINC_MAX, Hexagon_MEMH_AUTOINC_MIN, Hexagon_MEMW_AUTOINC_MAX, Hexagon_MEMW_AUTOINC_MIN, llvm::MVT::i16, llvm::MVT::i32, llvm::MVT::i64, llvm::MVT::i8, and llvm_unreachable.

bool HexagonInstrInfo::isValidOffset	(	const int	Opcode,
		const int	Offset
	)		const

Definition at line 1098 of file HexagonInstrInfo.cpp.

References Hexagon_ADDI_OFFSET_MAX, Hexagon_ADDI_OFFSET_MIN, Hexagon_MEMB_OFFSET_MAX, Hexagon_MEMB_OFFSET_MIN, Hexagon_MEMD_OFFSET_MAX, Hexagon_MEMD_OFFSET_MIN, Hexagon_MEMH_OFFSET_MAX, Hexagon_MEMH_OFFSET_MIN, Hexagon_MEMW_OFFSET_MAX, Hexagon_MEMW_OFFSET_MIN, llvm::ISD::INLINEASM, and llvm_unreachable.

Referenced by llvm::HexagonRegisterInfo::eliminateFrameIndex().

void HexagonInstrInfo::loadRegFromAddr	(	MachineFunction &	MF,
		unsigned	DestReg,
		SmallVectorImpl< MachineOperand > &	Addr,
		const TargetRegisterClass *	RC,
		SmallVectorImpl< MachineInstr * > &	NewMIs
	)		const

Definition at line 550 of file HexagonInstrInfo.cpp.

References llvm_unreachable.

void HexagonInstrInfo::loadRegFromStackSlot	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		unsigned	DestReg,
		int	FrameIndex,
		const TargetRegisterClass *	RC,
		const TargetRegisterInfo *	TRI
	)		const [override]

Definition at line 520 of file HexagonInstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), Align(), llvm::BuildMI(), llvm::MachineBasicBlock::findDebugLoc(), llvm::PseudoSourceValue::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm_unreachable, and llvm::MachineMemOperand::MOLoad.

bool HexagonInstrInfo::mayBeNewStore

(

const MachineInstr *

MI

)

const

Definition at line 1026 of file HexagonInstrInfo.cpp.

References F(), llvm::MachineInstr::getDesc(), getRegisterInfo(), llvm::HexagonSubtarget::hasV4TOps(), llvm::HexagonII::mayNVStoreMask, llvm::HexagonII::mayNVStorePos, llvm::HexagonRegisterInfo::Subtarget, and llvm::MCInstrDesc::TSFlags.

bool HexagonInstrInfo::NonExtEquivalentExists

(

const MachineInstr *

MI

)

const

Definition at line 1790 of file HexagonInstrInfo.cpp.

References llvm::HexagonII::Absolute, llvm::HexagonII::BaseImmOffset, getAddrMode(), llvm::MachineInstr::getDesc(), llvm::MachineInstr::getOpcode(), llvm::MCInstrDesc::mayLoad(), and llvm::MCInstrDesc::mayStore().

bool HexagonInstrInfo::PredicateInstruction	(	MachineInstr *	MI,
		const SmallVectorImpl< MachineOperand > &	Cond
	)		const [override]

Definition at line 805 of file HexagonInstrInfo.cpp.

References llvm::MachineInstr::addOperand(), llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::ChangeToRegister(), llvm::MachineRegisterInfo::clearKillFlags(), llvm::SmallVectorBase::empty(), llvm::MachineOperand::getImm(), llvm::MachineInstr::getNumOperands(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), llvm::MachineFunction::getRegInfo(), llvm::MachineOperand::isDead(), llvm::MachineOperand::isDebug(), llvm::MachineOperand::isDef(), llvm::MachineOperand::isGlobal(), llvm::MachineOperand::isImm(), llvm::MachineOperand::isImplicit(), llvm::MachineOperand::isKill(), isPredicable(), isReg(), llvm::MachineOperand::isReg(), llvm::MachineOperand::isUndef(), llvm::MachineOperand::isUse(), llvm::MachineInstr::RemoveOperand(), and llvm::MachineInstr::setDesc().

bool HexagonInstrInfo::PredOpcodeHasJMP_c

(

Opcode_t

Opcode

)

const

Definition at line 1846 of file HexagonInstrInfo.cpp.

Referenced by AnalyzeBranch().

bool HexagonInstrInfo::PredOpcodeHasNot

(

Opcode_t

Opcode

)

const

Definition at line 1855 of file HexagonInstrInfo.cpp.

Referenced by AnalyzeBranch().

unsigned HexagonInstrInfo::RemoveBranch

(

MachineBasicBlock &

MBB

)

const [override]

Definition at line 310 of file HexagonInstrInfo.cpp.

References llvm::MachineBasicBlock::begin(), llvm::MachineBasicBlock::end(), and I.

Referenced by InsertBranch().

bool HexagonInstrInfo::ReverseBranchCondition

(

SmallVectorImpl< MachineOperand > &

Cond

)

const [override]

Definition at line 1066 of file HexagonInstrInfo.cpp.

References llvm::SmallVectorTemplateCommon< T >::begin(), llvm::MachineOperand::CreateImm(), llvm::SmallVectorBase::empty(), llvm::SmallVectorImpl< T >::erase(), and llvm::SmallVectorImpl< T >::insert().

Referenced by InsertBranch().

void HexagonInstrInfo::storeRegToAddr	(	MachineFunction &	MF,
		unsigned	SrcReg,
		bool	isKill,
		SmallVectorImpl< MachineOperand > &	Addr,
		const TargetRegisterClass *	RC,
		SmallVectorImpl< MachineInstr * > &	NewMIs
	)		const

Definition at line 508 of file HexagonInstrInfo.cpp.

References llvm_unreachable.

void HexagonInstrInfo::storeRegToStackSlot	(	MachineBasicBlock &	MBB,
		MachineBasicBlock::iterator	MBBI,
		unsigned	SrcReg,
		bool	isKill,
		int	FrameIndex,
		const TargetRegisterClass *	RC,
		const TargetRegisterInfo *	TRI
	)		const [override]

Definition at line 473 of file HexagonInstrInfo.cpp.

References llvm::MachineInstrBuilder::addFrameIndex(), llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addMemOperand(), llvm::MachineInstrBuilder::addReg(), Align(), llvm::BuildMI(), llvm::MachineBasicBlock::findDebugLoc(), llvm::PseudoSourceValue::getFixedStack(), llvm::MachineFunction::getFrameInfo(), llvm::getKillRegState(), llvm::MachineFunction::getMachineMemOperand(), llvm::MachineFrameInfo::getObjectAlignment(), llvm::MachineFrameInfo::getObjectSize(), llvm::MachineBasicBlock::getParent(), llvm_unreachable, and llvm::MachineMemOperand::MOStore.

bool HexagonInstrInfo::SubsumesPredicate	(	const SmallVectorImpl< MachineOperand > &	Pred1,
		const SmallVectorImpl< MachineOperand > &	Pred2
	)		const [override]

Definition at line 1054 of file HexagonInstrInfo.cpp.

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The documentation for this class was generated from the following files:

• HexagonInstrInfo.h
• HexagonInstrInfo.cpp