LLVM API Documentation
#include <HexagonRegisterInfo.h>
Public Member Functions | |
HexagonRegisterInfo (HexagonSubtarget &st) | |
const MCPhysReg * | getCalleeSavedRegs (const MachineFunction *MF=nullptr) const override |
Code Generation virtual methods... | |
const TargetRegisterClass *const * | getCalleeSavedRegClasses (const MachineFunction *MF=nullptr) const |
BitVector | getReservedRegs (const MachineFunction &MF) const override |
void | eliminateFrameIndex (MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override |
void | determineFrameLayout (MachineFunction &MF) const |
bool | requiresRegisterScavenging (const MachineFunction &MF) const override |
bool | trackLivenessAfterRegAlloc (const MachineFunction &MF) const override |
unsigned | getRARegister () const |
unsigned | getFrameRegister (const MachineFunction &MF) const override |
unsigned | getFrameRegister () const |
unsigned | getStackRegister () const |
Public Attributes | |
HexagonSubtarget & | Subtarget |
Definition at line 45 of file HexagonRegisterInfo.h.
Definition at line 41 of file HexagonRegisterInfo.cpp.
void llvm::HexagonRegisterInfo::determineFrameLayout | ( | MachineFunction & | MF | ) | const |
determineFrameLayout - Determine the size of the frame and maximum call frame size.
void HexagonRegisterInfo::eliminateFrameIndex | ( | MachineBasicBlock::iterator | II, |
int | SPAdj, | ||
unsigned | FIOperandNum, | ||
RegScavenger * | RS = nullptr |
||
) | const [override] |
Definition at line 118 of file HexagonRegisterInfo.cpp.
References llvm::MachineInstrBuilder::addImm(), llvm::MachineInstrBuilder::addReg(), llvm::BuildMI(), llvm::MachineOperand::ChangeToImmediate(), llvm::MachineOperand::ChangeToRegister(), llvm::HexagonISD::CONST32_Int_Real, llvm::ISD::FrameIndex, llvm::MachineInstr::getDebugLoc(), llvm::MachineFunction::getFrameInfo(), llvm::TargetSubtargetInfo::getFrameLowering(), getFrameRegister(), llvm::MachineOperand::getIndex(), llvm::TargetSubtargetInfo::getInstrInfo(), llvm::MachineFrameInfo::getObjectOffset(), llvm::MachineInstr::getOpcode(), llvm::MachineInstr::getOperand(), llvm::MachineInstr::getParent(), llvm::MachineBasicBlock::getParent(), llvm::MachineOperand::getReg(), getStackRegister(), llvm::MachineFrameInfo::getStackSize(), llvm::MachineFunction::getSubtarget(), llvm::TargetFrameLowering::hasFP(), llvm::HexagonSubtarget::hasV4TOps(), llvm::MachineFrameInfo::hasVarSizedObjects(), HEXAGON_RESERVED_REG_1, Hexagon_WordSize, llvm::HexagonInstrInfo::immediateExtend(), llvm::HexagonInstrInfo::isConstExtended(), llvm::HexagonInstrInfo::isMemOp(), llvm::HexagonInstrInfo::isSpillPredRegOp(), llvm::HexagonInstrInfo::isValidOffset(), llvm_unreachable, llvm::AArch64CC::MI, Subtarget, and TII.
const TargetRegisterClass *const * HexagonRegisterInfo::getCalleeSavedRegClasses | ( | const MachineFunction * | MF = nullptr | ) | const |
Definition at line 90 of file HexagonRegisterInfo.cpp.
References llvm::HexagonSubtarget::getHexagonArchVersion(), llvm_unreachable, Subtarget, llvm::HexagonSubtarget::V1, llvm::HexagonSubtarget::V2, llvm::HexagonSubtarget::V3, llvm::HexagonSubtarget::V4, and llvm::HexagonSubtarget::V5.
const MCPhysReg * HexagonRegisterInfo::getCalleeSavedRegs | ( | const MachineFunction * | MF = nullptr | ) | const [override] |
Code Generation virtual methods...
Definition at line 47 of file HexagonRegisterInfo.cpp.
References llvm::HexagonSubtarget::getHexagonArchVersion(), llvm_unreachable, Subtarget, llvm::HexagonSubtarget::V1, llvm::HexagonSubtarget::V2, llvm::HexagonSubtarget::V3, llvm::HexagonSubtarget::V4, and llvm::HexagonSubtarget::V5.
unsigned HexagonRegisterInfo::getFrameRegister | ( | const MachineFunction & | MF | ) | const [override] |
Definition at line 279 of file HexagonRegisterInfo.cpp.
References llvm::TargetSubtargetInfo::getFrameLowering(), llvm::MachineFunction::getSubtarget(), and llvm::TargetFrameLowering::hasFP().
Referenced by llvm::HexagonTargetLowering::LowerFRAMEADDR().
Definition at line 289 of file HexagonRegisterInfo.cpp.
Referenced by eliminateFrameIndex().
unsigned HexagonRegisterInfo::getRARegister | ( | ) | const |
Definition at line 275 of file HexagonRegisterInfo.cpp.
Referenced by llvm::HexagonTargetLowering::LowerINLINEASM().
BitVector HexagonRegisterInfo::getReservedRegs | ( | const MachineFunction & | MF | ) | const [override] |
Definition at line 71 of file HexagonRegisterInfo.cpp.
References HEXAGON_RESERVED_REG_1, HEXAGON_RESERVED_REG_2, and llvm::BitVector::set().
bool llvm::HexagonRegisterInfo::requiresRegisterScavenging | ( | const MachineFunction & | MF | ) | const [inline, override] |
requiresRegisterScavenging - returns true since we may need scavenging for a temporary register when generating hardware loop instructions.
Definition at line 69 of file HexagonRegisterInfo.h.
bool llvm::HexagonRegisterInfo::trackLivenessAfterRegAlloc | ( | const MachineFunction & | MF | ) | const [inline, override] |
Definition at line 73 of file HexagonRegisterInfo.h.
Definition at line 46 of file HexagonRegisterInfo.h.
Referenced by areCombinableOperations(), eliminateFrameIndex(), getCalleeSavedRegClasses(), getCalleeSavedRegs(), llvm::HexagonInstrInfo::isConditionalALU32(), llvm::HexagonInstrInfo::isConditionalLoad(), llvm::HexagonInstrInfo::isConditionalStore(), and llvm::HexagonInstrInfo::mayBeNewStore().