LLVM API Documentation

VirtRegMap.h
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00001 //===-- llvm/CodeGen/VirtRegMap.h - Virtual Register Map -*- C++ -*--------===//
00002 //
00003 //                     The LLVM Compiler Infrastructure
00004 //
00005 // This file is distributed under the University of Illinois Open Source
00006 // License. See LICENSE.TXT for details.
00007 //
00008 //===----------------------------------------------------------------------===//
00009 //
00010 // This file implements a virtual register map. This maps virtual registers to
00011 // physical registers and virtual registers to stack slots. It is created and
00012 // updated by a register allocator and then used by a machine code rewriter that
00013 // adds spill code and rewrites virtual into physical register references.
00014 //
00015 //===----------------------------------------------------------------------===//
00016 
00017 #ifndef LLVM_CODEGEN_VIRTREGMAP_H
00018 #define LLVM_CODEGEN_VIRTREGMAP_H
00019 
00020 #include "llvm/ADT/IndexedMap.h"
00021 #include "llvm/CodeGen/MachineFunctionPass.h"
00022 #include "llvm/Target/TargetRegisterInfo.h"
00023 
00024 namespace llvm {
00025   class MachineInstr;
00026   class MachineFunction;
00027   class MachineRegisterInfo;
00028   class TargetInstrInfo;
00029   class raw_ostream;
00030   class SlotIndexes;
00031 
00032   class VirtRegMap : public MachineFunctionPass {
00033   public:
00034     enum {
00035       NO_PHYS_REG = 0,
00036       NO_STACK_SLOT = (1L << 30)-1,
00037       MAX_STACK_SLOT = (1L << 18)-1
00038     };
00039 
00040   private:
00041     MachineRegisterInfo *MRI;
00042     const TargetInstrInfo *TII;
00043     const TargetRegisterInfo *TRI;
00044     MachineFunction *MF;
00045 
00046     /// Virt2PhysMap - This is a virtual to physical register
00047     /// mapping. Each virtual register is required to have an entry in
00048     /// it; even spilled virtual registers (the register mapped to a
00049     /// spilled register is the temporary used to load it from the
00050     /// stack).
00051     IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2PhysMap;
00052 
00053     /// Virt2StackSlotMap - This is virtual register to stack slot
00054     /// mapping. Each spilled virtual register has an entry in it
00055     /// which corresponds to the stack slot this register is spilled
00056     /// at.
00057     IndexedMap<int, VirtReg2IndexFunctor> Virt2StackSlotMap;
00058 
00059     /// Virt2SplitMap - This is virtual register to splitted virtual register
00060     /// mapping.
00061     IndexedMap<unsigned, VirtReg2IndexFunctor> Virt2SplitMap;
00062 
00063     /// createSpillSlot - Allocate a spill slot for RC from MFI.
00064     unsigned createSpillSlot(const TargetRegisterClass *RC);
00065 
00066     VirtRegMap(const VirtRegMap&) LLVM_DELETED_FUNCTION;
00067     void operator=(const VirtRegMap&) LLVM_DELETED_FUNCTION;
00068 
00069   public:
00070     static char ID;
00071     VirtRegMap() : MachineFunctionPass(ID), Virt2PhysMap(NO_PHYS_REG),
00072                    Virt2StackSlotMap(NO_STACK_SLOT), Virt2SplitMap(0) { }
00073     bool runOnMachineFunction(MachineFunction &MF) override;
00074 
00075     void getAnalysisUsage(AnalysisUsage &AU) const override {
00076       AU.setPreservesAll();
00077       MachineFunctionPass::getAnalysisUsage(AU);
00078     }
00079 
00080     MachineFunction &getMachineFunction() const {
00081       assert(MF && "getMachineFunction called before runOnMachineFunction");
00082       return *MF;
00083     }
00084 
00085     MachineRegisterInfo &getRegInfo() const { return *MRI; }
00086     const TargetRegisterInfo &getTargetRegInfo() const { return *TRI; }
00087 
00088     void grow();
00089 
00090     /// @brief returns true if the specified virtual register is
00091     /// mapped to a physical register
00092     bool hasPhys(unsigned virtReg) const {
00093       return getPhys(virtReg) != NO_PHYS_REG;
00094     }
00095 
00096     /// @brief returns the physical register mapped to the specified
00097     /// virtual register
00098     unsigned getPhys(unsigned virtReg) const {
00099       assert(TargetRegisterInfo::isVirtualRegister(virtReg));
00100       return Virt2PhysMap[virtReg];
00101     }
00102 
00103     /// @brief creates a mapping for the specified virtual register to
00104     /// the specified physical register
00105     void assignVirt2Phys(unsigned virtReg, unsigned physReg) {
00106       assert(TargetRegisterInfo::isVirtualRegister(virtReg) &&
00107              TargetRegisterInfo::isPhysicalRegister(physReg));
00108       assert(Virt2PhysMap[virtReg] == NO_PHYS_REG &&
00109              "attempt to assign physical register to already mapped "
00110              "virtual register");
00111       Virt2PhysMap[virtReg] = physReg;
00112     }
00113 
00114     /// @brief clears the specified virtual register's, physical
00115     /// register mapping
00116     void clearVirt(unsigned virtReg) {
00117       assert(TargetRegisterInfo::isVirtualRegister(virtReg));
00118       assert(Virt2PhysMap[virtReg] != NO_PHYS_REG &&
00119              "attempt to clear a not assigned virtual register");
00120       Virt2PhysMap[virtReg] = NO_PHYS_REG;
00121     }
00122 
00123     /// @brief clears all virtual to physical register mappings
00124     void clearAllVirt() {
00125       Virt2PhysMap.clear();
00126       grow();
00127     }
00128 
00129     /// @brief returns true if VirtReg is assigned to its preferred physreg.
00130     bool hasPreferredPhys(unsigned VirtReg);
00131 
00132     /// @brief returns true if VirtReg has a known preferred register.
00133     /// This returns false if VirtReg has a preference that is a virtual
00134     /// register that hasn't been assigned yet.
00135     bool hasKnownPreference(unsigned VirtReg);
00136 
00137     /// @brief records virtReg is a split live interval from SReg.
00138     void setIsSplitFromReg(unsigned virtReg, unsigned SReg) {
00139       Virt2SplitMap[virtReg] = SReg;
00140     }
00141 
00142     /// @brief returns the live interval virtReg is split from.
00143     unsigned getPreSplitReg(unsigned virtReg) const {
00144       return Virt2SplitMap[virtReg];
00145     }
00146 
00147     /// getOriginal - Return the original virtual register that VirtReg descends
00148     /// from through splitting.
00149     /// A register that was not created by splitting is its own original.
00150     /// This operation is idempotent.
00151     unsigned getOriginal(unsigned VirtReg) const {
00152       unsigned Orig = getPreSplitReg(VirtReg);
00153       return Orig ? Orig : VirtReg;
00154     }
00155 
00156     /// @brief returns true if the specified virtual register is not
00157     /// mapped to a stack slot or rematerialized.
00158     bool isAssignedReg(unsigned virtReg) const {
00159       if (getStackSlot(virtReg) == NO_STACK_SLOT)
00160         return true;
00161       // Split register can be assigned a physical register as well as a
00162       // stack slot or remat id.
00163       return (Virt2SplitMap[virtReg] && Virt2PhysMap[virtReg] != NO_PHYS_REG);
00164     }
00165 
00166     /// @brief returns the stack slot mapped to the specified virtual
00167     /// register
00168     int getStackSlot(unsigned virtReg) const {
00169       assert(TargetRegisterInfo::isVirtualRegister(virtReg));
00170       return Virt2StackSlotMap[virtReg];
00171     }
00172 
00173     /// @brief create a mapping for the specifed virtual register to
00174     /// the next available stack slot
00175     int assignVirt2StackSlot(unsigned virtReg);
00176     /// @brief create a mapping for the specified virtual register to
00177     /// the specified stack slot
00178     void assignVirt2StackSlot(unsigned virtReg, int frameIndex);
00179 
00180     void print(raw_ostream &OS, const Module* M = nullptr) const override;
00181     void dump() const;
00182   };
00183 
00184   inline raw_ostream &operator<<(raw_ostream &OS, const VirtRegMap &VRM) {
00185     VRM.print(OS);
00186     return OS;
00187   }
00188 } // End llvm namespace
00189 
00190 #endif