llvm::final< T > Member List

This is the complete list of members for llvm::final< T >, including all inherited members.

addAnalysisPasses(PassManagerBase &PM) override	llvm::final< T >	[virtual]
addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth)	llvm::TargetLoweringBase	[inline, protected]
addPassesToEmitFile(PassManagerBase &PM, formatted_raw_ostream &Out, CodeGenFileType FileType, bool DisableVerify=true, AnalysisID StartAfter=nullptr, AnalysisID StopAfter=nullptr) override	llvm::LLVMTargetMachine	[virtual]
addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx, raw_ostream &OS, bool DisableVerify=true) override	llvm::LLVMTargetMachine	[virtual]
AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT)	llvm::TargetLoweringBase	[inline, protected]
addRegisterClass(MVT VT, const TargetRegisterClass *RC)	llvm::TargetLoweringBase	[inline, protected]
AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const	llvm::TargetLowering	[virtual]
allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align, bool *Fast) const override	llvm::final< T >	[virtual]
allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override	llvm::final< T >	[virtual]
AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl< MachineOperand > &Cond, bool AllowModify) const override	llvm::final< T >
analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const override	llvm::final< T >
append(in_iter in_start, in_iter in_end)	llvm::SmallVectorImpl< std::unique_ptr< UnitType > >	[inline]
append(size_type NumInputs, const std::unique_ptr< UnitType > &Elt)	llvm::SmallVectorImpl< std::unique_ptr< UnitType > >	[inline]
areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1, int64_t &Offset2) const override	llvm::final< T >
ArgListTy typedef	llvm::TargetLowering
AsmInfo	llvm::TargetMachine	[protected]
AsmOperandInfoVector typedef	llvm::TargetLowering
assign(unsigned NumElts, const std::unique_ptr< UnitType > &Elt)	llvm::SmallVectorImpl< std::unique_ptr< UnitType > >	[inline]
assignPassManager(PMStack &PMS, PassManagerType T) override	llvm::FunctionPass	[virtual]
AvailableFeatures	llvm::MCInstPrinter	[protected]
AVX enum value	llvm::final< T >	[protected]
AVX2 enum value	llvm::final< T >	[protected]
AVX512F enum value	llvm::final< T >	[protected]
back()	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >	[inline]
back() const	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >	[inline]
begin()	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >	[inline]
begin() const	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >	[inline]
BeginX	llvm::SmallVectorBase	[protected]
BooleanContent enum name	llvm::TargetLoweringBase
breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override	llvm::final< T >
BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl, SelectionDAG &DAG) const	llvm::TargetLowering
BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, SelectionDAG &DAG) const	llvm::final< T >
BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const	llvm::TargetLowering
BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, std::vector< SDNode * > *Created) const	llvm::TargetLowering	[inline, virtual]
BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, bool IsAfterLegalization, std::vector< SDNode * > *Created) const	llvm::TargetLowering
C_Memory enum value	llvm::TargetLowering
C_Other enum value	llvm::TargetLowering
C_Register enum value	llvm::TargetLowering
C_RegisterClass enum value	llvm::TargetLowering
C_Unknown enum value	llvm::TargetLowering
CallRegIndirect	llvm::final< T >	[protected]
callRegIndirect() const	llvm::final< T >	[inline]
canFoldMemoryOperand(const MachineInstr *, const SmallVectorImpl< unsigned > &) const override	llvm::final< T >
canInsertSelect(const MachineBasicBlock &, const SmallVectorImpl< MachineOperand > &Cond, unsigned, unsigned, int &, int &, int &) const override	llvm::final< T >
canOpTrap(unsigned Op, EVT VT) const	llvm::TargetLoweringBase	[virtual]
canRealignStack(const MachineFunction &MF) const	llvm::final< T >
capacity() const	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >	[inline]
capacity_in_bytes() const	llvm::SmallVectorBase	[inline]
capacity_ptr()	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >	[inline, protected]
capacity_ptr() const	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >	[inline, protected]
CapacityX	llvm::SmallVectorBase	[protected]
CGFT_AssemblyFile enum value	llvm::TargetMachine
CGFT_Null enum value	llvm::TargetMachine
CGFT_ObjectFile enum value	llvm::TargetMachine
ClassifyBlockAddressReference() const	llvm::final< T >
ClassifyGlobalReference(const GlobalValue *GV, const TargetMachine &TM) const	llvm::final< T >
classifyLEAReg(MachineInstr *MI, const MachineOperand &Src, unsigned LEAOpcode, bool AllowSP, unsigned &NewSrc, bool &isKill, bool &isUndef, MachineOperand &ImplicitOp) const	llvm::final< T >
clear()	llvm::SmallVectorImpl< std::unique_ptr< UnitType > >	[inline]
clearOperationActions()	llvm::TargetLoweringBase	[inline, protected]
clearRegisterClasses()	llvm::TargetLoweringBase	[inline, protected]
CodeGenFileType enum name	llvm::TargetMachine
CodeGenInfo	llvm::TargetMachine	[protected]
CommentStream	llvm::MCInstPrinter	[protected]
commuteInstruction(MachineInstr *MI, bool NewMI) const override	llvm::final< T >
ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const	llvm::TargetLowering	[virtual]
computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth=0) const override	llvm::final< T >	[virtual]
ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG, unsigned Depth) const override	llvm::final< T >	[virtual]
computeRegisterProperties()	llvm::TargetLoweringBase	[protected]
const_iterator typedef	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >
const_pointer typedef	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >
const_reference typedef	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >
const_reverse_iterator typedef	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >
ConstraintType enum name	llvm::TargetLowering
ConstraintWeight enum name	llvm::TargetLowering
convertToThreeAddress(MachineFunction::iterator &MFI, MachineBasicBlock::iterator &MBBI, LiveVariables *LV) const override	llvm::final< T >
copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const override	llvm::final< T >
createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const override	llvm::final< T >	[virtual]
createPass(AnalysisID ID)	llvm::Pass	[static]
createPassConfig(PassManagerBase &PM) override	llvm::final< T >	[virtual]
createPrinterPass(raw_ostream &O, const std::string &Banner) const override	llvm::FunctionPass	[virtual]
Custom enum value	llvm::TargetLoweringBase
CW_Best enum value	llvm::TargetLowering
CW_Better enum value	llvm::TargetLowering
CW_Constant enum value	llvm::TargetLowering
CW_Default enum value	llvm::TargetLowering
CW_Good enum value	llvm::TargetLowering
CW_Invalid enum value	llvm::TargetLowering
CW_Memory enum value	llvm::TargetLowering
CW_Okay enum value	llvm::TargetLowering
CW_Register enum value	llvm::TargetLowering
CW_SpecificReg enum value	llvm::TargetLowering
data()	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >	[inline]
data() const	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >	[inline]
destroy_range(std::unique_ptr< UnitType > *S, std::unique_ptr< UnitType > *E)	llvm::SmallVectorTemplateBase< std::unique_ptr< UnitType >, isPodLike< std::unique_ptr< UnitType > >::value >	[inline, protected, static]
difference_type typedef	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >
doFinalization(Module &)	llvm::Pass	[inline, virtual]
doInitialization(Module &)	llvm::Pass	[inline, virtual]
dump() const	llvm::Pass
dumpPassStructure(unsigned Offset=0)	llvm::Pass	[virtual]
eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, unsigned FIOperandNum, RegScavenger *RS=nullptr) const override	llvm::final< T >
EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const override	llvm::final< T >	[virtual]
emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord, bool IsStore, bool IsLoad) const	llvm::TargetLoweringBase	[inline, virtual]
emitLoadLinked(IRBuilder<> &Builder, Value *Addr, AtomicOrdering Ord) const	llvm::TargetLoweringBase	[inline, virtual]
emitPatchPoint(MachineInstr *MI, MachineBasicBlock *MBB) const	llvm::TargetLoweringBase	[protected]
emitStoreConditional(IRBuilder<> &Builder, Value *Val, Value *Addr, AtomicOrdering Ord) const	llvm::TargetLoweringBase	[inline, virtual]
emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord, bool IsStore, bool IsLoad) const	llvm::TargetLoweringBase	[inline, virtual]
empty() const	llvm::SmallVectorBase	[inline]
enableEarlyIfConversion() const override	llvm::final< T >
enableMachineScheduler() const override	llvm::final< T >	[inline]
end()	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >	[inline]
end() const	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >	[inline]
EndX	llvm::SmallVectorBase	[protected]
erase(iterator I)	llvm::SmallVectorImpl< std::unique_ptr< UnitType > >	[inline]
erase(iterator S, iterator E)	llvm::SmallVectorImpl< std::unique_ptr< UnitType > >	[inline]
Expand enum value	llvm::TargetLoweringBase
expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const	llvm::TargetLowering
ExpandInlineAsm(CallInst *CI) const override	llvm::final< T >	[virtual]
expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT, SelectionDAG &DAG, SDValue LL=SDValue(), SDValue LH=SDValue(), SDValue RL=SDValue(), SDValue RH=SDValue()) const	llvm::TargetLowering
expandPostRAPseudo(MachineBasicBlock::iterator MI) const override	llvm::final< T >
findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override	llvm::final< T >
findRepresentativeClass(MVT VT) const override	llvm::final< T >	[protected, virtual]
Fmt	llvm::format_object_base	[protected]
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, int FrameIndex) const override	llvm::final< T >
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl< unsigned > &Ops, MachineInstr *LoadMI) const override	llvm::final< T >
foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, unsigned OpNum, const SmallVectorImpl< MachineOperand > &MOs, unsigned Size, unsigned Alignment) const	llvm::final< T >
format_object1(const char *fmt, const T &val)	llvm::final< T >	[inline]
format_object2(const char *fmt, const T1 &val1, const T2 &val2)	llvm::final< T >	[inline]
format_object3(const char *fmt, const T1 &val1, const T2 &val2, const T3 &val3)	llvm::final< T >	[inline]
format_object4(const char *fmt, const T1 &val1, const T2 &val2, const T3 &val3, const T4 &val4)	llvm::final< T >	[inline]
format_object5(const char *fmt, const T1 &val1, const T2 &val2, const T3 &val3, const T4 &val4, const T5 &val5)	llvm::final< T >	[inline]
format_object6(const char *Fmt, const T1 &Val1, const T2 &Val2, const T3 &Val3, const T4 &Val4, const T5 &Val5, const T6 &Val6)	llvm::final< T >	[inline]
format_object_base(const char *fmt)	llvm::format_object_base	[inline]
formatDec(const int64_t Value) const	llvm::MCInstPrinter
formatHex(const int64_t Value) const	llvm::MCInstPrinter
formatHex(const uint64_t Value) const	llvm::MCInstPrinter
formatImm(const int64_t Value) const	llvm::MCInstPrinter	[inline]
front()	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >	[inline]
front() const	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >	[inline]
functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg) const	llvm::TargetLowering	[inline, virtual]
FunctionPass(char &pid)	llvm::FunctionPass	[inline, explicit]
FunctionTargetTransformInfo()	llvm::final< T >
GetAddrModeArguments(IntrinsicInst *, SmallVectorImpl< Value * > &, Type *&) const	llvm::TargetLoweringBase	[inline, virtual]
getAdjustedAnalysisPointer(AnalysisID ID)	llvm::Pass	[virtual]
getAnalysis() const	llvm::Pass
getAnalysis(Function &F)	llvm::Pass
getAnalysisID(AnalysisID PI) const	llvm::Pass
getAnalysisID(AnalysisID PI, Function &F)	llvm::Pass
getAnalysisIfAvailable() const	llvm::Pass
getAnalysisUsage(AnalysisUsage &AU) const override	llvm::final< T >	[virtual]
getAntiDepBreakMode() const override	llvm::final< T >	[inline]
getAsImmutablePass()	llvm::Pass	[virtual]
getAsmVerbosityDefault() const	llvm::TargetMachine
getAsPMDataManager()	llvm::Pass	[virtual]
getAvailableFeatures() const	llvm::MCInstPrinter	[inline]
getBaseRegister() const	llvm::final< T >	[inline]
getBooleanContents(bool isVec, bool isFloat) const	llvm::TargetLoweringBase	[inline]
getBooleanContents(EVT Type) const	llvm::TargetLoweringBase	[inline]
getBypassSlowDivWidths() const	llvm::TargetLoweringBase	[inline]
getByValTypeAlignment(Type *Ty) const override	llvm::final< T >	[virtual]
getBZeroEntry() const	llvm::final< T >
getCalleeSavedRegs(const MachineFunction *MF) const override	llvm::final< T >
getCallPreservedMask(CallingConv::ID) const override	llvm::final< T >
getClearCacheBuiltinName() const override	llvm::final< T >	[inline, virtual]
getCmpLibcallCC(RTLIB::Libcall Call) const	llvm::TargetLoweringBase	[inline]
getCmpLibcallReturnType() const	llvm::TargetLoweringBase	[virtual]
getCodeModel() const	llvm::TargetMachine
getCondCodeAction(ISD::CondCode CC, MVT VT) const	llvm::TargetLoweringBase	[inline]
getConstraintType(const std::string &Constraint) const override	llvm::final< T >	[virtual]
getCrossCopyRegClass(const TargetRegisterClass *RC) const override	llvm::final< T >
getDataLayout() const override	llvm::final< T >	[inline]
getDataSections() const	llvm::TargetMachine
getExceptionPointerRegister() const	llvm::TargetLoweringBase	[inline]
getExceptionSelectorRegister() const	llvm::TargetLoweringBase	[inline]
getExecutionDomain(const MachineInstr *MI) const override	llvm::final< T >
getExtendForContent(BooleanContent Content)	llvm::TargetLoweringBase	[inline, static]
getFrameLowering() const override	llvm::final< T >	[inline]
getFrameRegister(const MachineFunction &MF) const override	llvm::final< T >
getFunctionSections() const	llvm::TargetMachine
getGlobalBaseReg(MachineFunction *MF) const	llvm::final< T >
getIndexedLoadAction(unsigned IdxMode, MVT VT) const	llvm::TargetLoweringBase	[inline]
getIndexedStoreAction(unsigned IdxMode, MVT VT) const	llvm::TargetLoweringBase	[inline]
getInsertFencesForAtomic() const	llvm::TargetLoweringBase	[inline]
getInstrInfo() const override	llvm::final< T >	[inline]
getInstrItineraryData() const override	llvm::final< T >	[inline]
getIntrinsicInfo() const	llvm::TargetMachine	[inline, virtual]
getJumpBufAlignment() const	llvm::TargetLoweringBase	[inline]
getJumpBufSize() const	llvm::TargetLoweringBase	[inline]
getJumpTableEncoding() const override	llvm::final< T >	[virtual]
getLargestLegalSuperClass(const TargetRegisterClass *RC) const override	llvm::final< T >
getLibcallCallingConv(RTLIB::Libcall Call) const	llvm::TargetLoweringBase	[inline]
getLibcallName(RTLIB::Libcall Call) const	llvm::TargetLoweringBase	[inline]
getLoadExtAction(unsigned ExtType, EVT VT) const	llvm::TargetLoweringBase	[inline]
getMatchingSuperRegClass(const TargetRegisterClass *A, const TargetRegisterClass *B, unsigned Idx) const override	llvm::final< T >
getMaximalGlobalOffset() const	llvm::TargetLoweringBase	[inline, virtual]
getMaxInlineSizeThreshold() const	llvm::final< T >	[inline]
getMaxStoresPerMemcpy(bool OptSize) const	llvm::TargetLoweringBase	[inline]
getMaxStoresPerMemmove(bool OptSize) const	llvm::TargetLoweringBase	[inline]
getMaxStoresPerMemset(bool OptSize) const	llvm::TargetLoweringBase	[inline]
getMCAsmInfo() const	llvm::TargetMachine	[inline]
getMinFunctionAlignment() const	llvm::TargetLoweringBase	[inline]
getMinimumJumpTableEntries() const	llvm::TargetLoweringBase	[inline]
getMinStackArgumentAlignment() const	llvm::TargetLoweringBase	[inline]
getMultipleConstraintMatchWeight(AsmOperandInfo &info, int maIndex) const	llvm::TargetLowering	[virtual]
getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV, Mangler &Mang, bool MayAlwaysUsePrivate=false) const	llvm::TargetMachine
getNoopForMachoTarget(MCInst &NopInst) const override	llvm::final< T >
getNoPreservedMask() const	llvm::final< T >
getNumRegisters(LLVMContext &Context, EVT VT) const	llvm::TargetLoweringBase	[inline]
getObjFileLowering() const	llvm::TargetLoweringBase	[inline]
getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, unsigned *LoadRegIndex=nullptr) const override	llvm::final< T >
getOpcodeName(unsigned Opcode) const	llvm::MCInstPrinter
getOperationAction(unsigned Op, EVT VT) const	llvm::TargetLoweringBase	[inline]
getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, MachineFunction &MF) const override	llvm::final< T >	[virtual]
getOptLevel() const	llvm::TargetMachine
getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, const TargetRegisterInfo *TRI) const override	llvm::final< T >
getPassID() const	llvm::Pass	[inline]
getPassKind() const	llvm::Pass	[inline]
getPassName() const	llvm::Pass	[virtual]
getPICJumpTableRelocBase(SDValue Table, SelectionDAG &DAG) const override	llvm::final< T >	[virtual]
getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const override	llvm::final< T >	[virtual]
getPICStyle() const	llvm::final< T >	[inline]
getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override	llvm::final< T >
getPointerSizeInBits(uint32_t AS=0) const	llvm::TargetLoweringBase
getPointerTy(uint32_t=0) const	llvm::TargetLoweringBase	[virtual]
getPointerTypeSizeInBits(Type *Ty) const	llvm::TargetLoweringBase
getPostIndexedAddressParts(SDNode *, SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const	llvm::TargetLowering	[inline, virtual]
getPotentialPassManagerType() const override	llvm::FunctionPass	[virtual]
getPreferredVectorAction(EVT VT) const override	llvm::final< T >	[virtual]
getPrefFunctionAlignment() const	llvm::TargetLoweringBase	[inline]
getPrefLoopAlignment() const	llvm::TargetLoweringBase	[inline]
getPreIndexedAddressParts(SDNode *, SDValue &, SDValue &, ISD::MemIndexedMode &, SelectionDAG &) const	llvm::TargetLowering	[inline, virtual]
getPrintHexStyleHex() const	llvm::MCInstPrinter	[inline]
getPrintImmHex() const	llvm::MCInstPrinter	[inline]
getRegClassFor(MVT VT) const	llvm::TargetLoweringBase	[inline, virtual]
getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const override	llvm::final< T >	[virtual]
getRegisterByName(const char *RegName, EVT VT) const override	llvm::final< T >	[virtual]
getRegisterInfo() const	llvm::final< T >	[inline]
getRegisterInfo() const override	llvm::final< T >	[inline]
getRegisterName(unsigned RegNo)	llvm::final< T >	[static]
getRegisterName(unsigned RegNo)	llvm::final< T >	[static]
getRegisterType(MVT VT) const	llvm::TargetLoweringBase	[inline]
getRegisterType(LLVMContext &Context, EVT VT) const	llvm::TargetLoweringBase	[inline]
getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const override	llvm::final< T >
getRelocationModel() const	llvm::TargetMachine
getRepRegClassCostFor(MVT VT) const	llvm::TargetLoweringBase	[inline, virtual]
getRepRegClassFor(MVT VT) const	llvm::TargetLoweringBase	[inline, virtual]
getReservedRegs(const MachineFunction &MF) const override	llvm::final< T >
getResolver() const	llvm::Pass	[inline]
getReturnAddressFrameIndex(SelectionDAG &DAG) const	llvm::final< T >
getScalarShiftAmountTy(EVT LHSTy) const override	llvm::final< T >	[inline, virtual]
getScalingFactorCost(const AddrMode &AM, Type *Ty) const override	llvm::final< T >	[virtual]
getSchedulingPreference() const	llvm::TargetLoweringBase	[inline]
getSchedulingPreference(SDNode *) const	llvm::TargetLoweringBase	[inline, virtual]
getSEHRegNum(unsigned i) const	llvm::final< T >
getSelectionDAGInfo() const override	llvm::final< T >	[inline]
getSetCCResultType(LLVMContext &Context, EVT VT) const override	llvm::final< T >	[virtual]
getShiftAmountTy(EVT LHSTy) const	llvm::TargetLoweringBase
getSimpleValueType(Type *Ty, bool AllowUnknown=false) const	llvm::TargetLoweringBase	[inline]
getSingleConstraintMatchWeight(AsmOperandInfo &info, const char *constraint) const override	llvm::final< T >	[virtual]
getSlotSize() const	llvm::final< T >	[inline]
getStackAlignment() const	llvm::final< T >	[inline]
getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const override	llvm::final< T >	[virtual]
getStackPointerRegisterToSaveRestore() const	llvm::TargetLoweringBase	[inline]
getStackRegister() const	llvm::final< T >	[inline]
getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const override	llvm::final< T >
getSubtarget() const	llvm::final< T >	[inline]
llvm::LLVMTargetMachine::getSubtarget(const Function *) const	llvm::TargetMachine	[inline]
getSubtargetImpl() const override	llvm::final< T >	[inline, virtual]
llvm::LLVMTargetMachine::getSubtargetImpl(const Function *) const	llvm::TargetMachine	[inline, virtual]
getSymbol(const GlobalValue *GV, Mangler &Mang) const	llvm::TargetMachine
getTarget() const	llvm::TargetMachine	[inline]
getTargetCPU() const	llvm::TargetMachine	[inline]
getTargetFeatureString() const	llvm::TargetMachine	[inline]
getTargetLowering() const override	llvm::final< T >	[inline]
getTargetMachine() const	llvm::TargetLoweringBase	[inline]
getTargetNodeName(unsigned Opcode) const override	llvm::final< T >	[virtual]
getTargetTriple() const	llvm::final< T >	[inline]
getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, unsigned) const	llvm::TargetLoweringBase	[inline, virtual]
getTLSModel(const GlobalValue *GV) const	llvm::TargetMachine
getTrap(MCInst &MI) const override	llvm::final< T >
getTruncStoreAction(EVT ValVT, EVT MemVT) const	llvm::TargetLoweringBase	[inline]
getTypeAction(LLVMContext &Context, EVT VT) const	llvm::TargetLoweringBase	[inline]
getTypeAction(MVT VT) const	llvm::TargetLoweringBase	[inline]
getTypeConversion(LLVMContext &Context, EVT VT) const	llvm::TargetLoweringBase	[inline]
getTypeLegalizationCost(Type *Ty) const	llvm::TargetLoweringBase
getTypeToExpandTo(LLVMContext &Context, EVT VT) const	llvm::TargetLoweringBase	[inline]
getTypeToPromoteTo(unsigned Op, MVT VT) const	llvm::TargetLoweringBase	[inline]
getTypeToTransformTo(LLVMContext &Context, EVT VT) const	llvm::TargetLoweringBase	[inline]
getUnconditionalBranch(MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const override	llvm::final< T >
getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum, const TargetRegisterInfo *TRI) const override	llvm::final< T >
getUnitForOffset(uint32_t Offset) const	llvm::final< T >	[inline, virtual]
getUnrollingPreferences(Loop *L, TargetTransformInfo::UnrollingPreferences &UP) const	llvm::final< T >	[inline]
getUseMarkup() const	llvm::MCInstPrinter	[inline]
getValueType(Type *Ty, bool AllowUnknown=false) const	llvm::TargetLoweringBase	[inline]
getValueTypeActions() const	llvm::TargetLoweringBase	[inline]
getVectorIdxTy() const	llvm::TargetLoweringBase	[inline, virtual]
getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const	llvm::TargetLoweringBase
grow(size_t MinSize=0)	llvm::SmallVectorTemplateBase< std::unique_ptr< UnitType >, isPodLike< std::unique_ptr< UnitType > >::value >	[protected]
grow_pod(size_t MinSizeInBytes, size_t TSize)	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >	[inline, protected]
llvm::SmallVectorBase::grow_pod(void *FirstEl, size_t MinSizeInBytes, size_t TSize)	llvm::SmallVectorBase	[protected]
HandleByVal(CCState *, unsigned &, unsigned) const	llvm::TargetLowering	[inline, virtual]
has3DNow() const	llvm::final< T >	[inline]
has3DNowA() const	llvm::final< T >	[inline]
HasADX	llvm::final< T >	[protected]
hasADX() const	llvm::final< T >	[inline]
HasAES	llvm::final< T >	[protected]
hasAES() const	llvm::final< T >	[inline]
hasAVX() const	llvm::final< T >	[inline]
hasAVX2() const	llvm::final< T >	[inline]
hasAVX512() const	llvm::final< T >	[inline]
hasBasePointer(const MachineFunction &MF) const	llvm::final< T >
hasBigEndianPartOrdering(EVT VT) const	llvm::TargetLoweringBase	[inline]
hasBMI() const	llvm::final< T >	[inline]
HasBMI	llvm::final< T >	[protected]
hasBMI2() const	llvm::final< T >	[inline]
HasBMI2	llvm::final< T >	[protected]
HasBWI	llvm::final< T >	[protected]
hasBWI() const	llvm::final< T >	[inline]
HasCDI	llvm::final< T >	[protected]
hasCDI() const	llvm::final< T >	[inline]
HasCMov	llvm::final< T >	[protected]
hasCMov() const	llvm::final< T >	[inline]
HasCmpxchg16b	llvm::final< T >	[protected]
hasCmpxchg16b() const	llvm::final< T >	[inline]
HasDQI	llvm::final< T >	[protected]
hasDQI() const	llvm::final< T >	[inline]
HasERI	llvm::final< T >	[protected]
hasERI() const	llvm::final< T >	[inline]
hasExtractBitsInsn() const	llvm::TargetLoweringBase	[inline]
hasF16C() const	llvm::final< T >	[inline]
HasF16C	llvm::final< T >	[protected]
hasFloatingPointExceptions() const	llvm::TargetLoweringBase	[inline]
HasFMA	llvm::final< T >	[protected]
hasFMA() const	llvm::final< T >	[inline]
hasFMA4() const	llvm::final< T >	[inline]
HasFMA4	llvm::final< T >	[protected]
hasFp256() const	llvm::final< T >	[inline]
HasFSGSBase	llvm::final< T >	[protected]
hasFSGSBase() const	llvm::final< T >	[inline]
hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const override	llvm::final< T >
hasHLE() const	llvm::final< T >	[inline]
HasHLE	llvm::final< T >	[protected]
hasInt256() const	llvm::final< T >	[inline]
hasLoadLinkedStoreConditional() const	llvm::TargetLoweringBase	[inline, virtual]
HasLZCNT	llvm::final< T >	[protected]
hasLZCNT() const	llvm::final< T >	[inline]
hasMMX() const	llvm::final< T >	[inline]
hasMOVBE() const	llvm::final< T >	[inline]
HasMOVBE	llvm::final< T >	[protected]
hasMultipleConditionRegisters() const	llvm::TargetLoweringBase	[inline]
hasPairedLoad(Type *, unsigned &) const	llvm::TargetLoweringBase	[inline, virtual]
hasPairedLoad(EVT, unsigned &) const	llvm::TargetLoweringBase	[inline, virtual]
HasPCLMUL	llvm::final< T >	[protected]
hasPCLMUL() const	llvm::final< T >	[inline]
hasPFI() const	llvm::final< T >	[inline]
HasPFI	llvm::final< T >	[protected]
HasPOPCNT	llvm::final< T >	[protected]
hasPOPCNT() const	llvm::final< T >	[inline]
HasPRFCHW	llvm::final< T >	[protected]
hasPRFCHW() const	llvm::final< T >	[inline]
hasRDRAND() const	llvm::final< T >	[inline]
HasRDRAND	llvm::final< T >	[protected]
HasRDSEED	llvm::final< T >	[protected]
hasRDSEED() const	llvm::final< T >	[inline]
hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const override	llvm::final< T >
hasRTM() const	llvm::final< T >	[inline]
HasRTM	llvm::final< T >	[protected]
HasSGX	llvm::final< T >	[protected]
hasSGX() const	llvm::final< T >	[inline]
hasSHA() const	llvm::final< T >	[inline]
HasSHA	llvm::final< T >	[protected]
hasSinCos() const	llvm::final< T >
HasSlowDivide	llvm::final< T >	[protected]
hasSlowDivide() const	llvm::final< T >	[inline]
HasSMAP	llvm::final< T >	[protected]
hasSMAP() const	llvm::final< T >	[inline]
hasSSE1() const	llvm::final< T >	[inline]
hasSSE2() const	llvm::final< T >	[inline]
hasSSE3() const	llvm::final< T >	[inline]
hasSSE41() const	llvm::final< T >	[inline]
hasSSE42() const	llvm::final< T >	[inline]
HasSSE4A	llvm::final< T >	[protected]
hasSSE4A() const	llvm::final< T >	[inline]
hasSSSE3() const	llvm::final< T >	[inline]
hasTargetDAGCombine(ISD::NodeType NT) const	llvm::TargetLoweringBase	[inline]
HasTBM	llvm::final< T >	[protected]
hasTBM() const	llvm::final< T >	[inline]
HasVectorUAMem	llvm::final< T >	[protected]
hasVectorUAMem() const	llvm::final< T >	[inline]
hasVLX() const	llvm::final< T >	[inline]
HasVLX	llvm::final< T >	[protected]
HasX86_64	llvm::final< T >	[protected]
HasXOP	llvm::final< T >	[protected]
hasXOP() const	llvm::final< T >	[inline]
home()	llvm::format_object_base	[protected, virtual]
ID	llvm::final< T >	[static]
initActions()	llvm::TargetLoweringBase	[protected]
initAsmInfo()	llvm::LLVMTargetMachine	[protected]
insert(iterator I, std::unique_ptr< UnitType > &&Elt)	llvm::SmallVectorImpl< std::unique_ptr< UnitType > >	[inline]
insert(iterator I, const std::unique_ptr< UnitType > &Elt)	llvm::SmallVectorImpl< std::unique_ptr< UnitType > >	[inline]
insert(iterator I, size_type NumToInsert, const std::unique_ptr< UnitType > &Elt)	llvm::SmallVectorImpl< std::unique_ptr< UnitType > >	[inline]
insert(iterator I, ItTy From, ItTy To)	llvm::SmallVectorImpl< std::unique_ptr< UnitType > >	[inline]
InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl< MachineOperand > &Cond, DebugLoc DL) const override	llvm::final< T >
insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DstReg, const SmallVectorImpl< MachineOperand > &Cond, unsigned TrueReg, unsigned FalseReg) const override	llvm::final< T >
InstrItins	llvm::final< T >	[protected]
InstructionOpcodeToISD(unsigned Opcode) const	llvm::TargetLoweringBase
IntelAtom enum value	llvm::final< T >	[protected]
IntelSLM enum value	llvm::final< T >	[protected]
is16Bit() const	llvm::final< T >	[inline]
is32Bit() const	llvm::final< T >	[inline]
is64Bit() const	llvm::final< T >	[inline]
isAtom() const	llvm::final< T >	[inline]
isBigEndian() const	llvm::TargetLoweringBase	[inline]
IsBTMemSlow	llvm::final< T >	[protected]
isBTMemSlow() const	llvm::final< T >	[inline]
isCallingConvWin64(CallingConv::ID CC) const	llvm::final< T >	[inline]
isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const override	llvm::final< T >
isCondCodeLegal(ISD::CondCode CC, MVT VT) const	llvm::TargetLoweringBase	[inline]
isConstFalseVal(const SDNode *N) const	llvm::TargetLowering
isConstTrueVal(const SDNode *N) const	llvm::TargetLowering
isDesirableToCommuteWithShift(const SDNode *N) const	llvm::TargetLowering	[inline, virtual]
IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override	llvm::final< T >	[virtual]
isDesirableToTransformToIntegerOp(unsigned, EVT) const	llvm::TargetLowering	[inline, virtual]
isFAbsFree(EVT VT) const	llvm::TargetLoweringBase	[inline, virtual]
isFMAFasterThanFMulAndFAdd(EVT VT) const override	llvm::final< T >	[virtual]
isFNegFree(EVT VT) const	llvm::TargetLoweringBase	[inline, virtual]
isFPImmLegal(const APFloat &Imm, EVT VT) const override	llvm::final< T >	[virtual]
isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const override	llvm::final< T >	[virtual]
isHighLatencyDef(int opc) const override	llvm::final< T >
isIndexedLoadLegal(unsigned IdxMode, EVT VT) const	llvm::TargetLoweringBase	[inline]
isIndexedStoreLegal(unsigned IdxMode, EVT VT) const	llvm::TargetLoweringBase	[inline]
isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, SDValue &Chain) const	llvm::TargetLowering
isIntDivCheap() const	llvm::TargetLoweringBase	[inline]
isIntegerTypeFTOL(EVT VT) const	llvm::final< T >	[inline]
isJumpExpensive() const	llvm::TargetLoweringBase	[inline]
isLegalAddImmediate(int64_t Imm) const override	llvm::final< T >	[virtual]
isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override	llvm::final< T >	[virtual]
isLegalICmpImmediate(int64_t Imm) const override	llvm::final< T >	[virtual]
isLegalRC(const TargetRegisterClass *RC) const	llvm::TargetLoweringBase	[protected]
IsLegalToCallImmediateAddr(const TargetMachine &TM) const	llvm::final< T >
isLittleEndian() const	llvm::TargetLoweringBase	[inline]
isLoadBitCastBeneficial(EVT, EVT) const	llvm::TargetLoweringBase	[inline, virtual]
isLoadExtLegal(unsigned ExtType, EVT VT) const	llvm::TargetLoweringBase	[inline]
isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const override	llvm::final< T >
isLoadFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const override	llvm::final< T >
isMaskAndBranchFoldingLegal() const	llvm::TargetLoweringBase	[inline]
isNarrowingProfitable(EVT VT1, EVT VT2) const override	llvm::final< T >	[virtual]
isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override	llvm::final< T >	[virtual]
isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const	llvm::TargetLowering	[virtual]
isOperationExpand(unsigned Op, EVT VT) const	llvm::TargetLoweringBase	[inline]
isOperationLegal(unsigned Op, EVT VT) const	llvm::TargetLoweringBase	[inline]
isOperationLegalOrCustom(unsigned Op, EVT VT) const	llvm::TargetLoweringBase	[inline]
isOperationLegalOrPromote(unsigned Op, EVT VT) const	llvm::TargetLoweringBase	[inline]
isOSWindows() const	llvm::final< T >	[inline]
isPICStyleGOT() const	llvm::final< T >	[inline]
isPICStyleRIPRel() const	llvm::final< T >	[inline]
isPICStyleSet() const	llvm::final< T >	[inline]
isPICStyleStubAny() const	llvm::final< T >	[inline]
isPICStyleStubNoDynamic() const	llvm::final< T >	[inline]
isPICStyleStubPIC() const	llvm::final< T >	[inline]
isPow2SDivCheap() const	llvm::TargetLoweringBase	[inline]
isPredictableSelectExpensive() const	llvm::TargetLoweringBase	[inline]
isReallyTriviallyReMaterializable(const MachineInstr *MI, AliasAnalysis *AA) const override	llvm::final< T >
isSafeMemOpType(MVT VT) const override	llvm::final< T >	[virtual]
isSafeToClobberEFLAGS(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const	llvm::final< T >
isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override	llvm::final< T >
isScalarFPTypeInSSEReg(EVT VT) const	llvm::final< T >	[inline]
isSelectExpensive() const	llvm::TargetLoweringBase	[inline]
isSelectSupported(SelectSupportKind) const	llvm::TargetLoweringBase	[inline, virtual]
IsSHLDSlow	llvm::final< T >	[protected]
isSHLDSlow() const	llvm::final< T >	[inline]
isShuffleMaskLegal(const SmallVectorImpl< int > &Mask, EVT VT) const override	llvm::final< T >	[virtual]
isSLM() const	llvm::final< T >	[inline]
isSlowDivBypassed() const	llvm::TargetLoweringBase	[inline]
isSmall() const	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >	[inline, protected]
isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const override	llvm::final< T >
isStoreToStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const override	llvm::final< T >
isTarget64BitILP32() const	llvm::final< T >	[inline]
isTarget64BitLP64() const	llvm::final< T >	[inline]
isTargetCOFF() const	llvm::final< T >	[inline]
isTargetCygMing() const	llvm::final< T >	[inline]
isTargetDarwin() const	llvm::final< T >	[inline]
isTargetELF() const	llvm::final< T >	[inline]
isTargetFreeBSD() const	llvm::final< T >	[inline]
isTargetFTOL() const	llvm::final< T >
isTargetKnownWindowsMSVC() const	llvm::final< T >	[inline]
isTargetLinux() const	llvm::final< T >	[inline]
isTargetMacho() const	llvm::final< T >	[inline]
isTargetNaCl() const	llvm::final< T >	[inline]
isTargetNaCl32() const	llvm::final< T >	[inline]
isTargetNaCl64() const	llvm::final< T >	[inline]
isTargetSolaris() const	llvm::final< T >	[inline]
isTargetWin32() const	llvm::final< T >	[inline]
isTargetWin64() const	llvm::final< T >	[inline]
isTargetWindowsCygwin() const	llvm::final< T >	[inline]
isTargetWindowsGNU() const	llvm::final< T >	[inline]
isTargetWindowsMSVC() const	llvm::final< T >	[inline]
isTruncateFree(Type *Ty1, Type *Ty2) const override	llvm::final< T >	[virtual]
isTruncateFree(EVT VT1, EVT VT2) const override	llvm::final< T >	[virtual]
isTruncStoreLegal(EVT ValVT, EVT MemVT) const	llvm::TargetLoweringBase	[inline]
isTypeDesirableForOp(unsigned Opc, EVT VT) const override	llvm::final< T >	[virtual]
isTypeLegal(EVT VT) const	llvm::TargetLoweringBase	[inline]
IsUAMemFast	llvm::final< T >	[protected]
isUnalignedMemAccessFast() const	llvm::final< T >	[inline]
isUnpredicatedTerminator(const MachineInstr *MI) const override	llvm::final< T >
isVectorClearMaskLegal(const SmallVectorImpl< int > &Mask, EVT VT) const override	llvm::final< T >	[virtual]
isVectorShiftByScalarCheap(Type *Ty) const override	llvm::final< T >	[virtual]
isX86_64ExtendedReg(const MachineOperand &MO)	llvm::final< T >	[inline, static]
isZExtFree(Type *Ty1, Type *Ty2) const override	llvm::final< T >	[virtual]
isZExtFree(EVT VT1, EVT VT2) const override	llvm::final< T >	[virtual]
isZExtFree(SDValue Val, EVT VT2) const override	llvm::final< T >	[virtual]
iterator typedef	llvm::final< T >
iterator_range typedef	llvm::final< T >
LEAUsesAG	llvm::final< T >	[protected]
LEAusesAG() const	llvm::final< T >	[inline]
Legal enum value	llvm::TargetLoweringBase
LegalizeAction enum name	llvm::TargetLoweringBase
LegalizeKind typedef	llvm::TargetLoweringBase
LegalizeTypeAction enum name	llvm::TargetLoweringBase
LLVMTargetMachine(const Target &T, StringRef TargetTriple, StringRef CPU, StringRef FS, TargetOptions Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL)	llvm::LLVMTargetMachine	[protected]
loadRegFromAddr(MachineFunction &MF, unsigned DestReg, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl< MachineInstr * > &NewMIs) const	llvm::final< T >
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override	llvm::final< T >
lookupPassInfo(const void *TI)	llvm::Pass	[static]
lookupPassInfo(StringRef Arg)	llvm::Pass	[static]
LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const override	llvm::final< T >	[virtual]
LowerCallTo(CallLoweringInfo &CLI) const	llvm::TargetLowering
LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const override	llvm::final< T >	[virtual]
LowerOperation(SDValue Op, SelectionDAG &DAG) const override	llvm::final< T >	[virtual]
LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const	llvm::TargetLowering	[virtual]
LowerXConstraint(EVT ConstraintVT) const override	llvm::final< T >	[virtual]
MAI	llvm::MCInstPrinter	[protected]
makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SDLoc dl, bool doesNotReturn=false, bool isReturnValueUsed=true) const	llvm::TargetLowering
markup(StringRef s) const	llvm::MCInstPrinter
markup(StringRef a, StringRef b) const	llvm::MCInstPrinter
MaskAndBranchFoldingIsLegal	llvm::TargetLoweringBase	[protected]
max_size() const	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >	[inline]
MaxInlineSizeThreshold	llvm::final< T >	[protected]
MaxStoresPerMemcpy	llvm::TargetLoweringBase	[protected]
MaxStoresPerMemcpyOptSize	llvm::TargetLoweringBase	[protected]
MaxStoresPerMemmove	llvm::TargetLoweringBase	[protected]
MaxStoresPerMemmoveOptSize	llvm::TargetLoweringBase	[protected]
MaxStoresPerMemset	llvm::TargetLoweringBase	[protected]
MaxStoresPerMemsetOptSize	llvm::TargetLoweringBase	[protected]
MCInstPrinter(const MCAsmInfo &mai, const MCInstrInfo &mii, const MCRegisterInfo &mri)	llvm::MCInstPrinter	[inline]
MII	llvm::MCInstPrinter	[protected]
MMX enum value	llvm::final< T >	[protected]
move(It1 I, It1 E, It2 Dest)	llvm::SmallVectorTemplateBase< std::unique_ptr< UnitType >, isPodLike< std::unique_ptr< UnitType > >::value >	[inline, protected, static]
move_backward(It1 I, It1 E, It2 Dest)	llvm::SmallVectorTemplateBase< std::unique_ptr< UnitType >, isPodLike< std::unique_ptr< UnitType > >::value >	[inline, protected, static]
MRI	llvm::MCInstPrinter	[protected]
mustPreserveAnalysisID(char &AID) const	llvm::Pass
needsStackRealignment(const MachineFunction &MF) const override	llvm::final< T >
NoMMXSSE enum value	llvm::final< T >	[protected]
NoThreeDNow enum value	llvm::final< T >	[protected]
operator!=(const SmallVectorImpl &RHS) const	llvm::SmallVectorImpl< std::unique_ptr< UnitType > >	[inline]
operator<(const SmallVectorImpl &RHS) const	llvm::SmallVectorImpl< std::unique_ptr< UnitType > >	[inline]
SmallVector< std::unique_ptr< UnitType >, 1 >::operator=(const SmallVector &RHS)	llvm::SmallVector< std::unique_ptr< UnitType >, 1 >	[inline]
SmallVector< std::unique_ptr< UnitType >, 1 >::operator=(SmallVector &&RHS)	llvm::SmallVector< std::unique_ptr< UnitType >, 1 >	[inline]
SmallVectorImpl< std::unique_ptr< UnitType > >::operator=(const SmallVectorImpl &RHS)	llvm::SmallVectorImpl< std::unique_ptr< UnitType > >
SmallVectorImpl< std::unique_ptr< UnitType > >::operator=(SmallVectorImpl &&RHS)	llvm::SmallVectorImpl< std::unique_ptr< UnitType > >
operator==(const SmallVectorImpl &RHS) const	llvm::SmallVectorImpl< std::unique_ptr< UnitType > >	[inline]
operator[](unsigned idx)	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >	[inline]
operator[](unsigned idx) const	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >	[inline]
optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const override	llvm::final< T >
optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI, unsigned &FoldAsLoadDefReg, MachineInstr *&DefMI) const override	llvm::final< T >
Options	llvm::TargetMachine	[mutable]
Others enum value	llvm::final< T >	[protected]
PadShortFunctions	llvm::final< T >	[protected]
padShortFunctions() const	llvm::final< T >	[inline]
ParseConstraints(ImmutableCallSite CS) const	llvm::TargetLowering	[virtual]
ParseSubtargetFeatures(StringRef CPU, StringRef FS)	llvm::final< T >
Pass(PassKind K, char &pid)	llvm::Pass	[inline, explicit]
PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override	llvm::final< T >	[virtual]
PICStyle	llvm::final< T >	[protected]
pointer typedef	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >
pop_back()	llvm::SmallVectorTemplateBase< std::unique_ptr< UnitType >, isPodLike< std::unique_ptr< UnitType > >::value >	[inline]
pop_back_val()	llvm::SmallVectorImpl< std::unique_ptr< UnitType > >	[inline]
PredictableSelectIsExpensive	llvm::TargetLoweringBase	[protected]
preparePassManager(PMStack &)	llvm::Pass	[virtual]
prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL, SelectionDAG &DAG) const	llvm::TargetLowering	[inline, virtual]
llvm::print(char *Buffer, unsigned BufferSize) const	llvm::format_object_base	[inline]
llvm::FunctionPass::print(raw_ostream &O, const Module *M) const	llvm::Pass	[virtual]
printAliasInstr(const MCInst *MI, raw_ostream &OS)	llvm::final< T >
printAnnotation(raw_ostream &OS, StringRef Annot)	llvm::MCInstPrinter	[protected]
printAVXCC(const MCInst *MI, unsigned Op, raw_ostream &OS)	llvm::final< T >
printAVXCC(const MCInst *MI, unsigned Op, raw_ostream &O)	llvm::final< T >
printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, unsigned PrintMethodIdx, raw_ostream &O)	llvm::final< T >
printDstIdx(const MCInst *MI, unsigned OpNo, raw_ostream &OS)	llvm::final< T >
printDstIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >
printDstIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printDstIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printDstIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printDstIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printDstIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printDstIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printDstIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printDstIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printf128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printf128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printf256mem(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printf256mem(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printf32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printf32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printf512mem(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printf512mem(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printf64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printf64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printf80mem(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printf80mem(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
PrintHexStyle	llvm::MCInstPrinter	[protected]
printi128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printi128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printi16mem(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printi16mem(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printi256mem(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printi256mem(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printi32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printi32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printi512mem(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printi512mem(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printi64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printi64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printi8mem(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printi8mem(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
PrintImmHex	llvm::MCInstPrinter	[protected]
printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot) override	llvm::final< T >	[virtual]
printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot) override	llvm::final< T >	[virtual]
printInstruction(const MCInst *MI, raw_ostream &OS)	llvm::final< T >
printInstruction(const MCInst *MI, raw_ostream &O)	llvm::final< T >
printMemOffs16(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printMemOffs16(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printMemOffs32(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printMemOffs32(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printMemOffs64(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printMemOffs64(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printMemOffs8(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printMemOffs8(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &OS)	llvm::final< T >
printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >
printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS)	llvm::final< T >
printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O)	llvm::final< T >
printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS)	llvm::final< T >
printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >
printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &OS)	llvm::final< T >
printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >
printRegName(raw_ostream &OS, unsigned RegNo) const override	llvm::final< T >	[virtual]
printRegName(raw_ostream &OS, unsigned RegNo) const override	llvm::final< T >	[virtual]
printRoundingControl(const MCInst *MI, unsigned Op, raw_ostream &OS)	llvm::final< T >
printRoundingControl(const MCInst *MI, unsigned Op, raw_ostream &OS)	llvm::final< T >
printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &OS)	llvm::final< T >
printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >
printSrcIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printSrcIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printSrcIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printSrcIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printSrcIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printSrcIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printSrcIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printSrcIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O)	llvm::final< T >	[inline]
printSSECC(const MCInst *MI, unsigned Op, raw_ostream &OS)	llvm::final< T >
printSSECC(const MCInst *MI, unsigned Op, raw_ostream &O)	llvm::final< T >
Promote enum value	llvm::TargetLoweringBase
push_back(const std::unique_ptr< UnitType > &Elt)	llvm::SmallVectorTemplateBase< std::unique_ptr< UnitType >, isPodLike< std::unique_ptr< UnitType > >::value >	[inline]
push_back(std::unique_ptr< UnitType > &&Elt)	llvm::SmallVectorTemplateBase< std::unique_ptr< UnitType >, isPodLike< std::unique_ptr< UnitType > >::value >	[inline]
rbegin()	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >	[inline]
rbegin() const	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >	[inline]
reference typedef	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >
releaseMemory() override	llvm::final< T >	[virtual]
reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const override	llvm::final< T >
RemoveBranch(MachineBasicBlock &MBB) const override	llvm::final< T >
rend()	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >	[inline]
rend() const	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >	[inline]
ReplaceNodeResults(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const override	llvm::final< T >	[virtual]
requiresStructuredCFG() const	llvm::TargetMachine	[inline]
RequireStructuredCFG	llvm::TargetMachine	[protected]
reserve(unsigned N)	llvm::SmallVectorImpl< std::unique_ptr< UnitType > >	[inline]
resetOperationActions() override	llvm::final< T >	[virtual]
resetTargetOptions(const MachineFunction *MF) const	llvm::TargetMachine
resetToSmall()	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >	[inline, protected]
resize(unsigned N)	llvm::SmallVectorImpl< std::unique_ptr< UnitType > >	[inline]
resize(unsigned N, const std::unique_ptr< UnitType > &NV)	llvm::SmallVectorImpl< std::unique_ptr< UnitType > >	[inline]
reverse_iterator typedef	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >
ReverseBranchCondition(SmallVectorImpl< MachineOperand > &Cond) const override	llvm::final< T >
runOnFunction(Function &F) override	llvm::final< T >	[virtual]
ScalarCondVectorVal enum value	llvm::TargetLoweringBase
ScalarValSelect enum value	llvm::TargetLoweringBase
SelectSupportKind enum name	llvm::TargetLoweringBase
set_size(unsigned N)	llvm::SmallVectorImpl< std::unique_ptr< UnitType > >	[inline]
setAsmVerbosityDefault(bool)	llvm::TargetMachine
setAvailableFeatures(uint64_t Value)	llvm::MCInstPrinter	[inline]
setBooleanContents(BooleanContent Ty)	llvm::TargetLoweringBase	[inline, protected]
setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy)	llvm::TargetLoweringBase	[inline, protected]
setBooleanVectorContents(BooleanContent Ty)	llvm::TargetLoweringBase	[inline, protected]
setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC)	llvm::TargetLoweringBase	[inline]
setCommentStream(raw_ostream &OS)	llvm::MCInstPrinter	[inline]
setCondCodeAction(ISD::CondCode CC, MVT VT, LegalizeAction Action)	llvm::TargetLoweringBase	[inline, protected]
setDataSections(bool)	llvm::TargetMachine
setEnd(std::unique_ptr< UnitType > *P)	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >	[inline, protected]
setExceptionPointerRegister(unsigned R)	llvm::TargetLoweringBase	[inline, protected]
setExceptionSelectorRegister(unsigned R)	llvm::TargetLoweringBase	[inline, protected]
setExecutionDomain(MachineInstr *MI, unsigned Domain) const override	llvm::final< T >
setFastISel(bool Enable)	llvm::TargetMachine	[inline]
setFunctionSections(bool)	llvm::TargetMachine
setHasExtractBitsInsn(bool hasExtractInsn=true)	llvm::TargetLoweringBase	[inline, protected]
setHasFloatingPointExceptions(bool FPExceptions=true)	llvm::TargetLoweringBase	[inline, protected]
setHasMultipleConditionRegisters(bool hasManyRegs=true)	llvm::TargetLoweringBase	[inline, protected]
setIndexedLoadAction(unsigned IdxMode, MVT VT, LegalizeAction Action)	llvm::TargetLoweringBase	[inline, protected]
setIndexedStoreAction(unsigned IdxMode, MVT VT, LegalizeAction Action)	llvm::TargetLoweringBase	[inline, protected]
setInsertFencesForAtomic(bool fence)	llvm::TargetLoweringBase	[inline, protected]
setIntDivIsCheap(bool isCheap=true)	llvm::TargetLoweringBase	[inline, protected]
setJumpBufAlignment(unsigned Align)	llvm::TargetLoweringBase	[inline, protected]
setJumpBufSize(unsigned Size)	llvm::TargetLoweringBase	[inline, protected]
setJumpIsExpensive(bool isExpensive=true)	llvm::TargetLoweringBase	[inline, protected]
setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC)	llvm::TargetLoweringBase	[inline]
setLibcallName(RTLIB::Libcall Call, const char *Name)	llvm::TargetLoweringBase	[inline]
setLoadExtAction(unsigned ExtType, MVT VT, LegalizeAction Action)	llvm::TargetLoweringBase	[inline, protected]
setMinFunctionAlignment(unsigned Align)	llvm::TargetLoweringBase	[inline, protected]
setMinimumJumpTableEntries(int Val)	llvm::TargetLoweringBase	[inline, protected]
setMinStackArgumentAlignment(unsigned Align)	llvm::TargetLoweringBase	[inline, protected]
setOperationAction(unsigned Op, MVT VT, LegalizeAction Action)	llvm::TargetLoweringBase	[inline, protected]
setOptLevel(CodeGenOpt::Level Level) const	llvm::TargetMachine
setPICStyle(PICStyles::Style Style)	llvm::final< T >	[inline]
setPow2SDivIsCheap(bool isCheap=true)	llvm::TargetLoweringBase	[inline, protected]
setPrefFunctionAlignment(unsigned Align)	llvm::TargetLoweringBase	[inline, protected]
setPrefLoopAlignment(unsigned Align)	llvm::TargetLoweringBase	[inline, protected]
setPrintImmHex(bool Value)	llvm::MCInstPrinter	[inline]
setPrintImmHex(HexStyle::Style Value)	llvm::MCInstPrinter	[inline]
setRequiresStructuredCFG(bool Value)	llvm::TargetMachine	[inline]
setResolver(AnalysisResolver *AR)	llvm::Pass
setSchedulingPreference(Sched::Preference Pref)	llvm::TargetLoweringBase	[inline, protected]
setSelectIsExpensive(bool isExpensive=true)	llvm::TargetLoweringBase	[inline, protected]
setStackPointerRegisterToSaveRestore(unsigned R)	llvm::TargetLoweringBase	[inline, protected]
setTargetDAGCombine(ISD::NodeType NT)	llvm::TargetLoweringBase	[inline, protected]
setTruncStoreAction(MVT ValVT, MVT MemVT, LegalizeAction Action)	llvm::TargetLoweringBase	[inline, protected]
setUseMarkup(bool Value)	llvm::MCInstPrinter	[inline]
setUseUnderscoreLongJmp(bool Val)	llvm::TargetLoweringBase	[inline, protected]
setUseUnderscoreSetJmp(bool Val)	llvm::TargetLoweringBase	[inline, protected]
shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const override	llvm::final< T >	[virtual]
shouldExpandBuildVectorWithShuffles(EVT, unsigned DefinedValues) const	llvm::TargetLoweringBase	[inline, virtual]
shouldPrintMachineCode() const	llvm::TargetMachine	[inline]
shouldScheduleAdjacent(MachineInstr *First, MachineInstr *Second) const override	llvm::final< T >
shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, int64_t Offset1, int64_t Offset2, unsigned NumLoads) const override	llvm::final< T >
ShouldShrinkFPConstant(EVT VT) const override	llvm::final< T >	[inline, virtual]
SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth=0) const	llvm::TargetLowering
SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, SDLoc dl) const	llvm::TargetLowering
size() const	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >	[inline]
size_in_bytes() const	llvm::SmallVectorBase	[inline]
size_type typedef	llvm::SmallVectorImpl< std::unique_ptr< UnitType > >
skipOptnoneFunction(const Function &F) const	llvm::FunctionPass	[protected]
slowIncDec() const	llvm::final< T >	[inline]
SlowIncDec	llvm::final< T >	[protected]
SlowLEA	llvm::final< T >	[protected]
slowLEA() const	llvm::final< T >	[inline]
SmallVector()	llvm::SmallVector< std::unique_ptr< UnitType >, 1 >	[inline]
SmallVector(unsigned Size, const std::unique_ptr< UnitType > &Value=std::unique_ptr< UnitType >())	llvm::SmallVector< std::unique_ptr< UnitType >, 1 >	[inline, explicit]
SmallVector(ItTy S, ItTy E)	llvm::SmallVector< std::unique_ptr< UnitType >, 1 >	[inline]
SmallVector(const llvm::iterator_range< RangeTy > R)	llvm::SmallVector< std::unique_ptr< UnitType >, 1 >	[inline, explicit]
SmallVector(const SmallVector &RHS)	llvm::SmallVector< std::unique_ptr< UnitType >, 1 >	[inline]
SmallVector(SmallVector &&RHS)	llvm::SmallVector< std::unique_ptr< UnitType >, 1 >	[inline]
SmallVectorBase(void *FirstEl, size_t Size)	llvm::SmallVectorBase	[inline, protected]
SmallVectorImpl(unsigned N)	llvm::SmallVectorImpl< std::unique_ptr< UnitType > >	[inline, explicit, protected]
SmallVectorTemplateBase(size_t Size)	llvm::SmallVectorTemplateBase< std::unique_ptr< UnitType >, isPodLike< std::unique_ptr< UnitType > >::value >	[inline, protected]
SmallVectorTemplateCommon(size_t Size)	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >	[inline, protected]
snprint(char *Buffer, unsigned BufferSize) const override	llvm::final< T >	[inline, virtual]
snprint(char *Buffer, unsigned BufferSize) const override	llvm::final< T >	[inline, virtual]
snprint(char *Buffer, unsigned BufferSize) const override	llvm::final< T >	[inline, virtual]
snprint(char *Buffer, unsigned BufferSize) const override	llvm::final< T >	[inline, virtual]
snprint(char *Buffer, unsigned BufferSize) const override	llvm::final< T >	[inline, virtual]
snprint(char *Buffer, unsigned BufferSize) const override	llvm::final< T >	[inline, virtual]
softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, SDLoc DL) const	llvm::TargetLowering
SSE1 enum value	llvm::final< T >	[protected]
SSE2 enum value	llvm::final< T >	[protected]
SSE3 enum value	llvm::final< T >	[protected]
SSE41 enum value	llvm::final< T >	[protected]
SSE42 enum value	llvm::final< T >	[protected]
SSSE3 enum value	llvm::final< T >	[protected]
stackAlignment	llvm::final< T >	[protected]
storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl< MachineOperand > &Addr, const TargetRegisterClass *RC, MachineInstr::mmo_iterator MMOBegin, MachineInstr::mmo_iterator MMOEnd, SmallVectorImpl< MachineInstr * > &NewMIs) const	llvm::final< T >
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override	llvm::final< T >
Subtarget	llvm::final< T >
swap(SmallVectorImpl &RHS)	llvm::SmallVectorImpl< std::unique_ptr< UnitType > >
TargetCPU	llvm::TargetMachine	[protected]
TargetFS	llvm::TargetMachine	[protected]
TargetLowering(const TargetMachine &TM, const TargetLoweringObjectFile *TLOF)	llvm::TargetLowering	[explicit]
TargetLoweringBase(const TargetMachine &TM, const TargetLoweringObjectFile *TLOF)	llvm::TargetLoweringBase	[explicit]
TargetMachine(const Target &T, StringRef TargetTriple, StringRef CPU, StringRef FS, const TargetOptions &Options)	llvm::TargetMachine	[protected]
TargetTriple	llvm::final< T >	[protected]
TheTarget	llvm::TargetMachine	[protected]
ThreeDNow enum value	llvm::final< T >	[protected]
ThreeDNowA enum value	llvm::final< T >	[protected]
trackLivenessAfterRegAlloc(const MachineFunction &MF) const override	llvm::final< T >
TypeExpandFloat enum value	llvm::TargetLoweringBase
TypeExpandInteger enum value	llvm::TargetLoweringBase
TypeLegal enum value	llvm::TargetLoweringBase
TypePromoteInteger enum value	llvm::TargetLoweringBase
TypeScalarizeVector enum value	llvm::TargetLoweringBase
TypeSoftenFloat enum value	llvm::TargetLoweringBase
TypeSplitVector enum value	llvm::TargetLoweringBase
TypeWidenVector enum value	llvm::TargetLoweringBase
UndefinedBooleanContent enum value	llvm::TargetLoweringBase
unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl< MachineInstr * > &NewMIs) const override	llvm::final< T >
unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SmallVectorImpl< SDNode * > &NewNodes) const override	llvm::final< T >
uninitialized_copy(It1 I, It1 E, It2 Dest)	llvm::SmallVectorTemplateBase< std::unique_ptr< UnitType >, isPodLike< std::unique_ptr< UnitType > >::value >	[inline, protected, static]
uninitialized_move(It1 I, It1 E, It2 Dest)	llvm::SmallVectorTemplateBase< std::unique_ptr< UnitType >, isPodLike< std::unique_ptr< UnitType > >::value >	[inline, protected, static]
UnitVector typedef	llvm::final< T >
useLeaForSP() const	llvm::final< T >	[inline]
UseLeaForSP	llvm::final< T >	[protected]
useLoadStackGuardNode() const override	llvm::final< T >	[virtual]
UseMarkup	llvm::MCInstPrinter	[protected]
usesUnderscoreLongJmp() const	llvm::TargetLoweringBase	[inline]
usesUnderscoreSetJmp() const	llvm::TargetLoweringBase	[inline]
value_type typedef	llvm::SmallVectorTemplateCommon< std::unique_ptr< UnitType > >
VectorMaskSelect enum value	llvm::TargetLoweringBase
verifyAnalysis() const	llvm::Pass	[virtual]
verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const	llvm::TargetLowering
X863DNowEnum enum name	llvm::final< T >	[protected]
X863DNowLevel	llvm::final< T >	[protected]
X86ATTInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI)	llvm::final< T >	[inline]
X86InstrInfo(X86Subtarget &STI)	llvm::final< T >	[explicit]
X86IntelInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI)	llvm::final< T >	[inline]
X86ProcFamily	llvm::final< T >	[protected]
X86ProcFamilyEnum enum name	llvm::final< T >	[protected]
X86RegisterInfo(const X86Subtarget &STI)	llvm::final< T >
X86SSEEnum enum name	llvm::final< T >	[protected]
X86SSELevel	llvm::final< T >	[protected]
X86Subtarget(const std::string &TT, const std::string &CPU, const std::string &FS, X86TargetMachine &TM, unsigned StackAlignOverride)	llvm::final< T >
X86TargetLowering(X86TargetMachine &TM)	llvm::final< T >	[explicit]
X86TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL)	llvm::final< T >
ZeroOrNegativeOneBooleanContent enum value	llvm::TargetLoweringBase
ZeroOrOneBooleanContent enum value	llvm::TargetLoweringBase
~DWARFUnitSectionBase()	llvm::DWARFUnitSectionBase	[inline, protected]
~format_object_base()	llvm::format_object_base	[inline, protected]
~MCInstPrinter()	llvm::MCInstPrinter	[virtual]
~Pass()	llvm::Pass	[virtual]
~SmallVectorImpl()	llvm::SmallVectorImpl< std::unique_ptr< UnitType > >	[inline]
~TargetLoweringBase()	llvm::TargetLoweringBase	[virtual]
~TargetMachine()	llvm::TargetMachine	[virtual]