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4965.h
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1 /******************************************************************************
2  *
3  * GPL LICENSE SUMMARY
4  *
5  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of version 2 of the GNU General Public License as
9  * published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope that it will be useful, but
12  * WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14  * General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19  * USA
20  *
21  * The full GNU General Public License is included in this distribution
22  * in the file called LICENSE.GPL.
23  *
24  * Contact Information:
25  * Intel Linux Wireless <[email protected]>
26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27  *
28  *****************************************************************************/
29 
30 #ifndef __il_4965_h__
31 #define __il_4965_h__
32 
33 struct il_rx_queue;
34 struct il_rx_buf;
35 struct il_rx_pkt;
36 struct il_tx_queue;
37 struct il_rxon_context;
38 
39 /* configuration for the _4965 devices */
40 extern struct il_cfg il4965_cfg;
41 extern const struct il_ops il4965_ops;
42 
43 extern struct il_mod_params il4965_mod_params;
44 
45 /* tx queue */
46 void il4965_free_tfds_in_queue(struct il_priv *il, int sta_id, int tid,
47  int freed);
48 
49 /* RXON */
50 void il4965_set_rxon_chain(struct il_priv *il);
51 
52 /* uCode */
53 int il4965_verify_ucode(struct il_priv *il);
54 
55 /* lib */
56 void il4965_check_abort_status(struct il_priv *il, u8 frame_count, u32 status);
57 
58 void il4965_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq);
59 int il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq);
60 int il4965_hw_nic_init(struct il_priv *il);
61 int il4965_dump_fh(struct il_priv *il, char **buf, bool display);
62 
63 void il4965_nic_config(struct il_priv *il);
64 
65 /* rx */
66 void il4965_rx_queue_restock(struct il_priv *il);
67 void il4965_rx_replenish(struct il_priv *il);
68 void il4965_rx_replenish_now(struct il_priv *il);
69 void il4965_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq);
70 int il4965_rxq_stop(struct il_priv *il);
71 int il4965_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band);
72 void il4965_rx_handle(struct il_priv *il);
73 
74 /* tx */
75 void il4965_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq);
76 int il4965_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq,
77  dma_addr_t addr, u16 len, u8 reset, u8 pad);
78 int il4965_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq);
79 void il4965_hwrate_to_tx_control(struct il_priv *il, u32 rate_n_flags,
80  struct ieee80211_tx_info *info);
81 int il4965_tx_skb(struct il_priv *il,
82  struct ieee80211_sta *sta,
83  struct sk_buff *skb);
84 int il4965_tx_agg_start(struct il_priv *il, struct ieee80211_vif *vif,
85  struct ieee80211_sta *sta, u16 tid, u16 * ssn);
86 int il4965_tx_agg_stop(struct il_priv *il, struct ieee80211_vif *vif,
87  struct ieee80211_sta *sta, u16 tid);
88 int il4965_txq_check_empty(struct il_priv *il, int sta_id, u8 tid, int txq_id);
89 int il4965_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx);
90 void il4965_hw_txq_ctx_free(struct il_priv *il);
91 int il4965_txq_ctx_alloc(struct il_priv *il);
92 void il4965_txq_ctx_reset(struct il_priv *il);
93 void il4965_txq_ctx_stop(struct il_priv *il);
94 void il4965_txq_set_sched(struct il_priv *il, u32 mask);
95 
96 /*
97  * Acquire il->lock before calling this function !
98  */
99 void il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 idx);
107 void il4965_tx_queue_set_status(struct il_priv *il, struct il_tx_queue *txq,
108  int tx_fifo_id, int scd_retry);
109 
110 /* scan */
111 int il4965_request_scan(struct il_priv *il, struct ieee80211_vif *vif);
112 
113 /* station mgmt */
114 int il4965_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif,
115  bool add);
116 
117 /* hcmd */
118 int il4965_send_beacon_cmd(struct il_priv *il);
119 
120 #ifdef CONFIG_IWLEGACY_DEBUG
121 const char *il4965_get_tx_fail_reason(u32 status);
122 #else
123 static inline const char *
124 il4965_get_tx_fail_reason(u32 status)
125 {
126  return "";
127 }
128 #endif
129 
130 /* station management */
131 int il4965_alloc_bcast_station(struct il_priv *il);
132 int il4965_add_bssid_station(struct il_priv *il, const u8 *addr, u8 *sta_id_r);
133 int il4965_remove_default_wep_key(struct il_priv *il,
134  struct ieee80211_key_conf *key);
135 int il4965_set_default_wep_key(struct il_priv *il,
136  struct ieee80211_key_conf *key);
137 int il4965_restore_default_wep_keys(struct il_priv *il);
138 int il4965_set_dynamic_key(struct il_priv *il,
139  struct ieee80211_key_conf *key, u8 sta_id);
140 int il4965_remove_dynamic_key(struct il_priv *il,
141  struct ieee80211_key_conf *key, u8 sta_id);
142 void il4965_update_tkip_key(struct il_priv *il,
143  struct ieee80211_key_conf *keyconf,
144  struct ieee80211_sta *sta, u32 iv32,
145  u16 *phase1key);
146 int il4965_sta_tx_modify_enable_tid(struct il_priv *il, int sta_id, int tid);
147 int il4965_sta_rx_agg_start(struct il_priv *il, struct ieee80211_sta *sta,
148  int tid, u16 ssn);
149 int il4965_sta_rx_agg_stop(struct il_priv *il, struct ieee80211_sta *sta,
150  int tid);
151 void il4965_sta_modify_sleep_tx_count(struct il_priv *il, int sta_id, int cnt);
152 int il4965_update_bcast_stations(struct il_priv *il);
153 
154 /* rate */
155 static inline u8
156 il4965_hw_get_rate(__le32 rate_n_flags)
157 {
158  return le32_to_cpu(rate_n_flags) & 0xFF;
159 }
160 
161 /* eeprom */
162 void il4965_eeprom_get_mac(const struct il_priv *il, u8 * mac);
163 int il4965_eeprom_acquire_semaphore(struct il_priv *il);
164 void il4965_eeprom_release_semaphore(struct il_priv *il);
165 int il4965_eeprom_check_version(struct il_priv *il);
166 
167 /* mac80211 handlers (for 4965) */
168 void il4965_mac_tx(struct ieee80211_hw *hw,
169  struct ieee80211_tx_control *control,
170  struct sk_buff *skb);
171 int il4965_mac_start(struct ieee80211_hw *hw);
172 void il4965_mac_stop(struct ieee80211_hw *hw);
173 void il4965_configure_filter(struct ieee80211_hw *hw,
174  unsigned int changed_flags,
175  unsigned int *total_flags, u64 multicast);
176 int il4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
177  struct ieee80211_vif *vif, struct ieee80211_sta *sta,
178  struct ieee80211_key_conf *key);
179 void il4965_mac_update_tkip_key(struct ieee80211_hw *hw,
180  struct ieee80211_vif *vif,
181  struct ieee80211_key_conf *keyconf,
182  struct ieee80211_sta *sta, u32 iv32,
183  u16 *phase1key);
184 int il4965_mac_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
185  enum ieee80211_ampdu_mlme_action action,
186  struct ieee80211_sta *sta, u16 tid, u16 * ssn,
187  u8 buf_size);
188 int il4965_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
189  struct ieee80211_sta *sta);
190 void il4965_mac_channel_switch(struct ieee80211_hw *hw,
191  struct ieee80211_channel_switch *ch_switch);
192 
193 void il4965_led_enable(struct il_priv *il);
194 
195 /* EEPROM */
196 #define IL4965_EEPROM_IMG_SIZE 1024
197 
198 /*
199  * uCode queue management definitions ...
200  * The first queue used for block-ack aggregation is #7 (4965 only).
201  * All block-ack aggregation queues should map to Tx DMA/FIFO channel 7.
202  */
203 #define IL49_FIRST_AMPDU_QUEUE 7
204 
205 /* Sizes and addresses for instruction and data memory (SRAM) in
206  * 4965's embedded processor. Driver access is via HBUS_TARG_MEM_* regs. */
207 #define IL49_RTC_INST_LOWER_BOUND (0x000000)
208 #define IL49_RTC_INST_UPPER_BOUND (0x018000)
209 
210 #define IL49_RTC_DATA_LOWER_BOUND (0x800000)
211 #define IL49_RTC_DATA_UPPER_BOUND (0x80A000)
212 
213 #define IL49_RTC_INST_SIZE (IL49_RTC_INST_UPPER_BOUND - \
214  IL49_RTC_INST_LOWER_BOUND)
215 #define IL49_RTC_DATA_SIZE (IL49_RTC_DATA_UPPER_BOUND - \
216  IL49_RTC_DATA_LOWER_BOUND)
217 
218 #define IL49_MAX_INST_SIZE IL49_RTC_INST_SIZE
219 #define IL49_MAX_DATA_SIZE IL49_RTC_DATA_SIZE
220 
221 /* Size of uCode instruction memory in bootstrap state machine */
222 #define IL49_MAX_BSM_SIZE BSM_SRAM_SIZE
223 
224 static inline int
225 il4965_hw_valid_rtc_data_addr(u32 addr)
226 {
227  return (addr >= IL49_RTC_DATA_LOWER_BOUND &&
228  addr < IL49_RTC_DATA_UPPER_BOUND);
229 }
230 
231 /********************* START TEMPERATURE *************************************/
232 
264 #define TEMPERATURE_CALIB_KELVIN_OFFSET 8
265 #define TEMPERATURE_CALIB_A_VAL 259
266 
267 /* Limit range of calculated temperature to be between these Kelvin values */
268 #define IL_TX_POWER_TEMPERATURE_MIN (263)
269 #define IL_TX_POWER_TEMPERATURE_MAX (410)
270 
271 #define IL_TX_POWER_TEMPERATURE_OUT_OF_RANGE(t) \
272  ((t) < IL_TX_POWER_TEMPERATURE_MIN || \
273  (t) > IL_TX_POWER_TEMPERATURE_MAX)
274 
275 extern void il4965_temperature_calib(struct il_priv *il);
276 /********************* END TEMPERATURE ***************************************/
277 
278 /********************* START TXPOWER *****************************************/
279 
508 #define IL_TX_POWER_MIMO_REGULATORY_COMPENSATION (6)
509 
520 #define IL_TX_POWER_CCK_COMPENSATION_B_STEP (9)
521 #define IL_TX_POWER_CCK_COMPENSATION_C_STEP (5)
522 
523 /*
524  * 4965 power supply voltage compensation for txpower
525  */
526 #define TX_POWER_IL_VOLTAGE_CODES_PER_03V (7)
527 
559 #define MIN_TX_GAIN_IDX (0) /* highest gain, lowest idx, 2.4 */
560 #define MIN_TX_GAIN_IDX_52GHZ_EXT (-9) /* highest gain, lowest idx, 5 */
561 
793 #define IL_TX_POWER_DEFAULT_REGULATORY_24 (34)
794 #define IL_TX_POWER_DEFAULT_REGULATORY_52 (34)
795 #define IL_TX_POWER_REGULATORY_MIN (0)
796 #define IL_TX_POWER_REGULATORY_MAX (34)
797 
814 #define IL_TX_POWER_DEFAULT_SATURATION_24 (38)
815 #define IL_TX_POWER_DEFAULT_SATURATION_52 (38)
816 #define IL_TX_POWER_SATURATION_MIN (20)
817 #define IL_TX_POWER_SATURATION_MAX (50)
818 
833 /* Group 0, 5.2 GHz ch 34-43: 4.5 degrees per 1/2 dB. */
834 #define CALIB_IL_TX_ATTEN_GR1_FCH 34
835 #define CALIB_IL_TX_ATTEN_GR1_LCH 43
836 
837 /* Group 1, 5.3 GHz ch 44-70: 4.0 degrees per 1/2 dB. */
838 #define CALIB_IL_TX_ATTEN_GR2_FCH 44
839 #define CALIB_IL_TX_ATTEN_GR2_LCH 70
840 
841 /* Group 2, 5.5 GHz ch 71-124: 4.0 degrees per 1/2 dB. */
842 #define CALIB_IL_TX_ATTEN_GR3_FCH 71
843 #define CALIB_IL_TX_ATTEN_GR3_LCH 124
844 
845 /* Group 3, 5.7 GHz ch 125-200: 4.0 degrees per 1/2 dB. */
846 #define CALIB_IL_TX_ATTEN_GR4_FCH 125
847 #define CALIB_IL_TX_ATTEN_GR4_LCH 200
848 
849 /* Group 4, 2.4 GHz all channels: 3.5 degrees per 1/2 dB. */
850 #define CALIB_IL_TX_ATTEN_GR5_FCH 1
851 #define CALIB_IL_TX_ATTEN_GR5_LCH 20
852 
853 enum {
854  CALIB_CH_GROUP_1 = 0,
855  CALIB_CH_GROUP_2 = 1,
856  CALIB_CH_GROUP_3 = 2,
857  CALIB_CH_GROUP_4 = 3,
858  CALIB_CH_GROUP_5 = 4,
859  CALIB_CH_GROUP_MAX
860 };
861 
862 /********************* END TXPOWER *****************************************/
863 
884 #define IL49_NUM_FIFOS 7
885 #define IL49_CMD_FIFO_NUM 4
886 #define IL49_NUM_QUEUES 16
887 #define IL49_NUM_AMPDU_QUEUES 8
888 
907 struct il4965_scd_bc_tbl {
908  __le16 tfd_offset[TFD_QUEUE_BC_SIZE];
909  u8 pad[1024 - (TFD_QUEUE_BC_SIZE) * sizeof(__le16)];
910 } __packed;
911 
912 #define IL4965_RTC_INST_LOWER_BOUND (0x000000)
913 
914 /* RSSI to dBm */
915 #define IL4965_RSSI_OFFSET 44
916 
917 /* PCI registers */
918 #define PCI_CFG_RETRY_TIMEOUT 0x041
919 
920 /* PCI register values */
921 #define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
922 #define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
923 
924 #define IL4965_DEFAULT_TX_RETRY 15
925 
926 /* EEPROM */
927 #define IL4965_FIRST_AMPDU_QUEUE 10
928 
929 /* Calibration */
930 void il4965_chain_noise_calibration(struct il_priv *il, void *stat_resp);
931 void il4965_sensitivity_calibration(struct il_priv *il, void *resp);
932 void il4965_init_sensitivity(struct il_priv *il);
933 void il4965_reset_run_time_calib(struct il_priv *il);
934 
935 /* Debug */
936 #ifdef CONFIG_IWLEGACY_DEBUGFS
937 extern const struct il_debugfs_ops il4965_debugfs_ops;
938 #endif
939 
940 /****************************/
941 /* Flow Handler Definitions */
942 /****************************/
943 
948 #define FH49_MEM_LOWER_BOUND (0x1000)
949 #define FH49_MEM_UPPER_BOUND (0x2000)
950 
968 #define FH49_KW_MEM_ADDR_REG (FH49_MEM_LOWER_BOUND + 0x97C)
969 
982 #define FH49_MEM_CBBC_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x9D0)
983 #define FH49_MEM_CBBC_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xA10)
984 
985 /* Find TFD CB base pointer for given queue (range 0-15). */
986 #define FH49_MEM_CBBC_QUEUE(x) (FH49_MEM_CBBC_LOWER_BOUND + (x) * 0x4)
987 
1057 #define FH49_MEM_RSCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xBC0)
1058 #define FH49_MEM_RSCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xC00)
1059 #define FH49_MEM_RSCSR_CHNL0 (FH49_MEM_RSCSR_LOWER_BOUND)
1060 
1066 #define FH49_RSCSR_CHNL0_STTS_WPTR_REG (FH49_MEM_RSCSR_CHNL0)
1067 
1073 #define FH49_RSCSR_CHNL0_RBDCB_BASE_REG (FH49_MEM_RSCSR_CHNL0 + 0x004)
1074 
1081 #define FH49_RSCSR_CHNL0_RBDCB_WPTR_REG (FH49_MEM_RSCSR_CHNL0 + 0x008)
1082 #define FH49_RSCSR_CHNL0_WPTR (FH49_RSCSR_CHNL0_RBDCB_WPTR_REG)
1083 
1110 #define FH49_MEM_RCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xC00)
1111 #define FH49_MEM_RCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xCC0)
1112 #define FH49_MEM_RCSR_CHNL0 (FH49_MEM_RCSR_LOWER_BOUND)
1113 
1114 #define FH49_MEM_RCSR_CHNL0_CONFIG_REG (FH49_MEM_RCSR_CHNL0)
1115 
1116 #define FH49_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MSK (0x00000FF0) /* bits 4-11 */
1117 #define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MSK (0x00001000) /* bits 12 */
1118 #define FH49_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK (0x00008000) /* bit 15 */
1119 #define FH49_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MSK (0x00030000) /* bits 16-17 */
1120 #define FH49_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MSK (0x00F00000) /* bits 20-23 */
1121 #define FH49_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MSK (0xC0000000) /* bits 30-31 */
1122 
1123 #define FH49_RCSR_RX_CONFIG_RBDCB_SIZE_POS (20)
1124 #define FH49_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS (4)
1125 #define RX_RB_TIMEOUT (0x10)
1126 
1127 #define FH49_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
1128 #define FH49_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
1129 #define FH49_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
1130 
1131 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
1132 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K (0x00010000)
1133 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K (0x00020000)
1134 #define FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_16K (0x00030000)
1135 
1136 #define FH49_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY (0x00000004)
1137 #define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
1138 #define FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
1139 
1153 #define FH49_MEM_RSSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xC40)
1154 #define FH49_MEM_RSSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xD00)
1155 
1156 #define FH49_MEM_RSSR_SHARED_CTRL_REG (FH49_MEM_RSSR_LOWER_BOUND)
1157 #define FH49_MEM_RSSR_RX_STATUS_REG (FH49_MEM_RSSR_LOWER_BOUND + 0x004)
1158 #define FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV\
1159  (FH49_MEM_RSSR_LOWER_BOUND + 0x008)
1160 
1161 #define FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
1162 
1163 #define FH49_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
1164 
1165 /* TFDB Area - TFDs buffer table */
1166 #define FH49_MEM_TFDIB_DRAM_ADDR_LSB_MSK (0xFFFFFFFF)
1167 #define FH49_TFDIB_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x900)
1168 #define FH49_TFDIB_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0x958)
1169 #define FH49_TFDIB_CTRL0_REG(_chnl) (FH49_TFDIB_LOWER_BOUND + 0x8 * (_chnl))
1170 #define FH49_TFDIB_CTRL1_REG(_chnl) (FH49_TFDIB_LOWER_BOUND + 0x8 * (_chnl) + 0x4)
1171 
1194 #define FH49_TCSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xD00)
1195 #define FH49_TCSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xE60)
1196 
1197 /* Find Control/Status reg for given Tx DMA/FIFO channel */
1198 #define FH49_TCSR_CHNL_NUM (7)
1199 #define FH50_TCSR_CHNL_NUM (8)
1200 
1201 /* TCSR: tx_config register values */
1202 #define FH49_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
1203  (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl))
1204 #define FH49_TCSR_CHNL_TX_CREDIT_REG(_chnl) \
1205  (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x4)
1206 #define FH49_TCSR_CHNL_TX_BUF_STS_REG(_chnl) \
1207  (FH49_TCSR_LOWER_BOUND + 0x20 * (_chnl) + 0x8)
1208 
1209 #define FH49_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
1210 #define FH49_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRV (0x00000001)
1211 
1212 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE (0x00000000)
1213 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE (0x00000008)
1214 
1215 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
1216 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
1217 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
1218 
1219 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
1220 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
1221 #define FH49_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
1222 
1223 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
1224 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
1225 #define FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
1226 
1227 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
1228 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
1229 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
1230 
1231 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
1232 #define FH49_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
1233 
1246 #define FH49_TSSR_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0xEA0)
1247 #define FH49_TSSR_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0xEC0)
1248 
1249 #define FH49_TSSR_TX_STATUS_REG (FH49_TSSR_LOWER_BOUND + 0x010)
1250 
1268 #define FH49_TSSR_TX_ERROR_REG (FH49_TSSR_LOWER_BOUND + 0x018)
1269 
1270 #define FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) ((1 << (_chnl)) << 16)
1271 
1272 /* Tx service channels */
1273 #define FH49_SRVC_CHNL (9)
1274 #define FH49_SRVC_LOWER_BOUND (FH49_MEM_LOWER_BOUND + 0x9C8)
1275 #define FH49_SRVC_UPPER_BOUND (FH49_MEM_LOWER_BOUND + 0x9D0)
1276 #define FH49_SRVC_CHNL_SRAM_ADDR_REG(_chnl) \
1277  (FH49_SRVC_LOWER_BOUND + ((_chnl) - 9) * 0x4)
1278 
1279 #define FH49_TX_CHICKEN_BITS_REG (FH49_MEM_LOWER_BOUND + 0xE98)
1280 /* Instruct FH to increment the retry count of a packet when
1281  * it is brought from the memory to TX-FIFO
1282  */
1283 #define FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN (0x00000002)
1284 
1285 /* Keep Warm Size */
1286 #define IL_KW_SIZE 0x1000 /* 4k */
1287 
1288 #endif /* __il_4965_h__ */
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